; --------------------------------------------------------------------------------
; @Title: M0519 On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2022-03-02 NEJ
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: SVD generated, based on: M0519AE_v1.svd (Ver. 1.0)
; @Core: Cortex-M0
; @Chip: M0519LD3AE, M0519LE3AE, M0519SD3AE, M0519SE3AE, M0519VE3AE
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perm0519.per 14431 2022-03-02 16:52:26Z kwisniewski $

tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2.  "                CLKSOURCE     ,Always reads as one" "No effect,Processor clock"
textline "                 "
bitfld.long 0x00 1.  " TICKINT      ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0.  "       ENABLE        ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG    ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2.  "                CLKSOURCE     ,Always reads as one" "External clock,Processor clock"
textline "                 "
bitfld.long 0x00 1.  " TICKINT      ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0.  "       ENABLE        ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD       ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT      ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Reads as one" "0,1"
bitfld.long 0x00 30. "                SKEW          ,Reads as zero" "0,1"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS        ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF        ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. "  SKEW          ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline "                 "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS        ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER  ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. "               VARIANT       ,Implementation defined variant number"
textline "                 "
hexmask.long.byte 0x00 4.--15. 1.  " PARTNO       ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. "               REVISION      ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET   ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. "      PENDSVSET     ,Set a pending PendSV interrupt" "No effect,Set pending"
textline "                 "
bitfld.long 0x00 27. " PENDSVCLR    ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. "    PENDSTSET     ,Set a pending SysTick" "No effect,Set pending"
textline "                 "
bitfld.long 0x00 25. " PENDSVCLR    ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. "    ISRPREEMPT    ,Pending exception service" "No service,Service"
textline "                 "
bitfld.long 0x00 22. " ISRPENDING   ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. "     VECTPENDING   ,Active exception number field"
textline "                 "
hexmask.long.byte 0x00 0.--5. 1.  " VECTACTIVET  ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF       ,Vector table address"
else
textline "                 "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY      ,Vector Key"
bitfld.long 0x00 15. "             ENDIANNESS    ,Data endianness bit" "Little-endian,Big-endian"
textline "                 "
bitfld.long 0x00 2. " SYSRESETREQ  ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. "        VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND    ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. "       SLEEPDEEP     ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline "                 "
bitfld.long 0x00 1. " SLEEPONEXIT  ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN     ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. "         UNALIGN_TRP   ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11       ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15       ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. "               PRI_14        ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline "                 "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "     SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "     SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "     SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "     SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "     SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "     SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "     SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "     SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "     SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "     SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "     SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "     SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "     SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "     SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "     SET/CLRENA9  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "     SET/CLRENA8  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "     SET/CLRENA6  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "     SET/CLRENA5  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "     SET/CLRENA3  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "     SET/CLRENA2  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                     "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "     SET/CLRENA0  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEN9  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEN8  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEN6  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEN5  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEN3  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEN2  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                     "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEN0  ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3  ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. "  IP_2  ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. "  IP_1  ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7.   "  IP_0  ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7  ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. "  IP_6  ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. "  IP_5  ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7.   "  IP_4  ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. "  IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. "  IP_9  ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7.   "  IP_8  ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. "  IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. "  IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7.   "  IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. "  IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. "  IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7.   "  IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. "  IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. "  IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7.   "  IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. "  IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. "  IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7.   "  IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. "  IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. "  IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7.   "  IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL          ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. "    VCATCH             ,Vector catch flag" "No occurred,Occurred"
textline "                   "
eventfld.long 0x00 2. " DWTRAP            ,Data Watchpoint flag" "No match,Match"
textline "                   "
eventfld.long 0x00 1. " BKPT              ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. "       HALTED             ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 18. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
textline "                   "
textfld "                                 "
bitfld.long 0x00 0. " C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 18. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. "     C_STEP             ,Steps the core in halted debug" "Not halted,Halted"
textline "                   "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. "     C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
textline "                   "
textfld "                                 "
bitfld.long 0x00 0. " C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 30. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 29. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 28. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 27. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 26. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. "       S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline "                   "
bitfld.long 0x00 23. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 22. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 21. " DBGKEY            ,Debug Key" "0,1"
bitfld.long 0x00 20. "              DBGKEY             ,Debug Key" "0,1"
textline "                   "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY   ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. "  S_SLEEP/DBGKEY     ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline "                   "
bitfld.long 0x00 17. " S_HALT/DBGKEY     ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. "     S_REGRDY/DBGKEY    ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline "                   "
bitfld.long 0x00 3. " C_MASKINTS        ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. "     C_STEP             ,Steps the core in halted debug" "Not halted,Halted"
textline "                   "
bitfld.long 0x00 1. " C_HALT            ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. "     C_DEBUGEN          ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR            ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. "          REGSEL             ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA              ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA            ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. "       VC_HARDERR         ,Debug trap on a Hard Fault" "No error,Error"
textline "                   "
bitfld.long 0x04 0.  " VC_CORERESET      ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.     "              KEY  ,Key field" "No write,Write"
bitfld.long 0x00 0.     "  ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH  ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. "  COMP ,Comparison address"
bitfld.long 0x00 0.     "  ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1     ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK      ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED   ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. "  FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP      ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK      ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED   ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. "  FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ACMP"
base ad:0x400D0000
group.long 0x00++0x03
line.long 0x00 "ACMP0CR,Analog Comparator 0 Control Register"
bitfld.long 0x00 6. "ACMP0INV,Analog Comparator 0 Output Inverse Select \n" "0: The comparator output inverse function Disabled,1: The comparator output inverse function Enabled"
bitfld.long 0x00 4. "CN0,Analog Comparator 0 Negative Input Select \n" "0: The comparator reference pin P8.3/ACMP0_N is..,1: The internal band-gap voltage (VBG) is.."
newline
bitfld.long 0x00 3. "CP0,Analog Comparator 0 Positive Input Select \n" "0: The comparator reference pin P8.4/ACMP0_P is..,1: The internal OP amplifier 0 output is.."
bitfld.long 0x00 2. "ACMP0_HYS_EN,CMP Hysteresis Enable Bit\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled"
newline
bitfld.long 0x00 1. "ACMPIE0,Analog Comparator 0 Interrupt Enable Bit\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
bitfld.long 0x00 0. "ACMP0_EN,Analog Comparator 0 Enable Bit\n" "0: Analog comparator Disabled,1: Analog comparator Enabled"
group.long 0x04++0x03
line.long 0x00 "ACMP1CR,Analog Comparator 1 Control Register"
bitfld.long 0x00 6. "ACMP1INV,Analog Comparator 1 Output Inverse Select \n" "0: The comparator output inverse function Disabled,1: The comparator output inverse function Enabled"
bitfld.long 0x00 4. "CN1,Analog Comparator 1 Negative Input Select \n" "0: The comparator reference pin P6.4/ACMP1_N is..,1: The internal band-gap voltage (VBG) is.."
newline
bitfld.long 0x00 3. "CP1,Analog Comparator 1 Positive Input Select \n" "0: The comparator reference pin P6.5/ACMP1_P is..,1: The internal OP amplifier 1 output is.."
bitfld.long 0x00 2. "ACMP1_HYS_EN,CMP Hysteresis Enable Bit\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled"
newline
bitfld.long 0x00 1. "ACMPIE1,Analog Comparator 1 Interrupt Enable Bit\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
bitfld.long 0x00 0. "ACMP1_EN,Analog Comparator 1 Enable Bit\n" "0: Analog comparator Disabled,1: Analog comparator Enabled"
group.long 0x08++0x03
line.long 0x00 "ACMP2CR,Analog Comparator 2 Control Register"
bitfld.long 0x00 6. "ACMP2INV,Analog Comparator 2 Output Inverse Select \n" "0: The comparator output inverse function Disabled,1: The comparator output inverse function Enabled"
bitfld.long 0x00 4. "CN2,Analog Comparator 2 Negative Input Select \n" "0: The comparator reference pin P7.4/ACMP2_N is..,1: The internal band-gap voltage (VBG) is.."
newline
bitfld.long 0x00 2. "ACMP2_HYS_EN,CMP Hysteresis Enable Bit\n" "0: Hysteresis function Disabled,1: Hysteresis function Enabled"
bitfld.long 0x00 1. "ACMPIE2,Analog Comparator 2 Interrupt Enable Bit\n" "0: Interrupt function Disabled,1: Interrupt function Enabled"
newline
bitfld.long 0x00 0. "ACMP2_EN,Analog Comparator 2 Enable Bit\n" "0: Analog comparator Disabled,1: Analog comparator Enabled"
group.long 0x0C++0x03
line.long 0x00 "ACMPSR,Analog Comparator Status Register"
bitfld.long 0x00 10. "CO2,Compare 2 Output\n" "0,1"
bitfld.long 0x00 9. "CO1,Compare 1 Output\n" "0,1"
newline
bitfld.long 0x00 8. "CO0,Compare 0 Output\n" "0,1"
bitfld.long 0x00 5. "OPDF1,OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state" "0,1"
newline
bitfld.long 0x00 4. "OPDF0,OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state" "0,1"
bitfld.long 0x00 2. "ACMPF2,Compare 2 Flag\nThis bit is set by hardware whenever the comparator 2 output changes state" "0,1"
newline
bitfld.long 0x00 1. "ACMPF1,Compare 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state" "0,1"
bitfld.long 0x00 0. "ACMPF0,Compare 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state" "0,1"
tree.end
tree "BPWM0"
base ad:0x40040000
group.long 0x00++0x03
line.long 0x00 "PPR,BPWM0 Prescaler Register"
hexmask.long.byte 0x00 16.--23. 1. "DZI01,Dead-zone Interval for Pair of Channel 0 and Channel 1\nThese 8-bit determine the Dead-zone length.\n"
hexmask.long.byte 0x00 0.--7. 1. "CP01,Clock Prescaler\nClock input is divided by (CP01 + 1) before it is fed to the corresponding BPWM-timer\n"
group.long 0x04++0x03
line.long 0x00 "CSR,BPWM0 Clock Source Divider Select Register"
bitfld.long 0x00 4.--6. "CSR1,BPWM Timer 1 Clock Source Divider Selection\nSelect clock source divider for BPWM timer 1.\n" "0: Input clock divided by 2,1: Input clock divided by 4,2: Input clock divided by 8,3: Input clock divided by 16,4: Input clock divided by 1,?..."
bitfld.long 0x00 0.--2. "CSR0,BPWM Timer 0 Clock Source Divider Selection\nSelect clock source divider for BPWM timer 0 please refer to CSR1" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "PCR,BPWM0 Control Register"
bitfld.long 0x00 30. "PWM01TYPE,BPWM0_CH0/1 Aligned Type Selection Bit \n" "0: Edge-aligned type,1: Center-aligned type"
bitfld.long 0x00 11. "CH1MOD,BPWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit it will cause CNR1 and CMR1 be cleared" "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x00 10. "CH1INV,BPWM-timer 1 Output Inverter Enable Bit\n" "0: Inverter Disabled,1: Inverter Enabled"
bitfld.long 0x00 9. "CH1PINV,BPWM-timer 1 Output Polar Inverse Enable Bit\n" "0: BPWM0_CH1 output polar inverse Disabled,1: BPWM0_CH1 output polar inverse Enabled"
newline
bitfld.long 0x00 8. "CH1EN,BPWM-timer 1 Enable Bit\n" "0: Corresponding BPWM-Timer Stopped,1: Corresponding BPWM-Timer Start Running"
bitfld.long 0x00 4. "DZEN01,Dead-zone 0 Generator Enable Bit\nNote: When Dead-zone generator is enabled the pair of BPWM0_CH0 and BPWM0_CH1 becomes a complementary pair" "0: Dead-zone 0 generator Disabled,1: Dead-zone 0 generator Enabled"
newline
bitfld.long 0x00 3. "CH0MOD,BPWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit it will cause CNR0 and CMR0 be cleared" "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x00 2. "CH0INV,BPWM-timer 0 Output Inverter Enable Bit\n" "0: Inverter Disabled,1: Inverter Enabled"
newline
bitfld.long 0x00 1. "CH0PINV,BPWM-timer 0 Output Polar Inverse Enable Bit\n" "0: BPWM0_CH0 output polar inverse Disabled,1: BPWM0_CH0 output polar inverse Enabled"
bitfld.long 0x00 0. "CH0EN,BPWM-timer 0 Enable Bit\n" "0: The corresponding BPWM-Timer stops running,1: The corresponding BPWM-Timer starts running"
group.long 0x0C++0x03
line.long 0x00 "CNR0,BPWM0 Counter Register 0"
hexmask.long.word 0x00 0.--15. 1. "CNR,BPWM Timer Loaded Value\nCNR determines the BPWM period.\nNote: Any write to CNR will take effect in next BPWM cycle.\nNote: When BPWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE"
group.long 0x10++0x03
line.long 0x00 "CMR0,BPWM0 Comparator Register 0"
hexmask.long.word 0x00 0.--15. 1. "CMR,BPWM Comparator Register\nCMR determines the BPWM duty.\nNote: Any write to CMR will take effect in next BPWM cycle"
rgroup.long 0x14++0x03
line.long 0x00 "PDR0,BPWM0 Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "PDR,BPWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter"
group.long 0x18++0x03
line.long 0x00 "CNR1,BPWM0 Counter Register 1"
hexmask.long.word 0x00 0.--15. 1. "CNR,BPWM Timer Loaded Value\nCNR determines the BPWM period.\nNote: Any write to CNR will take effect in next BPWM cycle.\nNote: When BPWM operating at Center-aligned type CNR value should be set between 0x0000 to 0xFFFE"
group.long 0x1C++0x03
line.long 0x00 "CMR1,BPWM0 Comparator Register 1"
hexmask.long.word 0x00 0.--15. 1. "CMR,BPWM Comparator Register\nCMR determines the BPWM duty.\nNote: Any write to CMR will take effect in next BPWM cycle"
group.long 0x20++0x03
line.long 0x00 "PDR1,BPWM0 Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "PDR,BPWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter"
group.long 0x40++0x03
line.long 0x00 "PIER,BPWM0 Interrupt Enable Register"
bitfld.long 0x00 16. "INTTYPE,BPWM Interrupt Period Type Selection Bit\nNote: This bit is effective when BPWM in Center-aligned type only" "0: BPWMIFn will be set if BPWM counter underflow,1: BPWMIFn will be set if BPWM counter matches.."
bitfld.long 0x00 9. "BPWMDIE1,BPWM Channel 1 Duty Interrupt Enable Bit\n" "0: BPWM0_CH1 duty interrupt Disabled,1: BPWM0_CH1 duty interrupt Enabled"
newline
bitfld.long 0x00 8. "BPWMDIE0,BPWM Channel 0 Duty Interrupt Enable Bit\n" "0: BPWM0_CH0 duty interrupt Disabled,1: BPWM0_CH0 duty interrupt Enabled"
bitfld.long 0x00 1. "BPWMPIE1,BPWM Channel 1 Period Interrupt Enable Bit\n" "0: BPWM0_CH1 period interrupt Disabled,1: BPWM0_CH1 period interrupt Enabled"
newline
bitfld.long 0x00 0. "BPWMPIE0,BPWM Channel 0 Period Interrupt Enable Bit\n" "0: BPWM0_CH0 period interrupt Disabled,1: BPWM0_CH0 period interrupt Enabled"
group.long 0x44++0x03
line.long 0x00 "PIIR,BPWM0 Interrupt Indication Register"
bitfld.long 0x00 9. "BPWMDIF1,BPWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when BPWM0_CH1 counter down count and reaches CMR1 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type selection" "0,1"
bitfld.long 0x00 8. "BPWMDIF0,BPWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when BPWM0_CH0 counter down count and reaches CMR0 software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR this flag is not working in Edge-aligned type selection" "0,1"
newline
bitfld.long 0x00 1. "BPWMIF1,BPWM Channel 1 Period Interrupt Flag\nThis bit is set by hardware when BPWM0_CH1 counter reaches the requirement of interrupt (depend on INTTYPE bit of PIER register).\nNote: This bit can be cleared by writing '1' to it" "0,1"
bitfld.long 0x00 0. "BPWMIF0,BPWM Channel 0 Period Interrupt Flag\nThis bit is set by hardware when BPWM0_CH0 counter reaches the requirement of interrupt (depend on INTTYPE bit of PIER register)" "0,1"
group.long 0x50++0x03
line.long 0x00 "CCR,BPWM0 Capture Control Register"
bitfld.long 0x00 23. "CFLRI1,CFLR1 Latched Indicator Bit\nWhen BPWM0 input channel 1 has a falling transition CFLR1 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it" "0,1"
bitfld.long 0x00 22. "CRLRI1,CRLR1 Latched Indicator Bit\nWhen BPWM0 input channel 1 has a rising transition CRLR1 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it" "0,1"
newline
bitfld.long 0x00 20. "CAPIF1,Channel 1 Capture Interrupt Indication Flag\nNote: This bit can be cleared by writing '1' to it" "0,1"
bitfld.long 0x00 19. "CAPCH1EN,Channel 1 Capture Function Enable Bit\nWhen Enabled Capture latched the BPWM0-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen disabled capture does not update CRLR and CFLR and disable BPWM0_CH1 interrupt" "0: Capture function on BPWM0_CH1 Disabled,1: Capture function on BPWM0_CH1 Enabled"
newline
bitfld.long 0x00 18. "CFL_IE1,Channel 1 Falling Latch Interrupt Enable Bit\nWhen enabled if capture detects BPWM0_CH1 has falling transition capture will issue an interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
bitfld.long 0x00 17. "CRL_IE1,Channel 1 Rising Latch Interrupt Enable Bit\nWhen enabled if capture detects BPWM0_CH1 has rising transition capture will issue an interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
newline
bitfld.long 0x00 16. "INV1,Channel 1 Inverter Enable Bit\n" "0: Inverter Disabled,1: Inverter Enabled"
bitfld.long 0x00 7. "CFLRI0,CFLR0 Latched Indicator Bit\nWhen BPWM0 input channel 0 has a falling transition CFLR0 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it" "0,1"
newline
bitfld.long 0x00 6. "CRLRI0,CRLR0 Latched Indicator Bit\nWhen BPWM0 input channel 0 has a rising transition CRLR0 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it" "0,1"
bitfld.long 0x00 4. "CAPIF0,Channel 0 Capture Interrupt Indication Flag\nNote: This bit can be cleared by writing '1' to it" "0,1"
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bitfld.long 0x00 3. "CAPCH0EN,Channel 0 Capture Function Enable Bit\nWhen enabled capture latched the BPWM0-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen disabled capture does not update CRLR and CFLR and disable BPWM0 channel 0 Interrupt" "0: Capture function on BPWM0_CH0 Disabled,1: Capture function on BPWM0_CH0 Enabled"
bitfld.long 0x00 2. "CFL_IE0,Channel 0 Falling Latch Interrupt Enable Bit\nWhen Enabled if Capture detects BPWM0 channel 0 has falling transition Capture will issue an Interrupt" "0: Falling latch interrupt Disabled,1: Falling latch interrupt Enabled"
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bitfld.long 0x00 1. "CRL_IE0,Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled if capture detects BPWM0 channel 0 has rising transition capture will issue an interrupt" "0: Rising latch interrupt Disabled,1: Rising latch interrupt Enabled"
bitfld.long 0x00 0. "INV0,Channel 0 Inverter Enable Bit\n" "0: Inverter Disabled,1: Inverter Enabled"
rgroup.long 0x58++0x03
line.long 0x00 "CRLR0,BPWM0 Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x00 0.--15. 1. "CRLR,Capture Rising Latch Register\nLatch the BPWM0 counter when Channel 0/1 has rising transition"
rgroup.long 0x5C++0x03
line.long 0x00 "CFLR0,BPWM0 Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0x00 0.--15. 1. "CFLR,Capture Falling Latch Register\nLatch the BPWM0 counter when Channel 0/1 has Falling transition"
group.long 0x60++0x03
line.long 0x00 "CRLR1,BPWM0 Capture Rising Latch Register (Channel 1)"
hexmask.long.word 0x00 0.--15. 1. "CRLR,Capture Rising Latch Register\nLatch the BPWM0 counter when Channel 0/1 has rising transition"
group.long 0x64++0x03
line.long 0x00 "CFLR1,BPWM0 Capture Falling Latch Register (Channel 1)"
hexmask.long.word 0x00 0.--15. 1. "CFLR,Capture Falling Latch Register\nLatch the BPWM0 counter when Channel 0/1 has Falling transition"
group.long 0x78++0x03
line.long 0x00 "CAPENR,BPWM0 Capture Input Enable Register"
bitfld.long 0x00 1. "CINEN1,Channel 1 Capture Input Enable Bit\n" "0: BPWM0_CH1 capture input path Disabled,1: BPWM0_CH1 capture input path Enabled"
bitfld.long 0x00 0. "CINEN0,Channel 0 Capture Input Enable Bit\n" "0: BPWM0_CH0 capture input path Disabled,1: BPWM0_CH0 capture input path Enabled"
group.long 0x7C++0x03
line.long 0x00 "POE,BPWM0 Output Enable"
bitfld.long 0x00 1. "POE1,Channel 1 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to BPWM0 function" "0: BPWM0_CH1 output to pin Disabled,1: BPWM0_CH1 output to pin Enabled"
bitfld.long 0x00 0. "POE0,Channel 0 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to BPWM0 function" "0: BPWM0_CH0 output to pin Disabled,1: BPWM0_CH0 output to pin Enabled"
tree.end
tree "CLK"
base ad:0x50000200
group.long 0x00++0x03
line.long 0x00 "PWRCON,System Power-down Control Register"
bitfld.long 0x00 6. "PD_WU_STS,Power-down Mode Wake-up Interrupt Status\nSet by power down wake up event it indicates that resume from Power-down mode.\nWrite 1 to clear the bit to zero.\nNote: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1" "0,1"
bitfld.long 0x00 5. "PD_WU_INT_EN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.\nNote2: This bit is write protected bit" "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
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bitfld.long 0x00 3. "OSC10K_EN,Internal 10 kHz Oscillator Enable Bit (Write Protect)\nNote: This bit is write protected bit" "0: 10 kHz Oscillation Disabled,1: 10 kHz Oscillation Enabled"
bitfld.long 0x00 2. "OSC22M_EN,Internal 22.1184 MHz Oscillator Enable Bit (Write Protect)\nNote: This bit is write protected bit" "0: 22.1184 MHz Oscillation Disabled,1: 22.1184 MHz Oscillation Enabled"
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bitfld.long 0x00 0. "XTL12M_EN,External 4~24 MHz Crystal Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register CFOSC (Config0[26:24])" "0: External 4~24 MHz crystal Disabled,1: External 4~24 MHz crystal Enabled"
group.long 0x04++0x03
line.long 0x00 "AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x00 4. "HDIV_EN,Hardware Divider Controller Clock Enable Bit\n" "0: Hardware Divider engine clock Disabled,1: Hardware Divider engine clock Enabled"
group.long 0x08++0x03
line.long 0x00 "APBCLK,APB Devices Clock Enable Control Register"
bitfld.long 0x00 29. "OPA_EN,OPA0 and OPA1 Clock Enable Bit\n" "0: OPA0 and OPA1 clock Disabled,1: OPA0 and OPA1 clock Enabled"
bitfld.long 0x00 28. "EADC_EN,EADC Clock Enable Bit\n" "0: EADC clock Disabled,1: EADC clock Enabled"
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bitfld.long 0x00 27. "ECAP1_EN,Enhanced Input Capture 1 Clock Enable Bit\n" "0: Enhanced input capture 1 clock Disabled,1: Enhanced input capture 1 clock Enabled"
bitfld.long 0x00 26. "ECAP0_EN,Enhanced Input Capture 0 Clock Enable Bit\n" "0: Enhanced input capture 0 clock Disabled,1: Enhanced input capture 0 clock Enabled"
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bitfld.long 0x00 22. "ACMP_EN,Analog Comparator Clock Enable Bit\n" "0: Analog comparator clock Disabled,1: Analog comparator clock Enabled"
bitfld.long 0x00 21. "EPWM1_EN,Enhanced PWM1 Clock Enable Bit\n" "0: Enhanced PWM1 clock Disabled,1: Enhanced PWM1 clock Enabled"
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bitfld.long 0x00 20. "EPWM0_EN,Enhanced PWM0 Clock Enable Bit\n" "0: Enhanced PWM0 clock Disabled,1: Enhanced PWM0 clock Enabled"
bitfld.long 0x00 19. "BPWM0_EN,Basic PWM0 Clock Enable Bit\n" "0: Basic PWM0 clock Disabled,1: Basic PWM0 clock Enabled"
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bitfld.long 0x00 17. "UART1_EN,UART1 Clock Enable Bit\n" "0: UART1 clock Disabled,1: UART1 clock Enabled"
bitfld.long 0x00 16. "UART0_EN,UART0 Clock Enable Bit\n" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x00 14. "SPI2_EN,SPI2 Clock Enable Bit\n" "0: SPI2 clock Disabled,1: SPI2 clock Enabled"
bitfld.long 0x00 13. "SPI1_EN,SPI1 Clock Enable Bit\n" "0: SPI1 clock Disabled,1: SPI1 clock Enabled"
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bitfld.long 0x00 12. "SPI0_EN,SPI0 Clock Enable Bit\n" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
bitfld.long 0x00 8. "I2C0_EN,I2C0 Clock Enable Bit\n" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
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bitfld.long 0x00 6. "FDIV_EN,Frequency Divider Output Clock Enable Bit\n" "0: Frequency divider output clock Disabled,1: Frequency divider output clock Enabled"
bitfld.long 0x00 5. "TMR3_EN,Timer3 Clock Enable Bit\n" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
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bitfld.long 0x00 4. "TMR2_EN,Timer2 Clock Enable Bit\n" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
bitfld.long 0x00 3. "TMR1_EN,Timer1 Clock Enable Bit\n" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
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bitfld.long 0x00 2. "TMR0_EN,Timer0 Clock Enable Bit\n" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
bitfld.long 0x00 0. "WDT_EN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected bit" "0: Watchdog Timer clock Disabled,1: Watchdog Timer clock Enabled"
rgroup.long 0x0C++0x03
line.long 0x00 "CLKSTATUS,Clock Status Monitor Register"
bitfld.long 0x00 7. "CLK_SW_FAIL,Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL0[2:0])" "0: Clock switching success,1: Clock switching failure"
bitfld.long 0x00 4. "OSC22M_STB,Internal 22.1184M Hz Oscillator Clock Source Stable Flag (Read Only)\n" "0: Internal 22.1184M Hz oscillator clock is not..,1: Internal 22.1184M Hz oscillator clock is.."
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bitfld.long 0x00 3. "OSC10K_STB,Internal 10k Hz Clock Source Stable Flag (Read Only)\n" "0: Internal 10k Hz oscillator clock is not..,1: Internal 10k Hz oscillator clock is stable.."
bitfld.long 0x00 2. "PLL_STB,PLL Clock Source Stable Flag (Read Only)\n" "0: PLL clock is not stable or disabled,1: PLL clock is stable in normal mode"
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bitfld.long 0x00 0. "XTL12M_STB,External 4~24 MHz Crystal Clock Source Stable Flag (Read Only)\n" "0: External 4~24 MHz crystal clock is not stable..,1: External 4~24 MHz crystal clock is stable and.."
group.long 0x10++0x03
line.long 0x00 "CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x00 3.--5. "STCLK_S,Cortex-M0 SysTick Clock Source Selection (Write Protect)\n" "0: Clock source from external 4~24 MHz crystal..,1: Reserved,2: Clock source from external 4~24 MHz crystal..,3: Clock source from HCLK/2,?,?,?,7: Clock source from internal 22.1184 MHz.."
bitfld.long 0x00 0.--2. "HCLK_S,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turn on.\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration.." "0: Clock source from external 4~24 MHz crystal..,1: Reserved,2: Clock source from PLL clock,3: Clock source from internal 10 kHz oscillator..,?,?,?,7: Clock source from internal 22.1184 MHz.."
group.long 0x14++0x03
line.long 0x00 "CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x00 24.--25. "UART_S,UART Clock Source Selection\n" "0: Clock source from external 4~24 MHz crystal..,1: Clock source from PLL clock,2: Reserved,3: Clock source from internal 22.1184 MHz.."
bitfld.long 0x00 6. "SPI2_S,SPI2 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from HCLK"
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bitfld.long 0x00 5. "SPI1_S,SPI1 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from HCLK"
bitfld.long 0x00 4. "SPI0_S,SPI0 Clock Source Selection\n" "0: Clock source from PLL clock,1: Clock source from HCLK"
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bitfld.long 0x00 0.--1. "WDT_S,Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected bits" "0: Clock source from HCLK/128 clock,1: Clock source from HCLK/512 clock,2: Clock source from HCLK/2048 clock,3: Clock source from internal 10 kHz oscillator.."
group.long 0x18++0x03
line.long 0x00 "CLKDIV,Clock Divider Number Register"
hexmask.long.byte 0x00 16.--23. 1. "EADC_N,EADC Clock Divider\n"
bitfld.long 0x00 8.--11. "UART_N,UART Clock Divider\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "HCLK_N,HCLK Clock Divider\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x00 16.--17. "WWDT_S,Window Watchdog Timer Clock Source Selection\n" "0: Reserved,1: Reserved,2: Clock source from HCLK/2048 clock,3: Clock source from internal 10 kHz low speed.."
bitfld.long 0x00 2.--3. "FRQDIV_S,Clock Divider Clock Source Selection\n" "0: Clock source from external 4~24 MHz crystal..,1: Reserved,2: Clock source from HCLK,3: Clock source from internal 22.1184 MHz.."
group.long 0x20++0x03
line.long 0x00 "PLLCON,PLL Control Register"
bitfld.long 0x00 20. "FCO_SEL,PLL FCO Selection\n" "0: When the FCO frequency range between 100MHz..,1: When the FCO frequency range between 200MHz.."
bitfld.long 0x00 19. "PLL_SRC,PLL Source Clock Selection\n" "0: PLL source clock from external 4~24 MHz crystal,1: PLL source clock from internal 22.1184 MHz.."
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bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Bit\n" "0: PLL FOUT enable,1: PLL FOUT is fixed low"
bitfld.long 0x00 17. "BP,PLL Bypass Control\n" "0: PLL is in normal mode (default),1: PLL clock output is same as clock input"
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bitfld.long 0x00 16. "PD,Power-down Mode\n" "0: PLL is in normal mode,1: PLL is in power-down mode (default)"
bitfld.long 0x00 14.--15. "OUT_DV,PLL Output Divider Control Bits\nRefer to the formulas below the table" "0,1,2,3"
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bitfld.long 0x00 9.--13. "IN_DV,PLL Input Divider Control Bits\nRefer to the formulas below the table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--8. 1. "FB_DV,PLL Feedback Divider Control Bits\nRefer to the formulas below the table"
group.long 0x24++0x03
line.long 0x00 "FRQDIV,Frequency Divider Control Register"
bitfld.long 0x00 5. "DIV1,Frequency Divider Divide 1 Enable Bit\n" "0: Frequency divider will output clock with..,1: Frequency divider will output clock with.."
bitfld.long 0x00 4. "DIVIDER_EN,Frequency Divider Enable Bit\n" "0: Frequency divider Disabled,1: Frequency divider Enabled"
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bitfld.long 0x00 0.--3. "FSEL,Frequency Divider Output Selection Bits\nThe output formula is:\nwhere FFRQDIV_CLK is the input clock frequency FCLKO is the clock divider output frequency and N is the 4-bit value in FSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "EADC"
base ad:0x400E0000
rgroup.long 0x00++0x03
line.long 0x00 "ADDRA0,A/D Data Register 0 for SAMPLEA0"
bitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
bitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x04++0x03
line.long 0x00 "ADDRA1,A/D Data Register 1 for SAMPLEA1"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x08++0x03
line.long 0x00 "ADDRA2,A/D Data Register 2 for SAMPLEA2"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x0C++0x03
line.long 0x00 "ADDRA3,A/D Data Register 3 for SAMPLEA3"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x10++0x03
line.long 0x00 "ADDRA4,A/D Data Register 4 for SAMPLEA4"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x14++0x03
line.long 0x00 "ADDRA5,A/D Data Register 5 for SAMPLEA5"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x18++0x03
line.long 0x00 "ADDRA6,A/D Data Register 6 for SAMPLEA6"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x1C++0x03
line.long 0x00 "ADDRA7,A/D Data Register 7 for SAMPLEA7"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x20++0x03
line.long 0x00 "ADDRB0,A/D Data Register 8 for SAMPLEB0"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x24++0x03
line.long 0x00 "ADDRB1,A/D Data Register 9 for SAMPLEB1"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x28++0x03
line.long 0x00 "ADDRB2,A/D Data Register 10 for SAMPLEB2"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x2C++0x03
line.long 0x00 "ADDRB3,A/D Data Register 11 for SAMPLEB3"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x30++0x03
line.long 0x00 "ADDRB4,A/D Data Register 12 for SAMPLEB4"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x34++0x03
line.long 0x00 "ADDRB5,A/D Data Register 13 for SAMPLEB5"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x38++0x03
line.long 0x00 "ADDRB6,A/D Data Register 14 for SAMPLEB6"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x3C++0x03
line.long 0x00 "ADDRB7,A/D Data Register 15 for SAMPLEB7"
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is" "0: Data in RSLT[11:0] bits is not valid,1: Data in RSLT[11:0] bits is valid"
rbitfld.long 0x00 16. "OVERRUN,over Run Flag\n" "0: Data in RSLT[11:0] is the recent conversion..,1: Data in RSLT[11:0] is overwritten"
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hexmask.long.word 0x00 0.--11. 1. "RSLT,A/D Conversion Result\nThis field contains 12-bit conversion result"
group.long 0x40++0x03
line.long 0x00 "ADCR,A/D Control Register"
bitfld.long 0x00 5. "ADIE3,Specific SAMPLE A/D ADINT3 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF3 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion" "0: Specific SAMPLE A/D ADINT3 interrupt function..,1: Specific SAMPLE A/D ADINT3 interrupt function.."
bitfld.long 0x00 4. "ADIE2,Specific SAMPLE A/D ADINT2 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF2 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion" "0: Specific SAMPLE A/D ADINT2 interrupt function..,1: Specific SAMPLE A/D ADINT2 interrupt function.."
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bitfld.long 0x00 3. "ADIE1,Specific SAMPLE A/D ADINT1 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF1 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion" "0: Specific SAMPLE A/D ADINT1 interrupt function..,1: Specific SAMPLE A/D ADINT1 interrupt function.."
bitfld.long 0x00 2. "ADIE0,Specific SAMPLE A/D ADINT0 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF0 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion" "0: Specific SAMPLE A/D ADINT0 interrupt function..,1: Specific SAMPLE A/D ADINT0 interrupt function.."
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bitfld.long 0x00 1. "ADRESET,ADCA ADCB A/D Converter Control Circuits Reset\nNote: This bit remains 1 during ADC reset when ADC reset end the ADRESET bit is automatically cleared to 0" "0: Writing 0 has no effect,1: Writing 1 will cause ADC control circuits.."
bitfld.long 0x00 0. "AD_EN,A/D Converter Enable Bit\nNote: Before starting the A/D conversion function this bit should be set to 1" "0: A/D converter Disabled,1: A/D converter Enabled"
group.long 0x44++0x03
line.long 0x00 "ADCHISELR,A/D Channel Input Sources Select Register"
bitfld.long 0x00 2.--3. "PRESEL,A/D Channel AINA[7] Analog Input Selection\n" "0: Analog Input Channel AINA7,1: Band-gap (VBG) Analog Input,2: VTEMP Internal Temperature Sensor Analog Input,3: Analog ground"
bitfld.long 0x00 1. "AINB0SEL,A/D Channel AINB[0] Analog Input Selection\n" "0: AINB[0] pin P7.0E/EADC1_CH0 is selected as..,1: OP Amplifier 1 output is selected as the A/D.."
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bitfld.long 0x00 0. "AINA0SEL,A/D Channel AINA[0] Analog Input Selection \n" "0: AINA[0] pin P6.0/EADC0_CH0is selected as the..,1: OP Amplifier 0 output is selected as the ADC.."
wgroup.long 0x48++0x03
line.long 0x00 "ADSSTR,A/D SAMPLE Software Start Register"
hexmask.long.byte 0x00 8.--15. 1. "ADST15_8,A/D SAMPLEB7~0 Software Force to Start ADC Conversion Register \n"
hexmask.long.byte 0x00 0.--7. 1. "ADST7_0,A/D SAMPLEA7~0 Software Force to Start ADC Conversion Register \n"
rgroup.long 0x4C++0x03
line.long 0x00 "ADSTPFR,A/D SAMPLE Start of Conversion Pending Flag Register"
hexmask.long.byte 0x00 8.--15. 1. "STPF15_8,A/D SAMPLEB7~0 Start Conversion Pending Flag \n"
hexmask.long.byte 0x00 0.--7. 1. "STPF7_0,A/D SAMPLEA7~0 Start Conversion Pending Flag \n"
group.long 0x50++0x03
line.long 0x00 "ADIFOVR,A/D ADINT3~0 Interrupt Flag over Run Register"
bitfld.long 0x00 3. "ADFOV3,A/D ADINT3 Interrupt Flag over Run Bit\nNote: This bit is cleared by writing 1 to 1" "0: ADINT3 interrupt flag is not over run,1: ADINT3 interrupt pulse received when ADF3 is 1"
bitfld.long 0x00 2. "ADFOV2,A/D ADINT2 Interrupt Flag over Run Bit\nNote: This bit is cleared by writing 1 to 1" "0: ADINT2 interrupt flag is not over run,1: ADINT2 interrupt flag is overwrite to 1"
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bitfld.long 0x00 1. "ADFOV1,A/D ADINT1 Interrupt Flag over Run Bit\nNote: This bit is cleared by writing 1 to 1" "0: ADINT1 interrupt flag is not over run,1: ADINT1 interrupt flag is overwrite to 1"
bitfld.long 0x00 0. "ADFOV0,A/D ADINT0 Interrupt Flag over Run Bit\nNote: This bit is cleared by writing 1 to 1" "0: ADINT0 interrupt flag is not over run,1: ADINT0 interrupt flag is overwrite to 1"
group.long 0x54++0x03
line.long 0x00 "ADSPOVFR,A/D SAMPLE Start of Conversion over Run Flag Register"
hexmask.long.byte 0x00 8.--15. 1. "SPOVF15_8,A/D SAMPLEB7~SAMPLEB0 Start Conversion Overrun Flag\n"
hexmask.long.byte 0x00 0.--7. 1. "SPOVF7_0,A/D SAMPLEA7~SAMPLEA0 Start Conversion Overrun Flag\n"
group.long 0x58++0x03
line.long 0x00 "ADSPCRA0,A/D SAMPLEA0 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE Start Conversion Trigger Delay Time\n"
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: PWM00 trigger,9: PWM02 trigger,10: PWM04 trigger,11: PWM10 trigger,12: PWM12 trigger,13: PWM14 trigger,14: PWM20 trigger,15: PWM21 trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x5C++0x03
line.long 0x00 "ADSPCRA1,A/D SAMPLEA1 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE Start Conversion Trigger Delay Time\n"
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: PWM00 trigger,9: PWM02 trigger,10: PWM04 trigger,11: PWM10 trigger,12: PWM12 trigger,13: PWM14 trigger,14: PWM20 trigger,15: PWM21 trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x60++0x03
line.long 0x00 "ADSPCRA2,A/D SAMPLEA2 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE Start Conversion Trigger Delay Time\n"
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: PWM00 trigger,9: PWM02 trigger,10: PWM04 trigger,11: PWM10 trigger,12: PWM12 trigger,13: PWM14 trigger,14: PWM20 trigger,15: PWM21 trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x64++0x03
line.long 0x00 "ADSPCRA3,A/D SAMPLEA3 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE Start Conversion Trigger Delay Time\n"
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: PWM00 trigger,9: PWM02 trigger,10: PWM04 trigger,11: PWM10 trigger,12: PWM12 trigger,13: PWM14 trigger,14: PWM20 trigger,15: PWM21 trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x68++0x03
line.long 0x00 "ADSPCRA4,A/D SAMPLEA4 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 4.--6. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x6C++0x03
line.long 0x00 "ADSPCRA5,A/D SAMPLEA5 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 4.--6. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x70++0x03
line.long 0x00 "ADSPCRA6,A/D SAMPLEA6 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 4.--6. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x74++0x03
line.long 0x00 "ADSPCRA7,A/D SAMPLEA7 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 4.--6. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x78++0x03
line.long 0x00 "ADSPCRB0,A/D SAMPLEB0 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE Start Conversion Trigger Delay Time\n"
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: PWM00 trigger,9: PWM02 trigger,10: PWM04 trigger,11: PWM10 trigger,12: PWM12 trigger,13: PWM14 trigger,14: PWM20 trigger,15: PWM21 trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x7C++0x03
line.long 0x00 "ADSPCRB1,A/D SAMPLEB1 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE Start Conversion Trigger Delay Time\n"
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: PWM00 trigger,9: PWM02 trigger,10: PWM04 trigger,11: PWM10 trigger,12: PWM12 trigger,13: PWM14 trigger,14: PWM20 trigger,15: PWM21 trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x80++0x03
line.long 0x00 "ADSPCRB2,A/D SAMPLEB2 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE Start Conversion Trigger Delay Time\n"
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: PWM00 trigger,9: PWM02 trigger,10: PWM04 trigger,11: PWM10 trigger,12: PWM12 trigger,13: PWM14 trigger,14: PWM20 trigger,15: PWM21 trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x84++0x03
line.long 0x00 "ADSPCRB3,A/D SAMPLEB3 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 16.--17. "TRGDLYDIV,A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,A/D SAMPLE Start Conversion Trigger Delay Time\n"
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bitfld.long 0x00 4.--7. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger,8: PWM00 trigger,9: PWM02 trigger,10: PWM04 trigger,11: PWM10 trigger,12: PWM12 trigger,13: PWM14 trigger,14: PWM20 trigger,15: PWM21 trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x88++0x03
line.long 0x00 "ADSPCRB4,A/D SAMPLEB4 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 4.--6. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x8C++0x03
line.long 0x00 "ADSPCRB5,A/D SAMPLEB5 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 4.--6. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x90++0x03
line.long 0x00 "ADSPCRB6,A/D SAMPLEB6 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 4.--6. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0x94++0x03
line.long 0x00 "ADSPCRB7,A/D SAMPLEB7 Control Register"
bitfld.long 0x00 21. "EXTFEN,A/D External Trigger Falling Edge Enable Bit\n" "0: Falling edge Disabled when A/D selects STADC..,1: Falling edge Enabled when A/D selects STADC.."
bitfld.long 0x00 20. "EXTREN,A/D External Trigger Rising Edge Enable Bit\n" "0: Rising edge Disabled when A/D selects STADC..,1: Rising edge Enabled when A/D selects STADC as.."
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bitfld.long 0x00 4.--6. "TRGSEL,A/D SAMPLE Start Conversion Trigger Source Selection\n" "0: Disable hardware trigger,1: External trigger from STADC pin input,2: ADC ADINT0 interrupt EOC pulse trigger,3: ADC ADINT1 interrupt EOC pulse trigger,4: Timer0 overflow pulse trigger,5: Timer1 overflow pulse trigger,6: Timer2 overflow pulse trigger,7: Timer3 overflow pulse trigger"
bitfld.long 0x00 0.--2. "CHSEL,A/D SAMPLEA B Channel Selection\n" "0: AINx[0],1: AINx[1],2: AINx[2],3: AINx[3],4: AINx[4],5: AINx[5],6: AINx[6],7: AINx[7]"
group.long 0xA4++0x03
line.long 0x00 "ADSMSELR,A/D SAMPLE Simultaneous Mode Select Register"
bitfld.long 0x00 7. "SIMUSEL7,A/D SAMPLEA7 SAMPLEB7 Simultaneous Sampling Mode Selection\n" "0: SAMPLEA7 SAMPLEB7 are in single sampling mode..,1: SAMPLEA7 SAMPLEB7 are in simultaneous.."
bitfld.long 0x00 6. "SIMUSEL6,A/D SAMPLEA6 SAMPLEB6 Simultaneous Sampling Mode Selection \n" "0: SAMPLEA6 SAMPLEB6 are in single sampling mode..,1: SAMPLEA6 SAMPLEB6 are in simultaneous.."
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bitfld.long 0x00 5. "SIMUSEL5,A/D SAMPLEA5 SAMPLEB5 Simultaneous Sampling Mode Selection \n" "0: SAMPLEA5 SAMPLEB5 are in single sampling mode..,1: SAMPLEA5 SAMPLEB5 are in simultaneous.."
bitfld.long 0x00 4. "SIMUSEL4,A/D SAMPLEA4 SAMPLEB4 Simultaneous Sampling Mode Select Ion\n" "0: SAMPLEA4 SAMPLEB4 are in single sampling mode..,1: SAMPLEA4 SAMPLEB4 are in simultaneous.."
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bitfld.long 0x00 3. "SIMUSEL3,A/D SAMPLEA3 SAMPLEB3 Simultaneous Sampling Mode Select Ion\n" "0: SAMPLEA3 SAMPLEB3 are in single sampling mode..,1: SAMPLEA3 SAMPLEB3 are in simultaneous.."
bitfld.long 0x00 2. "SIMUSEL2,A/D SAMPLEA2 SAMPLEB2 Simultaneous Sampling Mode Selection \n" "0: SAMPLEA2 SAMPLEB2 are in single sampling mode..,1: SAMPLEA2 SAMPLEB2 are in simultaneous.."
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bitfld.long 0x00 1. "SIMUSEL1,A/D SAMPLEA1 SAMPLEB1 Simultaneous Sampling Mode Selection \n" "0: SAMPLEA1 SAMPLEB1 are in single sampling mode..,1: SAMPLEA1 SAMPLEB1 are in simultaneous.."
bitfld.long 0x00 0. "SIMUSEL0,A/D SAMPLEA0 SAMPLEB0 Simultaneous Sampling Mode Selection \n" "0: SAMPLEA0 SAMPLEB0 are in single sampling mode..,1: SAMPLEA0 SAMPLEB0 are in simultaneous.."
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0xA8)++0x03
line.long 0x00 "ADCMPR$1,A/D Result Compare Register $1"
hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12 bits data is used to compare with the conversion result of specified SAMPLE"
bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--5. "CMPSMPL,Compare SAMPLE Selection\n" "0: SAMPLEA0 conversion result ADDRA0 is selected..,1: SAMPLEA1 conversion result ADDRA1 is selected..,2: SAMPLEA2 conversion result ADDRA2 is selected..,3: SAMPLEA3 conversion result ADDRA3 is selected..,4: SAMPLEB0 conversion result ADDRB0 is selected..,5: SAMPLEB1 conversion result ADDRB1 is selected..,6: SAMPLEB2 conversion result ADDRB2 is selected..,7: SAMPLEB3 conversion result ADDRB3 is selected.."
bitfld.long 0x00 2. "CMPCOND,Compare Condition\n" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,A/D Result Compare Interrupt Enable Bit\n" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
bitfld.long 0x00 0. "ADCMP_EN,A/D Result Compare Enable Bit\n" "0: Compare Disabled,1: Compare Enabled"
repeat.end
rgroup.long 0xB0++0x03
line.long 0x00 "ADSR0,A/D Status Register 0"
hexmask.long.byte 0x00 24.--31. 1. "OVERRUN31_24,ADDRB7~0 over Run Flag\n"
hexmask.long.byte 0x00 16.--23. 1. "OVERRUN26_16,ADDRA7~0 over Run Flag\n"
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hexmask.long.byte 0x00 8.--15. 1. "VALID15_8,ADDRB7~0 Data Valid Flag\n"
hexmask.long.byte 0x00 0.--7. 1. "VALID7_0,ADDRA7~0 Data Valid Flag\n"
group.long 0xB4++0x03
line.long 0x00 "ADSR1,A/D Status Register 1"
bitfld.long 0x00 27. "AOVERRUN,All SAMPLE A/D Result Data Register over Run Flags Check \n" "0: None of SAMPLE data register over run flag..,1: Any one of SAMPLE data register over run flag.."
bitfld.long 0x00 26. "AVALID,All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check\n" "0: None of SAMPLE data register valid flag..,1: Any one of SAMPLE data register valid flag.."
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bitfld.long 0x00 25. "ASPOVF,All A/D SAMPLE Start Conversion over Run Flags Check\n" "0: None of SAMPLE event over run flag SPOVFn is..,1: Any one of SAMPLE event over run flag SPOVFn.."
bitfld.long 0x00 24. "AADFOV,All A/D Interrupt Flag over Run Bits Check \n" "0: None of ADINT interrupt flag ADFOVn is..,1: Any one of ADINT interrupt flag ADFOVn is.."
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rbitfld.long 0x00 20.--22. "CHANNELB,Current Conversion Channel (Read Only)\n" "0: AINB[0],1: AINB[1],2: AINB[2],3: AINB[3],4: AINB[4],5: AINB[5],6: AINB[6],7: AINB[7]"
rbitfld.long 0x00 16. "BUSYB,BUSY/IDLE (Read Only)\n" "0: A/D converter B (ADCB) is in idle state,1: A/D converter B (ADCB) is busy at conversion"
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rbitfld.long 0x00 12.--14. "CHANNELA,Current Conversion Channel (Read Only)\n" "0: AINA[0],1: AINA[1],2: AINA[2],3: AINA[3],4: AINA[4],5: AINA[5],6: AINA[6],7: AINA[7]"
rbitfld.long 0x00 8. "BUSYA,BUSY/IDLE (Read Only)\n" "0: A/D converter A (ADCA) is in idle state,1: A/D converter A (ADCA) is busy at conversion"
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bitfld.long 0x00 7. "ADCMPF1,ADC Compare 1 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR1 register then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1.."
bitfld.long 0x00 6. "ADCMPF0,ADC Compare 0 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0.."
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bitfld.long 0x00 5. "ADCMPO1,ADC Compare 1 Output Status Bit\nThe 12 bits compare1 data CMPD(ADCMPR1[27:16]) is used to compare with conversion result of specified SAMPLE" "0: Conversion result in ADDR less than..,1: Conversion result in ADDR great than or equal.."
bitfld.long 0x00 4. "ADCMPO0,ADC Compare 0 Output Status Bit\nThe 12 bits compare0 data CMPD(ADCMPR0[27:16]) is used to compare with conversion result of specified SAMPLE" "0: Conversion result in ADDR is less than..,1: Conversion result in ADDR is great than or.."
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bitfld.long 0x00 3. "ADF3,A/D ADINT3 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed" "0: No ADINT3 interrupt pulse received,1: ADINT3 interrupt pulse received"
bitfld.long 0x00 2. "ADF2,A/D ADINT2 Interrupt Flag\nNote1: It is cleared by writing 1" "0: No ADINT2 interrupt pulse received,1: ADINT2 interrupt pulse received"
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bitfld.long 0x00 1. "ADF1,A/D ADINT1 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed" "0: no ADINT1 interrupt pulse received,1: ADINT1 interrupt pulse has been received"
bitfld.long 0x00 0. "ADF0,A/D ADINT0 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed" "0: No ADINT0 interrupt pulse received,1: ADINT0 interrupt pulse received"
group.long 0xB8++0x03
line.long 0x00 "ADTCR,A/D Timing Control Register"
hexmask.long.byte 0x00 16.--23. 1. "ADBEST,ADCB Extend Sampling Time \nWhen A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy User can extend A/D sampling time after trigger source is coming to get enough.."
hexmask.long.byte 0x00 0.--7. 1. "ADAEST,ADCA Extend Sampling Time \nWhen A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy User can extend A/D sampling time after trigger source is coming to get enough.."
rgroup.long 0x100++0x03
line.long 0x00 "ADDRDBA0,A/D Data Register Double Buffer for SAMPLEA0"
bitfld.long 0x00 16. "VALID,Valid Flag\n" "0: Double data in RSLTDB[11:0] bits is not valid,1: Double data in RSLTDB[11:0] bits is valid"
hexmask.long.word 0x00 0.--11. 1. "RSLTDB,A/D Conversion Result\n"
repeat 3. (strings "1" "2" "3" )(list 0x00 0x04 0x08 )
group.long ($2+0x104)++0x03
line.long 0x00 "ADDRDBA$1,A/D Data Register Double Buffer for SAMPLEA $1"
rbitfld.long 0x00 16. "VALID,Valid Flag\n" "0: Double data in RSLTDB[11:0] bits is not valid,1: Double data in RSLTDB[11:0] bits is valid"
hexmask.long.word 0x00 0.--11. 1. "RSLTDB,A/D Conversion Result\n"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x120)++0x03
line.long 0x00 "ADDRDBB$1,A/D Data Register Double Buffer for SAMPLEB $1"
rbitfld.long 0x00 16. "VALID,Valid Flag\n" "0: Double data in RSLTDB[11:0] bits is not valid,1: Double data in RSLTDB[11:0] bits is valid"
hexmask.long.word 0x00 0.--11. 1. "RSLTDB,A/D Conversion Result\n"
repeat.end
group.long 0x130++0x03
line.long 0x00 "ADDBM,A/D Double Buffer Mode Select"
bitfld.long 0x00 11. "DBMB3,Double Buffer Mode for SAMPLE B3 \n" "0: SampleB3 has one sample result register,1: SampleB3 has two sample result registers"
bitfld.long 0x00 10. "DBMB2,Double Buffer Mode for SAMPLE B2 \n" "0: SampleB2 has one sample result register,1: SampleB2 has two sample result registers"
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bitfld.long 0x00 9. "DBMB1,Double Buffer Mode for SAMPLE B1 \n" "0: SampleB1 has one sample result register,1: SampleB1 has two sample result registers"
bitfld.long 0x00 8. "DBMB0,Double Buffer Mode for SAMPLE B0 \n" "0: SampleB0 has one sample result register,1: SampleB0 has two sample result registers"
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bitfld.long 0x00 3. "DBMA3,Double Buffer Mode for SAMPLE A3 \n" "0: SampleA3 has one sample result register,1: SampleA3 has two sample result registers"
bitfld.long 0x00 2. "DBMA2,Double Buffer Mode for SAMPLE A2 \n" "0: SampleA2 has one sample result register,1: SampleA2 has two sample result registers"
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bitfld.long 0x00 1. "DBMA1,Double Buffer Mode for SAMPLE A1 \n" "0: SampleA1 has one sample result register,1: SampleA1 has two sample result registers"
bitfld.long 0x00 0. "DBMA0,Double Buffer Mode for SAMPLE A0 \n" "0: SampleA0 has one sample result register,1: SampleA0 has two sample result registers"
group.long 0x134++0x03
line.long 0x00 "ADINT0SRCTL,A/D Interrupt 0 Source Enable Control Register"
bitfld.long 0x00 15. "IESPLB7,SAMPLE B7 Interrupt Mask Enable Bit\n" "0: SAMPLE B7 interrupt mask Disabled,1: SAMPLE B7 interrupt mask Enabled"
bitfld.long 0x00 14. "IESPLB6,SAMPLE B6 Interrupt Mask Enable Bit\n" "0: SAMPLE B6 interrupt mask Disabled,1: SAMPLE B6 interrupt mask Enabled"
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bitfld.long 0x00 13. "IESPLB5,SAMPLE B5 Interrupt Mask Enable Bit\n" "0: SAMPLE B5 interrupt mask Disabled,1: SAMPLE B5 interrupt mask Enabled"
bitfld.long 0x00 12. "IESPLB4,SAMPLE B4 Interrupt Mask Enable Bit\n" "0: SAMPLE B4 interrupt mask Disabled,1: SAMPLE B4 interrupt mask Enabled"
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bitfld.long 0x00 11. "IESPLB3,SAMPLE B3 Interrupt Mask Enable Bit\n" "0: SAMPLE B3 interrupt mask Disabled,1: SAMPLE B3 interrupt mask Enabled"
bitfld.long 0x00 10. "IESPLB2,SAMPLE B2 Interrupt Mask Enable Bit\n" "0: SAMPLE B2 interrupt mask Disabled,1: SAMPLE B2 interrupt mask Enabled"
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bitfld.long 0x00 9. "IESPLB1,SAMPLE B1 Interrupt Mask Enable Bit\n" "0: SAMPLE B1 interrupt mask Disabled,1: SAMPLE B1 interrupt mask Enabled"
bitfld.long 0x00 8. "IESPLB0,SAMPLE B0 Interrupt Mask Enable Bit\n" "0: SAMPLE B0 interrupt mask Disabled,1: SAMPLE B0 interrupt mask Enabled"
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bitfld.long 0x00 7. "IESPLA7,SAMPLE A7 Interrupt Mask Enable Bit\n" "0: SAMPLE A7 interrupt mask Disabled,1: SAMPLE A7 interrupt mask Enabled"
bitfld.long 0x00 6. "IESPLA6,SAMPLE A6 Interrupt Mask Enable Bit\n" "0: SAMPLE A6 interrupt mask Disabled,1: SAMPLE A6 interrupt mask Enabled"
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bitfld.long 0x00 5. "IESPLA5,SAMPLE A5 Interrupt Mask Enable Bit\n" "0: SAMPLE A5 interrupt mask Disabled,1: SAMPLE A5 interrupt mask Enabled"
bitfld.long 0x00 4. "IESPLA4,SAMPLE A4 Interrupt Mask Enable Bit\n" "0: SAMPLE A4 interrupt mask Disabled,1: SAMPLE A4 interrupt mask Enabled"
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bitfld.long 0x00 3. "IESPLA3,SAMPLE A3 Interrupt Mask Enable Bit\n" "0: SAMPLE A3 interrupt mask Disabled,1: SAMPLE A3 interrupt mask Enabled"
bitfld.long 0x00 2. "IESPLA2,SAMPLE A2 Interrupt Mask Enable Bit\n" "0: SAMPLE A2 interrupt mask Disabled,1: SAMPLE A2 interrupt mask Enabled"
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bitfld.long 0x00 1. "IESPLA1,SAMPLE A1 Interrupt Mask Enable Bit\n" "0: SAMPLE A1 interrupt mask Disabled,1: SAMPLE A1 interrupt mask Enabled"
bitfld.long 0x00 0. "IESPLA0,SAMPLE A0 Interrupt Mask Enable Bit\n" "0: SAMPLE A0 interrupt mask Disabled,1: SAMPLE A0 interrupt mask Enabled"
group.long 0x138++0x03
line.long 0x00 "ADINT1SRCTL,A/D Interrupt 1 Source Enable Control Register"
bitfld.long 0x00 15. "IESPLB7,SAMPLE B7 Interrupt Mask Enable Bit\n" "0: SAMPLE B7 interrupt mask Disabled,1: SAMPLE B7 interrupt mask Enabled"
bitfld.long 0x00 14. "IESPLB6,SAMPLE B6 Interrupt Mask Enable Bit\n" "0: SAMPLE B6 interrupt mask Disabled,1: SAMPLE B6 interrupt mask Enabled"
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bitfld.long 0x00 13. "IESPLB5,SAMPLE B5 Interrupt Mask Enable Bit\n" "0: SAMPLE B5 interrupt mask Disabled,1: SAMPLE B5 interrupt mask Enabled"
bitfld.long 0x00 12. "IESPLB4,SAMPLE B4 Interrupt Mask Enable Bit\n" "0: SAMPLE B4 interrupt mask Disabled,1: SAMPLE B4 interrupt mask Enabled"
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bitfld.long 0x00 11. "IESPLB3,SAMPLE B3 Interrupt Mask Enable Bit\n" "0: SAMPLE B3 interrupt mask Disabled,1: SAMPLE B3 interrupt mask Enabled"
bitfld.long 0x00 10. "IESPLB2,SAMPLE B2 Interrupt Mask Enable Bit\n" "0: SAMPLE B2 interrupt mask Disabled,1: SAMPLE B2 interrupt mask Enabled"
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bitfld.long 0x00 9. "IESPLB1,SAMPLE B1 Interrupt Mask Enable Bit\n" "0: SAMPLE B1 interrupt mask Disabled,1: SAMPLE B1 interrupt mask Enabled"
bitfld.long 0x00 8. "IESPLB0,SAMPLE B0 Interrupt Mask Enable Bit\n" "0: SAMPLE B0 interrupt mask Disabled,1: SAMPLE B0 interrupt mask Enabled"
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bitfld.long 0x00 7. "IESPLA7,SAMPLE A7 Interrupt Mask Enable Bit\n" "0: SAMPLE A7 interrupt mask Disabled,1: SAMPLE A7 interrupt mask Enabled"
bitfld.long 0x00 6. "IESPLA6,SAMPLE A6 Interrupt Mask Enable Bit\n" "0: SAMPLE A6 interrupt mask Disabled,1: SAMPLE A6 interrupt mask Enabled"
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bitfld.long 0x00 5. "IESPLA5,SAMPLE A5 Interrupt Mask Enable Bit\n" "0: SAMPLE A5 interrupt mask Disabled,1: SAMPLE A5 interrupt mask Enabled"
bitfld.long 0x00 4. "IESPLA4,SAMPLE A4 Interrupt Mask Enable Bit\n" "0: SAMPLE A4 interrupt mask Disabled,1: SAMPLE A4 interrupt mask Enabled"
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bitfld.long 0x00 3. "IESPLA3,SAMPLE A3 Interrupt Mask Enable Bit\n" "0: SAMPLE A3 interrupt mask Disabled,1: SAMPLE A3 interrupt mask Enabled"
bitfld.long 0x00 2. "IESPLA2,SAMPLE A2 Interrupt Mask Enable Bit\n" "0: SAMPLE A2 interrupt mask Disabled,1: SAMPLE A2 interrupt mask Enabled"
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bitfld.long 0x00 1. "IESPLA1,SAMPLE A1 Interrupt Mask Enable Bit\n" "0: SAMPLE A1 interrupt mask Disabled,1: SAMPLE A1 interrupt mask Enabled"
bitfld.long 0x00 0. "IESPLA0,SAMPLE A0 Interrupt Mask Enable Bit\n" "0: SAMPLE A0 interrupt mask Disabled,1: SAMPLE A0 interrupt mask Enabled"
group.long 0x13C++0x03
line.long 0x00 "ADINT2SRCTL,A/D Interrupt 2 Source Enable Control Register"
bitfld.long 0x00 15. "IESPLB7,SAMPLE B7 Interrupt Mask Enable Bit\n" "0: SAMPLE B7 interrupt mask Disabled,1: SAMPLE B7 interrupt mask Enabled"
bitfld.long 0x00 14. "IESPLB6,SAMPLE B6 Interrupt Mask Enable Bit\n" "0: SAMPLE B6 interrupt mask Disabled,1: SAMPLE B6 interrupt mask Enabled"
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bitfld.long 0x00 13. "IESPLB5,SAMPLE B5 Interrupt Mask Enable Bit\n" "0: SAMPLE B5 interrupt mask Disabled,1: SAMPLE B5 interrupt mask Enabled"
bitfld.long 0x00 12. "IESPLB4,SAMPLE B4 Interrupt Mask Enable Bit\n" "0: SAMPLE B4 interrupt mask Disabled,1: SAMPLE B4 interrupt mask Enabled"
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bitfld.long 0x00 11. "IESPLB3,SAMPLE B3 Interrupt Mask Enable Bit\n" "0: SAMPLE B3 interrupt mask Disabled,1: SAMPLE B3 interrupt mask Enabled"
bitfld.long 0x00 10. "IESPLB2,SAMPLE B2 Interrupt Mask Enable Bit\n" "0: SAMPLE B2 interrupt mask Disabled,1: SAMPLE B2 interrupt mask Enabled"
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bitfld.long 0x00 9. "IESPLB1,SAMPLE B1 Interrupt Mask Enable Bit\n" "0: SAMPLE B1 interrupt mask Disabled,1: SAMPLE B1 interrupt mask Enabled"
bitfld.long 0x00 8. "IESPLB0,SAMPLE B0 Interrupt Mask Enable Bit\n" "0: SAMPLE B0 interrupt mask Disabled,1: SAMPLE B0 interrupt mask Enabled"
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bitfld.long 0x00 7. "IESPLA7,SAMPLE A7 Interrupt Mask Enable Bit\n" "0: SAMPLE A7 interrupt mask Disabled,1: SAMPLE A7 interrupt mask Enabled"
bitfld.long 0x00 6. "IESPLA6,SAMPLE A6 Interrupt Mask Enable Bit\n" "0: SAMPLE A6 interrupt mask Disabled,1: SAMPLE A6 interrupt mask Enabled"
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bitfld.long 0x00 5. "IESPLA5,SAMPLE A5 Interrupt Mask Enable Bit\n" "0: SAMPLE A5 interrupt mask Disabled,1: SAMPLE A5 interrupt mask Enabled"
bitfld.long 0x00 4. "IESPLA4,SAMPLE A4 Interrupt Mask Enable Bit\n" "0: SAMPLE A4 interrupt mask Disabled,1: SAMPLE A4 interrupt mask Enabled"
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bitfld.long 0x00 3. "IESPLA3,SAMPLE A3 Interrupt Mask Enable Bit\n" "0: SAMPLE A3 interrupt mask Disabled,1: SAMPLE A3 interrupt mask Enabled"
bitfld.long 0x00 2. "IESPLA2,SAMPLE A2 Interrupt Mask Enable Bit\n" "0: SAMPLE A2 interrupt mask Disabled,1: SAMPLE A2 interrupt mask Enabled"
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bitfld.long 0x00 1. "IESPLA1,SAMPLE A1 Interrupt Mask Enable Bit\n" "0: SAMPLE A1 interrupt mask Disabled,1: SAMPLE A1 interrupt mask Enabled"
bitfld.long 0x00 0. "IESPLA0,SAMPLE A0 Interrupt Mask Enable Bit\n" "0: SAMPLE A0 interrupt mask Disabled,1: SAMPLE A0 interrupt mask Enabled"
group.long 0x140++0x03
line.long 0x00 "ADINT3SRCTL,A/D Interrupt 3 Source Enable Control Register"
bitfld.long 0x00 15. "IESPLB7,SAMPLE B7 Interrupt Mask Enable Bit\n" "0: SAMPLE B7 interrupt mask Disabled,1: SAMPLE B7 interrupt mask Enabled"
bitfld.long 0x00 14. "IESPLB6,SAMPLE B6 Interrupt Mask Enable Bit\n" "0: SAMPLE B6 interrupt mask Disabled,1: SAMPLE B6 interrupt mask Enabled"
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bitfld.long 0x00 13. "IESPLB5,SAMPLE B5 Interrupt Mask Enable Bit\n" "0: SAMPLE B5 interrupt mask Disabled,1: SAMPLE B5 interrupt mask Enabled"
bitfld.long 0x00 12. "IESPLB4,SAMPLE B4 Interrupt Mask Enable Bit\n" "0: SAMPLE B4 interrupt mask Disabled,1: SAMPLE B4 interrupt mask Enabled"
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bitfld.long 0x00 11. "IESPLB3,SAMPLE B3 Interrupt Mask Enable Bit\n" "0: SAMPLE B3 interrupt mask Disabled,1: SAMPLE B3 interrupt mask Enabled"
bitfld.long 0x00 10. "IESPLB2,SAMPLE B2 Interrupt Mask Enable Bit\n" "0: SAMPLE B2 interrupt mask Disabled,1: SAMPLE B2 interrupt mask Enabled"
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bitfld.long 0x00 9. "IESPLB1,SAMPLE B1 Interrupt Mask Enable Bit\n" "0: SAMPLE B1 interrupt mask Disabled,1: SAMPLE B1 interrupt mask Enabled"
bitfld.long 0x00 8. "IESPLB0,SAMPLE B0 Interrupt Mask Enable Bit\n" "0: SAMPLE B0 interrupt mask Disabled,1: SAMPLE B0 interrupt mask Enabled"
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bitfld.long 0x00 7. "IESPLA7,SAMPLE A7 Interrupt Mask Enable Bit\n" "0: SAMPLE A7 interrupt mask Disabled,1: SAMPLE A7 interrupt mask Enabled"
bitfld.long 0x00 6. "IESPLA6,SAMPLE A6 Interrupt Mask Enable Bit\n" "0: SAMPLE A6 interrupt mask Disabled,1: SAMPLE A6 interrupt mask Enabled"
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bitfld.long 0x00 5. "IESPLA5,SAMPLE A5 Interrupt Mask Enable Bit\n" "0: SAMPLE A5 interrupt mask Disabled,1: SAMPLE A5 interrupt mask Enabled"
bitfld.long 0x00 4. "IESPLA4,SAMPLE A4 Interrupt Mask Enable Bit\n" "0: SAMPLE A4 interrupt mask Disabled,1: SAMPLE A4 interrupt mask Enabled"
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bitfld.long 0x00 3. "IESPLA3,SAMPLE A3 Interrupt Mask Enable Bit\n" "0: SAMPLE A3 interrupt mask Disabled,1: SAMPLE A3 interrupt mask Enabled"
bitfld.long 0x00 2. "IESPLA2,SAMPLE A2 Interrupt Mask Enable Bit\n" "0: SAMPLE A2 interrupt mask Disabled,1: SAMPLE A2 interrupt mask Enabled"
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bitfld.long 0x00 1. "IESPLA1,SAMPLE A1 Interrupt Mask Enable Bit\n" "0: SAMPLE A1 interrupt mask Disabled,1: SAMPLE A1 interrupt mask Enabled"
bitfld.long 0x00 0. "IESPLA0,SAMPLE A0 Interrupt Mask Enable Bit\n" "0: SAMPLE A0 interrupt mask Disabled,1: SAMPLE A0 interrupt mask Enabled"
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x144)++0x03
line.long 0x00 "SMPTRGA$1,A/D Trigger Condition for SAMPLEA $1"
bitfld.long 0x00 31. "PWM21CEN,BPWM0_CH1 Center Trigger Enable Bit\n" "0: BPWM0_CH1 center trigger Disabled,1: BPWM0_CH1 center trigger Enabled"
bitfld.long 0x00 30. "PWM21PEN,BPWM0_CH1 Period Trigger Enable Bit\n" "0: BPWM0_CH1 period trigger Disabled,1: BPWM0_CH1 period trigger Enabled"
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bitfld.long 0x00 29. "PWM21FEN,BPWM0_CH1 Falling Edge Trigger Enable Bit\n" "0: BPWM0_CH1 falling edge trigger Disabled,1: BPWM0_CH1 falling edge trigger Enabled"
bitfld.long 0x00 28. "PWM21REN,BPWM0_CH1 Rising Edge Trigger Enable Bit\n" "0: BPWM0_CH1 rising edge trigger Disabled,1: BPWM0_CH1 rising edge trigger Enabled"
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bitfld.long 0x00 27. "PWM20CEN,BPWM0_CH0 Center Trigger Enable Bit\n" "0: BPWM0_CH0 center trigger Disabled,1: BPWM0_CH0 center trigger Enabled"
bitfld.long 0x00 26. "PWM20PEN,BPWM0_CH0 Period Trigger Enable Bit\n" "0: BPWM0_CH0 period trigger Disabled,1: BPWM0_CH0 period trigger Enabled"
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bitfld.long 0x00 25. "PWM20FEN,BPWM0_CH0 Falling Edge Trigger Enable Bit\n" "0: BPWM0_CH0 falling edge trigger Disabled,1: BPWM0_CH0 falling edge trigger Enabled"
bitfld.long 0x00 24. "PWM20REN,BPWM0_CH0 Rising Edge Trigger Enable Bit\n" "0: BPWM0_CH0 rising edge trigger Disabled,1: BPWM0_CH0 rising edge trigger Enabled"
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bitfld.long 0x00 23. "PWM14CEN,PWM1_CH4 Center Trigger Enable Bit\n" "0: PWM1_CH4 center trigger Disabled,1: PWM1_CH4 center trigger Enabled"
bitfld.long 0x00 22. "PWM14PEN,PWM1_CH4 Period Trigger Enable Bit\n" "0: PWM1_CH4 period trigger Disabled,1: PWM1_CH4 period trigger Enabled"
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bitfld.long 0x00 21. "PWM14FEN,PWM1_CH4 Falling Edge Trigger Enable Bit\n" "0: PWM1_CH4 falling edge trigger Disabled,1: PWM1_CH4 falling edge trigger Enabled"
bitfld.long 0x00 20. "PWM14REN,PWM1_CH4 Rising Edge Trigger Enable Bit\n" "0: PWM1_CH4 rising edge trigger Disabled,1: PWM1_CH4 rising edge trigger Enabled"
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bitfld.long 0x00 19. "PWM12CEN,PWM1_CH2 Center Trigger Enable Bit\n" "0: PWM1_CH2 center trigger Disabled,1: PWM1_CH2 center trigger Enabled"
bitfld.long 0x00 18. "PWM12PEN,PWM1_CH2 Period Trigger Enable Bit\n" "0: PWM1_CH2 period trigger Disabled,1: PWM1_CH2 period trigger Enabled"
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bitfld.long 0x00 17. "PWM12FEN,PWM1_CH2 Falling Edge Trigger Enable Bit\n" "0: PWM1_CH2 falling edge trigger Disabled,1: PWM1_CH2 falling edge trigger Enabled"
bitfld.long 0x00 16. "PWM12REN,PWM1_CH2 Rising Edge Trigger Enable Bit\n" "0: PWM1_CH2 rising edge trigger Disabled,1: PWM1_CH2 rising edge trigger Enabled"
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bitfld.long 0x00 15. "PWM10CEN,PWM1_CH0 Center Trigger Enable Bit\n" "0: PWM1_CH0 center trigger Disabled,1: PWM1_CH0 center trigger Enabled"
bitfld.long 0x00 14. "PWM10PEN,PWM1_CH0 Period Trigger Enable Bit\n" "0: PWM1_CH0 period trigger Disabled,1: PWM1_CH0 period trigger Enabled"
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bitfld.long 0x00 13. "PWM10FEN,PWM1_CH0 Falling Edge Trigger Enable Bit\n" "0: PWM1_CH0 falling edge trigger Disabled,1: PWM1_CH0 falling edge trigger Enabled"
bitfld.long 0x00 12. "PWM10REN,PWM1_CH0 Rising Edge Trigger Enable Bit\n" "0: PWM1_CH0 rising edge trigger Disabled,1: PWM1_CH0 rising edge trigger Enabled"
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bitfld.long 0x00 11. "PWM04CEN,PWM0_CH4 Center Trigger Enable Bit\n" "0: PWM0_CH4 center trigger Disabled,1: PWM0_CH4 center trigger Enabled"
bitfld.long 0x00 10. "PWM04PEN,PWM0_CH4 Period Trigger Enable Bit\n" "0: PWM0_CH4 period trigger Disabled,1: PWM0_CH4 period trigger Enabled"
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bitfld.long 0x00 9. "PWM04FEN,PWM0_CH4 Falling Rdge Trigger Enable Bit\n" "0: PWM0_CH4 falling edge trigger Disabled,1: PWM0_CH4 falling edge trigger Enabled"
bitfld.long 0x00 8. "PWM04REN,PWM0_CH4 Rising Edge Trigger Enable Bit\n" "0: PWM0_CH4 rising edge trigger Disabled,1: PWM0_CH4 rising edge trigger Enabled"
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bitfld.long 0x00 7. "PWM02CEN,PWM0_CH2 Center Trigger Enable Bit\n" "0: PWM0_CH2 center trigger Disabled,1: PWM0_CH2 center trigger Enabled"
bitfld.long 0x00 6. "PWM02PEN,PWM0_CH2 Period Trigger Enable Bit\n" "0: PWM0_CH2 period trigger Disabled,1: PWM0_CH2 period trigger Enabled"
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bitfld.long 0x00 5. "PWM02FEN,PWM0_CH2 Falling Edge Trigger Enable Bit\n" "0: PWM0_CH2 falling edge trigger Disabled,1: PWM0_CH2 falling edge trigger Enabled"
bitfld.long 0x00 4. "PWM02REN,PWM0_CH2 Rising Edge Trigger Enable Bit\n" "0: PWM0_CH2 rising edge trigger Disabled,1: PWM0_CH2 rising edge trigger Enabled"
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bitfld.long 0x00 3. "PWM00CEN,PWM0_CH0 Center Trigger Enable Bit\n" "0: PWM0_CH0 center trigger Disabled,1: PWM0_CH0 center trigger Enabled"
bitfld.long 0x00 2. "PWM00PEN,PWM0_CH0 Period Trigger Enable Bit\n" "0: PWM0_CH0 period trigger Disabled,1: PWM0_CH0 period trigger Enabled"
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bitfld.long 0x00 1. "PWM00FEN,PWM0_CH0 Falling Edge Trigger Enable Bit\n" "0: PWM0_CH0 falling edge trigger Disabled,1: PWM0_CH0 falling edge trigger Enabled"
bitfld.long 0x00 0. "PWM00REN,PWM0_CH0 Rising Edge Trigger Enable Bit\n" "0: PWM0_CH0 rising edge trigger Disabled,1: PWM0_CH0 rising edge trigger Enabled"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x154)++0x03
line.long 0x00 "SMPTRGB$1,A/D Trigger Condition for SAMPLEB $1"
bitfld.long 0x00 31. "PWM21CEN,BPWM0_CH1 Center Trigger Enable Bit\n" "0: BPWM0_CH1 center trigger Disabled,1: BPWM0_CH1 center trigger Enabled"
bitfld.long 0x00 30. "PWM21PEN,BPWM0_CH1 Period Trigger Enable Bit\n" "0: BPWM0_CH1 period trigger Disabled,1: BPWM0_CH1 period trigger Enabled"
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bitfld.long 0x00 29. "PWM21FEN,BPWM0_CH1 Falling Edge Trigger Enable Bit\n" "0: BPWM0_CH1 falling edge trigger Disabled,1: BPWM0_CH1 falling edge trigger Enabled"
bitfld.long 0x00 28. "PWM21REN,BPWM0_CH1 Rising Edge Trigger Enable Bit\n" "0: BPWM0_CH1 rising edge trigger Disabled,1: BPWM0_CH1 rising edge trigger Enabled"
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bitfld.long 0x00 27. "PWM20CEN,BPWM0_CH0 Center Trigger Enable Bit\n" "0: BPWM0_CH0 center trigger Disabled,1: BPWM0_CH0 center trigger Enabled"
bitfld.long 0x00 26. "PWM20PEN,BPWM0_CH0 Period Trigger Enable Bit\n" "0: BPWM0_CH0 period trigger Disabled,1: BPWM0_CH0 period trigger Enabled"
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bitfld.long 0x00 25. "PWM20FEN,BPWM0_CH0 Falling Edge Trigger Enable Bit\n" "0: BPWM0_CH0 falling edge trigger Disabled,1: BPWM0_CH0 falling edge trigger Enabled"
bitfld.long 0x00 24. "PWM20REN,BPWM0_CH0 Rising Edge Trigger Enable Bit\n" "0: BPWM0_CH0 rising edge trigger Disabled,1: BPWM0_CH0 rising edge trigger Enabled"
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bitfld.long 0x00 23. "PWM14CEN,PWM1_CH4 Center Trigger Enable Bit\n" "0: PWM1_CH4 center trigger Disabled,1: PWM1_CH4 center trigger Enabled"
bitfld.long 0x00 22. "PWM14PEN,PWM1_CH4 Period Trigger Enable Bit\n" "0: PWM1_CH4 period trigger Disabled,1: PWM1_CH4 period trigger Enabled"
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bitfld.long 0x00 21. "PWM14FEN,PWM1_CH4 Falling Edge Trigger Enable Bit\n" "0: PWM1_CH4 falling edge trigger Disabled,1: PWM1_CH4 falling edge trigger Enabled"
bitfld.long 0x00 20. "PWM14REN,PWM1_CH4 Rising Edge Trigger Enable Bit\n" "0: PWM1_CH4 rising edge trigger Disabled,1: PWM1_CH4 rising edge trigger Enabled"
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bitfld.long 0x00 19. "PWM12CEN,PWM1_CH2 Center Trigger Enable Bit\n" "0: PWM1_CH2 center trigger Disabled,1: PWM1_CH2 center trigger Enabled"
bitfld.long 0x00 18. "PWM12PEN,PWM1_CH2 Period Trigger Enable Bit\n" "0: PWM1_CH2 period trigger Disabled,1: PWM1_CH2 period trigger Enabled"
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bitfld.long 0x00 17. "PWM12FEN,PWM1_CH2 Falling Edge Trigger Enable Bit\n" "0: PWM1_CH2 falling edge trigger Disabled,1: PWM1_CH2 falling edge trigger Enabled"
bitfld.long 0x00 16. "PWM12REN,PWM1_CH2 Rising Edge Trigger Enable Bit\n" "0: PWM1_CH2 rising edge trigger Disabled,1: PWM1_CH2 rising edge trigger Enabled"
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bitfld.long 0x00 15. "PWM10CEN,PWM1_CH0 Center Trigger Enable Bit\n" "0: PWM1_CH0 center trigger Disabled,1: PWM1_CH0 center trigger Enabled"
bitfld.long 0x00 14. "PWM10PEN,PWM1_CH0 Period Trigger Enable Bit\n" "0: PWM1_CH0 period trigger Disabled,1: PWM1_CH0 period trigger Enabled"
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bitfld.long 0x00 13. "PWM10FEN,PWM1_CH0 Falling Edge Trigger Enable Bit\n" "0: PWM1_CH0 falling edge trigger Disabled,1: PWM1_CH0 falling edge trigger Enabled"
bitfld.long 0x00 12. "PWM10REN,PWM1_CH0 Rising Edge Trigger Enable Bit\n" "0: PWM1_CH0 rising edge trigger Disabled,1: PWM1_CH0 rising edge trigger Enabled"
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bitfld.long 0x00 11. "PWM04CEN,PWM0_CH4 Center Trigger Enable Bit\n" "0: PWM0_CH4 center trigger Disabled,1: PWM0_CH4 center trigger Enabled"
bitfld.long 0x00 10. "PWM04PEN,PWM0_CH4 Period Trigger Enable Bit\n" "0: PWM0_CH4 period trigger Disabled,1: PWM0_CH4 period trigger Enabled"
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bitfld.long 0x00 9. "PWM04FEN,PWM0_CH4 Falling Rdge Trigger Enable Bit\n" "0: PWM0_CH4 falling edge trigger Disabled,1: PWM0_CH4 falling edge trigger Enabled"
bitfld.long 0x00 8. "PWM04REN,PWM0_CH4 Rising Edge Trigger Enable Bit\n" "0: PWM0_CH4 rising edge trigger Disabled,1: PWM0_CH4 rising edge trigger Enabled"
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bitfld.long 0x00 7. "PWM02CEN,PWM0_CH2 Center Trigger Enable Bit\n" "0: PWM0_CH2 center trigger Disabled,1: PWM0_CH2 center trigger Enabled"
bitfld.long 0x00 6. "PWM02PEN,PWM0_CH2 Period Trigger Enable Bit\n" "0: PWM0_CH2 period trigger Disabled,1: PWM0_CH2 period trigger Enabled"
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bitfld.long 0x00 5. "PWM02FEN,PWM0_CH2 Falling Edge Trigger Enable Bit\n" "0: PWM0_CH2 falling edge trigger Disabled,1: PWM0_CH2 falling edge trigger Enabled"
bitfld.long 0x00 4. "PWM02REN,PWM0_CH2 Rising Edge Trigger Enable Bit\n" "0: PWM0_CH2 rising edge trigger Disabled,1: PWM0_CH2 rising edge trigger Enabled"
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bitfld.long 0x00 3. "PWM00CEN,PWM0_CH0 Center Trigger Enable Bit\n" "0: PWM0_CH0 center trigger Disabled,1: PWM0_CH0 center trigger Enabled"
bitfld.long 0x00 2. "PWM00PEN,PWM0_CH0 Period Trigger Enable Bit\n" "0: PWM0_CH0 period trigger Disabled,1: PWM0_CH0 period trigger Enabled"
newline
bitfld.long 0x00 1. "PWM00FEN,PWM0_CH0 Falling Edge Trigger Enable Bit\n" "0: PWM0_CH0 falling edge trigger Disabled,1: PWM0_CH0 falling edge trigger Enabled"
bitfld.long 0x00 0. "PWM00REN,PWM0_CH0 Rising Edge Trigger Enable Bit\n" "0: PWM0_CH0 rising edge trigger Disabled,1: PWM0_CH0 rising edge trigger Enabled"
repeat.end
tree.end
tree "ECAP"
repeat 2. (list 0. 1.) (list ad:0x401B0000 ad:0x401B4000)
tree "ECAP$1"
base $2
group.long 0x00++0x03
line.long 0x00 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
hexmask.long.tbyte 0x00 0.--23. 1. "VAL,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter"
repeat 3. (strings "0" "1" "2" )(list 0x0 0x4 0x8 )
group.long ($2+0x04)++0x03
line.long 0x00 "ECAP_HOLD$1,Input Capture Counter Hold Register $1"
hexmask.long.tbyte 0x00 0.--23. 1. "VAL,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAP_CNT value is latched into the corresponding holding register"
repeat.end
group.long 0x10++0x03
line.long 0x00 "ECAP_CNTCMP,Input Capture Counter Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "VAL,Input Capture Counter Compare Register\n"
group.long 0x14++0x03
line.long 0x00 "ECAP_CTL0,Input Capture Control Register 0"
bitfld.long 0x00 29. "CAPEN,Input Capture Timer/Counter Enable Bit\n" "0: Input Capture function Disabled,1: Input Capture function Enabled"
bitfld.long 0x00 28. "CMPEN,Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CMPF will be set" "0: The compare function Disabled,1: The compare function Enabled"
newline
bitfld.long 0x00 27. "RLDEN,Reload Function Enable Bit \nSetting this bit to enable the reload function" "0: The reload function Disabled,1: The reload function Enabled"
bitfld.long 0x00 26. "CPTCLR,Input Capture Counter Cleared by Capture Events Control\nIf this bit is set to 1 the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs" "0: Capture events (CAPF0~3) can clear capture..,1: Capture events (CAPF0~3) can clear capture.."
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bitfld.long 0x00 25. "CMPCLR,Input Capture Counter Cleared by Compare-match Control\n" "0: Compare-match event (CAMCMPF) can clear..,1: Compare-match event (CAMCMPF) can clear.."
bitfld.long 0x00 24. "CNTEN,Input Capture Counter Start\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK)" "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
newline
bitfld.long 0x00 21. "CMPIEN,CMPF Trigger Input Capture Interrupt Enable Bit\n" "0: The flag CMPF can trigger Input Capture..,1: The flag CMPF can trigger Input Capture.."
bitfld.long 0x00 20. "OVIEN,OVF Trigger Input Capture Interrupt Enable Bit\n" "0: The flag OVUNF can trigger Input Capture..,1: The flag OVUNF can trigger Input Capture.."
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bitfld.long 0x00 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Bit\n" "0: The flag CAPF2 can trigger Input Capture..,1: The flag CAPF2 can trigger Input Capture.."
bitfld.long 0x00 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Bit\n" "0: The flag CAPF1 can trigger Input Capture..,1: The flag CAPF1 can trigger Input Capture.."
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bitfld.long 0x00 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Bit\n" "0: The flag CAPF0 can trigger Input Capture..,1: The flag CAPF0 can trigger Input Capture.."
bitfld.long 0x00 12.--13. "CAPSEL2,CAP2 Input Source Selection\n" "0: CAP2 input is from pin RCAPx_IC2,1: CAP2 input is from CO2 (ACMPSR[10]),2: Reserved,3: CAP2 input is from signal ADCMPOx (ADC.."
newline
bitfld.long 0x00 10.--11. "CAPSEL1,CAP1 Input Source Selection\n" "0: CAP1 input is from pin ECAPx_IC1,1: CAP1 input is from CO1 (ACMPSR[9]),2: Reserved,3: CAP1 input is from OPDO1 (OPASR[1])"
bitfld.long 0x00 8.--9. "CAPSEL0,CAP0 Input Source Selection\n" "0: CAP0 input is from pin ECAPx_IC0,1: CAP0 input is from CO0 (ACMPSR[8]),2: Reserved,3: CAP0 input is from OPDO0 (OPASR[0])"
newline
bitfld.long 0x00 6. "CAPEN2,Pin ECAPx_IC2 Input to Input Capture Unit Enable Bit\n" "0: ECAPx_IC2 input to Input Capture Unit Disabled,1: ECAPx_IC2 input to Input Capture Unit Enabled"
bitfld.long 0x00 5. "CAPEN1,Pin ECAPx_IC1 Input to Input Capture Unit Enable Bit\n" "0: ECAPx_IC1 input to Input Capture Unit Disabled,1: ECAPx_IC1 input to Input Capture Unit Enabled"
newline
bitfld.long 0x00 4. "CAPEN0,Pin ECAPx_IC0 Input to Input Capture Unit Enable Bit\n" "0: ECAPx_IC0 input to Input Capture Unit Disabled,1: ECAPx_IC0 input to Input Capture Unit Enabled"
bitfld.long 0x00 3. "CAPNF_DIS,Input Capture Noise Filter Disable Bit\n" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled"
newline
bitfld.long 0x00 0.--1. "NFDIS,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock \n" "0: CAP_CLK,1: CAP_CLK/2,2: CAP_CLK/4,3: CAP_CLK/16"
group.long 0x18++0x03
line.long 0x00 "ECAP_CTL1,Input Capture Control Register 1"
bitfld.long 0x00 16.--17. "SRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source.\n" "0: CAP_CLK (default),1: CAP0,2: CAP1,3: CAP2"
bitfld.long 0x00 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[1:0].\n" "0: CAP_CLK/1,1: CAP_CLK/4,2: CAP_CLK/16,3: CAP_CLK/32,4: CAP_CLK/64,5: CAP_CLK/96,6: CAP_CLK/112,7: CAP_CLK/128"
newline
bitfld.long 0x00 8.--10. "RLDSEL,ECAP_CNT Reload Trigger Source Selection\n" "0: CAPF0,1: CAPF1,2: CAPF2,?,4: OVF,?..."
bitfld.long 0x00 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture can detect falling edge change or rising edge change only or one of both edge changes" "0: Detect rising edge,1: Detect falling edge.\nDetect either rising or..,?..."
newline
bitfld.long 0x00 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only rising edge change only or one of both edge change \n" "0: Detect rising edge,1: Detect falling edge.\nDetect either rising or..,?..."
bitfld.long 0x00 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only rising edge change only or one of both edge change \n" "0: Detect rising edge,1: Detect falling edge.\nDetect either rising or..,?..."
group.long 0x1C++0x03
line.long 0x00 "ECAP_STATUS,Input Capture Status Register"
bitfld.long 0x00 5. "OVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it" "0: No overflow occurs in ECAP_CNT,1: ECAP_CNT overflows"
bitfld.long 0x00 4. "CMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it" "0: ECAP_CNT does not match with ECAP_CNTCMP value,1: ECAP_CNT counts to the same as ECAP_CNTCMP.."
newline
bitfld.long 0x00 2. "CAPF2,Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPF2 to high" "0: No valid edge change is detected at CAP2 input,1: A valid edge change is detected at CAP2 input"
bitfld.long 0x00 1. "CAPF1,Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPF1 to high" "0: No valid edge change is detected at CAP1 input,1: A valid edge change is detected at CAP1 input"
newline
bitfld.long 0x00 0. "CAPF0,Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPF0 to high" "0: No valid edge change is detected at CAP0 input,1: A valid edge change is detected at CAP0 input"
tree.end
repeat.end
tree.end
tree "EPWM"
repeat 2. (list 0. 1.) (list ad:0x40190000 ad:0x40194000)
tree "EPWM$1"
base $2
group.long 0x00++0x03
line.long 0x00 "PWMCON,EPWM Control Register"
bitfld.long 0x00 31. "CLDMD,Center Reload Mode Enable Bit\nThis bit only works when EPWM operating in Center-aligned mode" "0: EPWM reload duty register at the period point..,1: EPWM reload duty register at the center point.."
bitfld.long 0x00 29. "BK1NF_DIS,PWM Brake 1 Noise Filter Disable Bit\n" "0: Noise filter of PWM Brake 1 Enabled,1: Noise filter of PWM Brake 1 Disabled"
newline
bitfld.long 0x00 28. "BK0NF_DIS,PWM Brake 0 Noise Filter Disable Bit\n" "0: Noise filter of PWM Brake 0 Enabled,1: Noise filter of PWM Brake 0 Disabled"
bitfld.long 0x00 27. "LVDBK_EN,Low-level Detection Trigger PWM Brake Function 1 Enable Bit\n" "0: Brake Function 1 triggered by Low-level..,1: Brake Function 1 triggered by Low-level.."
newline
bitfld.long 0x00 26. "CPO2BK_EN,ACMP2 Digital Output As Brake 0 Source Enable Bit\n" "0: CO2 (ACMPSR[10]) as one brake source in Brake..,1: CO2 (ACMPSR[10]) as one brake source in Brake.."
bitfld.long 0x00 25. "CPO1BK_EN,ACMP1 Digital Output As Brake 0 Source Enable Bit\n" "0: CO1 (ACMPSR[9]) as one brake source in Brake..,1: CO1 (ACMPSR[9]) as one brake source in Brake.."
newline
bitfld.long 0x00 24. "CPO0BK_EN,ACMP0 Digital Output As Brake0 Source Enable Bit\n" "0: CO0 (ACMPSR[8]) as one brake source in Brake..,1: CO0 (ACMPSR[8]) as one brake source in Brake.."
bitfld.long 0x00 22.--23. "BK1FILT,Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n" "0: filter clock is HCLK,1: filter clock is HCLK/2,2: filter clock is HCLK/4,3: filter clock is HCLK/16"
newline
bitfld.long 0x00 20.--21. "BK0FILT,Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n" "0: filter clock is HCLK,1: filter clock is HCLK/2,2: filter clock is HCLK/4,3: filter clock is HCLK/16"
bitfld.long 0x00 18.--19. "BK1SEL,Brake Function 1 Source Selection\n" "0: brake signal is from external pin..,1: brake signal is from analog comparator 0..,2: brake signal is from analog comparator 1..,3: brake signal is from analog comparator 2.."
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bitfld.long 0x00 17. "BKEN1,BRAKE1 Pin Trigger Brake Function 1 Enable Bit\n" "0: PWMx brake function 1 Disabled,1: PWMx brake function 1 Enabled"
bitfld.long 0x00 16. "BKEN0,BRAKE0 Pin Trigger Brake Function 0 Enable Bit\n" "0: PWMx brake function 0 Disabled,1: PWMx brake function 0 Enabled"
newline
bitfld.long 0x00 15. "INVBKP1,Inverse Brake 1 Pin State\n" "0: The state of pin EPWMx_BRAKE1 is passed to..,1: The inversed state of pin EPWMx_BRAKE1 is.."
bitfld.long 0x00 14. "INVBKP0,Inverse Brake 0 Pin State\n" "0: The state of pin EPWMx_BRAKE0 is passed to..,1: The inversed state of pin EPWMx_BRAKE0 is.."
newline
bitfld.long 0x00 13. "GRP,Group Bit\n" "0: The signals timing of PWM_CH0 PWM_CH2 and..,1: Unify the signals timing of PWM_CH0 PWM_CH2.."
bitfld.long 0x00 12. "PWMTYPE,PWM Aligned Type Selection Bit\n" "0: Edge-aligned type,1: Center-aligned type"
newline
bitfld.long 0x00 11. "CLRPWM,Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware" "0: Ignored,1: Clear 16-bit PWM counter to 0000H"
bitfld.long 0x00 9. "PWMINV,Inverse PWM Comparator Output\nWhen PWMINV is set to high the PWM comparator output signals will be inversed therefore the PWM Duty (in percentage) is changed to (1-Duty) before PWMINV is set to high.\n" "0: Not inverse PWM comparator output,1: Inverse PWM comparator output"
newline
bitfld.long 0x00 8. "INT_TYPE,PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM is in Center-aligned mode only" "0: PWMF will be set if PWM counter underflow,1: PWMF will be set if PWM counter matches PWMP.."
bitfld.long 0x00 7. "PWMRUN,Start PWMRUN Control Bit\n" "0: The PWM stops running,1: The PWM counter starts running"
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bitfld.long 0x00 6. "LOAD,Reload PWM Period Registers (PWMP) and PWM Duty Registers (PWM0~4) Control Bit\nNote: This bit is written by software cleared by hardware and always read as 0" "0: No action if written with 0,1: Hardware will update the value of PWM period.."
bitfld.long 0x00 5. "BRKI_EN,Brake0 and Brak1 Interrupt Enable Bit\n" "0: Flags BKF0 (PWMSTS[0]) and BKF1 (PWMSTS[1])..,1: Flags BKF0 (PWMSTS[0]) and BKF1 (PWMSTS[1]).."
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bitfld.long 0x00 4. "PWMI_EN,PWM Interrupt Enable Bit\n" "0: Flag PWMF (PWMSTS[2]) Disabled to trigger PWM..,1: Flag PWMF (PWMSTS[2]) Enabled to trigger PWM.."
bitfld.long 0x00 2.--3. "PWMDIV,PWM Clock Pre-divider Selection\n" "0: PWM clock is EPWMx_CLK,1: PWM clock is EPWMx_CLK/2,2: PWM clock is EPWMx_CLK/4,3: PWM clock is EPWMx_CLK/16"
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bitfld.long 0x00 0.--1. "PWMMOD,PWM Mode Selection\n" "0: PWM mode is independent mode,1: PWM mode is pair/complementary mode,2: PWM mode is synchronized mode,3: Reserved"
group.long 0x04++0x03
line.long 0x00 "PWMSTS,EPWM Status Register"
rbitfld.long 0x00 25. "BK1STS,Brake 1 Status (Read Only)\n" "0: PWM had been out of Brake 1 state,1: PWM is in Brake 1 state"
rbitfld.long 0x00 24. "BK0STS,Brake 0 Status (Read Only)\n" "0: PWM had been out of Brake 0 state,1: PWM is in Brake 0 state"
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bitfld.long 0x00 8. "BKLK0,PWM Brake 0 Locked \nNote: This bit must be cleared by writing 1 to itself through software" "0: Brake 0 state is released,1: When PWM Brake detects a falling signal at.."
bitfld.long 0x00 6. "PWM4EF,PWM Channel 4 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software" "0: PWM_CH4 not toggled,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 5. "PWM2EF,PWM Channel 2 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software" "0: PWM_CH2 not toggled,1: Hardware will set this flag to high at the.."
bitfld.long 0x00 4. "PWM0EF,PWM Channel 0 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software" "0: PWM_CH0 not toggled,1: Hardware will set this flag to high at the.."
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bitfld.long 0x00 2. "PWMF,PWM Period Flag\nNote: This bit must be cleared by writing 1 to itself through software" "0: The PWM Counter has not up counted to the..,1: Hardware will set this flag to high at the.."
bitfld.long 0x00 1. "BKF1,PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to itself through software" "0: PWM Brake 1 is able to poll falling signal at..,1: When PWM Brake 1 detects a falling signal at.."
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bitfld.long 0x00 0. "BKF0,PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to itself through software" "0: PWM Brake 0 is able to poll falling signal at..,1: When PWM Brake 0 detects a falling signal at.."
group.long 0x08++0x03
line.long 0x00 "PWMP,EPWM Period Register"
hexmask.long.word 0x00 0.--15. 1. "PWMP,PWM Period Register\nEdge-aligned:\n"
group.long 0x0C++0x03
line.long 0x00 "PWM0,EPWM PWM0 Duty Register"
hexmask.long.word 0x00 0.--15. 1. "PWM_Duty,PWM Duty Register\nEdge-aligned:\n"
group.long 0x10++0x03
line.long 0x00 "PWM2,EPWM PWM2 Duty Register"
hexmask.long.word 0x00 0.--15. 1. "PWM_Duty,PWM Duty Register\nEdge-aligned:\n"
group.long 0x14++0x03
line.long 0x00 "PWM4,EPWM PWM4 Duty Register"
hexmask.long.word 0x00 0.--15. 1. "PWM_Duty,PWM Duty Register\nEdge-aligned:\n"
group.long 0x18++0x03
line.long 0x00 "PMSKE,EPWM Mask Mode Enable Register"
bitfld.long 0x00 0.--5. "PMSKE,PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled" "0: PWM generator signal is output to next stage,1: PWM generator signal is masked and PMSKD[n]..,?..."
group.long 0x1C++0x03
line.long 0x00 "PMSKD,EPWM Mask Mode Data Register"
bitfld.long 0x00 0.--5. "PMSKD,PWM Mask Data Bit\n" "0: Output logic low to PWM_CHn,1: Output logic high to PWM_CHn,?..."
group.long 0x2C++0x03
line.long 0x00 "PDTC,EPWM Dead-time Control Register"
bitfld.long 0x00 18. "DTEN4,Enable Dead-time Insertion for PWMx Pair (PWM_CH4 PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
bitfld.long 0x00 17. "DTEN2,Enable Dead-time Insertion for PWMx Pair (PWM_CH2 PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
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bitfld.long 0x00 16. "DTEN0,Enable Dead-time Insertion for PWMx Pair (PWM_CH0 PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair..,1: Dead-time insertion Enabled on the pin pair.."
hexmask.long.word 0x00 0.--10. 1. "DTCNT,Dead-time Counter\nThe dead-time can be calculated according to the following formula: \n"
group.long 0x30++0x03
line.long 0x00 "PWMB,EPWM Brake Output Register"
bitfld.long 0x00 0.--5. "PWMB,PWM Brake Output\n" "0: PWM_CHn output before polarity control is low..,1: PWM_CHn output before polarity control is..,?..."
group.long 0x34++0x03
line.long 0x00 "PNPC,EPWM Negative Polarity Control Register"
bitfld.long 0x00 0.--5. "PNP,PWM Negative Polarity Control\n" "0: PWM_CHn output is active high,1: PWM_CHn output is active low,?..."
group.long 0x3C++0x03
line.long 0x00 "PWMFCNT,EPWMF Compared Counter Register"
bitfld.long 0x00 0.--3. "PWMFCNT,PWMF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PWMF (PWMSTS[2]) to request the PWM period interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "PWMEIC,EPWM Edge Interrupt Control Register"
bitfld.long 0x00 10. "EINT4_TYPE,PWM Channel 4 Edge Interrupt Type\n" "0: PWM4EF will be set if falling edge is..,1: PWM4EF will be set if rising edge is detected.."
bitfld.long 0x00 9. "EINT2_TYPE,PWM Channel 2 Edge Interrupt Type\n" "0: PWM2EF will be set if falling edge is..,1: PWM2EF will be set if rising edge is detected.."
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bitfld.long 0x00 8. "EINT0_TYPE,PWM Channel 0 Edge Interrupt Type\n" "0: PWM0EF will be set if falling edge is..,1: PWM0EF will be set if rising edge is detected.."
bitfld.long 0x00 2. "PWM4EI_EN,Enable PWM Channel 4 Edge Interrupt\n" "0: Flag PWM4EF Disabled to trigger PWM interrupt,1: Flag PWM4EF Enabled to trigger PWM interrupt"
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bitfld.long 0x00 1. "PWM2EI_EN,Enable PWM Channel 2 Edge Interrupt\n" "0: Flag PWM2EF Disabled to trigger PWM interrupt,1: Flag PWM2EF Enabled to trigger PWM interrupt"
bitfld.long 0x00 0. "PWM0EI_EN,Enable PWM Channel 0 Edge Interrupt\n" "0: Flag PWM0EF Disabled to trigger PWM interrupt,1: Flag PWM0EF Enabled to trigger PWM interrupt"
tree.end
repeat.end
tree.end
tree "FMC"
base ad:0x5000C000
group.long 0x00++0x03
line.long 0x00 "ISPCON,ISP Control Register"
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is.." "0,1"
bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\n" "0: LDROM cannot be updated,1: LDROM can be updated when chip runs in APROM"
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bitfld.long 0x00 4. "CFGUEN,Config-bits Update Enable Bit (Write Protect)\n" "0: User Configuration cannot be updated,1: User Configuration can be updated"
bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\n" "0: APROM cannot be updated when chip runs in APROM,1: APROM can be updated when chip runs in APROM"
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bitfld.long 0x00 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: Boot from APROM,1: Boot from LDROM"
bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
group.long 0x04++0x03
line.long 0x00 "ISPADR,ISP Address Register"
hexmask.long 0x00 0.--31. 1. "ISPADR,ISP Address\nThe NuMicro M0519 Series has a maximum 32Kx32 (128 KB) of embedded Flash which supports word program only"
group.long 0x08++0x03
line.long 0x00 "ISPDAT,ISP Data Register"
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation"
group.long 0x0C++0x03
line.long 0x00 "ISPCMD,ISP Command Register"
bitfld.long 0x00 0.--5. "CMD,ISP Command\nISP command table is shown below:\nThe other commands are invalid" "0: FLASH,?,?,?,4: Read Unique ID,?,?,?,?,?,?,11: Read Company ID,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,33: FLASH Program,34: FLASH Page Erase,?,?,?,?,?,?,?,?,?,?,?,46: Vector Remap,?..."
group.long 0x10++0x03
line.long 0x00 "ISPTRG,ISP Trigger Control Register"
bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit It means programming this bit needs to write 59h 16h 88h.." "0: ISP operation finished,1: ISP progressed"
rgroup.long 0x14++0x03
line.long 0x00 "DFBADR,Data Flash Base Address"
hexmask.long 0x00 0.--31. 1. "DFBADR,Data Flash Base Address\nThis register indicates data flash start address"
group.long 0x18++0x03
line.long 0x00 "FATCON,Flash Access Time Control Register"
bitfld.long 0x00 6. "FOM_SEL1,Chip Frequency Optimization Mode Select (Write Protect)\n" "0,1"
bitfld.long 0x00 4. "FOM_SEL0,Chip Frequency Optimization Mode Select (Write Protect)\n" "0,1"
group.long 0x40++0x03
line.long 0x00 "ISPSTA,ISP Status Register"
hexmask.long.word 0x00 9.--20. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0] 9'h000} ~ {VECMAP[11:0] 9'h1FF}\nNote: vector map function only workable when IAP mode enabled"
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (ISPCON[6]) it needs to be cleared by writing 1 to ISPCON[6] or FMC_ISPSTA[6]" "0,1"
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rbitfld.long 0x00 1.--2. "CBS,Chip Boot Selection of CONFIG (Read Only)\n" "0: Boot from LDROM with IAP mode,1: Boot from LDROM without IAP mode,2: Boot from APROM with IAP mode,3: Boot from APROM without IAP mode"
rbitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with ISPTRG bit0" "0: ISP operation finished,1: ISP operation progressed"
tree.end
tree "GCR"
base ad:0x50000000
rgroup.long 0x00++0x03
line.long 0x00 "PDID,Part Device Identification Number Register"
hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number\nThis register reflects device part number code"
group.long 0x04++0x03
line.long 0x00 "RSTSRC,System Reset Source Register"
bitfld.long 0x00 7. "RSTS_CPU,CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0" "0: No reset from CPU,1: Cortex-M0 CPU kernel and FMC are reset by.."
bitfld.long 0x00 5. "RSTS_SYS,SYS Reset Flag\nThe RSTS_SYS flag is set by the Reset Signal from the Cortex-M0 kernel to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
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bitfld.long 0x00 4. "RSTS_BOD,Brown-out Detector Reset Flag\nThe RSTS_BOD flag is set by the Reset Signal from the Brown-out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.."
bitfld.long 0x00 3. "RSTS_LVR,Low Voltage Reset Flag\nThe RSTS_LVR flag is set by the Reset Signal from the Low-Voltage-Reset controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: The LVR controller had issued the reset.."
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bitfld.long 0x00 2. "RSTS_WDT,Watchdog Timer Reset Flag\nThe RSTS_WDT flag is set by the Reset Signal from the watchdog timer or window watchdog timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register.." "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
bitfld.long 0x00 1. "RSTS_RESET,Reset Pin Reset Flag\nThe RSTS_RESET flag is set by the Reset Signal from the nRESET pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from the nRESET pin,1: The nRESET pin had issued the reset signal to.."
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bitfld.long 0x00 0. "RSTS_POR,Power-on Reset Flag\nThe RSTS_POR flag is set by the Reset Signal from the Power-on Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIP_RST (IPRSTC1[0]),1: Power-on Reset (POR) or CHIP_RST (IPRSTC1[0]).."
group.long 0x08++0x03
line.long 0x00 "IPRSTC1,Peripheral Reset Control Register1"
bitfld.long 0x00 4. "HDIV_RST,HDIV Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the hardware divider" "0: Hardware divider controller normal operation,1: Hardware divider controller reset"
bitfld.long 0x00 1. "CPU_RST,Cortex-M0 Core One-shot Reset (Write Protect)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller (FMC) and this bit will automatically return 0 after the two clock cycles.\nNote: This bit is write protected" "0: CPU normal operation,1: CPU one-shot reset"
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bitfld.long 0x00 0. "CHIP_RST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including CPU kernel and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset" "0: Chip normal operation,1: Chip one-shot reset"
group.long 0x0C++0x03
line.long 0x00 "IPRSTC2,Peripheral Reset Control Register2"
bitfld.long 0x00 29. "OPA_RST,OPA0 and OPA1 Controller Reset\n" "0: OPA0 and OPA1 controller normal operation,1: OPA0 and OPA1 controller reset"
bitfld.long 0x00 28. "EADC_RST,EADC Controller Reset\n" "0: EADC controller normal operation,1: EADC controller reset"
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bitfld.long 0x00 27. "ECAP1_RST,Enhanced Input Capture 1 Controller Reset\n" "0: Enhanced input capture 1 controller normal..,1: Enhanced input capture 1 controller reset"
bitfld.long 0x00 26. "ECAP0_RST,Enhanced Input Capture 0 Controller Reset\n" "0: Enhanced input capture 0 controller normal..,1: Enhanced input capture 0 controller reset"
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bitfld.long 0x00 22. "ACMP_RST,Analog Comparator Controller Reset\n" "0: Analog Comparator controller normal operation,1: Analog Comparator controller reset"
bitfld.long 0x00 21. "EPWM1_RST,Enhanced PWM1 Controller Reset\n" "0: EPWM1 controller normal operation,1: EPWM1 controller reset"
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bitfld.long 0x00 20. "EPWM0_RST,Enhanced PWM0 Controller Reset\n" "0: EPWM0 controller normal operation,1: EPWM0 controller reset"
bitfld.long 0x00 19. "BPWM0_RST,Basic PWM0 Controller Reset\n" "0: Basic PWM0 controller normal operation,1: Basic PWM0 controller reset"
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bitfld.long 0x00 17. "UART1_RST,UART1 Controller Reset\n" "0: UART1 controller normal operation,1: UART1 controller reset"
bitfld.long 0x00 16. "UART0_RST,UART0 Controller Reset\n" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x00 14. "SPI2_RST,SPI2 Controller Reset\n" "0: SPI2 controller normal operation,1: SPI2 controller reset"
bitfld.long 0x00 13. "SPI1_RST,SPI1 Controller Reset\n" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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bitfld.long 0x00 12. "SPI0_RST,SPI0 Controller Reset\n" "0: SPI0 controller normal operation,1: SPI0 controller reset"
bitfld.long 0x00 8. "I2C0_RST,I2C0 Controller Reset\n" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x00 5. "TMR3_RST,Timer3 Controller Reset\n" "0: Timer3 controller normal operation,1: Timer3 controller reset"
bitfld.long 0x00 4. "TMR2_RST,Timer2 Controller Reset\n" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x00 3. "TMR1_RST,Timer1 Controller Reset\n" "0: Timer1 controller normal operation,1: Timer1 controller reset"
bitfld.long 0x00 2. "TMR0_RST,Timer0 Controller Reset\n" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x00 1. "GPIO_RST,GPIO Controller Reset\n" "0: GPIO controller normal operation,1: GPIO controller reset"
group.long 0x18++0x03
line.long 0x00 "BODCR,Brown-out Detector Control Register"
bitfld.long 0x00 7. "LVR_EN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled - After.."
bitfld.long 0x00 6. "BOD_OUT,Brown-out Detector Output Status\n" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x00 5. "BOD_LPM,Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100 uA in Normal mode and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected" "0: BOD operated in Normal mode (default),1: BOD Low Power mode Enabled"
bitfld.long 0x00 4. "BOD_INTF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x00 3. "BOD_RSTEN,Brown-out Reset Enable Bit (Write Protect)\nNote1: While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high) BOD will assert a signal to reset chip when the detected voltage is lower than.." "0: Brown-out INTERRUPT function Enabled,1: Brown-out RESET function Enabled"
bitfld.long 0x00 1.--2. "BOD_VL,Brown-out Detector Threshold Voltage Select (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (Config0[22:21]) bits.\nNote: This bit is write protected" "0: Brown-out voltage is 2.2V,1: Brown-out voltage is 2.7V,2: Brown-out voltage is 3.7V,3: Brown-out voltage is 4.4V"
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bitfld.long 0x00 0. "BOD_EN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (Config0[23]) bit.\nNote: This bit is write protected" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
group.long 0x1C++0x03
line.long 0x00 "TEMPCR,Temperature Sensor Control Register"
bitfld.long 0x00 0. "VTEMP_EN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1 the value of temperature sensor output can be obtained from the ADC conversion result" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
group.long 0x24++0x03
line.long 0x00 "PORCR,Power-on Reset Controller Register"
hexmask.long.word 0x00 0.--15. 1. "POR_DIS_CODE,Power-on Reset Enable Bits (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
group.long 0x30++0x03
line.long 0x00 "P0_MFP,P0 Multiple Function and Input Type Control Register"
bitfld.long 0x00 23. "P0_TYPE7,Port 0 Schmitt Trigger Input Enable Bits\n" "0: Port 0 bit m Schmitt trigger input function..,1: Port 0 bit m Schmitt trigger input function.."
bitfld.long 0x00 22. "P0_TYPE6,Port 0 Schmitt Trigger Input Enable Bits\n" "0: Port 0 bit m Schmitt trigger input function..,1: Port 0 bit m Schmitt trigger input function.."
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bitfld.long 0x00 21. "P0_TYPE5,Port 0 Schmitt Trigger Input Enable Bits\n" "0: Port 0 bit m Schmitt trigger input function..,1: Port 0 bit m Schmitt trigger input function.."
bitfld.long 0x00 20. "P0_TYPE4,Port 0 Schmitt Trigger Input Enable Bits\n" "0: Port 0 bit m Schmitt trigger input function..,1: Port 0 bit m Schmitt trigger input function.."
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bitfld.long 0x00 19. "P0_TYPE3,Port 0 Schmitt Trigger Input Enable Bits\n" "0: Port 0 bit m Schmitt trigger input function..,1: Port 0 bit m Schmitt trigger input function.."
bitfld.long 0x00 18. "P0_TYPE2,Port 0 Schmitt Trigger Input Enable Bits\n" "0: Port 0 bit m Schmitt trigger input function..,1: Port 0 bit m Schmitt trigger input function.."
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bitfld.long 0x00 17. "P0_TYPE1,Port 0 Schmitt Trigger Input Enable Bits\n" "0: Port 0 bit m Schmitt trigger input function..,1: Port 0 bit m Schmitt trigger input function.."
bitfld.long 0x00 16. "P0_TYPE0,Port 0 Schmitt Trigger Input Enable Bits\n" "0: Port 0 bit m Schmitt trigger input function..,1: Port 0 bit m Schmitt trigger input function.."
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bitfld.long 0x00 11. "P0_ALT3,P0.3 Alternative Function\nSee P0_MFP[3]" "0,1"
bitfld.long 0x00 10. "P0_ALT2,P0.2 Alternative Function\nSee P0_MFP[2]" "0,1"
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bitfld.long 0x00 9. "P0_ALT1,P0.1 Alternative Function\nSee P0_MFP[1]" "0,1"
bitfld.long 0x00 8. "P0_ALT0,P0.0 Alternative Function\nSee P0_MFP[0]" "0,1"
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bitfld.long 0x00 7. "P0_MFP7,P0.7 Multi-function Selection\n" "0: The GPIO P0.7 is selected,1: The STADC function is selected"
bitfld.long 0x00 6. "P0_MFP6,P0.6 Multi-function Selection\n" "0: The GPIO P0.6 is selected,1: The EPWM0_BRAKE1 function is selected"
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bitfld.long 0x00 5. "P0_MFP5,P0.5 Multi-function Selection\n" "0: The GPIO P0.5 is selected,1: The EPWM0_CH5 function is selected"
bitfld.long 0x00 4. "P0_MFP4,P0.4 Multi-function Selection\n" "0: The GPIO P0.4 is selected,1: The EPWM0_CH4 function is selected"
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bitfld.long 0x00 3. "P0_MFP3,P0.3 Multi-function Selection\nBits P0_ALT[3] and P0_MFP[3] determine the P0.3 function.\n(P0_ALT[3] P0_MFP[3]) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 2. "P0_MFP2,P0.2 Multi-function Selection\nBits P0_ALT[2] and P0_MFP[2] determine the P0.2 function.\n(P0_ALT[2] P0_MFP[2]) value and function mapping is as following list.\n" "0,1"
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bitfld.long 0x00 1. "P0_MFP1,P0.1 Multi-function Selection\nBits P0_ALT[1] and P0_MFP[1] determine the P0.1 function.\n(P0_ALT[2] P0_MFP[2]) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 0. "P0_MFP0,P0.0 Multi-function Selection\nBits P0_ALT[0] and P0_MFP[0] determine the P0.0 function.\n(P0_ALT[0] P0_MFP[0]) value and function mapping is as following list.\n" "0,1"
group.long 0x34++0x03
line.long 0x00 "P1_MFP,P1 Multiple Function and Input Type Control Register"
bitfld.long 0x00 23. "P1_TYPE7,Port 1 Schmitt Trigger Input Enable Bits\n" "0: Port 1 bit m Schmitt trigger input function..,1: Port 1 bit m Schmitt trigger input function.."
bitfld.long 0x00 22. "P1_TYPE6,Port 1 Schmitt Trigger Input Enable Bits\n" "0: Port 1 bit m Schmitt trigger input function..,1: Port 1 bit m Schmitt trigger input function.."
newline
bitfld.long 0x00 21. "P1_TYPE5,Port 1 Schmitt Trigger Input Enable Bits\n" "0: Port 1 bit m Schmitt trigger input function..,1: Port 1 bit m Schmitt trigger input function.."
bitfld.long 0x00 20. "P1_TYPE4,Port 1 Schmitt Trigger Input Enable Bits\n" "0: Port 1 bit m Schmitt trigger input function..,1: Port 1 bit m Schmitt trigger input function.."
newline
bitfld.long 0x00 19. "P1_TYPE3,Port 1 Schmitt Trigger Input Enable Bits\n" "0: Port 1 bit m Schmitt trigger input function..,1: Port 1 bit m Schmitt trigger input function.."
bitfld.long 0x00 18. "P1_TYPE2,Port 1 Schmitt Trigger Input Enable Bits\n" "0: Port 1 bit m Schmitt trigger input function..,1: Port 1 bit m Schmitt trigger input function.."
newline
bitfld.long 0x00 17. "P1_TYPE1,Port 1 Schmitt Trigger Input Enable Bits\n" "0: Port 1 bit m Schmitt trigger input function..,1: Port 1 bit m Schmitt trigger input function.."
bitfld.long 0x00 16. "P1_TYPE0,Port 1 Schmitt Trigger Input Enable Bits\n" "0: Port 1 bit m Schmitt trigger input function..,1: Port 1 bit m Schmitt trigger input function.."
newline
bitfld.long 0x00 7. "P1_MFP7,P1.7 Multi-function Selection\n" "0: The GPIO P1.7 is selected,1: The EPWM1_BRAKE0 function is selected"
bitfld.long 0x00 6. "P1_MFP6,P1.6 Multi-function Selection\n" "0: The GPIO P1.6 is selected,1: The EPWM0_BRAKE0 function is selected"
newline
bitfld.long 0x00 5. "P1_MFP5,P1.5 Multi-function Selection\n" "0: The GPIO P1.5 is selected,1: The EPWM1_CH5 function is selected"
bitfld.long 0x00 4. "P1_MFP4,P1.4 Multi-function Selection\n" "0: The GPIO P1.4 is selected,1: The EPWM1_CH4 function is selected"
newline
bitfld.long 0x00 3. "P1_MFP3,P1.3 Multi-function Selection\n" "0: The GPIO P1.3 is selected,1: The EPWM1_CH3 function is selected"
bitfld.long 0x00 2. "P1_MFP2,P1.2 Multi-function Selection\n" "0: The GPIO P1.2 is selected,1: The EPWM1_CH2 function is selected"
newline
bitfld.long 0x00 1. "P1_MFP1,P1.1 Multi-function Selection\n" "0: The GPIO P1.1 is selected,1: The EPWM1_CH1 function is selected"
bitfld.long 0x00 0. "P1_MFP0,P1.0 Multi-function Selection\n" "0: The GPIO P1.0 is selected,1: The EPWM1_CH0 function is selected"
group.long 0x38++0x03
line.long 0x00 "P2_MFP,P2 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "P2_TYPE,Port 2 Schmitt Trigger Input Enable Bits\n"
bitfld.long 0x00 15. "P2_ALT7,P2.7 Alternative Function\nSee P2_MFP[7]" "0,1"
newline
bitfld.long 0x00 14. "P2_ALT6,P2.6 Alternative Function\nSee P2_MFP[6]" "0,1"
bitfld.long 0x00 13. "P2_ALT5,P2.5 Alternative Function\nSee P2_MFP[5]" "0,1"
newline
bitfld.long 0x00 12. "P2_ALT4,P2.4 Alternative Function\nSee P2_MFP[4]" "0,1"
bitfld.long 0x00 8. "P2_ALT0,P2.0 Alternative Function\nSee P2_MFP[0]" "0,1"
newline
bitfld.long 0x00 7. "P2_MFP7,P2.7 Multi-function Selection\nBits P2_ALT[7] and P2_MFP[7] determine the P2.7 function.\n(P2_ALT[7] P2_MFP[7]) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 6. "P2_MFP6,P2.6 Multi-function Selection\nBits P2_ALT[6] and P2_MFP[6] determine the P2.6 function.\n(P2_ALT[6] P2_MFP[6]) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 5. "P2_MFP5,P2.5 Multi-function Selection\nBits P2_ALT[5] and P2_MFP[5] determine the P2.5 function.\n(P2_ALT[5] P2_MFP[5]) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 4. "P2_MFP4,P2.4 Multi-function Selection\nBits P2_ALT[4] and P2_MFP[4] determine the P2.4 function.\n(P2_ALT[4] P2_MFP[4]) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 3. "P2_MFP3,P2.3 Multi-function Selection\n" "0: The GPIO P2.3 is selected,1: The ECAP0_IC0 function is selected"
bitfld.long 0x00 2. "P2_MFP2,P2.2 Multi-function Selection\n" "0: The GPIO P2.2 is selected,1: The ECAP0_IC1 function is selected"
newline
bitfld.long 0x00 1. "P2_MFP1,P2.1 Multi-function Selection\n" "0: The GPIO P2.1 is selected,1: The ECAP0_IC2 function is selected"
bitfld.long 0x00 0. "P2_MFP0,P2.0 Multi-function Selection\nBits P2_ALT[0] and P2_MFP[0] determine the P2.0 function.\n(P2_ALT[0] P2_MFP[0]) value and function mapping is as following list.\n" "0,1"
group.long 0x3C++0x03
line.long 0x00 "P3_MFP,P3 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "P3_TYPE,Port 3 Schmitt Trigger Input Enable Bit\n"
bitfld.long 0x00 13. "P3_ALT5,P3.5 Alternative Function\nSee P3_MFP[5]" "0,1"
newline
bitfld.long 0x00 12. "P3_ALT4,P3.4 Alternative Function\nSee P3_MFP[4]" "0,1"
bitfld.long 0x00 9. "P3_ALT1,P3.1 Alternative Function\nSee P3_MFP[1]" "0,1"
newline
bitfld.long 0x00 8. "P3_ALT0,P3.0 Alternative Function\nSee P3_MFP[0]" "0,1"
bitfld.long 0x00 7. "P3_MFP7,P3.7 Multi-function Selection\nShould be 0 for GPIO P3.7" "0,1"
newline
bitfld.long 0x00 6. "P3_MFP6,P3.6 Multi-function Selection\nShould be 0 for GPIO P3.6" "0,1"
bitfld.long 0x00 5. "P3_MFP5,P3.5 Multi-function Selection\nBits P3_ALT[5] and P3_MFP[5] determine the P3.5 function.\n(P3_ALT[5] P3_MFP[5]) value and function mapping is as following list.\n" "0,1"
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bitfld.long 0x00 4. "P3_MFP4,P3.4 Multi-function Selection\nBits P3_ALT[4] and P3_MFP[4] determine the P3.4 function.\n(P3_ALT[4] P3_MFP[4]) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 3. "P3_MFP3,P3.3 Multi-function Selection\n" "0: The GPIO P3.3 is selected,1: The INT1 function is selected"
newline
bitfld.long 0x00 2. "P3_MFP2,P3.2 Multi-function Selection\n" "0: The GPIO P3.2 is selected,1: The INT0 function is selected"
bitfld.long 0x00 1. "P3_MFP1,P3.1 Multi-function Selection\nBits P3_ALT[1] and P3_MFP[1] determine the P3.1 function.\n(P3_ALT[1] P3_MFP[1]) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 0. "P3_MFP0,P3.0 Multi-function Selection\nBits P3_ALT[0] and P3_MFP[0] determine the P3.0 function.\n(P3_ALT[0] P3_MFP[0]) value and function mapping is as following list.\n" "0,1"
group.long 0x40++0x03
line.long 0x00 "P4_MFP,P4 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "P4_TYPE,Port 4 Schmitt Trigger Input Enable Bit\n"
bitfld.long 0x00 14. "P4_ALT,P4.6 Alternative Function\nSee P4_MFP[6]" "0,1"
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bitfld.long 0x00 7. "P4_MFP7,P4.7 Multi-function Selection\n" "0: The GPIO P4.7 is selected,1: The TM3 function is selected"
bitfld.long 0x00 6. "P4_MFP6,P4.6 Multi-function Selection\nBits P4_ALT[6] and P4_MFP[6] determine the P4.6 function.\n(P4_ALT[6] P4_MFP[6]) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 5. "P4_MFP5,P4.5 Multi-function Selection\n" "0: The GPIO P4.5 is selected,1: Reserved"
bitfld.long 0x00 4. "P4_MFP4,P4.4 Multi-function Selection\n" "0: The GPIO P4.4 is selected,1: Reserved"
newline
bitfld.long 0x00 2. "P4_MFP2,P4.2 Multi-function Selection\n" "0: The GPIO P4.2 is selected,1: The ECAP1_IC2 function is selected"
bitfld.long 0x00 1. "P4_MFP1,P4.1 Multi-function Selection\n" "0: The GPIO P4.1 is selected,1: The ECAP1_IC1 function is selected"
newline
bitfld.long 0x00 0. "P4_MFP0,P4.0 Multi-function Selection\n" "0: The GPIO P4.0 is selected,1: The ECAP1_IC0 function is selected"
group.long 0x44++0x03
line.long 0x00 "P5_MFP,P5 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "P5_TYPE,Port 5 Schmitt Trigger Input Enable Bit\n"
bitfld.long 0x00 10. "P5_ALT2,P5.2 Alternative Function\nSee P5_MFP[2]" "0,1"
newline
bitfld.long 0x00 9. "P5_ALT1,P5.1 Alternative Function\nSee P5_MFP[1]" "0,1"
bitfld.long 0x00 8. "P5_ALT0,P5.0 Alternative Function\nSee P5_MFP[0]" "0,1"
newline
bitfld.long 0x00 7. "P5_MFP7,P5.7 Multi-function Selection\n" "0: The GPIO P5.7 is selected,1: The BPWM0_CH1 function is selected"
bitfld.long 0x00 6. "P5_MFP6,P5.6 Multi-function Selection\n" "0: The GPIO P5.6 is selected,1: The BPWM0_CH0 function is selected"
newline
bitfld.long 0x00 5. "P5_MFP5,P5.5 Multi-function Selection\n" "0: The GPIO P5.5 is selected,1: The CLKO function is selected"
bitfld.long 0x00 4. "P5_MFP4,P5.4 Multi-function Selection\n" "0: The GPIO P5.4 is selected,1: The SPI2_SS function is selected"
newline
bitfld.long 0x00 3. "P5_MFP3,P5.3 Multi-function Selection\n" "0: The GPIO P5.3 is selected,1: The SPI2_CLK function is selected"
bitfld.long 0x00 2. "P5_MFP2,P5.2 Multi-function Selection\nBits P5_ALT[2] and P5_MFP[2] determine the P5.2 function.\n(P5_ALT[2] P5_MFP[2]) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 1. "P5_MFP1,P5.1 Multi-function Selection\nBits P5_ALT[1] and P5_MFP[1] determine the P5.1 function.\n(P5_ALT[1] P5_MFP[1]) value and function mapping is as following list.\n" "0,1"
bitfld.long 0x00 0. "P5_MFP0,P5.0 Multi-function Selection\nThis bit combined with P5_ALT[0] selects P5.0 multi-function.\nBits P5_ALT[0] and P5_MFP[0] determine the P5.0 function.\n(P5_ALT[0] P5_MFP[0]) value and function mapping is as following list.\n" "0,1"
group.long 0x48++0x03
line.long 0x00 "P6_MFP,P6 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "P6_TYPE,Port 6 Schmitt Trigger Input Enable Bit\n"
bitfld.long 0x00 7. "P6_MFP7,P6.7 Multi-function Selection\n" "0: The GPIO P6.7 is selected,1: The EADC0_CH7 function is selected"
newline
bitfld.long 0x00 6. "P6_MFP6,P6.6 Multi-function Selection\n" "0: The GPIO P6.6 is selected,1: The EADC0_CH6 function is selected"
bitfld.long 0x00 5. "P6_MFP5,P6.5 Multi-function Selection\n" "0: The GPIO P6.5 is selected,1: The EADC0_CH5 or ACMP1_P function is selected"
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bitfld.long 0x00 4. "P6_MFP4,P6.4 Multi-function Selection\n" "0: The GPIO P6.4 is selected,1: The EADC0_CH4 or ACMP1_N function is selected"
bitfld.long 0x00 3. "P6_MFP3,P6.3 Multi-function Selection\n" "0: The GPIO P6.3 is selected,1: The EADC0_CH3 function is selected"
newline
bitfld.long 0x00 2. "P6_MFP2,P6.2 Multi-function Selection\n" "0: The GPIO P6.2 is selected,1: The EADC0_CH2 function is selected"
bitfld.long 0x00 1. "P6_MFP1,P6.1 Multi-function Selection\n" "0: The GPIO P6.1 is selected,1: The EADC0_CH1 function is selected"
newline
bitfld.long 0x00 0. "P6_MFP0,P6.0 Multi-function Selection\n" "0: The GPIO P6.0 is selected,1: The EADC0_CH0 function is selected"
group.long 0x4C++0x03
line.long 0x00 "P7_MFP,P7 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "P7_TYPE,Port 7 Schmitt Trigger Input Enable Bit\n"
bitfld.long 0x00 7. "P7_MFP7,P7.7 Multi-function Selection\n" "0: The GPIO P7.7 is selected,1: The EADC1_CH7 function is selected"
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bitfld.long 0x00 6. "P7_MFP6,P7.6 Multi-function Selection\n" "0: The GPIO P7.6 is selected,1: The EADC1_CH6 function is selected"
bitfld.long 0x00 5. "P7_MFP5,P7.5 Multi-function Selection\n" "0: The GPIO P7.5 is selected,1: The EADC1_CH5 or ACMP2_P function is selected"
newline
bitfld.long 0x00 4. "P7_MFP4,P7.4 Multi-function Selection\n" "0: The GPIO P7.4 is selected,1: The EADC1_CH4 or ACMP2_N function is selected"
bitfld.long 0x00 3. "P7_MFP3,P7.3 Multi-function Selection\n" "0: The GPIO P7.3 is selected,1: The EADC1_CH3 function is selected"
newline
bitfld.long 0x00 2. "P7_MFP2,P7.2 Multi-function Selection\n" "0: The GPIO P7.2 is selected,1: The EADC1_CH2 function is selected"
bitfld.long 0x00 1. "P7_MFP1,P7.1 Multi-function Selection\n" "0: The GPIO P7.1 is selected,1: The EADC1_CH1 function is selected"
newline
bitfld.long 0x00 0. "P7_MFP0,P7.0 Multi-function Selection\n" "0: The GPIO P7.0 is selected,1: The EADC1_CH0 function is selected"
group.long 0x50++0x03
line.long 0x00 "P8_MFP,P8 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "P8_TYPE,Port 8 Schmitt Trigger Input Enable Bits\n"
bitfld.long 0x00 7. "P8_MFP7,P8.7 Multi-function Selection\n" "0: The GPIO P8.7 is selected,1: The ACMP0_O function is selected"
newline
bitfld.long 0x00 4. "P8_MFP4,P8.4 Multi-function Selection\n" "0: The GPIO P8.4 is selected,1: The ACMP0_P function is selected"
bitfld.long 0x00 3. "P8_MFP3,P8.3 Multi-function Selection\n" "0: The GPIO P8.3 is selected,1: The ACMP0_N function is selected"
newline
bitfld.long 0x00 2. "P8_MFP2,P8.2 Multi-function Selection\n" "0: The GPIO P8.2 is selected,1: The OP0_O function is selected"
bitfld.long 0x00 1. "P8_MFP1,P8.1 Multi-function Selection\n" "0: The GPIO P8.1 is selected,1: The OP0_N function is selected"
newline
bitfld.long 0x00 0. "P8_MFP0,P8.0 Multi-function Selection\n" "0: The GPIO P8.0 is selected,1: The OP0_P function is selected"
group.long 0x54++0x03
line.long 0x00 "P9_MFP,P9 Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "P9_TYPE,Port 9 Schmitt Trigger Input Enable Bits\n"
bitfld.long 0x00 7. "P9_MFP7,P9.7 Multi-function Selection\n" "0: The GPIO P9.7 is selected,1: The SPI1_SS function is selected"
newline
bitfld.long 0x00 6. "P9_MFP6,P9.6 Multi-function Selection\n" "0: The GPIO P9.6 is selected,1: The SPI1_MOSI function is selected"
bitfld.long 0x00 5. "P9_MFP5,P9.5 Multi-function Selection\n" "0: The GPIO P9.5 is selected,1: The SPI1_MISO function is selected"
newline
bitfld.long 0x00 4. "P9_MFP4,P9.4 Multi-function Selection\n" "0: The GPIO P9.4 is selected,1: The SPI1_CLK function is selected"
bitfld.long 0x00 3. "P9_MFP3,P9.3 Multi-function Selection\n" "0: The GPIO P9.3 is selected,1: The EPWM1_BRAKE1 function is selected"
newline
bitfld.long 0x00 2. "P9_MFP2,P9.2 Multi-function Selection\n" "0: The GPIO P9.2 is selected,1: The OP1_P function is selected"
bitfld.long 0x00 1. "P9_MFP1,P9.1 Multi-function Selection\n" "0: The GPIO P9.1 is selected,1: The OP1_N function is selected"
newline
bitfld.long 0x00 0. "P9_MFP0,P9.0 Multi-function Selection\n" "0: The GPIO P9.0 is selected,1: The OP1_O function is selected"
group.long 0x58++0x03
line.long 0x00 "PA_MFP,PA Multiple Function and Input Type Control Register"
hexmask.long.byte 0x00 16.--23. 1. "PA_TYPE,Port a Schmitt Trigger Input Enable Bits\n"
bitfld.long 0x00 9. "PA_ALT1,PA.1 Alternative Function\nSee PA_MFP[1]" "0,1"
newline
bitfld.long 0x00 8. "PA_ALT0,PA.0 Alternative Function\nSee PA_MFP[0]" "0,1"
bitfld.long 0x00 1. "PA_MFP1,PA.1 Multi-function Selection\nBits PA_ALT[1] and PA_MFP[1] determine the PA.1 function.\n(PA_ALT[1] PA_MFP[1]) value and function mapping is as following list.\n" "0,1"
newline
bitfld.long 0x00 0. "PA_MFP0,PA.0 Multi-function Selection\nBits PA_ALT[0] and PA_MFP[0] determine the PA.0 function.\n(PA_ALT[0] PA_MFP[0]) value and function mapping is as following list.\n" "0,1"
group.long 0x100++0x03
line.long 0x00 "REGWRPROT,Register Write-protection Control Register"
hexmask.long.byte 0x00 1.--7. 1. "REGWRPROT,Register Write-protection Code (Write Only)\nSome registers have write-protection function"
rbitfld.long 0x00 0. "REGPROTDIS,Register Write-protection Disable Index (Read Only)\nNote: This bit is write protected bit" "0: Write-protection Enabled for writing..,1: Write-protection Disabled for writing.."
tree.end
tree "GPIO"
base ad:0x50004000
group.long 0x00++0x03
line.long 0x00 "P0_PMD,GPIO Port 0 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x04++0x03
line.long 0x00 "P0_OFFD,GPIO Port 0 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x08++0x03
line.long 0x00 "P0_DOUT,GPIO Port 0 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x0C++0x03
line.long 0x00 "P0_DMASK,GPIO Port 0 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
rgroup.long 0x10++0x03
line.long 0x00 "P0_PIN,GPIO Port 0 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x14++0x03
line.long 0x00 "P0_DBEN,GPIO Port 0 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x18++0x03
line.long 0x00 "P0_IMD,GPIO Port 0 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x1C++0x03
line.long 0x00 "P0_IEN,GPIO Port 0 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x20++0x03
line.long 0x00 "P0_ISF,GPIO Port 0 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x40++0x03
line.long 0x00 "P1_PMD,GPIO Port 1 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x44++0x03
line.long 0x00 "P1_OFFD,GPIO Port 1 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x48++0x03
line.long 0x00 "P1_DOUT,GPIO Port 1 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x4C++0x03
line.long 0x00 "P1_DMASK,GPIO Port 1 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x50++0x03
line.long 0x00 "P1_PIN,GPIO Port 1 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x54++0x03
line.long 0x00 "P1_DBEN,GPIO Port 1 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x58++0x03
line.long 0x00 "P1_IMD,GPIO Port 1 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x5C++0x03
line.long 0x00 "P1_IEN,GPIO Port 1 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x60++0x03
line.long 0x00 "P1_ISF,GPIO Port 1 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x80++0x03
line.long 0x00 "P2_PMD,GPIO Port 2 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x84++0x03
line.long 0x00 "P2_OFFD,GPIO Port 2 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x88++0x03
line.long 0x00 "P2_DOUT,GPIO Port 2 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x8C++0x03
line.long 0x00 "P2_DMASK,GPIO Port 2 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x90++0x03
line.long 0x00 "P2_PIN,GPIO Port 2 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x94++0x03
line.long 0x00 "P2_DBEN,GPIO Port 2 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x98++0x03
line.long 0x00 "P2_IMD,GPIO Port 2 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x9C++0x03
line.long 0x00 "P2_IEN,GPIO Port 2 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0xA0++0x03
line.long 0x00 "P2_ISF,GPIO Port 2 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0xC0++0x03
line.long 0x00 "P3_PMD,GPIO Port 3 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0xC4++0x03
line.long 0x00 "P3_OFFD,GPIO Port 3 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0xC8++0x03
line.long 0x00 "P3_DOUT,GPIO Port 3 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0xCC++0x03
line.long 0x00 "P3_DMASK,GPIO Port 3 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0xD0++0x03
line.long 0x00 "P3_PIN,GPIO Port 3 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0xD4++0x03
line.long 0x00 "P3_DBEN,GPIO Port 3 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0xD8++0x03
line.long 0x00 "P3_IMD,GPIO Port 3 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0xDC++0x03
line.long 0x00 "P3_IEN,GPIO Port 3 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0xE0++0x03
line.long 0x00 "P3_ISF,GPIO Port 3 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x100++0x03
line.long 0x00 "P4_PMD,GPIO Port 4 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x104++0x03
line.long 0x00 "P4_OFFD,GPIO Port 4 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x108++0x03
line.long 0x00 "P4_DOUT,GPIO Port 4 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x10C++0x03
line.long 0x00 "P4_DMASK,GPIO Port 4 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x110++0x03
line.long 0x00 "P4_PIN,GPIO Port 4 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x114++0x03
line.long 0x00 "P4_DBEN,GPIO Port 4 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x118++0x03
line.long 0x00 "P4_IMD,GPIO Port 4 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x11C++0x03
line.long 0x00 "P4_IEN,GPIO Port 4 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x120++0x03
line.long 0x00 "P4_ISF,GPIO Port 4 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x140++0x03
line.long 0x00 "P5_PMD,GPIO Port 5 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x144++0x03
line.long 0x00 "P5_OFFD,GPIO Port 5 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x148++0x03
line.long 0x00 "P5_DOUT,GPIO Port 5 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x14C++0x03
line.long 0x00 "P5_DMASK,GPIO Port 5 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x150++0x03
line.long 0x00 "P5_PIN,GPIO Port 5 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x154++0x03
line.long 0x00 "P5_DBEN,GPIO Port 5 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x158++0x03
line.long 0x00 "P5_IMD,GPIO Port 5 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x15C++0x03
line.long 0x00 "P5_IEN,GPIO Port 5 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x160++0x03
line.long 0x00 "P5_ISF,GPIO Port 5 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x180++0x03
line.long 0x00 "P6_PMD,GPIO Port 6 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x184++0x03
line.long 0x00 "P6_OFFD,GPIO Port 6 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x188++0x03
line.long 0x00 "P6_DOUT,GPIO Port 6 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x18C++0x03
line.long 0x00 "P6_DMASK,GPIO Port 6 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x190++0x03
line.long 0x00 "P6_PIN,GPIO Port 6 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x194++0x03
line.long 0x00 "P6_DBEN,GPIO Port 6 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x198++0x03
line.long 0x00 "P6_IMD,GPIO Port 6 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x19C++0x03
line.long 0x00 "P6_IEN,GPIO Port 6 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x1C0++0x03
line.long 0x00 "P7_PMD,GPIO Port 7 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x1C4++0x03
line.long 0x00 "P7_OFFD,GPIO Port 7 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x1C8++0x03
line.long 0x00 "P7_DOUT,GPIO Port 7 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x1CC++0x03
line.long 0x00 "P7_DMASK,GPIO Port 7 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x1D0++0x03
line.long 0x00 "P7_PIN,GPIO Port 7 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x1D4++0x03
line.long 0x00 "P7_DBEN,GPIO Port 7 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x1D8++0x03
line.long 0x00 "P7_IMD,GPIO Port 7 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x1DC++0x03
line.long 0x00 "P7_IEN,GPIO Port 7 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x1E0++0x03
line.long 0x00 "P7_ISF,GPIO Port 7 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x200++0x03
line.long 0x00 "P6_ISF,GPIO Port 6 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x200++0x03
line.long 0x00 "P8_PMD,GPIO Port 8 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x204++0x03
line.long 0x00 "P8_OFFD,GPIO Port 8 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x208++0x03
line.long 0x00 "P8_DOUT,GPIO Port 8 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x20C++0x03
line.long 0x00 "P8_DMASK,GPIO Port 8 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x210++0x03
line.long 0x00 "P8_PIN,GPIO Port 8 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x214++0x03
line.long 0x00 "P8_DBEN,GPIO Port 8 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x218++0x03
line.long 0x00 "P8_IMD,GPIO Port 8 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x21C++0x03
line.long 0x00 "P8_IEN,GPIO Port 8 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x220++0x03
line.long 0x00 "P8_ISF,GPIO Port 8 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x240++0x03
line.long 0x00 "P9_PMD,GPIO Port 9 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x244++0x03
line.long 0x00 "P9_OFFD,GPIO Port 9 Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x248++0x03
line.long 0x00 "P9_DOUT,GPIO Port 9 Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x24C++0x03
line.long 0x00 "P9_DMASK,GPIO Port 9 Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x250++0x03
line.long 0x00 "P9_PIN,GPIO Port 9 Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x254++0x03
line.long 0x00 "P9_DBEN,GPIO Port 9 De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x258++0x03
line.long 0x00 "P9_IMD,GPIO Port 9 Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x25C++0x03
line.long 0x00 "P9_IEN,GPIO Port 9 Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x260++0x03
line.long 0x00 "P9_ISF,GPIO Port 9 Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x280++0x03
line.long 0x00 "PA_PMD,GPIO Port A Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 12.--13. "PMD6,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
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bitfld.long 0x00 10.--11. "PMD5,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 8.--9. "PMD4,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 6.--7. "PMD3,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 4.--5. "PMD2,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
newline
bitfld.long 0x00 2.--3. "PMD1,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
bitfld.long 0x00 0.--1. "PMD0,Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n" "0: GPIO port [n] pin is in Input mode,1: GPIO port [n] pin is in Push-pull Output mode,2: GPIO port [n] pin is in Open-drain Output mode,3: GPIO port [n] pin is in Quasi-bidirectional.."
group.long 0x284++0x03
line.long 0x00 "PA_OFFD,GPIO Port A Pin Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled"
group.long 0x288++0x03
line.long 0x00 "PA_DOUT,GPIO Port A Data Output Value"
hexmask.long.byte 0x00 0.--7. 1. "DOUT,Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n"
group.long 0x28C++0x03
line.long 0x00 "PA_DMASK,GPIO Port A Data Output Write Mask"
hexmask.long.byte 0x00 0.--7. 1. "DMASK,Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]"
group.long 0x290++0x03
line.long 0x00 "PA_PIN,GPIO Port A Pin Value"
hexmask.long.byte 0x00 0.--7. 1. "PIN,Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin"
group.long 0x294++0x03
line.long 0x00 "PA_DBEN,GPIO Port A De-bounce Enable"
hexmask.long.byte 0x00 0.--7. 1. "DBEN,Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit"
group.long 0x298++0x03
line.long 0x00 "PA_IMD,GPIO Port A Interrupt Mode Control"
hexmask.long.byte 0x00 0.--7. 1. "IMD,Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge"
group.long 0x29C++0x03
line.long 0x00 "PA_IEN,GPIO Port A Interrupt Enable"
hexmask.long.byte 0x00 16.--23. 1. "IR_EN,Port 0-a Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]"
hexmask.long.byte 0x00 0.--7. 1. "IF_EN,Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]"
group.long 0x2A0++0x03
line.long 0x00 "PA_ISF,GPIO Port A Interrupt Source Flag"
hexmask.long.byte 0x00 0.--7. 1. "IF_ISF,Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x if GPG0_INT or GPG1_INT enable bit is set the corresponding interrupt service routine will be served"
group.long 0x2E0++0x03
line.long 0x00 "DBNCECON,External Interrupt De-bounce Control"
bitfld.long 0x00 5. "ICLK_ON,Interrupt Clock on Mode\nIt is recommended to turn off this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection\n" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the.."
newline
bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection\n" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
group.long 0x2E4++0x03
line.long 0x00 "PWMPOEN,PWM Port Output Enable"
bitfld.long 0x00 4. "HZ_BPWM,Basic PWM0 Ports Output Control\nNote: The initial value is loaded from CHZ_BPWM (Config0[12]) after any reset" "0: The driving mode of Basic PWM ports are..,1: The driving mode of Basic PWM ports are.."
bitfld.long 0x00 3. "HZ_Odd1,Enhanced PWM Unit1 Odd Ports Output Control\nNote: The initial value is loaded from CHZ_Odd1 (Config0[11]) after any reset" "0: The driving mode of Enhanced PWM unit1 odd..,1: The driving mode of Enhanced PWM unit1 odd.."
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bitfld.long 0x00 2. "HZ_Even1,Enhanced PWM Unit1 Even Ports Output Control\nNote: The initial value is loaded from CHZ_Even1 (Config0[10]) after any reset" "0: The driving mode of Enhanced PWM unit1 even..,1: The driving mode of Enhanced PWM unit1 even.."
bitfld.long 0x00 1. "HZ_Odd0,Enhanced PWM Unit0 Odd Ports Output Control\nNote: The initial value is loaded from CHZ_Odd0 (Config0[9]) after any reset" "0: The driving mode of Enhanced PWM unit0 odd..,1: The driving mode of Enhanced PWM unit0 odd.."
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bitfld.long 0x00 0. "HZ_Even0,Enhanced PWM Unit0 Even Ports Output Control\nNote: The initial value is loaded from CHZ_Even0 (Config0[8]) after any reset" "0: The driving mode of Enhanced PWM unit0 even..,1: The driving mode of Enhanced PWM unit0 even.."
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x300)++0x03
line.long 0x00 "P0_$1,GPIO P0.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat.end
group.long 0x320++0x03
line.long 0x00 "P1_0,GPIO P1.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x324)++0x03
line.long 0x00 "P1_$1,GPIO P1.n Pin Data Input/Output"
repeat.end
group.long 0x340++0x03
line.long 0x00 "P2_0,GPIO P2.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x344)++0x03
line.long 0x00 "P2_$1,GPIO P2.n Pin Data Input/Output"
repeat.end
group.long 0x360++0x03
line.long 0x00 "P3_0,GPIO P3.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x364)++0x03
line.long 0x00 "P3_$1,GPIO P3.n Pin Data Input/Output"
repeat.end
group.long 0x380++0x03
line.long 0x00 "P4_0,GPIO P4.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x384)++0x03
line.long 0x00 "P4_$1,GPIO P4.n Pin Data Input/Output"
repeat.end
group.long 0x3A0++0x03
line.long 0x00 "P5_0,GPIO P5.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x3A4)++0x03
line.long 0x00 "P5_$1,GPIO P5.n Pin Data Input/Output"
repeat.end
group.long 0x3C0++0x03
line.long 0x00 "P6_0,GPIO P6.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x3C4)++0x03
line.long 0x00 "P6_$1,GPIO P6.n Pin Data Input/Output"
repeat.end
group.long 0x3E0++0x03
line.long 0x00 "P7_0,GPIO P7.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x3E4)++0x03
line.long 0x00 "P7_$1,GPIO P7.n Pin Data Input/Output"
repeat.end
group.long 0x400++0x03
line.long 0x00 "P8_0,GPIO P8.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x404)++0x03
line.long 0x00 "P8_$1,GPIO P8.n Pin Data Input/Output"
repeat.end
group.long 0x420++0x03
line.long 0x00 "P9_0,GPIO P9.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x424)++0x03
line.long 0x00 "P9_$1,GPIO P9.n Pin Data Input/Output"
repeat.end
group.long 0x440++0x03
line.long 0x00 "PA_0,GPIO PA.n Pin Data Input/Output"
bitfld.long 0x00 0. "Pxn,GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0] read P0_0 will return the value of.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
group.long 0x444++0x03
line.long 0x00 "PA_1,GPIO PA.n Pin Data Input/Output"
tree.end
tree "HDIV"
base ad:0x50014000
group.long 0x04++0x03
line.long 0x00 "DIVIDEND,Dividend Source Register (Signed 32-bit)"
hexmask.long 0x00 0.--31. 1. "Dividend,Dividend Source\nThis register is given the dividend (signed 32-bit) of divider before calculation starts"
group.long 0x08++0x03
line.long 0x00 "DIVISOR,Divisor Source Resister (Signed 16-bit)"
hexmask.long.word 0x00 0.--15. 1. "Divisor,Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written hardware divider will start calculation"
rgroup.long 0x0C++0x03
line.long 0x00 "DIVQUO,Quotient Result Resister (Signed 32-bit)"
hexmask.long 0x00 0.--31. 1. "Quotient,Quotient Result\nThis register holds the quotient (signed 32-bit) result of divider after calculation completed"
rgroup.long 0x10++0x03
line.long 0x00 "DIVREM,Reminder Result Register (Signed 16-bit)"
hexmask.long.word 0x00 0.--15. 1. "Reminder,Reminder Result\nThis register holds the reminder (signed 16-bit) result of divider after calculation completed"
group.long 0x14++0x03
line.long 0x00 "DIVSTS,Divider Status Register"
bitfld.long 0x00 2. "DIVFF,Divider Operation Finish Flag\nWhen divider calculation has finished this bit is set to 1" "0,1"
bitfld.long 0x00 1. "DIV0,Divisor Zero Warning\nThis register is read only" "0: The divisor is not 0,1: The divisor is 0"
newline
bitfld.long 0x00 0. "DIV_FINISH,Divider Operation Finished\nThis register is read only" "0: The divider calculation not finished yet,1: The divider calculation finished"
tree.end
tree "I2C"
base ad:0x40020000
group.long 0x00++0x03
line.long 0x00 "I2CON,I2C Control Register"
bitfld.long 0x00 7. "EI,Interrupt Enable Bit\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x00 6. "ENS1,I2C Controller Enable Bit\n" "0: I2C controller Disabled,1: I2C controller Enabled"
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bitfld.long 0x00 5. "STA,I2C START Control Bit\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
bitfld.long 0x00 4. "STO,I2C STOP Control Bit\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically" "0,1"
newline
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested" "0,1"
bitfld.long 0x00 2. "AA,Assert Acknowledge Control Bit\n" "0,1"
group.long 0x04++0x03
line.long 0x00 "I2CADDR0,I2C Slave Address Register0"
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
group.long 0x08++0x03
line.long 0x00 "I2CDAT,I2C Data Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CDAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port"
rgroup.long 0x0C++0x03
line.long 0x00 "I2CSTATUS,I2C Status Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CSTATUS,I2C Status Register\nThe three least significant bits are always 0"
group.long 0x10++0x03
line.long 0x00 "I2CLK,I2C Clock Divided Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CLK,I2C Clock Divided Register\nNote: The minimum value of I2CLK is 4"
group.long 0x14++0x03
line.long 0x00 "I2CTOC,I2C Time Out Counter Register"
bitfld.long 0x00 2. "ENTI,Time-out Counter Enable Bit\nWhen Enabled the 14-bit time out counter will start counting when SI is clear" "0: Time out counter Disabled,1: Time out counter Enabled"
bitfld.long 0x00 1. "DIV4,Time-out Counter Input Clock Is Divided by 4\nWhen Enabled the time out period is extend 4 times.\n" "0: The time out counter input clock divided by 4..,1: The time out counter input clock divided by 4.."
newline
bitfld.long 0x00 0. "TIF,Time-out Flag\nThis bit is set by H/W when I2C time out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0,1"
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
group.long ($2+0x18)++0x03
line.long 0x00 "I2CADDR$1,I2C Slave Address Register $1"
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call function Disabled,1: General Call function Enabled"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x24)++0x03
line.long 0x00 "I2CADM$1,I2C Slave Address Mask Register $1"
hexmask.long.byte 0x00 1.--7. 1. "I2CADM,I2C Address Mask Register\nI2C bus controller supports multiple address recognition with four address mask registers"
repeat.end
group.long 0x3C++0x03
line.long 0x00 "I2CWKUPCON,I2C Wake Up Control Register"
bitfld.long 0x00 0. "WKUPEN,I2C Wake-up Function Enable Bit\n" "0: I2C wake up function Disabled,1: I2C wake up function Enabled"
group.long 0x40++0x03
line.long 0x00 "I2CWKUPSTS,I2C Wake Up Status Register"
bitfld.long 0x00 0. "WKUPIF,I2C Wake-up Interrupt Flag\nWhen chip is woken-up from Power-down mode by I2C this bit is set to 1" "0,1"
tree.end
tree "INT"
base ad:0x50000300
rgroup.long 0x00++0x03
line.long 0x00 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity"
bitfld.long 0x00 0. "BOD_INT,IRQ0 Source Identity\n" "0: IRQ0 source is not from BOD interrupt (BOD_INT),1: IRQ0 source is from BOD interrupt (BOD_INT)"
rgroup.long 0x04++0x03
line.long 0x00 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity"
bitfld.long 0x00 1. "WWDT_INT,IRQ1 Source Identity\n" "0: IRQ1 source is not from window-watchdog..,1: IRQ1 source is from window-watchdog interrupt.."
bitfld.long 0x00 0. "WDT_INT,IRQ1 Source Identity\n" "0: IRQ1 source is not from watchdog interrupt..,1: IRQ1 source is from watchdog interrupt.."
rgroup.long 0x08++0x03
line.long 0x00 "IRQ2_SRC,IRQ2 (EINT0) Interrupt Source Identity"
bitfld.long 0x00 0. "EINT0,IRQ2 Source Identity\n" "0: IRQ2 source is not from external signal..,1: IRQ2 source is from external signal interrupt.."
rgroup.long 0x0C++0x03
line.long 0x00 "IRQ3_SRC,IRQ3 (EINT1) Interrupt Source Identity"
bitfld.long 0x00 0. "EINT1,IRQ3 Source Identity\n" "0: IRQ3 source is not from external signal..,1: IRQ3 source is from external signal interrupt.."
rgroup.long 0x10++0x03
line.long 0x00 "IRQ4_SRC,IRQ4 (P0-P4) Interrupt Source Identity"
bitfld.long 0x00 4. "P4_INT,IRQ4 Source Identity\n" "0: IRQ4 source is not from P4 interrupt (P4_INT),1: IRQ4 source is from P4 interrupt (P4_INT)"
bitfld.long 0x00 3. "P3_INT,IRQ4 Source Identity\n" "0: IRQ4 source is not from P3 interrupt (P3_INT),1: IRQ4 source is from P3 interrupt (P3_INT)"
newline
bitfld.long 0x00 2. "P2_INT,IRQ4 Source Identity\n" "0: IRQ4 source is not from P2 interrupt (P2_INT),1: IRQ4 source is from P2 interrupt (P2_INT)"
bitfld.long 0x00 1. "P1_INT,IRQ4 Source Identity\n" "0: IRQ4 source is not from P1 interrupt (P1_INT),1: IRQ4 source is from P1 interrupt (P1_INT)"
newline
bitfld.long 0x00 0. "P0_INT,IRQ4 Source Identity\n" "0: IRQ4 source is not from P0 interrupt (P0_INT),1: IRQ4 source is from P0 interrupt (P0_INT)"
rgroup.long 0x14++0x03
line.long 0x00 "IRQ5_SRC,IRQ5 (P5-PA) Interrupt Source Identity"
bitfld.long 0x00 5. "PA_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from PA interrupt (PA_INT),1: IRQ5 source is from PA interrupt (PA_INT)"
bitfld.long 0x00 4. "P9_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from P9 interrupt (P9_INT),1: IRQ5 source is from P9 interrupt (P9_INT)"
newline
bitfld.long 0x00 3. "P8_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from P8 interrupt (P8_INT),1: IRQ5 source is from P8 interrupt (P8_INT)"
bitfld.long 0x00 2. "P7_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from P7 interrupt (P7_INT),1: IRQ5 source is from P7 interrupt (P7_INT)"
newline
bitfld.long 0x00 1. "P6_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from P6 interrupt (P6_INT),1: IRQ5 source is from P6 interrupt (P6_INT)"
bitfld.long 0x00 0. "P5_INT,IRQ5 Source Identity\n" "0: IRQ5 source is not from P5 interrupt (P5_INT),1: IRQ5 source is from P5 interrupt (P5_INT)"
rgroup.long 0x18++0x03
line.long 0x00 "IRQ6_SRC,IRQ6 (BPWM0) Interrupt Source Identity"
bitfld.long 0x00 1. "BPCH1_INT,IRQ6 Source Identity\n" "0: IRQ6 source is not from BPWM0 channel 1..,1: IRQ6 source is from BPWM0 channel 1 interrupt.."
bitfld.long 0x00 0. "BPCH0_INT,IRQ6 Source Identity\n" "0: IRQ6 source is not from BPWM0 channel 0..,1: IRQ6 source is from BPWM0 channel 0 interrupt.."
rgroup.long 0x1C++0x03
line.long 0x00 "IRQ7_SRC,IRQ7 (EADC0) Interrupt Source Identity"
bitfld.long 0x00 0. "EADC0_INT,IRQ7 Source Identity \n" "0: IRQ7 source is not from EADC0 interrupt..,1: IRQ7 source is from EADC0 interrupt (EADC0_INT)"
rgroup.long 0x20++0x03
line.long 0x00 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity"
bitfld.long 0x00 0. "TMR0_INT,IRQ8 Source Identity \n" "0: IRQ8 source is not from Timer0 interrupt..,1: IRQ8 source is from Timer0 interrupt (TMR0_INT)"
rgroup.long 0x24++0x03
line.long 0x00 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity"
bitfld.long 0x00 0. "TMR1_INT,IRQ9 Source Identity \n" "0: IRQ9 source is not from Timer1 interrupt..,1: IRQ9 source is from Timer1 interrupt (TMR1_INT)"
rgroup.long 0x28++0x03
line.long 0x00 "IRQ10_SRC,IRQ10 (TMR2) Interrupt Source Identity"
bitfld.long 0x00 0. "TMR2_INT,IRQ10 Source Identity \n" "0: IRQ10 source is not from Timer2 interrupt..,1: IRQ10 source is from Timer2 interrupt.."
rgroup.long 0x2C++0x03
line.long 0x00 "IRQ11_SRC,IRQ11 (TMR3) Interrupt Source Identity"
bitfld.long 0x00 0. "TMR3_INT,IRQ11 Source Identity \n" "0: IRQ11 source is not from Timer3 interrupt..,1: IRQ11 source is from Timer3 interrupt.."
rgroup.long 0x30++0x03
line.long 0x00 "IRQ12_SRC,IRQ12 (UART0) Interrupt Source Identity"
bitfld.long 0x00 0. "UART0_INT,IRQ12 Source Identity\n" "0: IRQ12 source is not from UART0 interrupt..,1: IRQ12 source is from UART0 interrupt.."
rgroup.long 0x34++0x03
line.long 0x00 "IRQ13_SRC,IRQ13 (UART1) Interrupt Source Identity"
bitfld.long 0x00 0. "UART1_INT,IRQ13 Source Identity\n" "0: IRQ13 source is not from UART1 interrupt..,1: IRQ13 source is from UART1 interrupt.."
rgroup.long 0x38++0x03
line.long 0x00 "IRQ14_SRC,IRQ14 (SPI0) Interrupt Source Identity"
bitfld.long 0x00 0. "SPI0_INT,IRQ14 Source Identity\n" "0: IRQ14 source is not from SPI0 interrupt..,1: IRQ14 source is from SPI0 interrupt (SPI0_INT)"
rgroup.long 0x3C++0x03
line.long 0x00 "IRQ15_SRC,IRQ15 (SPI1) Interrupt Source Identity"
bitfld.long 0x00 0. "SPI1_INT,IRQ15 Source Identity\n" "0: IRQ15 source is not from SPI1 interrupt..,1: IRQ15 source is from SPI1 interrupt (SPI1_INT)"
rgroup.long 0x40++0x03
line.long 0x00 "IRQ16_SRC,IRQ16 (SPI2) Interrupt Source Identity"
bitfld.long 0x00 0. "SPI2_INT,IRQ16 Source Identity\n" "0: IRQ16 source is not from SPI2 interrupt..,1: IRQ16 source is from SPI2 interrupt (SPI2_INT)"
rgroup.long 0x48++0x03
line.long 0x00 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity"
bitfld.long 0x00 0. "I2C0_INT,IRQ18 Source Identity\n" "0: IRQ18 source is not from I2C0 interrupt..,1: IRQ18 source is from I2C0 interrupt (I2C0_INT)"
rgroup.long 0x4C++0x03
line.long 0x00 "IRQ19_SRC,IRQ19 (CKD) Interrupt Source Identity"
bitfld.long 0x00 0. "CKD_INT,IRQ19 Source Identity\n" "0: IRQ19 source is not from CKD interrupt..,1: IRQ19 source is from CKD interrupt (CKD_INT)"
rgroup.long 0x54++0x03
line.long 0x00 "IRQ21_SRC,IRQ21 (EPWM0) Interrupt Source Identity"
bitfld.long 0x00 0. "EPWM0_INT,IRQ21 Source Identity\n" "0: IRQ21 source is not from EPWM0 interrupt..,1: IRQ21 source is from EPWM0 interrupt.."
rgroup.long 0x58++0x03
line.long 0x00 "IRQ22_SRC,IRQ22 (EPWM1) Interrupt Source Identity"
bitfld.long 0x00 0. "EPWM1_INT,IRQ22 Source Identity\n" "0: IRQ22 source is not from EPWM1 interrupt..,1: IRQ22 source is from EPWM1 interrupt.."
rgroup.long 0x5C++0x03
line.long 0x00 "IRQ23_SRC,IRQ23 (ECAP0) Interrupt Source Identity"
bitfld.long 0x00 0. "ECAP0_INT,IRQ23 Source Identity\n" "0: IRQ23 source is not from ECAP0 interrupt..,1: IRQ23 source is from ECAP0 interrupt.."
rgroup.long 0x60++0x03
line.long 0x00 "IRQ24_SRC,IRQ24 (ECAP1) Interrupt Source Identity"
bitfld.long 0x00 0. "ECAP1_INT,IRQ24 Source Identity\n" "0: IRQ24 source is not from ECAP1 interrupt..,1: IRQ24 source is from ECAP1 interrupt.."
rgroup.long 0x64++0x03
line.long 0x00 "IRQ25_SRC,IRQ25 (ACMP) Interrupt Source Identity"
bitfld.long 0x00 0. "ACMP_INT,IRQ25 Source Identity\n" "0: IRQ25 source is not from ACMP interrupt..,1: IRQ25 source is from ACMP interrupt (ACMP_INT)"
rgroup.long 0x70++0x03
line.long 0x00 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity"
bitfld.long 0x00 0. "PWRWU_INT,IRQ28 Source Identity\n" "0: IRQ28 source is not from PWRWU interrupt..,1: IRQ28 source is from PWREU interrupt.."
rgroup.long 0x74++0x03
line.long 0x00 "IRQ29_SRC,IRQ29 (EADC1) Interrupt Source Identity"
bitfld.long 0x00 0. "EADC1_INT,IRQ29 Source Identity \n" "0: IRQ29 source is not from EADC1 interrupt..,1: IRQ29 source is from EADC1 interrupt.."
rgroup.long 0x78++0x03
line.long 0x00 "IRQ30_SRC,IRQ30 (EADC2) Interrupt Source Identity"
bitfld.long 0x00 0. "EADC2_INT,IRQ30 Source Identity \n" "0: IRQ30 source is not from EADC2 interrupt..,1: IRQ30 source is from EADC2 interrupt.."
rgroup.long 0x7C++0x03
line.long 0x00 "IRQ31_SRC,IRQ31 (EADC3) Interrupt Source Identity"
bitfld.long 0x00 0. "EADC3_INT,IRQ31 Source Identity \n" "0: IRQ31 source is not from EADC3 interrupt..,1: IRQ31 source is from EADC3 interrupt.."
group.long 0x80++0x03
line.long 0x00 "NMI_SEL,NMI Interrupt Source Select Control Register"
bitfld.long 0x00 8. "NMI_EN,NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected bit" "0: IRQ0~31 assigned to NMI Disabled,1: IRQ0~31 assigned to NMI Enabled"
bitfld.long 0x00 0.--4. "NMI_SEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of IRQ0~IRQ31 by setting NMI_SEL with IRQ number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x84++0x03
line.long 0x00 "MCU_IRQ,MCU Interrupt Request Source Register"
hexmask.long 0x00 0.--31. 1. "MCU_IRQ,MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the.."
group.long 0x88++0x03
line.long 0x00 "MCU_IRQCR,MCU Interrupt Request Control Register"
bitfld.long 0x00 0. "FAST_IRQ,Fast IRQ Latency Enable Bit\n" "0: MCU IRQ latency is fixed at 13 HCLK MCU will..,1: MCU IRQ latency will not fixed MCU will enter.."
tree.end
tree "NVIC"
base ad:0xE000E100
group.long 0x00++0x03
line.long 0x00 "NVIC_ISER,IRQ0 ~ IRQ31 Set-enable Control Register"
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Enable Register\nEnable one or more interrupts"
group.long 0x80++0x03
line.long 0x00 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-enable Control Register"
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt Clear Enable Bits\nDisable one or more interrupts"
group.long 0x100++0x03
line.long 0x00 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-pending Control Register"
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending\nThe ISPR forces interrupts into the pending state and shows the interrupts that are pending"
group.long 0x180++0x03
line.long 0x00 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-pending Control Register"
hexmask.long 0x00 0.--31. 1. "CLRPEND,Interrupt Clear-pending\nThe ICPR removes the pending state from interrupts and shows the interrupts that are pending"
group.long 0x300++0x03
line.long 0x00 "NVIC_IPR0,IRQ0 ~ IRQ3 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_3,Priority of IRQ3\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_2,Priority of IRQ2\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_1,Priority of IRQ1\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_0,Priority of IRQ0\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x304++0x03
line.long 0x00 "NVIC_IPR1,IRQ4 ~ IRQ7 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_7,Priority of IRQ7\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_6,Priority of IRQ6\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_5,Priority of IRQ5\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_4,Priority of IRQ4\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x308++0x03
line.long 0x00 "NVIC_IPR2,IRQ8 ~ IRQ11 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_11,Priority of IRQ11\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_10,Priority of IRQ10\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_9,Priority of IRQ9\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_8,Priority of IRQ8\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x30C++0x03
line.long 0x00 "NVIC_IPR3,IRQ12 ~ IRQ15 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_15,Priority of IRQ15\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority of IRQ14\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_13,Priority of IRQ13\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_12,Priority of IRQ12\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x310++0x03
line.long 0x00 "NVIC_IPR4,IRQ16 ~ IRQ19 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_19,Priority of IRQ19\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_18,Priority of IRQ18\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_17,Priority of IRQ17\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_16,Priority of IRQ16\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x314++0x03
line.long 0x00 "NVIC_IPR5,IRQ20 ~ IRQ23 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_23,Priority of IRQ23\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_22,Priority of IRQ22\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_21,Priority of IRQ21\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_20,Priority of IRQ20\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x318++0x03
line.long 0x00 "NVIC_IPR6,IRQ24 ~ IRQ27 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_27,Priority of IRQ27\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_26,Priority of IRQ26\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_25,Priority of IRQ25\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_24,Priority of IRQ24\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x31C++0x03
line.long 0x00 "NVIC_IPR7,IRQ28 ~ IRQ31 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_31,Priority of IRQ31\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_30,Priority of IRQ30\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_29,Priority of IRQ29\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_28,Priority of IRQ28\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
tree.end
tree "OPA"
base ad:0x400F0000
group.long 0x00++0x03
line.long 0x00 "OPACR,OP Amplifier Control Register"
bitfld.long 0x00 9. "OPDIE1,OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit\nThe OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state in the meanwhile if OPDIE1 is set to 1 a.." "0: OP Amplifier 1 digital output interrupt..,1: OP Amplifier 1 digital output interrupt.."
bitfld.long 0x00 8. "OPDIE0,OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit\nThe OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state in the meanwhile if OPDIE0 is set to 1 a.." "0: OP Amplifier 0 digital output interrupt..,1: OP Amplifier 0 digital output interrupt.."
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bitfld.long 0x00 5. "OPSCH1_EN,OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit\n" "0: OP Amplifier 1 Schmitt trigger Disabled,1: OP Amplifier 1 Schmitt trigger Enabled"
bitfld.long 0x00 4. "OPSCH0_EN,OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit\n" "0: OP Amplifier 0 Schmitt trigger Disabled,1: OP Amplifier 0 Schmitt trigger Enabled"
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bitfld.long 0x00 1. "OP1_EN,OP Amplifier 1 Enable Bit\n" "0: OP Amplifier 1 Disabled,1: OP Amplifier 1 Enabled"
bitfld.long 0x00 0. "OP0_EN,OP Amplifier 0 Enable Bit\n" "0: OP Amplifier 0 Disabled,1: OP Amplifier 0 Enabled"
group.long 0x04++0x03
line.long 0x00 "OPASR,OP Amplifier Status Register"
bitfld.long 0x00 5. "OPDF1,OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nOPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state" "0,1"
bitfld.long 0x00 4. "OPDF0,OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state" "0,1"
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bitfld.long 0x00 1. "OPDO1,OP Amplifier 1 Digital Output\n" "0,1"
bitfld.long 0x00 0. "OPDO0,OP Amplifier 0 Digital Output\n" "0,1"
tree.end
tree "SCB"
base ad:0xE000ED00
rgroup.long 0x00++0x03
line.long 0x00 "CPUID,CPUID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer Code Assigned by ARM \n"
bitfld.long 0x00 16.--19. "PART,Architecture of the Processor\nRead as 0xC corresponding to ARMv6-M architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "PARTNO,Part Number of the Processor\nReads as 0xC20 corresponding to Cortex-M0"
bitfld.long 0x00 0.--3. "REVISION,Revision Number\nReads as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nBecause NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: no effect.\nNMI exception is not pending,1: changes NMI exception state to pending.\nNMI.."
bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending" "0: no effect.\nPendSV exception is not pending,1: changes PendSV exception state to.."
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bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit (Write Only)\n" "0: no effect,1: removes the pending state from the PendSV.."
bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:\n" "0: no effect.\nSysTick exception is not pending,1: changes SysTick exception state to.."
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bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit (Write Only)\n" "0: no effect,1: removes the pending state from the SysTick.."
rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag (Read Only)\nIndicates if an external configurable (NVIC generated) interrupt is pending.\n" "0: interrupt not pending,1: interrupt pending"
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rbitfld.long 0x00 12.--17. "VECTPENDING,Vector Pending Indicator (Read Only)\nThis field indicates the exception number of the highest priority pending enabled exception:\n" "0: no pending exceptions,?..."
rbitfld.long 0x00 0.--5. "VECTACTIVE,Vector Active Indicator (Read Only)\nThis field contains the active exception number:\n" "0: Thread mode,?..."
group.long 0x0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register Key (Write Only)\nWhen writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored"
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request (Write Only)\n" "0: no effect,1: requests a system level reset"
group.long 0x10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Oonly enabled interrupts or events can wake..,1: Enabled events and all interrupts including.."
bitfld.long 0x00 2. "SLEEPDEEP,Deep Sleep Mode Enable Bit\nThis bit controls whether the processor uses sleep or deep sleep as its low power mode:\n" "0: Sleep mode,1: Deep sleep mode"
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bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Bit\nThis bit controls sleep-on-exit when returning from Handler mode to Thread mode:\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep on return from an.."
group.long 0x1C++0x03
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler 11 SVCall\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
group.long 0x20++0x03
line.long 0x00 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler 15 SysTick\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler 14 PendSV\n 0 denotes the highest priority and 3 denotes the lowest priority" "0,1,2,3"
tree.end
tree "SPI"
repeat 3. (list 0. 1. 2.) (list ad:0x40030000 ad:0x40034000 ad:0x40130000)
tree "SPI$1"
base $2
group.long 0x00++0x03
line.long 0x00 "SPI_CNTRL,Control and Status Register"
rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STAUTS[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[25].\n" "0: Receive FIOF buffer is not full,1: Receive FIFO buffer is full"
rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 21. "FIFO,FIFO Mode Enable Bit\nNote:\nBefore enabling FIFO mode the other related settings should be set in advance.\nIn Master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer.." "0: FIFO mode Disabled,1: FIFO mode Enabled"
bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits.\nIn Slave mode with level-trigger configuration the slave select pin must be kept at active state during the byte.." "0: Byte reorder function Disabled,1: Byte reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Enable Bit\n" "0: Master mode,1: Slave mode"
bitfld.long 0x00 17. "IE,Unit Transfer Interrupt Enable Bit\n" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x00 16. "IF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
bitfld.long 0x00 12.--15. "SP_CYCLE,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "CLKP,Clock Polarity\n" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
bitfld.long 0x00 10. "LSB,Send LSB First\n" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 3.--7. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "TX_NEG,Transmit on Negative Edge\n" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RX_NEG,Receive on Negative Edge\n" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
bitfld.long 0x00 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled during the data transfer this bit keeps the value of 1" "0: Data transfer stopped,1: In Master mode writing 1 to this bit to start.."
group.long 0x04++0x03
line.long 0x00 "SPI_DIVIDER,Clock Divider Register"
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock fspi_eclk and the SPI bus clock of SPI master"
group.long 0x08++0x03
line.long 0x00 "SPI_SSR,Slave Select Register"
bitfld.long 0x00 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn Slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done" "0: Transferred bit length of one transaction..,1: Transferred bit length meets the specified.."
bitfld.long 0x00 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave Only)\n" "0: Slave select signal is edge-trigger,1: Slave select signal is level-trigger"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master Only)\n" "0: If this bit is cleared slave select signals..,1: If this bit is set SPI_SS signals will be.."
bitfld.long 0x00 2. "SS_LVL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS).\n" "0: The slave select signal SPI_SS is active on..,1: The slave select signal SPI_SS is active on.."
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bitfld.long 0x00 0. "SSR,Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared\n" "0: Set the SPIx_SS pin to inactive state.\nKeep..,1: Set the SPIx_SS pin to active state.\nSelect.."
rgroup.long 0x10++0x03
line.long 0x00 "SPI_RX,Data Receive Register"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin"
wgroup.long 0x20++0x03
line.long 0x00 "SPI_TX,Data Transmit Register"
hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer"
group.long 0x3C++0x03
line.long 0x00 "SPI_CNTRL2,Control and Status Register 2"
bitfld.long 0x00 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
bitfld.long 0x00 11. "SLV_START_INTSTS,Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode" "0: Slave has not detected any SPI clock..,1: A transaction has started in Slave 3-wire mode"
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bitfld.long 0x00 10. "SSTA_INTEN,Slave 3-wire Mode Start Interrupt Enable Bit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode" "0: Transaction start interrupt Disabled,1: Transaction start interrupt Enabled"
bitfld.long 0x00 9. "SLV_ABORT,Slave 3-wire Mode Abort Control\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock.." "0: No effect,1: Force the current transaction done"
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bitfld.long 0x00 8. "NOSLVSEL,Slave 3-wire Mode Enable Bit\n In Slave 3-wire mode the SPI controller can work with 3-wire interface including SPI_CLK SPI_MISO and SPI_MOSI.\nNote: In Slave 3-wire mode the SS_LTRIG (SPI_SSR[4]) will be set as 1 automatically" "0: 4-wire bi-direction interface in Slave mode,1: 3-wire bi-direction interface in Slave mode"
group.long 0x40++0x03
line.long 0x00 "SPI_FIFO_CTL,SPI FIFO Control Register"
bitfld.long 0x00 28.--30. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "RX_THRESHOLD,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable Bit\n" "0: Time-out interrupt Disabled,1: Time-out interrupt Enabled"
bitfld.long 0x00 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable Bit\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 3. "TX_INTEN,Transmit Threshold Interrupt Enable Bit\n" "0: TX threshold interrupt Disabled,1: TX threshold interrupt Enabled"
bitfld.long 0x00 2. "RX_INTEN,Receive Threshold Interrupt Enable Bit\n" "0: RX threshold interrupt Disabled,1: RX threshold interrupt Enabled"
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bitfld.long 0x00 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer"
bitfld.long 0x00 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer"
group.long 0x44++0x03
line.long 0x00 "SPI_STATUS,SPI Status Register"
rbitfld.long 0x00 28.--31. "TX_FIFO_COUNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[27].\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[26].\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[25].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[24].\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
bitfld.long 0x00 20. "TIMEOUT,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 16. "IF,SPI Unit Transfer Interrupt Flag\nA mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
rbitfld.long 0x00 12.--15. "RX_FIFO_COUNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode" "0: Slave has not detected any SPI clock..,1: A transaction has started in Slave 3-wire mode"
rbitfld.long 0x00 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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bitfld.long 0x00 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself" "0: Receive FIFO does not overrun,1: Receive FIFO overruns"
rbitfld.long 0x00 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
tree.end
repeat.end
tree.end
tree "SYST"
base ad:0xE000E010
group.long 0x00++0x03
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register (SYST_CVR)" "0,1"
bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection\n" "0: Clock source is optional refer to STCLK_S..,1: Core clock used for SysTick timer"
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bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled\n" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x00 0. "ENABLE,System Tick Counter Enable Bit\n" "0: SysTick counter Disabled,1: SysTick counter Enabled"
group.long 0x04++0x03
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0"
group.long 0x08++0x03
line.long 0x00 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
tree.end
tree "TMR"
tree "TMR01"
base ad:0x40010000
group.long 0x00++0x03
line.long 0x00 "TCSR0,Timer0 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x00 27.--28. "MODE,Timer Counting Mode Select\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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bitfld.long 0x00 26. "CRST,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value TDR and also force CEN (TCSR[30]) to 0 if CACT (TCSR[25]) is 1.\n" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.."
rbitfld.long 0x00 25. "CACT,Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n" "0: Timer is not active,1: Timer is active"
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bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen this bit is set timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
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hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n"
group.long 0x04++0x03
line.long 0x00 "TCMPR0,Timer0 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
group.long 0x08++0x03
line.long 0x00 "TISR0,Timer0 Interrupt Status Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter TDR value reaches to TCMP (TCMPR[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
rgroup.long 0x0C++0x03
line.long 0x00 "TDR0,Timer0 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf CTB (TCSR[24] ) is 0 user can read TDR value for getting current 24- bit counter value .\nIf CTB (TCSR[24] ) is 1 user can read TDR value for getting current 24- bit event input counter value"
rgroup.long 0x10++0x03
line.long 0x00 "TCAP0,Timer0 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\n"
group.long 0x14++0x03
line.long 0x00 "TEXCON0,Timer0 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "TEXDB,Timer External Capture Pin De-bounce Enable Bit \nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\n" "0: TMx (x= 0~3) pin detection Interrupt Disabled,1: TMx (x= 0~3) pin detection Interrupt Enabled"
bitfld.long 0x00 4. "RSTCAPSEL,Capture Function Selection\n" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "TEXEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx pin" "0: TMx (x= 0~3) pin Disabled,1: TMx (x= 0~3) pin Enabled"
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect\n" "0: A Falling edge on TMx (x= 0~3) pin will be..,1: A Rising edge on TMx (x= 0~3) pin will be..,2: Either Rising or Falling edge on TMx (x= 0~3)..,3: Reserved"
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bitfld.long 0x00 0. "TX_PHASE,Timer External Count Phase \n" "0: A Falling edge of external counting pin will..,1: A Rising edge of external counting pin will.."
group.long 0x18++0x03
line.long 0x00 "TEXISR0,Timer0 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the TEXIF status" "0: TMx (x= 0~3) pin interrupt did not occur,1: TMx (x= 0~3) pin interrupt occurred"
group.long 0x20++0x03
line.long 0x00 "TCSR1,Timer1 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x00 27.--28. "MODE,Timer Counting Mode Select\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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bitfld.long 0x00 26. "CRST,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value TDR and also force CEN (TCSR[30]) to 0 if CACT (TCSR[25]) is 1.\n" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.."
rbitfld.long 0x00 25. "CACT,Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n" "0: Timer is not active,1: Timer is active"
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bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen this bit is set timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
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hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n"
group.long 0x24++0x03
line.long 0x00 "TCMPR1,Timer1 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
group.long 0x28++0x03
line.long 0x00 "TISR1,Timer1 Interrupt Status Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter TDR value reaches to TCMP (TCMPR[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
group.long 0x2C++0x03
line.long 0x00 "TDR1,Timer1 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf CTB (TCSR[24] ) is 0 user can read TDR value for getting current 24- bit counter value .\nIf CTB (TCSR[24] ) is 1 user can read TDR value for getting current 24- bit event input counter value"
group.long 0x30++0x03
line.long 0x00 "TCAP1,Timer1 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\n"
group.long 0x34++0x03
line.long 0x00 "TEXCON1,Timer1 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "TEXDB,Timer External Capture Pin De-bounce Enable Bit \nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\n" "0: TMx (x= 0~3) pin detection Interrupt Disabled,1: TMx (x= 0~3) pin detection Interrupt Enabled"
bitfld.long 0x00 4. "RSTCAPSEL,Capture Function Selection\n" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "TEXEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx pin" "0: TMx (x= 0~3) pin Disabled,1: TMx (x= 0~3) pin Enabled"
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect\n" "0: A Falling edge on TMx (x= 0~3) pin will be..,1: A Rising edge on TMx (x= 0~3) pin will be..,2: Either Rising or Falling edge on TMx (x= 0~3)..,3: Reserved"
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bitfld.long 0x00 0. "TX_PHASE,Timer External Count Phase \n" "0: A Falling edge of external counting pin will..,1: A Rising edge of external counting pin will.."
group.long 0x38++0x03
line.long 0x00 "TEXISR1,Timer1 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the TEXIF status" "0: TMx (x= 0~3) pin interrupt did not occur,1: TMx (x= 0~3) pin interrupt occurred"
tree.end
tree "TMR23"
base ad:0x40110000
group.long 0x00++0x03
line.long 0x00 "TCSR2,Timer2 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x00 27.--28. "MODE,Timer Counting Mode Select\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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bitfld.long 0x00 26. "CRST,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value TDR and also force CEN (TCSR[30]) to 0 if CACT (TCSR[25]) is 1.\n" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.."
rbitfld.long 0x00 25. "CACT,Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n" "0: Timer is not active,1: Timer is active"
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bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen this bit is set timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
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hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n"
group.long 0x04++0x03
line.long 0x00 "TCMPR2,Timer2 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
group.long 0x08++0x03
line.long 0x00 "TISR2,Timer2 Interrupt Status Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter TDR value reaches to TCMP (TCMPR[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
rgroup.long 0x0C++0x03
line.long 0x00 "TDR2,Timer2 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf CTB (TCSR[24] ) is 0 user can read TDR value for getting current 24- bit counter value .\nIf CTB (TCSR[24] ) is 1 user can read TDR value for getting current 24- bit event input counter value"
rgroup.long 0x10++0x03
line.long 0x00 "TCAP2,Timer2 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\n"
group.long 0x14++0x03
line.long 0x00 "TEXCON2,Timer2 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "TEXDB,Timer External Capture Pin De-bounce Enable Bit \nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\n" "0: TMx (x= 0~3) pin detection Interrupt Disabled,1: TMx (x= 0~3) pin detection Interrupt Enabled"
bitfld.long 0x00 4. "RSTCAPSEL,Capture Function Selection\n" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "TEXEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx pin" "0: TMx (x= 0~3) pin Disabled,1: TMx (x= 0~3) pin Enabled"
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect\n" "0: A Falling edge on TMx (x= 0~3) pin will be..,1: A Rising edge on TMx (x= 0~3) pin will be..,2: Either Rising or Falling edge on TMx (x= 0~3)..,3: Reserved"
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bitfld.long 0x00 0. "TX_PHASE,Timer External Count Phase \n" "0: A Falling edge of external counting pin will..,1: A Rising edge of external counting pin will.."
group.long 0x18++0x03
line.long 0x00 "TEXISR2,Timer2 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the TEXIF status" "0: TMx (x= 0~3) pin interrupt did not occur,1: TMx (x= 0~3) pin interrupt occurred"
group.long 0x20++0x03
line.long 0x00 "TCSR3,Timer3 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x00 27.--28. "MODE,Timer Counting Mode Select\n" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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bitfld.long 0x00 26. "CRST,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value TDR and also force CEN (TCSR[30]) to 0 if CACT (TCSR[25]) is 1.\n" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.."
rbitfld.long 0x00 25. "CACT,Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n" "0: Timer is not active,1: Timer is active"
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bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
bitfld.long 0x00 16. "TDR_EN,Data Load Enable Bit\nWhen this bit is set timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
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hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Prescale Counter\n"
group.long 0x24++0x03
line.long 0x00 "TCMPR3,Timer3 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nTCMP is a 24-bit compared value register"
group.long 0x28++0x03
line.long 0x00 "TISR3,Timer3 Interrupt Status Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter TDR value reaches to TCMP (TCMPR[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TDR value matches the TCMP value"
group.long 0x2C++0x03
line.long 0x00 "TDR3,Timer3 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nIf CTB (TCSR[24] ) is 0 user can read TDR value for getting current 24- bit counter value .\nIf CTB (TCSR[24] ) is 1 user can read TDR value for getting current 24- bit event input counter value"
group.long 0x30++0x03
line.long 0x00 "TCAP3,Timer3 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\n"
group.long 0x34++0x03
line.long 0x00 "TEXCON3,Timer3 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "TEXDB,Timer External Capture Pin De-bounce Enable Bit \nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 5. "TEXIEN,Timer External Capture Interrupt Enable Bit\n" "0: TMx (x= 0~3) pin detection Interrupt Disabled,1: TMx (x= 0~3) pin detection Interrupt Enabled"
bitfld.long 0x00 4. "RSTCAPSEL,Capture Function Selection\n" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "TEXEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx pin" "0: TMx (x= 0~3) pin Disabled,1: TMx (x= 0~3) pin Enabled"
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Capture Pin Edge Detect\n" "0: A Falling edge on TMx (x= 0~3) pin will be..,1: A Rising edge on TMx (x= 0~3) pin will be..,2: Either Rising or Falling edge on TMx (x= 0~3)..,3: Reserved"
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bitfld.long 0x00 0. "TX_PHASE,Timer External Count Phase \n" "0: A Falling edge of external counting pin will..,1: A Rising edge of external counting pin will.."
group.long 0x38++0x03
line.long 0x00 "TEXISR3,Timer3 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the TEXIF status" "0: TMx (x= 0~3) pin interrupt did not occur,1: TMx (x= 0~3) pin interrupt occurred"
tree.end
tree.end
tree "UART"
repeat 2. (list 0. 1.) (list ad:0x40050000 ad:0x40150000)
tree "UART$1"
base $2
rgroup.long 0x00++0x03
line.long 0x00 "UA_RBR,UART Receive Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return an 8-bit data received from UART_RXD pin (LSB first)"
wgroup.long 0x00++0x03
line.long 0x00 "UA_THR,UART Transmit Holding Register"
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UA_IER,UART Interrupt Enable Register"
bitfld.long 0x00 13. "AUTO_CTS_EN,nCTS Auto Flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
bitfld.long 0x00 12. "AUTO_RTS_EN,nRTS Auto Flow Control Enable Bit\nWhen nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TIME_OUT_EN,Receive Buffer Time Out Counter Enable Bit\n" "0: Receive Buffer time out counter Disabled,1: Receive Buffer time out counter Enabled"
bitfld.long 0x00 8. "LIN_IEN,LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode" "0: Lin bus interrupt Disabled,1: Lin bus interrupt Enabled"
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bitfld.long 0x00 6. "WAKE_EN,UART Wake-up Function Enable Bit\n" "0: UART wake-up function Disabled,1: UART wake-up function Enabled when the chip.."
bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable Bit\n" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "TOUT_IEN,RX Time Out Interrupt Enable Bit\n" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable Bit\n" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable Bit\n" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable Bit\n" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable Bit\n" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UA_FCR,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTS_TRI_LEV,nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
bitfld.long 0x00 8. "RX_DIS,Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDA_IF will be set (if RDA_IEN(UA_IER [0]) enabled and an interrupt will be generated).\n" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TFR is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RFR is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UA_LCR,UART Line Control Register"
bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UA_LCR[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: No parity bit,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of STOP Bit \n" "0: One STOP bit is generated in the transmitted..,1: When select 5-bit word length 1.5 STOP bit is.."
bitfld.long 0x00 0.--1. "WLS,Word Length Selection\n" "0: character length is 5-bit,1: character length is 6-bit,2: character length is 7-bit,3: character length is 8-bit"
group.long 0x10++0x03
line.long 0x00 "UA_MCR,UART Modem Control Register"
rbitfld.long 0x00 13. "RTS_ST,nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "LEV_RTS,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 678 and Figure 679 for UART function mode.\nNote2: Refer to Figure 682 and Figure 683 for RS-485 function mode" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with LEV_RTS bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is.." "0: nRTS signal is active,1: nRTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UA_MSR,UART Modem Status Register"
bitfld.long 0x00 8. "LEV_CTS,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
rbitfld.long 0x00 4. "CTS_ST,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is low level voltage logic state"
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bitfld.long 0x00 0. "DCTSF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER[3]) is set to 1.\nWrite 1 to clear this bit to 0" "0,1"
group.long 0x18++0x03
line.long 0x00 "UA_FSR,UART FIFO Status Register"
rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
bitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit indicates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit indicates RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Error Interrupt Flag\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0: No Break error is generated,1: Break error is generated"
bitfld.long 0x00 5. "FEF,Frame Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as a logic 0).\nNote: This bit can be cleared by writing '1' to it" "0: No frame error is generated,1: Frame error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
bitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UA_ISR,UART Interrupt Status Register"
rbitfld.long 0x00 15. "LIN_INT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF (UA_ISR[7]) are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and BUF_ERR_IF (UA_ISR[5]) are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "TOUT_INT,Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4]) and TOUT_IF (UA_ISR[4]) are both set to 1.\n" "0: No time-out interrupt is generated,1: Time-out interrupt is generated"
rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN (UA_IER[3]) and MODEM_IF (UA_ISR[3]) are both set to 1.\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2] and RLS_IF (UA_ISR[2]) are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1]) and THRE_IF (UA_ISR[1]) are both set to 1.\n" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
rbitfld.long 0x00 7. "LIN_IF,LIN Bus Flag (Read Only)\nNote: This bit is read only" "0: None of LINS_HDET_F LIN_BKDET_F BIT_ERR_F..,1: At least one of LINS_HDET_F LIN_BKDET_F.."
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rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set. When BUF_ERR_IF (UA_ISR[5]) is set the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]).." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
rbitfld.long 0x00 4. "TOUT_IF,Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC (UA_TOR[7:0])" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only)\nNote: This bit is reset to 0 when bit DCTSF (UA_MSR[0]) is cleared by a write 1 on DCTSF (UA_MSR[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UA_FSR[6]) FEF (UA_FSR[5]) and PEF (UA_FSR[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL (UA_FCR[7:4]) then the RDA_IF (UA_ISR[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UA_TOR,UART Time Out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time Out Interrupt Comparator\n"
group.long 0x24++0x03
line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable Bit\nNote1: The detail description is shown in UART Controller Baud Rate Generator section.\nNote2: In IrDA mode this bit must disable" "0: Divider X Disabled (the equation of M = 16),1: Divider X Enabled (the equation of M = X+1.."
bitfld.long 0x00 28. "DIV_X_ONE,Divider X Equal to 1\nNote: The detail description is shown in UART Controller Baud Rate Generator section" "0: Divider M = X+1 (the equation of M = X+1 but..,1: Divider M = 1"
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bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X\n" "?,1: This field is used for baud rate calculation in,2: The detail description is shown in UART,?..."
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UA_IRCR,UART IrDA Control Register"
bitfld.long 0x00 6. "INV_RX,IrDA Inverse Receive Input Signal\n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "INV_TX,IrDA Inverse Transmitting Output Signal\n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TX_SELECT,IrDA Receiver/Transmitter Selection Enable Bit\n" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation mode (AUO)..,1: RS-485 Auto Direction Operation mode (AUO).."
bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable Bit\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
bitfld.long 0x00 0.--3. "LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1.\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UA_FUN_SEL,UART Function Select Register"
bitfld.long 0x00 0.--1. "FUN_SEL,Function Select Enable Bit\n" "0: UART function Enabled,1: LIN function Enabled,2: IrDA function Enabled,3: RS-485 function Enabled"
group.long 0x34++0x03
line.long 0x00 "UA_LIN_CTL,UART LIN Control Register"
hexmask.long.byte 0x00 24.--31. 1. "LIN_PID,LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode the frame ID parity can be generated by software or hardware depends on LIN_IDPEN (UA_LIN_CTL[9])"
bitfld.long 0x00 22.--23. "LIN_HEAD_SEL,LIN Header Select\n" "0: The LIN header includes break field,1: The LIN header includes break field and sync..,2: The LIN header includes break field sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "LIN_BS_LEN,LIN Break/Sync Delimiter Length\n\nNote: This bit is used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1 bit..,?,2: The LIN break/sync delimiter length is 2 bit..,3: The LIN break/sync delimiter length is 4 bit.."
bitfld.long 0x00 16.--19. "LIN_BKFL,LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UA_ALT_CSR[19:16]) User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BIT_ERR_EN,Bit Error Detect Enable Bit\n" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
bitfld.long 0x00 11. "LIN_RX_DIS,LIN Receiver Disable Bit\n" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "LIN_BKDET_EN,LIN Break Detection Enable Bit\n" "0: LIN break detection Disabled,1: LIN break detection Enabled"
bitfld.long 0x00 9. "LIN_IDPEN,LIN ID Parity Enable Bit\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "LIN_SHD,LIN TX Send Header Enable Bit\nThe LIN TX header can be break field or break and sync field or break sync and frame ID field it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]).\nNote1: These registers are shadow registers of LIN_TX_EN.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
bitfld.long 0x00 4. "LIN_MUTE_EN,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in LIN slave mode" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "LINS_DUM_EN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode" "0: UA_BAUD updated is writing by software (if no..,1: UA_BAUD is updated at the next received.."
bitfld.long 0x00 2. "LINS_ARS_EN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (DIV_X_EN (UA_BAUD [29]) and DIV_X_ONE (UA_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "LINS_HDET_EN,LIN Slave Header Detection Enable Bit\n" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
bitfld.long 0x00 0. "LINS_EN,LIN Slave Mode Enable Bit\n" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
group.long 0x38++0x03
line.long 0x00 "UA_LIN_SR,UART LIN Status Register"
bitfld.long 0x00 9. "BIT_ERR_F,Bit Error Detect Status Flag\nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BIT_ERR_F (UA_LIN_SR[9]) will be set.\n" "0,1"
bitfld.long 0x00 8. "LIN_BKDET_F,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\n" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "LINS_SYNC_F,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in automatic resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
bitfld.long 0x00 2. "LINS_IDPERR_F,LIN Slave ID Parity Error Flag\nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: no active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "LINS_HERR_F,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
bitfld.long 0x00 0. "LINS_HDET_F,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n" "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
tree.end
repeat.end
tree.end
tree "WDT"
base ad:0x40004000
group.long 0x00++0x03
line.long 0x00 "WTCR,WDT Control Register"
bitfld.long 0x00 31. "DBGACK_WDT,ICE Debug Mode Acknowledge Disable (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 8.--10. "WTIS,WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected" "0: 24 * WDT_CLK,1: 26 * WDT_CLK,2: 28 * WDT_CLK,3: 210 * WDT_CLK,4: 212 * WDT_CLK,5: 214 * WDT_CLK,6: 216 * WDT_CLK,7: 218 * WDT_CLK"
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bitfld.long 0x00 7. "WTE,WDT Enable Bit (Write Protect)\nNote1: This bit is write protected" "0: WDT Disabled (This action will reset the..,1: WDT Enabled"
bitfld.long 0x00 6. "WTIE,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x00 5. "WTWKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
bitfld.long 0x00 4. "WTWKE,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WTCR[3]) is generated to 1 and interrupt enable bit WTIE (WTCR[6]) is enabled the WDT time-out interrupt signal will generate a.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.."
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bitfld.long 0x00 3. "WTIF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
bitfld.long 0x00 2. "WTRF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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bitfld.long 0x00 1. "WTRE,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
bitfld.long 0x00 0. "WTR,Reset WDT Up Counter (Write Protect)\nNote1: This bit is write protected" "0: No effect,1: Reset the internal 18-bit WDT up counter value"
group.long 0x04++0x03
line.long 0x00 "WTCRALT,WDT Alternative Control Register"
bitfld.long 0x00 0.--1. "WTRDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by setting WTR (WTCR[0]) to prevent WDT time-out reset happened" "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,2: WDT Reset Delay Period is 18 * WDT_CLK,3: WDT Reset Delay Period is 3 * WDT_CLK"
tree.end
tree "WWDT"
base ad:0x40004100
wgroup.long 0x00++0x03
line.long 0x00 "WWDTRLD,WWDT Reload Counter Register"
hexmask.long 0x00 0.--31. 1. "WWDTRLD,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F"
group.long 0x04++0x03
line.long 0x00 "WWDTCR,WWDT Control Register"
bitfld.long 0x00 31. "DBGACK_WWDT,ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 16.--21. "WINCMP,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--11. "PERIODSEL,WWDT Counter Prescale Period Selection\n" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
bitfld.long 0x00 1. "WWDTIE,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU.\n" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit\nSet this bit to enable WWDT counter counting\n" "0: WWDT counter is stopped,1: WWDT counter is starting counting"
group.long 0x08++0x03
line.long 0x00 "WWDTSR,WWDT Status Register"
bitfld.long 0x00 1. "WWDTRF,WWDT Time-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches WINCMP (WWDTCR[21:16]).\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches WINCMP value"
rgroup.long 0x0C++0x03
line.long 0x00 "WWDTCVR,WWDT Counter Value Register"
bitfld.long 0x00 0.--5. "WWDTCVAL,WWDT Counter Value\nWWDTCVAL will be updated continuously to monitor 6-bit down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
autoindent.off
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