; -------------------------------------------------------------------------------- ; @Title: ADSP-SC594 On-Chip Peripherals ; @Props: Released ; @Author: KWI, KRZ ; @Changelog: 2020-12-22 KWI ; 2022-08-09 KRZ ; @Manufacturer: Analog Devices ; @Doc: XML generated (BLACKFINXML 1.2), based on: ADSP-SC594-registers.xml, ; ADSP-SC594W-registers.xml ; @Core: Cortex-A5 ; @Chip: ADSP-SC594, ADSP-SC594W ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: peradspsc594.per 15295 2022-10-10 17:34:36Z skrausse $ config 16. 8. AUTOINDENT.PUSH AUTOINDENT.OFF tree "Core Registers (Cortex-A5)" width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" textline " " bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x200++0x0 line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register" rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries" bitfld.long 0x0 1. " TLB_SIZE ,TLB Size" "64,128" textline " " bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,Separate" rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3" rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " OSS ,Outer Shareable Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." textline " " bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x0010++0x00 line.long 0x00 "PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0310++0x00 line.long 0x00 "AFR0,Auxiliary Feature Register 0" hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes" bitfld.long 0x00 18. " BTDIS ,Disable indirect Branch Target Address Cache" "No,Yes" bitfld.long 0x00 17. " RSDIS ,Disable return stack operation" "No,Yes" textline " " bitfld.long 0x00 15.--16. " BP ,Branch prediction policy" "Normal,Taken,Not taken,?..." bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 prefetch,2 prefetches,3 prefetches" bitfld.long 0x00 12. " RADIS ,Disable Data Cache read-allocate mode" "No,Yes" textline " " bitfld.long 0x00 11. " DWBST ,Disable data write bursts to normal non-cacheable memory" "No,Yes" bitfld.long 0x00 10. " DODMBS ,Disable optimized Data Memory Barrier behavior" "No,Yes" bitfld.long 0x00 7. " EXCL ,Exclusive L1/L2 cache control" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SMP ,Data requests with Inner Cacheable Shared attributes are treated as cacheable" "Disabled,Enabled" bitfld.long 0x00 0. " FW ,FW" "Low,High" group.long c15:0x201++0x0 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 6. " NET ,Not early termination" "Not early,Early" bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" textline " " bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" textline " " bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x111++0x0 line.long 0x0 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "Denied,Permitted" textline " " bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "Denied,Permitted" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted" group.long c15:0x0311++0x00 line.long 0x00 "VCR,Virtualization Control Register" bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1" bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1" bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1" textline " " group.long c15:0x000c++0x00 line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address" group.long c15:0x10c++0x00 line.long 0x0 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address" rgroup.long c15:0x1C++0x0 line.long 0x0 "ISR,Interrupt status Register" bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending" bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending" bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending" group.long c15:0x11c++0x0 line.long 0x00 "VIR,Virtualization Interrupt Register" bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1" bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1" bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1" group.long c15:0x400f++0x0 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address" tree.end width 0x08 tree "Memory Management Unit" group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address" bitfld.long 0x00 6. 0. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address" bitfld.long 0x00 6. 0. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated" textline " " bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated" bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable" bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable" bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000" textline " " group.long c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address" group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address" group.long c15:0x0015++0x00 line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register" hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status" group.long c15:0x0115++0x00 line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register" hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status" textline " " group.long c15:0x0047++0x00 line.long 0x00 "PAR,PA Register" hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress" bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured" textline " " bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable" bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back" textline " " bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back" bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful" textline " " group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP" group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate" textline " " group.long c15:0x500f++0x0 line.long 0x00 "TLBHR,TLB Hitmap Register" bitfld.long 0x00 3. " 16MB ,16MB supersections are present in the TLB" "no,yes" bitfld.long 0x00 2. " 1MB ,1MB sections are present in the TLB" "no,yes" bitfld.long 0x00 1. " 16kB ,16kB pages are present in the TLB" "no,yes" bitfld.long 0x00 0. " 4kB ,4kB pages are present in the TLB" "no,yes" textline " " group.long c15:0x10d++0x0 line.long 0x0 "CONTEXT,Context ID Register" hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID" hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID" group.long c15:0x020d++0x00 line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register" hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID" group.long c15:0x030d++0x00 line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register" hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID" group.long c15:0x040d++0x00 line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register" hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID" tree.end width 0x8 tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..." rgroup.long c15:0x1700++0x0 line.long 0x0 "AIDR,Auxiliary ID Register" hexmask.long 0x00 0.--31. 1. " AID ,Auxiliary ID" rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words" group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction" tree.end width 0x8 tree "L2 Preload Engine" rgroup c15:0x000b++0x00 line.long 0x00 "PLEIDR,PLE Identification Register 0" bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present" rgroup c15:0x020b++0x00 line.long 0x00 "PLESR,PLE Status Register" bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running" rgroup c15:0x040b++0x00 line.long 0x00 "PLEFSR,PLE FIFO Status Register" group c15:0x001b++0x00 line.long 0x00 "PLEUAR,PLE User Accessibility Register" bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted" group c15:0x011b++0x00 line.long 0x00 "PLEPCR,PLE Parameters Control Register" tree.end width 12. tree "System Performance Monitor" group.long c15:0xC9++0x0 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled" group.long c15:0x1C9++0x0 line.long 0x0 "PMCNTENSET,Count Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x2C9++0x0 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled" group.long c15:0x3C9++0x0 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" wgroup.long c15:0x4C9++0x0 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" textline " " eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5C9++0x0 line.long 0x0 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..." group.long c15:0xD9++0x0 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 line.long 0x00 "PMCNT,Performance Monitor Count Register" group.long c15:0xE9++0x0 line.long 0x0 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled" group.long c15:0x1E9++0x0 line.long 0x0 "PMINTENSET,Interrupt Enable Set Register" bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2E9++0x0 line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" tree.end width 0xb tree "Debug" width 10. tree "Debug Registers" rgroup c14:0x000--0x000 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " Context ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..." textline " " bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " Security ,Security Extensions implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group c14:0x22--0x22 line.long 0x0 "DBGDSCR,Debug Status and Control Register" bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full" bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full" textline " " bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full" bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full" textline " " bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired" bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing" textline " " bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..." bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded" textline " " bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured" bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled" textline " " bitfld.long 0x0 16. " nSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled" bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled" bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled" bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled" textline " " bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced" bitfld.long 0x0 8. " uExt ,Sticky Undefined Exception" "No exception,Exception" textline " " bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted" bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted" textline " " bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..." bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited" textline " " bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state" textline " " if (((per.long(c14:0x00))&0x01000)==0x00000) group c14:0x007--0x007 line.long 0x0 "DBGVCR,Vector Catch Register" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled" bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" else group c14:0x007--0x007 line.long 0x0 "DBGVCR,Vector Catch Register" bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled" bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled" bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" endif hgroup c14:0x020--0x020 hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)" in group c14:0x023--0x023 line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)" group c14:0x09++0x00 line.long 0x00 "DBGECR,Event Catch Register" bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled" group c14:0x0a++0x00 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal" bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal" wgroup c14:0x21++0x00 line.long 0x00 "DBGITR,Instruction Transfer Register" rgroup c14:0x21++0x00 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCSV ,Program Counter sample value" bitfld.long 0x00 0.--1. " MPCSV ,Meaning of PC sample value" "ARM,Thumb,Jazelle,Thumb" wgroup c14:0x24++0x00 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared" textline " " bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested" bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested" rgroup c14:0x28++0x00 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCSV ,Program Counter sample value" bitfld.long 0x00 0.--1. " MPCSV ,Meaning of PC sample value" "ARM,Thumb,Jazelle,Thumb" rgroup c14:0x29++0x00 line.long 0x00 "DBGCIDSR,Context ID Sampling Register" wgroup c14:0xc0++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup c14:0xc1++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented" group c14:0xc2++0x00 line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register" hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore" group c14:0xc4++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "Not held,Held" bitfld.long 0x00 0. " DBGNOPWRDWN ,DBGNOPWRDWN output signal" "Low,High" group c14:0xc5++0x00 line.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" width 11. tree "Processor Identifier Registers" rgroup c14:0x340--0x340 line.long 0x00 "CPUID,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup c14:0x341--0x341 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." textline " " bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup c14:0x343--0x343 line.long 0x00 "TLBTYPE,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries" textline " " bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128" bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate" rgroup c14:0x348--0x348 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup c14:0x349--0x349 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup c14:0x34a--0x34a line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." rgroup c14:0x34b--0x34b line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature" rgroup c14:0x34c--0x34c line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " OSS ,Outer Shareable Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." textline " " bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup c14:0x34d--0x34d line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup c14:0x34e--0x34e line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup c14:0x34f--0x34f line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." rgroup c14:0x350--0x350 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup c14:0x351--0x351 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..." rgroup c14:0x352--0x352 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c14:0x353--0x353 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup c14:0x354--0x354 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup c14:0x355--0x355 line.long 0x00 "ID_ISAR5,ISA Feature Register 5 (Reserved)" tree.end width 17. tree "Coresight Management Registers" textline " " group c14:0x03bd++0x00 line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register" bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1" bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1" textline " " bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1" bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1" textline " " bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1" bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1" group c14:0x03be++0x00 line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register" bitfld.long 0x00 7. " nDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1" bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1" textline " " bitfld.long 0x00 5. " nDMAIRQ ,External nDMAIRQ" "0,1" bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1" textline " " bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1" bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1" textline " " bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1" bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1" rgroup c14:0x03bf++0x00 line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register" bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1" bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1" textline " " bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1" bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1" textline " " bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1" bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1" textline " " bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1" group c14:0x3c0--0x3c0 line.long 0x0 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group c14:0x3e8--0x3e8 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set" group c14:0x3e9--0x3e9 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared" wgroup c14:0x3ec--0x3ec line.long 0x0 "DBGLAR,Lock Access Register" rgroup c14:0x3ed--0x3ed line.long 0x0 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit" bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked" textline " " bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented" rgroup c14:0x3ee--0x3ee line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled" hgroup c14:0x3f2--0x3f2 hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)" rgroup c14:0x3f3--0x3f3 line.long 0x0 "DBGDEVTYPE,Device Type" bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup c14:0x3f8--0x3f8 line.long 0x00 "DBGPID0,Debug Peripheral ID 0" hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]" rgroup c14:0x3f9--0x3f9 line.long 0x00 "DBGPID1,Debug Peripheral ID 1" hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]" hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]" rgroup c14:0x3fa--0x3fa line.long 0x00 "DBGPID2,Debug Peripheral ID 2" hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled" hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]" rgroup c14:0x3fb--0x3fb line.long 0x00 "DBGPID3,Debug Peripheral ID 3" hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision" hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified" rgroup c14:0x3f4--0x3f4 line.long 0x00 "DBGPID4,Debug Peripheral ID 4" hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code" rgroup c14:0x3fc--0x3fc line.long 0x00 "DBGCID0,Debug Component ID 0" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0" rgroup c14:0x3fd--0x3fd line.long 0x00 "DBGCID1,Debug Component ID 1" hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1" rgroup c14:0x3fe--0x3fe line.long 0x00 "DBGCID2,Debug Component ID 2" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2" rgroup c14:0x3ff--0x3ff line.long 0x00 "DBGCID3,Debug Component ID 3" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3" tree.end tree.end width 6. tree "Breakpoint Registers" group c14:0x40++0x00 line.long 0x00 "BVR0,Breakpoint Value Register 0" group c14:0x50++0x00 line.long 0x00 "BCR0,Breakpoint Control Register 0" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x41++0x00 line.long 0x00 "BVR1,Breakpoint Value Register 1" group c14:0x51++0x00 line.long 0x00 "BCR1,Breakpoint Control Register 1" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x42++0x00 line.long 0x00 "BVR2,Breakpoint Value Register 2" group c14:0x52++0x00 line.long 0x00 "BCR2,Breakpoint Control Register 2" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end width 6. tree "Watchpoint Control Registers" group c14:0x60++0x00 line.long 0x00 "WVR0,Watchpoint Value Register 0" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group c14:0x70--0x70 line.long 0x0 "WCR0,Watchpoint Control Register 0" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x61++0x00 line.long 0x00 "WVR1,Watchpoint Value Register 1" hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1" group c14:0x71--0x71 line.long 0x0 "WCR1,Watchpoint Control Register 1" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x006--0x006 line.long 0x0 "WFAR,Watchpoint Fault Address Register" hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction" textline " " tree.end tree.end width 0x0B sif corename()=="CORTEXA5MPCORE" width 9. base ad:(d.l(c15:0x400f)) tree "Snoop Control Unit (SCU)" group.long 0x00++0x03 line.long 0x00 "SCUCR,SCU Control Register" bitfld.long 0x00 2. " PON ,Parity ON" "Off,On" bitfld.long 0x00 1. " AFEN ,Address filtering enable" "Off,On" bitfld.long 0x00 0. " SCUEN ,SCU enable" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SCUCON,SCU Configuration Register" bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,Reserved,64KB" bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,Reserved,64KB" bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,Reserved,64KB" textline " " bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,Reserved,64KB" bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP" bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP" textline " " bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP" bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP" bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3" group.long 0x08++0x03 line.long 0x00 "SCUSTAT,SCU CPU Power Status Register" bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off" textline " " bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off" bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off" wgroup.long 0x0c++0x03 line.long 0x00 "INV,SCU Invalidate All Register" bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x03 line.long 0x00 "FSAR,Filtering Start Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address" group.long 0x44++0x03 line.long 0x00 "FEAR,Filtering End Address Register" hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address" group.long 0x50++0x03 line.long 0x00 "SAC,SCU Access Control Register" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" group.long 0x54++0x03 line.long 0x00 "SSAC,SCU Secure Access Control Register" bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure" bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure" bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure" bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure" textline " " bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure" bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access" textline " " bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access" bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access" bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access" tree.end width 0xb width 8. tree "Timer and Watchdog Blocks" base ad:(d.l(c15:0x400f))+0x600 group.long 0x00++0xb "Timer" line.long 0x00 "TLR,Timer Load Register" line.long 0x04 "TCR,Timer Counter Register" line.long 0x08 "TCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "TISR,Timer Interrupt Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x20++0x13 "Watchdog" line.long 0x00 "WLR,Watchdog Load Register" line.long 0x04 "WCR,Watchdog Counter Register" line.long 0x08 "WCONR,Watchdog Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog" bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled" bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload" textline " " bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled" line.long 0x0c "WISR,Watchdog Interrupt Status Register" eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1" line.long 0x10 "WRSR,Watchdog Reset Sent Register" eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset" wgroup.long 0x34++0x3 line.long 0x00 "WDR,Watchdog Disable Register" base ad:(d.l(c15:0x400f))+0x200 group.long 0x00++0xb "Global Timer" line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register" line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register" line.long 0x08 "GTCONR,Timer Control Register" hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler" bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment" bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled" bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled" group.long 0x0c++0x3 line.long 0x00 "GTSR,Timer Status Register" eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1" group.long 0x10++0xb line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register" line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register" line.long 0x08 "GTINCR,Auto-increment Register for Comparator" tree.end width 11. endif tree.end AUTOINDENT.POP tree "ARMDBG0" base ad:0x31120000 width 20. group.long 0x0++0x3 line.long 0x00 "ARMDBG0_DIDR,ARMDBG0 Debug ID Register." group.long 0x18++0x3 line.long 0x00 "ARMDBG0_WFAR,ARMDBG0 The Watchpoint Fault Address Register." group.long 0x1C++0x3 line.long 0x00 "ARMDBG0_VCR,ARMDBG0 Vector Catch Register." group.long 0x24++0x3 line.long 0x00 "ARMDBG0_ECR,ARMDBG0 Event Catch Register." group.long 0x28++0x3 line.long 0x00 "ARMDBG0_DSCCR,ARMDBG0 Debug State Cache Control Register." group.long 0x2C++0x3 line.long 0x00 "ARMDBG0_DSMCR,ARMDBG0 Debug State MMU Control Register." group.long 0x80++0x3 line.long 0x00 "ARMDBG0_DTRRX,ARMDBG0 Read Data Transfer Register." group.long 0x84++0x3 line.long 0x00 "ARMDBG0_ITR,ARMDBG0 Instruction Transfer Register." group.long 0x88++0x3 line.long 0x00 "ARMDBG0_DSCR,ARMDBG0 Debug Status and Control Register." group.long 0x8C++0x3 line.long 0x00 "ARMDBG0_DTRTX,ARMDBG0 Write Data Transfer Register." group.long 0x90++0x3 line.long 0x00 "ARMDBG0_DRCR,ARMDBG0 Debug Run Control Register." group.long 0xA0++0x3 line.long 0x00 "ARMDBG0_PCSR,ARMDBG0 Program Counter Sampling Register." group.long 0xA4++0x3 line.long 0x00 "ARMDBG0_CIDSR,ARMDBG0 Context ID Sampling Register." group.long 0x100++0x3 line.long 0x00 "ARMDBG0_BVR0,ARMDBG0 Breakpoint Value Register 0." group.long 0x104++0x3 line.long 0x00 "ARMDBG0_BVR1,ARMDBG0 Breakpoint Value Register 1." group.long 0x108++0x3 line.long 0x00 "ARMDBG0_BVR2,ARMDBG0 Breakpoint Value Register 2." group.long 0x140++0x3 line.long 0x00 "ARMDBG0_BCR0,ARMDBG0 Breakpoint Control Register 0." group.long 0x144++0x3 line.long 0x00 "ARMDBG0_BCR1,ARMDBG0 Breakpoint Control Register 1." group.long 0x148++0x3 line.long 0x00 "ARMDBG0_BCR2,ARMDBG0 Breakpoint Control Register 2." group.long 0x180++0x3 line.long 0x00 "ARMDBG0_WVR0,ARMDBG0 Watchpoint Value Register 0." group.long 0x184++0x3 line.long 0x00 "ARMDBG0_WVR1,ARMDBG0 Watchpoint Value Register 1." group.long 0x1C0++0x3 line.long 0x00 "ARMDBG0_WCR0,ARMDBG0 Watchpoint Control Register 0." group.long 0x1C4++0x3 line.long 0x00 "ARMDBG0_WCR1,ARMDBG0 Watchpoint Control Register 1." group.long 0x300++0x3 line.long 0x00 "ARMDBG0_OSLAR,ARMDBG0 Operating System Lock Access Register." group.long 0x304++0x3 line.long 0x00 "ARMDBG0_OSLSR,ARMDBG0 Operating System Lock Status Register." group.long 0x310++0x3 line.long 0x00 "ARMDBG0_PRCR,ARMDBG0 Device Powerdown and Reset Control Register." group.long 0x314++0x3 line.long 0x00 "ARMDBG0_PRSR,ARMDBG0 Device Powerdown and Reset Status Register." group.long 0xD00++0x3 line.long 0x00 "ARMDBG0_MIDR,ARMDBG0 Main ID Register." group.long 0xD04++0x3 line.long 0x00 "ARMDBG0_CTR,ARMDBG0 Cache Type Register." group.long 0xD08++0x3 line.long 0x00 "ARMDBG0_TCMTR,ARMDBG0 TCM Type Register." group.long 0xD0C++0x3 line.long 0x00 "ARMDBG0_TLBTR,ARMDBG0 TCM Type Register." group.long 0xD10++0x3 line.long 0x00 "ARMDBG0_MPUIR,ARMDBG0 MPU Type Register (alias of MIDR in VMSA)." group.long 0xD14++0x3 line.long 0x00 "ARMDBG0_MPIDR,ARMDBG0 Multiprocessor Affinity Register." group.long 0xD18++0x3 line.long 0x00 "ARMDBG0_MIDRALIAS1,ARMDBG0 Main ID Register (alias at 0xd18)." group.long 0xD1C++0x3 line.long 0x00 "ARMDBG0_MIDRALIAS2,ARMDBG0 Main ID Register (alias at 0xd1c)." group.long 0xD20++0x3 line.long 0x00 "ARMDBG0_ID_PFR0,ARMDBG0 Processor Feature Register 0." group.long 0xD24++0x3 line.long 0x00 "ARMDBG0_ID_PFR1,ARMDBG0 Processor Feature Register 1." group.long 0xD28++0x3 line.long 0x00 "ARMDBG0_ID_DFR0,ARMDBG0 Debug Feature Register 0." group.long 0xD2C++0x3 line.long 0x00 "ARMDBG0_ID_AFR0,ARMDBG0 Auxiliary Feature Register 0." group.long 0xD30++0x3 line.long 0x00 "ARMDBG0_ID_MMFR0,ARMDBG0 Memory Model Feature Register 0." group.long 0xD34++0x3 line.long 0x00 "ARMDBG0_ID_MMFR1,ARMDBG0 Memory Model Feature Register 1." group.long 0xD38++0x3 line.long 0x00 "ARMDBG0_ID_MMFR2,ARMDBG0 Memory Model Feature Register 2." group.long 0xD3C++0x3 line.long 0x00 "ARMDBG0_ID_MMFR3,ARMDBG0 Memory Model Feature Register 3." group.long 0xD40++0x3 line.long 0x00 "ARMDBG0_ID_ISAR0,ARMDBG0 ISA Feature Register 0." group.long 0xD44++0x3 line.long 0x00 "ARMDBG0_ID_ISAR1,ARMDBG0 ISA Feature Register 1." group.long 0xD48++0x3 line.long 0x00 "ARMDBG0_ID_ISAR2,ARMDBG0 ISA Feature Register 2." group.long 0xD4C++0x3 line.long 0x00 "ARMDBG0_ID_ISAR3,ARMDBG0 ISA Feature Register 3." group.long 0xD50++0x3 line.long 0x00 "ARMDBG0_ID_ISAR4,ARMDBG0 ISA Feature Register 4." group.long 0xD54++0x3 line.long 0x00 "ARMDBG0_ID_ISAR5,ARMDBG0 ISA Feature Register 5." group.long 0xEF8++0x3 line.long 0x00 "ARMDBG0_ITMISCOUT,ARMDBG0 Miscellaneous Outputs Integration Register." group.long 0xEFC++0x3 line.long 0x00 "ARMDBG0_ITMISCIN,ARMDBG0 Miscellaneous Inputs Integration Register." group.long 0xF00++0x3 line.long 0x00 "ARMDBG0_ITCTRL,ARMDBG0 Integration Mode Control Register." group.long 0xFA0++0x3 line.long 0x00 "ARMDBG0_CLAIMSET,ARMDBG0 Claim Tag Set Register." group.long 0xFA4++0x3 line.long 0x00 "ARMDBG0_CLAIMCLR,ARMDBG0 Claim Tag Clear Register." group.long 0xFB0++0x3 line.long 0x00 "ARMDBG0_LOCKACCESS,ARMDBG0 Lock Access Register." group.long 0xFB4++0x3 line.long 0x00 "ARMDBG0_LOCKSTATUS,ARMDBG0 Lock Status Register." group.long 0xFB8++0x3 line.long 0x00 "ARMDBG0_AUTHSTATUS,ARMDBG0 Authentication Status Register." group.long 0xFC8++0x3 line.long 0x00 "ARMDBG0_DEVID,ARMDBG0 Device Identifier." group.long 0xFCC++0x3 line.long 0x00 "ARMDBG0_DEVTYPE,ARMDBG0 Device Type Register." group.long 0xFD0++0x3 line.long 0x00 "ARMDBG0_PIR4,ARMDBG0 Peripheral ID Register 4." group.long 0xFE0++0x3 line.long 0x00 "ARMDBG0_PIR0,ARMDBG0 Peripheral ID Register 0." group.long 0xFE4++0x3 line.long 0x00 "ARMDBG0_PIR1,ARMDBG0 Peripheral ID Register 1." group.long 0xFE8++0x3 line.long 0x00 "ARMDBG0_PIR2,ARMDBG0 Peripheral ID Register 2." group.long 0xFEC++0x3 line.long 0x00 "ARMDBG0_PIR3,ARMDBG0 Peripheral ID Register 3." group.long 0xFF0++0x3 line.long 0x00 "ARMDBG0_CIR0,ARMDBG0 Component ID Register 0." group.long 0xFF4++0x3 line.long 0x00 "ARMDBG0_CIR1,ARMDBG0 Component ID Register 1." group.long 0xFF8++0x3 line.long 0x00 "ARMDBG0_CIR2,ARMDBG0 Component ID Register 2." group.long 0xFFC++0x3 line.long 0x00 "ARMDBG0_CIR3,ARMDBG0 Component ID Register 3." tree.end tree "ARMETM0" base ad:0x3112C000 width 22. group.long 0x0++0x3 line.long 0x00 "ARMETM0_CR,ARMETM0 Main Control Register" group.long 0x4++0x3 line.long 0x00 "ARMETM0_CCR,ARMETM0 Configuration Code Register" group.long 0x8++0x3 line.long 0x00 "ARMETM0_TRIGGER,ARMETM0 Trigger Event Register" group.long 0xC++0x3 line.long 0x00 "ARMETM0_ASICCTLR,ARMETM0 ASIC Control Register" group.long 0x10++0x3 line.long 0x00 "ARMETM0_SR,ARMETM0 Status Register" group.long 0x14++0x3 line.long 0x00 "ARMETM0_SCR,ARMETM0 System Configuration Register" group.long 0x18++0x3 line.long 0x00 "ARMETM0_TSSCR,ARMETM0 TraceEnable Start/Stop Control Register" group.long 0x1C++0x3 line.long 0x00 "ARMETM0_TECR2,ARMETM0 TraceEnable Control Register 2" group.long 0x20++0x3 line.long 0x00 "ARMETM0_TEEVR,ARMETM0 TraceEnable Event Register" group.long 0x24++0x3 line.long 0x00 "ARMETM0_TECR1,ARMETM0 TraceEnable Control Register 1" group.long 0x2C++0x3 line.long 0x00 "ARMETM0_FFLR,ARMETM0 FIFOFULL Level Register" group.long 0x30++0x3 line.long 0x00 "ARMETM0_VDEVR,ARMETM0 ViewData Event Register" group.long 0x34++0x3 line.long 0x00 "ARMETM0_VDCR1,ARMETM0 ViewData Control Register 1" group.long 0x3C++0x3 line.long 0x00 "ARMETM0_VDCR3,ARMETM0 ViewData Control Register 3" group.long 0x40++0x3 line.long 0x00 "ARMETM0_ACVR1,ARMETM0 Address Comparator Value Register 1" group.long 0x44++0x3 line.long 0x00 "ARMETM0_ACVR2,ARMETM0 Address Comparator Value Register 2" group.long 0x48++0x3 line.long 0x00 "ARMETM0_ACVR3,ARMETM0 Address Comparator Value Register 3" group.long 0x4C++0x3 line.long 0x00 "ARMETM0_ACVR4,ARMETM0 Address Comparator Value Register 4" group.long 0x50++0x3 line.long 0x00 "ARMETM0_ACVR5,ARMETM0 Address Comparator Value Register 5" group.long 0x54++0x3 line.long 0x00 "ARMETM0_ACVR6,ARMETM0 Address Comparator Value Register 6" group.long 0x58++0x3 line.long 0x00 "ARMETM0_ACVR7,ARMETM0 Address Comparator Value Register 7" group.long 0x5C++0x3 line.long 0x00 "ARMETM0_ACVR8,ARMETM0 Address Comparator Value Register 8" group.long 0x80++0x3 line.long 0x00 "ARMETM0_ACTR1,ARMETM0 Address Comparator Access Type Register 1" group.long 0x84++0x3 line.long 0x00 "ARMETM0_ACTR2,ARMETM0 Address Comparator Access Type Register 2" group.long 0x88++0x3 line.long 0x00 "ARMETM0_ACTR3,ARMETM0 Address Comparator Access Type Register 3" group.long 0x8C++0x3 line.long 0x00 "ARMETM0_ACTR4,ARMETM0 Address Comparator Access Type Registers 4" group.long 0x90++0x3 line.long 0x00 "ARMETM0_ACTR5,ARMETM0 Address Comparator Access Type Register 5" group.long 0x94++0x3 line.long 0x00 "ARMETM0_ACTR6,ARMETM0 Address Comparator Access Type Register 6" group.long 0x98++0x3 line.long 0x00 "ARMETM0_ACTR7,ARMETM0 Address Comparator Access Type Register 7" group.long 0x9C++0x3 line.long 0x00 "ARMETM0_ACTR8,ARMETM0 Address Comparator Access Type Register 8" group.long 0xC0++0x3 line.long 0x00 "ARMETM0_DCVR1,ARMETM0 Data Comparator Value Register 1" group.long 0xC8++0x3 line.long 0x00 "ARMETM0_DCVR3,ARMETM0 Data Comparator Value Register 3" group.long 0x100++0x3 line.long 0x00 "ARMETM0_DCMR1,ARMETM0 Data Comparator Mask Register 1" group.long 0x108++0x3 line.long 0x00 "ARMETM0_DCMR3,ARMETM0 Data Comparator Mask Register 3" group.long 0x140++0x3 line.long 0x00 "ARMETM0_CNTRLDVR1,ARMETM0 Counter Reload Value Register 1" group.long 0x144++0x3 line.long 0x00 "ARMETM0_CNTRLDVR2,ARMETM0 Counter Reload Value Register 2" group.long 0x150++0x3 line.long 0x00 "ARMETM0_CNTENR1,ARMETM0 Counter Enable Register 1" group.long 0x154++0x3 line.long 0x00 "ARMETM0_CNTENR2,ARMETM0 Counter Enable Register 2" group.long 0x160++0x3 line.long 0x00 "ARMETM0_CNTRLDEVR1,ARMETM0 Counter Reload Event Register 1" group.long 0x164++0x3 line.long 0x00 "ARMETM0_CNTRLDEVR2,ARMETM0 Counter Reload Event Register 2" group.long 0x170++0x3 line.long 0x00 "ARMETM0_CNTVR1,ARMETM0 Counter Value Register 1" group.long 0x174++0x3 line.long 0x00 "ARMETM0_CNTVR2,ARMETM0 Counter Value Register 2" group.long 0x180++0x3 line.long 0x00 "ARMETM0_SQ12EVR,ARMETM0 Sequencer State Transition 12 Event Register" group.long 0x184++0x3 line.long 0x00 "ARMETM0_SQ21EVR,ARMETM0 Sequencer State Transition 21 Event Register" group.long 0x188++0x3 line.long 0x00 "ARMETM0_SQ23EVR,ARMETM0 Sequencer State Transition 23 Event Register" group.long 0x18C++0x3 line.long 0x00 "ARMETM0_SQ31EVR,ARMETM0 Sequencer State Transition 31 Event Register" group.long 0x190++0x3 line.long 0x00 "ARMETM0_SQ32EVR,ARMETM0 Sequencer State Transition 32 Event Register" group.long 0x194++0x3 line.long 0x00 "ARMETM0_SQ13EVR,ARMETM0 Sequencer State Transition 13 Event Register" group.long 0x19C++0x3 line.long 0x00 "ARMETM0_SQR,ARMETM0 Current Sequencer State Register" group.long 0x1A0++0x3 line.long 0x00 "ARMETM0_EXTOUTEVR1,ARMETM0 External Output Event Register 1" group.long 0x1A4++0x3 line.long 0x00 "ARMETM0_EXTOUTEVR2,ARMETM0 External Output Event Register 2" group.long 0x1B0++0x3 line.long 0x00 "ARMETM0_CIDCVR,ARMETM0 Context ID Comparator Value Register" group.long 0x1BC++0x3 line.long 0x00 "ARMETM0_CIDCMR,ARMETM0 Context ID Comparator Mask Register" group.long 0x1E0++0x3 line.long 0x00 "ARMETM0_SYNCFR,ARMETM0 Synchronization Frequency Register" group.long 0x1E4++0x3 line.long 0x00 "ARMETM0_IDR,ARMETM0 ETM ID Register" group.long 0x1E8++0x3 line.long 0x00 "ARMETM0_CCER,ARMETM0 Configuration Code Extension Register" group.long 0x1EC++0x3 line.long 0x00 "ARMETM0_EXTINSELR,ARMETM0 Extended External Input Selection Register" group.long 0x1F8++0x3 line.long 0x00 "ARMETM0_TSEVR,ARMETM0 Timestamp Event Register" group.long 0x1FC++0x3 line.long 0x00 "ARMETM0_AUXCR,ARMETM0 Auxiliary Control Register" group.long 0x200++0x3 line.long 0x00 "ARMETM0_TRACEIDR,ARMETM0 CoreSight Trace ID Register" group.long 0x208++0x3 line.long 0x00 "ARMETM0_ETMAUXIDR,ARMETM0 Auxiliary ID Register" group.long 0x314++0x3 line.long 0x00 "ARMETM0_PDSR,ARMETM0 Power-Down Status Register" group.long 0xEDC++0x3 line.long 0x00 "ARMETM0_ITMISCOUT,ARMETM0 Miscellaneous Outputs Register" group.long 0xEE0++0x3 line.long 0x00 "ARMETM0_ITMISCIN,ARMETM0 Miscellaneous Inputs Register" group.long 0xEE8++0x3 line.long 0x00 "ARMETM0_ITTRIGGERREQ,ARMETM0 Trigger Request Register" group.long 0xEEC++0x3 line.long 0x00 "ARMETM0_ITATBDATA0,ARMETM0 ATB Data Register 0" group.long 0xEF0++0x3 line.long 0x00 "ARMETM0_ITATBCTR2,ARMETM0 ATB Control Register 2" group.long 0xEF4++0x3 line.long 0x00 "ARMETM0_ITATBCTR1,ARMETM0 ATB Control Register 1" group.long 0xEF8++0x3 line.long 0x00 "ARMETM0_ITATBCTR0,ARMETM0 ATB Control Register 0" group.long 0xF00++0x3 line.long 0x00 "ARMETM0_ITCTRL,ARMETM0 Integration Mode Control Register" group.long 0xFA0++0x3 line.long 0x00 "ARMETM0_CLAIMSET,ARMETM0 Claim Tag Set Register" group.long 0xFA4++0x3 line.long 0x00 "ARMETM0_CLAIMCLR,ARMETM0 Claim Tag Clear Register" group.long 0xFB0++0x3 line.long 0x00 "ARMETM0_LAR,ARMETM0 Lock Access Register" group.long 0xFB4++0x3 line.long 0x00 "ARMETM0_LSR,ARMETM0 Lock Status Register" group.long 0xFB8++0x3 line.long 0x00 "ARMETM0_AUTHSTATUS,ARMETM0 Authentication Status Register" group.long 0xFC8++0x3 line.long 0x00 "ARMETM0_DEVID,ARMETM0 Device Identifier" group.long 0xFCC++0x3 line.long 0x00 "ARMETM0_DEVTYPE,ARMETM0 Device Type Register" group.long 0xFD0++0x3 line.long 0x00 "ARMETM0_PIR4,ARMETM0 Peripheral ID Register 4" group.long 0xFD4++0x3 line.long 0x00 "ARMETM0_PIR5,ARMETM0 Peripheral ID Register 5" group.long 0xFD8++0x3 line.long 0x00 "ARMETM0_PIR6,ARMETM0 Peripheral ID Register 6" group.long 0xFDC++0x3 line.long 0x00 "ARMETM0_PIR7,ARMETM0 Peripheral ID Register 7" group.long 0xFE0++0x3 line.long 0x00 "ARMETM0_PIR0,ARMETM0 Peripheral ID Register 0" group.long 0xFE4++0x3 line.long 0x00 "ARMETM0_PIR1,ARMETM0 Peripheral ID Register 1" group.long 0xFE8++0x3 line.long 0x00 "ARMETM0_PIR2,ARMETM0 Peripheral ID Register 2" group.long 0xFEC++0x3 line.long 0x00 "ARMETM0_PIR3,ARMETM0 Peripheral ID Register 3" group.long 0xFF0++0x3 line.long 0x00 "ARMETM0_CIR0,ARMETM0 Component ID Register 0" group.long 0xFF4++0x3 line.long 0x00 "ARMETM0_CIR1,ARMETM0 Component ID Register 1" group.long 0xFF8++0x3 line.long 0x00 "ARMETM0_CIR2,ARMETM0 Component ID Register 2" group.long 0xFFC++0x3 line.long 0x00 "ARMETM0_CIR3,ARMETM0 Component ID Register 3" tree.end tree "ARMPMU0" base ad:0x31121000 width 22. group.long 0x0++0x3 line.long 0x00 "ARMPMU0_PMXEVCNTR0,ARMPMU0 PM0 Counter Register." group.long 0x4++0x3 line.long 0x00 "ARMPMU0_PMXEVCNTR1,ARMPMU0 PM1 Counter Register." group.long 0x7C++0x3 line.long 0x00 "ARMPMU0_PMCCNTR,ARMPMU0 Cycle Count Register." group.long 0x400++0x3 line.long 0x00 "ARMPMU0_PMXEVTYPER0,ARMPMU0 PM0 Event Type Register." group.long 0x404++0x3 line.long 0x00 "ARMPMU0_PMXEVTYPER1,ARMPMU0 PM0 Event Type Register." group.long 0x47C++0x3 line.long 0x00 "ARMPMU0_PMCCFILTR,ARMPMU0 Cycle Count Filter Control Register." group.long 0xC00++0x3 line.long 0x00 "ARMPMU0_PMCNTENSET,ARMPMU0 Count Enable Set Register." group.long 0xC20++0x3 line.long 0x00 "ARMPMU0_PMCNTENCLR,ARMPMU0 Count Enable Clear Register." group.long 0xC40++0x3 line.long 0x00 "ARMPMU0_PMINTENSET,ARMPMU0 Interrupt Enable Set Register." group.long 0xC60++0x3 line.long 0x00 "ARMPMU0_PMINTENCLR,ARMPMU0 Interrupt Enable Clear Register." group.long 0xC80++0x3 line.long 0x00 "ARMPMU0_PMOVSR,ARMPMU0 Overflow Flag Status Register." group.long 0xCA0++0x3 line.long 0x00 "ARMPMU0_PMSWINC,ARMPMU0 Software Increment Register." group.long 0xE00++0x3 line.long 0x00 "ARMPMU0_PMCFGR,ARMPMU0 Configuration Register." group.long 0xE04++0x3 line.long 0x00 "ARMPMU0_PMCR,ARMPMU0 Control Register." group.long 0xE08++0x3 line.long 0x00 "ARMPMU0_PMUSERENR,ARMPMU0 User Enable Register." group.long 0xE20++0x3 line.long 0x00 "ARMPMU0_PMCEID0,ARMPMU0 Common Event Identification Register 0." group.long 0xE24++0x3 line.long 0x00 "ARMPMU0_PMCEID1,ARMPMU0 Common Event Identification Register 1." group.long 0xFB0++0x3 line.long 0x00 "ARMPMU0_PMLAR,ARMPMU0 Lock Access Register." group.long 0xFB4++0x3 line.long 0x00 "ARMPMU0_PMLSR,ARMPMU0 Lock Status Register." group.long 0xFB8++0x3 line.long 0x00 "ARMPMU0_PMAUTHSTATUS,ARMPMU0 Authentication Status Register." group.long 0xFCC++0x3 line.long 0x00 "ARMPMU0_PMDEVTYPE,ARMPMU0 Device Type Register." group.long 0xFD0++0x3 line.long 0x00 "ARMPMU0_PIR4,ARMPMU0 Peripheral ID Register 4." group.long 0xFE0++0x3 line.long 0x00 "ARMPMU0_PIR0,ARMPMU0 Peripheral ID Register 0." group.long 0xFE4++0x3 line.long 0x00 "ARMPMU0_PIR1,ARMPMU0 Peripheral ID Register 1." group.long 0xFE8++0x3 line.long 0x00 "ARMPMU0_PIR2,ARMPMU0 Peripheral ID Register 2." group.long 0xFEC++0x3 line.long 0x00 "ARMPMU0_PIR3,ARMPMU0 Peripheral ID Register 3." group.long 0xFF0++0x3 line.long 0x00 "ARMPMU0_CIR0,ARMPMU0 Component ID Register 0." group.long 0xFF4++0x3 line.long 0x00 "ARMPMU0_CIR1,ARMPMU0 Component ID Register 1." group.long 0xFF8++0x3 line.long 0x00 "ARMPMU0_CIR2,ARMPMU0 Component ID Register 2." group.long 0xFFC++0x3 line.long 0x00 "ARMPMU0_CIR3,ARMPMU0 Component ID Register 3." tree.end tree "ARMROM0" base ad:0x31110000 width 20. group.long 0x0++0x3 line.long 0x00 "ARMROM0_ROMENTRY00,ARMROM0 ROM Entry 00" group.long 0x4++0x3 line.long 0x00 "ARMROM0_ROMENTRY01,ARMROM0 ROM Entry 01" group.long 0x8++0x3 line.long 0x00 "ARMROM0_ROMENTRY02,ARMROM0 ROM Entry 02" group.long 0xC++0x3 line.long 0x00 "ARMROM0_ROMENTRY03,ARMROM0 ROM Entry 03" group.long 0x10++0x3 line.long 0x00 "ARMROM0_ROMENTRY04,ARMROM0 ROM Entry 04" group.long 0x14++0x3 line.long 0x00 "ARMROM0_ROMENTRY05,ARMROM0 ROM Entry 05" group.long 0x18++0x3 line.long 0x00 "ARMROM0_ROMENTRY06,ARMROM0 ROM Entry 06" group.long 0x1C++0x3 line.long 0x00 "ARMROM0_ROMENTRY07,ARMROM0 ROM Entry 07" group.long 0x20++0x3 line.long 0x00 "ARMROM0_ROMENTRY08,ARMROM0 ROM Entry 08" group.long 0x24++0x3 line.long 0x00 "ARMROM0_ROMENTRY09,ARMROM0 ROM Entry 09" group.long 0x28++0x3 line.long 0x00 "ARMROM0_ROMENTRY10,ARMROM0 ROM Entry 10" group.long 0x2C++0x3 line.long 0x00 "ARMROM0_ROMENTRY11,ARMROM0 ROM Entry 11" group.long 0x30++0x3 line.long 0x00 "ARMROM0_ROMENTRY12,ARMROM0 ROM Entry 12" group.long 0x34++0x3 line.long 0x00 "ARMROM0_ROMENTRY13,ARMROM0 ROM Entry 13" group.long 0x38++0x3 line.long 0x00 "ARMROM0_ROMENTRY14,ARMROM0 ROM Entry 14" group.long 0x3C++0x3 line.long 0x00 "ARMROM0_ROMENTRY15,ARMROM0 ROM Entry 15" tree.end tree "ASRC (Asynchronous Sample Rate Converter)" tree "ASRC0" base ad:0x310C9240 width 13. group.long 0x0++0x3 line.long 0x00 "ASRC0_CTL01,ASRC0 Control Register for ASRC 0 and 1" bitfld.long 0x00 31. " EN1 ,Enable SRC 1" "0,1" bitfld.long 0x00 30. " MPHASE1 ,Matched-phase Mode 1" "0,1" bitfld.long 0x00 28.--29. " LENOUT1 ,Length Output 1" "0,1,2,3" newline bitfld.long 0x00 26.--27. " SMODEOUT1 ,Serial Mode Output 1" "0,1,2,3" bitfld.long 0x00 25. " DITHER1 ,Dither Enable 1" "0,1" bitfld.long 0x00 24. " SOFTMUTE1 ,Soft Mute 1" "0,1" newline bitfld.long 0x00 22.--23. " DEEMPHASIS1 ,De-emphasize Audio 1" "0,1,2,3" bitfld.long 0x00 21. " BYP1 ,Bypass 1" "0,1" bitfld.long 0x00 18.--20. " SMODEIN1 ,Serial Mode Input 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17. " AUTOMUTE1 ,Auto Hard Mute 1" "0,1" bitfld.long 0x00 16. " HARDMUTE1 ,Hard Mute 1" "0,1" bitfld.long 0x00 15. " EN0 ,Enable SRC 0" "0,1" newline bitfld.long 0x00 14. " MPHASE0 ,Matched-phase Mode 0" "0,1" bitfld.long 0x00 12.--13. " LENOUT0 ,Length Output 0" "0,1,2,3" bitfld.long 0x00 10.--11. " SMODEOUT0 ,Serial Mode Output 0" "0,1,2,3" newline bitfld.long 0x00 9. " DITHER0 ,Dither Enable 0" "0,1" bitfld.long 0x00 8. " SOFTMUTE0 ,Soft Mute 0" "0,1" bitfld.long 0x00 6.--7. " DEEMPHASIS0 ,De-emphasize Audio 0" "0,1,2,3" newline bitfld.long 0x00 5. " BYP0 ,Bypass 0" "0,1" bitfld.long 0x00 2.--4. " SMODEIN0 ,Serial Mode Input 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AUTOMUTE0 ,Auto Hard Mute 0" "0,1" newline bitfld.long 0x00 0. " HARDMUTE0 ,Hard Mute 0" "0,1" group.long 0x4++0x3 line.long 0x00 "ASRC0_CTL23,ASRC0 Control Register for ASRC 2 and 3" bitfld.long 0x00 31. " EN3 ,Enable SRC 3" "0,1" bitfld.long 0x00 30. " MPHASE3 ,Matched-phase Mode 3" "0,1" bitfld.long 0x00 28.--29. " LENOUT3 ,Length Output 3" "0,1,2,3" newline bitfld.long 0x00 26.--27. " SMODEOUT3 ,Serial Mode Output 3" "0,1,2,3" bitfld.long 0x00 25. " DITHER3 ,Dither Enable 3" "0,1" bitfld.long 0x00 24. " SOFTMUTE3 ,Soft Mute 3" "0,1" newline bitfld.long 0x00 22.--23. " DEEMPHASIS3 ,De-emphasize Audio 3" "0,1,2,3" bitfld.long 0x00 21. " BYP3 ,Bypass 3" "0,1" bitfld.long 0x00 18.--20. " SMODEIN3 ,Serial Mode Input 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17. " AUTOMUTE3 ,Auto Hard Mute 3" "0,1" bitfld.long 0x00 16. " HARDMUTE3 ,Hard Mute 3" "0,1" bitfld.long 0x00 15. " EN2 ,Enable SRC 2" "0,1" newline bitfld.long 0x00 14. " MPHASE2 ,Matched-phase Mode 2" "0,1" bitfld.long 0x00 12.--13. " LENOUT2 ,Length Output 2" "0,1,2,3" bitfld.long 0x00 10.--11. " SMODEOUT2 ,Serial Mode Output 2" "0,1,2,3" newline bitfld.long 0x00 9. " DITHER2 ,Dither Enable 2" "0,1" bitfld.long 0x00 8. " SOFTMUTE2 ,Soft Mute 2" "0,1" bitfld.long 0x00 6.--7. " DEEMPHASIS2 ,De-emphasize Audio 2" "0,1,2,3" newline bitfld.long 0x00 5. " BYP2 ,Bypass 2" "0,1" bitfld.long 0x00 2.--4. " SMODEIN2 ,Serial Mode Input 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AUTOMUTE2 ,Auto Hard Mute 2" "0,1" newline bitfld.long 0x00 0. " HARDMUTE2 ,Hard Mute 2" "0,1" group.long 0x8++0x3 line.long 0x00 "ASRC0_MUTE,ASRC0 Mute Register" bitfld.long 0x00 3. " MUTE3 ,Mute ASRC3" "0,1" bitfld.long 0x00 2. " MUTE2 ,Mute ASRC2" "0,1" bitfld.long 0x00 1. " MUTE1 ,Mute ASRC1" "0,1" newline bitfld.long 0x00 0. " MUTE0 ,Mute ASRC0" "0,1" group.long 0x20++0x3 line.long 0x00 "ASRC0_RAT01,ASRC0 Ratio Register for ASRC 0 and 1" bitfld.long 0x00 31. " MUTEOUT1 ,Mute Status for ASRC1" "0,1" hexmask.long.word 0x00 16.--30. 1. " RATIO1 ,Sampling Ratio of Frame Syncs for ASRC1" bitfld.long 0x00 15. " MUTEOUT0 ,Mute Status for ASRC0" "0,1" newline hexmask.long.word 0x00 0.--14. 1. " RATIO0 ,Sampling Ratio of Frame Syncs for ASRC0" group.long 0x24++0x3 line.long 0x00 "ASRC0_RAT23,ASRC0 Ratio Register for ASRC 2 and 3" bitfld.long 0x00 31. " MUTEOUT3 ,Mute Status for ASRC3" "0,1" hexmask.long.word 0x00 16.--30. 1. " RATIO3 ,Sampling Ratio of Frame Syncs for ASRC3" bitfld.long 0x00 15. " MUTEOUT2 ,Mute Status for ASRC2" "0,1" newline hexmask.long.word 0x00 0.--14. 1. " RATIO2 ,Sampling Ratio of Frame Syncs for ASRC2" tree.end tree "ASRC1" base ad:0x310CA240 width 13. group.long 0x0++0x3 line.long 0x00 "ASRC1_CTL01,ASRC1 Control Register for ASRC 0 and 1" bitfld.long 0x00 31. " EN1 ,Enable SRC 1" "0,1" bitfld.long 0x00 30. " MPHASE1 ,Matched-phase Mode 1" "0,1" bitfld.long 0x00 28.--29. " LENOUT1 ,Length Output 1" "0,1,2,3" newline bitfld.long 0x00 26.--27. " SMODEOUT1 ,Serial Mode Output 1" "0,1,2,3" bitfld.long 0x00 25. " DITHER1 ,Dither Enable 1" "0,1" bitfld.long 0x00 24. " SOFTMUTE1 ,Soft Mute 1" "0,1" newline bitfld.long 0x00 22.--23. " DEEMPHASIS1 ,De-emphasize Audio 1" "0,1,2,3" bitfld.long 0x00 21. " BYP1 ,Bypass 1" "0,1" bitfld.long 0x00 18.--20. " SMODEIN1 ,Serial Mode Input 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17. " AUTOMUTE1 ,Auto Hard Mute 1" "0,1" bitfld.long 0x00 16. " HARDMUTE1 ,Hard Mute 1" "0,1" bitfld.long 0x00 15. " EN0 ,Enable SRC 0" "0,1" newline bitfld.long 0x00 14. " MPHASE0 ,Matched-phase Mode 0" "0,1" bitfld.long 0x00 12.--13. " LENOUT0 ,Length Output 0" "0,1,2,3" bitfld.long 0x00 10.--11. " SMODEOUT0 ,Serial Mode Output 0" "0,1,2,3" newline bitfld.long 0x00 9. " DITHER0 ,Dither Enable 0" "0,1" bitfld.long 0x00 8. " SOFTMUTE0 ,Soft Mute 0" "0,1" bitfld.long 0x00 6.--7. " DEEMPHASIS0 ,De-emphasize Audio 0" "0,1,2,3" newline bitfld.long 0x00 5. " BYP0 ,Bypass 0" "0,1" bitfld.long 0x00 2.--4. " SMODEIN0 ,Serial Mode Input 0" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AUTOMUTE0 ,Auto Hard Mute 0" "0,1" newline bitfld.long 0x00 0. " HARDMUTE0 ,Hard Mute 0" "0,1" group.long 0x4++0x3 line.long 0x00 "ASRC1_CTL23,ASRC1 Control Register for ASRC 2 and 3" bitfld.long 0x00 31. " EN3 ,Enable SRC 3" "0,1" bitfld.long 0x00 30. " MPHASE3 ,Matched-phase Mode 3" "0,1" bitfld.long 0x00 28.--29. " LENOUT3 ,Length Output 3" "0,1,2,3" newline bitfld.long 0x00 26.--27. " SMODEOUT3 ,Serial Mode Output 3" "0,1,2,3" bitfld.long 0x00 25. " DITHER3 ,Dither Enable 3" "0,1" bitfld.long 0x00 24. " SOFTMUTE3 ,Soft Mute 3" "0,1" newline bitfld.long 0x00 22.--23. " DEEMPHASIS3 ,De-emphasize Audio 3" "0,1,2,3" bitfld.long 0x00 21. " BYP3 ,Bypass 3" "0,1" bitfld.long 0x00 18.--20. " SMODEIN3 ,Serial Mode Input 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17. " AUTOMUTE3 ,Auto Hard Mute 3" "0,1" bitfld.long 0x00 16. " HARDMUTE3 ,Hard Mute 3" "0,1" bitfld.long 0x00 15. " EN2 ,Enable SRC 2" "0,1" newline bitfld.long 0x00 14. " MPHASE2 ,Matched-phase Mode 2" "0,1" bitfld.long 0x00 12.--13. " LENOUT2 ,Length Output 2" "0,1,2,3" bitfld.long 0x00 10.--11. " SMODEOUT2 ,Serial Mode Output 2" "0,1,2,3" newline bitfld.long 0x00 9. " DITHER2 ,Dither Enable 2" "0,1" bitfld.long 0x00 8. " SOFTMUTE2 ,Soft Mute 2" "0,1" bitfld.long 0x00 6.--7. " DEEMPHASIS2 ,De-emphasize Audio 2" "0,1,2,3" newline bitfld.long 0x00 5. " BYP2 ,Bypass 2" "0,1" bitfld.long 0x00 2.--4. " SMODEIN2 ,Serial Mode Input 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " AUTOMUTE2 ,Auto Hard Mute 2" "0,1" newline bitfld.long 0x00 0. " HARDMUTE2 ,Hard Mute 2" "0,1" group.long 0x8++0x3 line.long 0x00 "ASRC1_MUTE,ASRC1 Mute Register" bitfld.long 0x00 3. " MUTE3 ,Mute ASRC3" "0,1" bitfld.long 0x00 2. " MUTE2 ,Mute ASRC2" "0,1" bitfld.long 0x00 1. " MUTE1 ,Mute ASRC1" "0,1" newline bitfld.long 0x00 0. " MUTE0 ,Mute ASRC0" "0,1" group.long 0x20++0x3 line.long 0x00 "ASRC1_RAT01,ASRC1 Ratio Register for ASRC 0 and 1" bitfld.long 0x00 31. " MUTEOUT1 ,Mute Status for ASRC1" "0,1" hexmask.long.word 0x00 16.--30. 1. " RATIO1 ,Sampling Ratio of Frame Syncs for ASRC1" bitfld.long 0x00 15. " MUTEOUT0 ,Mute Status for ASRC0" "0,1" newline hexmask.long.word 0x00 0.--14. 1. " RATIO0 ,Sampling Ratio of Frame Syncs for ASRC0" group.long 0x24++0x3 line.long 0x00 "ASRC1_RAT23,ASRC1 Ratio Register for ASRC 2 and 3" bitfld.long 0x00 31. " MUTEOUT3 ,Mute Status for ASRC3" "0,1" hexmask.long.word 0x00 16.--30. 1. " RATIO3 ,Sampling Ratio of Frame Syncs for ASRC3" bitfld.long 0x00 15. " MUTEOUT2 ,Mute Status for ASRC2" "0,1" newline hexmask.long.word 0x00 0.--14. 1. " RATIO2 ,Sampling Ratio of Frame Syncs for ASRC2" tree.end tree.end sif cpuis("ADSP-SC594W") tree "CANFD0" base ad:0x31046000 width 27. group.long 0x0++0x3 line.long 0x00 "CANFD0_CFG,CANFD0 Configuration Register" bitfld.long 0x00 31. " DIS ,Module Disable" "0,1" bitfld.long 0x00 30. " FRZ ,Freeze Mode Enable" "0,1" bitfld.long 0x00 29. " RFEN ,Rx FIFO Enable" "0,1" newline bitfld.long 0x00 28. " HALT ,Freeze Mode Enable" "0,1" bitfld.long 0x00 27. " NOTRDY ,FlexCAN Not Ready" "0,1" bitfld.long 0x00 26. " WAKMSK ,Wakeup Interrupt Mask" "0,1" newline bitfld.long 0x00 25. " SOFTRST ,Soft Reset" "0,1" bitfld.long 0x00 24. " FRZACK ,Freeze Mode Acknowledge" "0,1" bitfld.long 0x00 23. " SUPVEN ,Supervisor Mode" "0,1" newline bitfld.long 0x00 22. " SLFWAKEN ,Self Wakeup Enable" "0,1" bitfld.long 0x00 21. " WRNEN ,Warning Interrupt Enable" "0,1" bitfld.long 0x00 20. " LPMACK ,Low Power Mode Enable" "0,1" newline bitfld.long 0x00 19. " WSFLTREN ,Wakeup Source" "0,1" bitfld.long 0x00 18. " DOZEN ,Doze Mode Enable" "0,1" bitfld.long 0x00 17. " SRXDIS ,Self Reception Enable" "0,1" newline bitfld.long 0x00 16. " IRMQEN ,Rx Masking And Queue Enable" "0,1" bitfld.long 0x00 15. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 14. " PNETEN ,Pretended Networking Enable" "0,1" newline bitfld.long 0x00 13. " LPRIOEN ,Local Priority Enable" "0,1" bitfld.long 0x00 12. " ABORTEN ,Abort Enable" "0,1" bitfld.long 0x00 11. " FDEN ,CANFD Enable" "0,1" newline bitfld.long 0x00 8.--9. " IDAM ,ID Acceptance Mode" "0,1,2,3" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the Last Message Buffer" group.long 0x4++0x3 line.long 0x00 "CANFD0_CTL1,CANFD0 Control1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ," bitfld.long 0x00 22.--23. " RJW ," "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PSEG2 ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " BOFFMSK ," "0,1" bitfld.long 0x00 14. " ERRMSK ," "0,1" newline bitfld.long 0x00 13. " CLKSRC ," "0,1" bitfld.long 0x00 12. " LBEN ," "0,1" bitfld.long 0x00 11. " TWRNMSK ," "0,1" newline bitfld.long 0x00 10. " RWRNMSK ," "0,1" bitfld.long 0x00 7. " SMP ," "0,1" bitfld.long 0x00 6. " BOFFREC ," "0,1" newline bitfld.long 0x00 5. " TSYNEN ," "0,1" bitfld.long 0x00 4. " LBUF ," "0,1" bitfld.long 0x00 3. " LOMEN ," "0,1" newline bitfld.long 0x00 0.--2. " PROPSEG ," "0,1,2,3,4,5,6,7" group.long 0x8++0x3 line.long 0x00 "CANFD0_TMR,CANFD0 Timer Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ," group.long 0x10++0x3 line.long 0x00 "CANFD0_RX_MB_GMSK,CANFD0 Receive Mailbox Global Mask Register" bitfld.long 0x00 31. " MB31 ," "0,1" bitfld.long 0x00 30. " MB30 ," "0,1" bitfld.long 0x00 29. " MB29 ," "0,1" newline bitfld.long 0x00 28. " MB28 ," "0,1" bitfld.long 0x00 27. " MB27 ," "0,1" bitfld.long 0x00 26. " MB26 ," "0,1" newline bitfld.long 0x00 25. " MB25 ," "0,1" bitfld.long 0x00 24. " MB24 ," "0,1" bitfld.long 0x00 23. " MB23 ," "0,1" newline bitfld.long 0x00 22. " MB22 ," "0,1" bitfld.long 0x00 21. " MB21 ," "0,1" bitfld.long 0x00 20. " MB20 ," "0,1" newline bitfld.long 0x00 19. " MB19 ," "0,1" bitfld.long 0x00 18. " MB18 ," "0,1" bitfld.long 0x00 17. " MB17 ," "0,1" newline bitfld.long 0x00 16. " MB16 ," "0,1" bitfld.long 0x00 15. " MB15 ," "0,1" bitfld.long 0x00 14. " MB14 ," "0,1" newline bitfld.long 0x00 13. " MB13 ," "0,1" bitfld.long 0x00 12. " MB12 ," "0,1" bitfld.long 0x00 11. " MB11 ," "0,1" newline bitfld.long 0x00 10. " MB10 ," "0,1" bitfld.long 0x00 9. " MB09 ," "0,1" bitfld.long 0x00 8. " MB08 ," "0,1" newline bitfld.long 0x00 7. " MB07 ," "0,1" bitfld.long 0x00 6. " MB06 ," "0,1" bitfld.long 0x00 5. " MB05 ," "0,1" newline bitfld.long 0x00 4. " MB04 ," "0,1" bitfld.long 0x00 3. " MB03 ," "0,1" bitfld.long 0x00 2. " MB02 ," "0,1" newline bitfld.long 0x00 1. " MB01 ," "0,1" bitfld.long 0x00 0. " MB00 ," "0,1" group.long 0x14++0x3 line.long 0x00 "CANFD0_RX_14_MSK,CANFD0 Receive Mailbox14 Mask Register" group.long 0x18++0x3 line.long 0x00 "CANFD0_RX_15_MSK,CANFD0 Receive Mailbox15 Mask Register" group.long 0x1C++0x3 line.long 0x00 "CANFD0_ECR,CANFD0 Error Count Register" hexmask.long.byte 0x00 24.--31. 1. " RXERRCNTF ," hexmask.long.byte 0x00 16.--23. 1. " TXERRCNTF ," hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ," newline hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ," group.long 0x20++0x3 line.long 0x00 "CANFD0_ESR1,CANFD0 Error and Status1 Register" bitfld.long 0x00 31. " B1ERRF ," "0,1" bitfld.long 0x00 30. " B0ERRF ," "0,1" bitfld.long 0x00 28. " CRCERRF ," "0,1" newline bitfld.long 0x00 27. " FRMERRF ," "0,1" bitfld.long 0x00 26. " STFERRF ," "0,1" bitfld.long 0x00 21. " ERROVR ," "0,1" newline bitfld.long 0x00 20. " ERRINTF ," "0,1" bitfld.long 0x00 19. " BOFFDONEINT ," "0,1" bitfld.long 0x00 18. " SYNC ," "0,1" newline bitfld.long 0x00 17. " TXWRNINT ," "0,1" bitfld.long 0x00 16. " RXWRNINT ," "0,1" bitfld.long 0x00 15. " B1ERR ," "0,1" newline bitfld.long 0x00 14. " B0ERR ," "0,1" bitfld.long 0x00 13. " ACKERR ," "0,1" bitfld.long 0x00 12. " CRCERR ," "0,1" newline bitfld.long 0x00 11. " FRMERR ," "0,1" bitfld.long 0x00 10. " STFERR ," "0,1" bitfld.long 0x00 9. " TXWRN ," "0,1" newline bitfld.long 0x00 8. " RXWRN ," "0,1" bitfld.long 0x00 7. " IDLE ," "0,1" bitfld.long 0x00 6. " TXINPROG ," "0,1" newline bitfld.long 0x00 4.--5. " FLTCONF ," "0,1,2,3" bitfld.long 0x00 3. " RXINPROG ," "0,1" bitfld.long 0x00 2. " BOFFINT ," "0,1" newline bitfld.long 0x00 1. " ERRINT ," "0,1" bitfld.long 0x00 0. " WAKINT ," "0,1" group.long 0x24++0x3 line.long 0x00 "CANFD0_IMSK2,CANFD0 Mailbox Interrupt Mask2 Register" bitfld.long 0x00 31. " MB63 ,Message Buffer 63 Interrupt Mask" "0,1" bitfld.long 0x00 30. " MB62 ,Message Buffer 62 Interrupt Mask" "0,1" bitfld.long 0x00 29. " MB61 ,Message Buffer 61 Interrupt Mask" "0,1" newline bitfld.long 0x00 28. " MB60 ,Message Buffer 60 Interrupt Mask" "0,1" bitfld.long 0x00 27. " MB59 ,Message Buffer 59 Interrupt Mask" "0,1" bitfld.long 0x00 26. " MB58 ,Message Buffer 58 Interrupt Mask" "0,1" newline bitfld.long 0x00 25. " MB57 ,Message Buffer 57 Interrupt Mask" "0,1" bitfld.long 0x00 24. " MB56 ,Message Buffer 56 Interrupt Mask" "0,1" bitfld.long 0x00 23. " MB55 ,Message Buffer 55 Interrupt Mask" "0,1" newline bitfld.long 0x00 22. " MB54 ,Message Buffer 54 Interrupt Mask" "0,1" bitfld.long 0x00 21. " MB53 ,Message Buffer 53 Interrupt Mask" "0,1" bitfld.long 0x00 20. " MB52 ,Message Buffer 52 Interrupt Mask" "0,1" newline bitfld.long 0x00 19. " MB51 ,Message Buffer 51 Interrupt Mask" "0,1" bitfld.long 0x00 18. " MB50 ,Message Buffer 50 Interrupt Mask" "0,1" bitfld.long 0x00 17. " MB49 ,Message Buffer 49 Interrupt Mask" "0,1" newline bitfld.long 0x00 16. " MB48 ,Message Buffer 48 Interrupt Mask" "0,1" bitfld.long 0x00 15. " MB47 ,Message Buffer 47 Interrupt Mask" "0,1" bitfld.long 0x00 14. " MB46 ,Message Buffer 46 Interrupt Mask" "0,1" newline bitfld.long 0x00 13. " MB45 ,Message Buffer 45 Interrupt Mask" "0,1" bitfld.long 0x00 12. " MB44 ,Message Buffer 44 Interrupt Mask" "0,1" bitfld.long 0x00 11. " MB43 ,Message Buffer 43 Interrupt Mask" "0,1" newline bitfld.long 0x00 10. " MB42 ,Message Buffer 42 Interrupt Mask" "0,1" bitfld.long 0x00 9. " MB41 ,Message Buffer 41 Interrupt Mask" "0,1" bitfld.long 0x00 8. " MB40 ,Message Buffer 40 Interrupt Mask" "0,1" newline bitfld.long 0x00 7. " MB39 ,Message Buffer 39 Interrupt Mask" "0,1" bitfld.long 0x00 6. " MB38 ,Message Buffer 38 Interrupt Mask" "0,1" bitfld.long 0x00 5. " MB37 ,Message Buffer 37 Interrupt Mask" "0,1" newline bitfld.long 0x00 4. " MB36 ,Message Buffer 36 Interrupt Mask" "0,1" bitfld.long 0x00 3. " MB35 ,Message Buffer 35 Interrupt Mask" "0,1" bitfld.long 0x00 2. " MB34 ,Message Buffer 34 Interrupt Mask" "0,1" newline bitfld.long 0x00 1. " MB33 ,Message Buffer 33 Interrupt Mask" "0,1" bitfld.long 0x00 0. " MB32 ,Message Buffer 32 Interrupt Mask" "0,1" group.long 0x28++0x3 line.long 0x00 "CANFD0_IMSK1,CANFD0 Mailbox Interrupt Mask1 Register" bitfld.long 0x00 31. " MB31 ,Messge Buffer31 Interrupt Mask" "0,1" bitfld.long 0x00 30. " MB30 ,Messge Buffer30 Interrupt Mask" "0,1" bitfld.long 0x00 29. " MB29 ,Messge Buffer29 Interrupt Mask" "0,1" newline bitfld.long 0x00 28. " MB28 ,Messge Buffer28 Interrupt Mask" "0,1" bitfld.long 0x00 27. " MB27 ,Messge Buffer27 Interrupt Mask" "0,1" bitfld.long 0x00 26. " MB26 ,Messge Buffer26 Interrupt Mask" "0,1" newline bitfld.long 0x00 25. " MB25 ,Messge Buffer25 Interrupt Mask" "0,1" bitfld.long 0x00 24. " MB24 ,Messge Buffer24 Interrupt Mask" "0,1" bitfld.long 0x00 23. " MB23 ,Messge Buffer23 Interrupt Mask" "0,1" newline bitfld.long 0x00 22. " MB22 ,Messge Buffer22 Interrupt Mask" "0,1" bitfld.long 0x00 21. " MB21 ,Messge Buffer21 Interrupt Mask" "0,1" bitfld.long 0x00 20. " MB20 ,Messge Buffer20 Interrupt Mask" "0,1" newline bitfld.long 0x00 19. " MB19 ,Messge Buffer19 Interrupt Mask" "0,1" bitfld.long 0x00 18. " MB18 ,Messge Buffer18 Interrupt Mask" "0,1" bitfld.long 0x00 17. " MB17 ,Messge Buffer17 Interrupt Mask" "0,1" newline bitfld.long 0x00 16. " MB16 ,Messge Buffer16 Interrupt Mask" "0,1" bitfld.long 0x00 15. " MB15 ,Messge Buffer15 Interrupt Mask" "0,1" bitfld.long 0x00 14. " MB14 ,Messge Buffer14 Interrupt Mask" "0,1" newline bitfld.long 0x00 13. " MB13 ,Messge Buffer13 Interrupt Mask" "0,1" bitfld.long 0x00 12. " MB12 ,Messge Buffer12 Interrupt Mask" "0,1" bitfld.long 0x00 11. " MB11 ,Messge Buffer11 Interrupt Mask" "0,1" newline bitfld.long 0x00 10. " MB10 ,Messge Buffer10 Interrupt Mask" "0,1" bitfld.long 0x00 9. " MB09 ,Messge Buffer09 Interrupt Mask" "0,1" bitfld.long 0x00 8. " MB08 ,Messge Buffer08 Interrupt Mask" "0,1" newline bitfld.long 0x00 7. " MB07 ,Messge Buffer07 Interrupt Mask" "0,1" bitfld.long 0x00 6. " MB06 ,Messge Buffer06 Interrupt Mask" "0,1" bitfld.long 0x00 5. " MB05 ,Messge Buffer05 Interrupt Mask" "0,1" newline bitfld.long 0x00 4. " MB04 ,Messge Buffer04 Interrupt Mask" "0,1" bitfld.long 0x00 3. " MB03 ,Messge Buffer03 Interrupt Mask" "0,1" bitfld.long 0x00 2. " MB02 ,Messge Buffer02 Interrupt Mask" "0,1" newline bitfld.long 0x00 1. " MB01 ,Messge Buffer01 Interrupt Mask" "0,1" bitfld.long 0x00 0. " MB00 ,Messge Buffer00 Interrupt Mask" "0,1" group.long 0x2C++0x3 line.long 0x00 "CANFD0_IFLG2,CANFD0 Mailbox Interrupt Flag2 Register" bitfld.long 0x00 31. " MB63 ,Message Buffer 63 Interrupt Flag" "0,1" bitfld.long 0x00 30. " MB62 ,Message Buffer 62 Interrupt Flag" "0,1" bitfld.long 0x00 29. " MB61 ,Message Buffer 61 Interrupt Flag" "0,1" newline bitfld.long 0x00 28. " MB60 ,Message Buffer 60 Interrupt Flag" "0,1" bitfld.long 0x00 27. " MB59 ,Message Buffer 59 Interrupt Flag" "0,1" bitfld.long 0x00 26. " MB58 ,Message Buffer 58 Interrupt Flag" "0,1" newline bitfld.long 0x00 25. " MB57 ,Message Buffer 57 Interrupt Flag" "0,1" bitfld.long 0x00 24. " MB56 ,Message Buffer 56 Interrupt Flag" "0,1" bitfld.long 0x00 23. " MB55 ,Message Buffer 55 Interrupt Flag" "0,1" newline bitfld.long 0x00 22. " MB54 ,Message Buffer 54 Interrupt Flag" "0,1" bitfld.long 0x00 21. " MB53 ,Message Buffer 53 Interrupt Flag" "0,1" bitfld.long 0x00 20. " MB52 ,Message Buffer 52 Interrupt Flag" "0,1" newline bitfld.long 0x00 19. " MB51 ,Message Buffer 51 Interrupt Flag" "0,1" bitfld.long 0x00 18. " MB50 ,Message Buffer 50 Interrupt Flag" "0,1" bitfld.long 0x00 17. " MB49 ,Message Buffer 49 Interrupt Flag" "0,1" newline bitfld.long 0x00 16. " MB48 ,Message Buffer 48 Interrupt Flag" "0,1" bitfld.long 0x00 15. " MB47 ,Message Buffer 47 Interrupt Flag" "0,1" bitfld.long 0x00 14. " MB46 ,Message Buffer 46 Interrupt Flag" "0,1" newline bitfld.long 0x00 13. " MB45 ,Message Buffer 45 Interrupt Flag" "0,1" bitfld.long 0x00 12. " MB44 ,Message Buffer 44 Interrupt Flag" "0,1" bitfld.long 0x00 11. " MB43 ,Message Buffer 43 Interrupt Flag" "0,1" newline bitfld.long 0x00 10. " MB42 ,Message Buffer 42 Interrupt Flag" "0,1" bitfld.long 0x00 9. " MB41 ,Message Buffer 41 Interrupt Flag" "0,1" bitfld.long 0x00 8. " MB40 ,Message Buffer 40 Interrupt Flag" "0,1" newline bitfld.long 0x00 7. " MB39 ,Message Buffer 39 Interrupt Flag" "0,1" bitfld.long 0x00 6. " MB38 ,Message Buffer 38 Interrupt Flag" "0,1" bitfld.long 0x00 5. " MB37 ,Message Buffer 37 Interrupt Flag" "0,1" newline bitfld.long 0x00 4. " MB36 ,Message Buffer 36 Interrupt Flag" "0,1" bitfld.long 0x00 3. " MB35 ,Message Buffer 35 Interrupt Flag" "0,1" bitfld.long 0x00 2. " MB34 ,Message Buffer 34 Interrupt Flag" "0,1" newline bitfld.long 0x00 1. " MB33 ,Message Buffer 33 Interrupt Flag" "0,1" bitfld.long 0x00 0. " MB32 ,Message Buffer 32 Interrupt Flag" "0,1" group.long 0x30++0x3 line.long 0x00 "CANFD0_IFLG1,CANFD0 Mailbox Interrupt Flag1 Register" bitfld.long 0x00 31. " MB31 ,Message Buffer 31 Interrupt Flag" "0,1" bitfld.long 0x00 30. " MB30 ,Message Buffer 30 Interrupt Flag" "0,1" bitfld.long 0x00 29. " MB29 ,Message Buffer 29 Interrupt Flag" "0,1" newline bitfld.long 0x00 28. " MB28 ,Message Buffer 28 Interrupt Flag" "0,1" bitfld.long 0x00 27. " MB27 ,Message Buffer 27 Interrupt Flag" "0,1" bitfld.long 0x00 26. " MB26 ,Message Buffer 26 Interrupt Flag" "0,1" newline bitfld.long 0x00 25. " MB25 ,Message Buffer 25 Interrupt Flag" "0,1" bitfld.long 0x00 24. " MB24 ,Message Buffer 24 Interrupt Flag" "0,1" bitfld.long 0x00 23. " MB23 ,Message Buffer 23 Interrupt Flag" "0,1" newline bitfld.long 0x00 22. " MB22 ,Message Buffer 22 Interrupt Flag" "0,1" bitfld.long 0x00 21. " MB21 ,Message Buffer 21 Interrupt Flag" "0,1" bitfld.long 0x00 20. " MB20 ,Message Buffer 20 Interrupt Flag" "0,1" newline bitfld.long 0x00 19. " MB19 ,Message Buffer 19 Interrupt Flag" "0,1" bitfld.long 0x00 18. " MB18 ,Message Buffer 18 Interrupt Flag" "0,1" bitfld.long 0x00 17. " MB17 ,Message Buffer 17 Interrupt Flag" "0,1" newline bitfld.long 0x00 16. " MB16 ,Message Buffer 16 Interrupt Flag" "0,1" bitfld.long 0x00 15. " MB15 ,Message Buffer 15 Interrupt Flag" "0,1" bitfld.long 0x00 14. " MB14 ,Message Buffer 14 Interrupt Flag" "0,1" newline bitfld.long 0x00 13. " MB13 ,Message Buffer 13 Interrupt Flag" "0,1" bitfld.long 0x00 12. " MB12 ,Message Buffer 12 Interrupt Flag" "0,1" bitfld.long 0x00 11. " MB11 ,Message Buffer 11 Interrupt Flag" "0,1" newline bitfld.long 0x00 10. " MB10 ,Message Buffer 10 Interrupt Flag" "0,1" bitfld.long 0x00 9. " MB09 ,Message Buffer 9 Interrupt Flag" "0,1" bitfld.long 0x00 8. " MB08 ,Message Buffer 8 Interrupt Flag" "0,1" newline bitfld.long 0x00 7. " MB07 ,Message Buffer 7 Interrupt Flag" "0,1" bitfld.long 0x00 6. " MB06 ,Message Buffer 6 Interrupt Flag" "0,1" bitfld.long 0x00 5. " MB05 ,Message Buffer 5 Interrupt Flag" "0,1" newline bitfld.long 0x00 4. " MB04 ,Message Buffer 4 Interrupt Flag" "0,1" bitfld.long 0x00 3. " MB03 ,Message Buffer 3 Interrupt Flag" "0,1" bitfld.long 0x00 2. " MB02 ,Message Buffer 2 Interrupt Flag" "0,1" newline bitfld.long 0x00 1. " MB01 ,Message Buffer 1 Interrupt Flag" "0,1" bitfld.long 0x00 0. " MB00 ,Message Buffer 0 Interrupt Flag" "0,1" group.long 0x34++0x3 line.long 0x00 "CANFD0_CTL2,CANFD0 Control2 Register" bitfld.long 0x00 31. " ERRMSKF ," "0,1" bitfld.long 0x00 30. " BOFFDONEIMSK ," "0,1" bitfld.long 0x00 29. " ECRWREN ," "0,1" newline bitfld.long 0x00 28. " WRMFRZEN ," "0,1" bitfld.long 0x00 24.--27. " RFFNUM ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19.--23. " TXASDLY ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRPRIO ," "0,1" bitfld.long 0x00 17. " RRS ," "0,1" bitfld.long 0x00 16. " EACEN ," "0,1" newline bitfld.long 0x00 15. " TMRSRC_SEL ," "0,1" bitfld.long 0x00 14. " PREXEN ," "0,1" bitfld.long 0x00 12. " ISOFDEN ," "0,1" newline bitfld.long 0x00 11. " EDFLTDIS ," "0,1" group.long 0x38++0x3 line.long 0x00 "CANFD0_ESR2,CANFD0 Error and Status2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTXMB ," bitfld.long 0x00 14. " VPS ," "0,1" bitfld.long 0x00 13. " IMB ," "0,1" group.long 0x44++0x3 line.long 0x00 "CANFD0_CRC,CANFD0 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MB ," hexmask.long.word 0x00 0.--14. 1. " TX ," group.long 0x48++0x3 line.long 0x00 "CANFD0_RX_FIFO_GMSK,CANFD0 Receive FIFO Global Mask Register" bitfld.long 0x00 31. " VALUE31 ," "0,1" bitfld.long 0x00 30. " VALUE30 ," "0,1" bitfld.long 0x00 29. " VALUE29 ," "0,1" newline bitfld.long 0x00 28. " VALUE28 ," "0,1" bitfld.long 0x00 27. " VALUE27 ," "0,1" bitfld.long 0x00 26. " VALUE26 ," "0,1" newline bitfld.long 0x00 25. " VALUE25 ," "0,1" bitfld.long 0x00 24. " VALUE24 ," "0,1" bitfld.long 0x00 23. " VALUE23 ," "0,1" newline bitfld.long 0x00 22. " VALUE22 ," "0,1" bitfld.long 0x00 21. " VALUE21 ," "0,1" bitfld.long 0x00 20. " VALUE20 ," "0,1" newline bitfld.long 0x00 19. " VALUE19 ," "0,1" bitfld.long 0x00 18. " VALUE18 ," "0,1" bitfld.long 0x00 17. " VALUE17 ," "0,1" newline bitfld.long 0x00 16. " VALUE16 ," "0,1" bitfld.long 0x00 15. " VALUE15 ," "0,1" bitfld.long 0x00 14. " VALUE14 ," "0,1" newline bitfld.long 0x00 13. " VALUE13 ," "0,1" bitfld.long 0x00 12. " VALUE12 ," "0,1" bitfld.long 0x00 11. " VALUE11 ," "0,1" newline bitfld.long 0x00 10. " VALUE10 ," "0,1" bitfld.long 0x00 9. " VALUE9 ," "0,1" bitfld.long 0x00 8. " VALUE8 ," "0,1" newline bitfld.long 0x00 7. " VALUE7 ," "0,1" bitfld.long 0x00 6. " VALUE6 ," "0,1" bitfld.long 0x00 5. " VALUE5 ," "0,1" newline bitfld.long 0x00 4. " VALUE4 ," "0,1" bitfld.long 0x00 3. " VALUE3 ," "0,1" bitfld.long 0x00 2. " VALUE2 ," "0,1" newline bitfld.long 0x00 1. " VALUE1 ," "0,1" bitfld.long 0x00 0. " VALUE0 ," "0,1" group.long 0x4C++0x3 line.long 0x00 "CANFD0_RX_FIFO,CANFD0 Receive FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ," group.long 0x50++0x3 line.long 0x00 "CANFD0_TIMING,CANFD0 Can Bit Timing Register" bitfld.long 0x00 31. " BTF ," "0,1" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ," bitfld.long 0x00 16.--20. " ERJW ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--15. " EPROPSEG ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5.--9. " EPSEG1 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x880++0x3 line.long 0x00 "CANFD0_RX_IMSK0,CANFD0 Receive Individual Mask Register" group.long 0x884++0x3 line.long 0x00 "CANFD0_RX_IMSK1,CANFD0 Receive Individual Mask Register" group.long 0x888++0x3 line.long 0x00 "CANFD0_RX_IMSK2,CANFD0 Receive Individual Mask Register" group.long 0x88C++0x3 line.long 0x00 "CANFD0_RX_IMSK3,CANFD0 Receive Individual Mask Register" group.long 0x890++0x3 line.long 0x00 "CANFD0_RX_IMSK4,CANFD0 Receive Individual Mask Register" group.long 0x894++0x3 line.long 0x00 "CANFD0_RX_IMSK5,CANFD0 Receive Individual Mask Register" group.long 0x898++0x3 line.long 0x00 "CANFD0_RX_IMSK6,CANFD0 Receive Individual Mask Register" group.long 0x89C++0x3 line.long 0x00 "CANFD0_RX_IMSK7,CANFD0 Receive Individual Mask Register" group.long 0x8A0++0x3 line.long 0x00 "CANFD0_RX_IMSK8,CANFD0 Receive Individual Mask Register" group.long 0x8A4++0x3 line.long 0x00 "CANFD0_RX_IMSK9,CANFD0 Receive Individual Mask Register" group.long 0x8A8++0x3 line.long 0x00 "CANFD0_RX_IMSK10,CANFD0 Receive Individual Mask Register" group.long 0x8AC++0x3 line.long 0x00 "CANFD0_RX_IMSK11,CANFD0 Receive Individual Mask Register" group.long 0x8B0++0x3 line.long 0x00 "CANFD0_RX_IMSK12,CANFD0 Receive Individual Mask Register" group.long 0x8B4++0x3 line.long 0x00 "CANFD0_RX_IMSK13,CANFD0 Receive Individual Mask Register" group.long 0x8B8++0x3 line.long 0x00 "CANFD0_RX_IMSK14,CANFD0 Receive Individual Mask Register" group.long 0x8BC++0x3 line.long 0x00 "CANFD0_RX_IMSK15,CANFD0 Receive Individual Mask Register" group.long 0x8C0++0x3 line.long 0x00 "CANFD0_RX_IMSK16,CANFD0 Receive Individual Mask Register" group.long 0x8C4++0x3 line.long 0x00 "CANFD0_RX_IMSK17,CANFD0 Receive Individual Mask Register" group.long 0x8C8++0x3 line.long 0x00 "CANFD0_RX_IMSK18,CANFD0 Receive Individual Mask Register" group.long 0x8CC++0x3 line.long 0x00 "CANFD0_RX_IMSK19,CANFD0 Receive Individual Mask Register" group.long 0x8D0++0x3 line.long 0x00 "CANFD0_RX_IMSK20,CANFD0 Receive Individual Mask Register" group.long 0x8D4++0x3 line.long 0x00 "CANFD0_RX_IMSK21,CANFD0 Receive Individual Mask Register" group.long 0x8D8++0x3 line.long 0x00 "CANFD0_RX_IMSK22,CANFD0 Receive Individual Mask Register" group.long 0x8DC++0x3 line.long 0x00 "CANFD0_RX_IMSK23,CANFD0 Receive Individual Mask Register" group.long 0x8E0++0x3 line.long 0x00 "CANFD0_RX_IMSK24,CANFD0 Receive Individual Mask Register" group.long 0x8E4++0x3 line.long 0x00 "CANFD0_RX_IMSK25,CANFD0 Receive Individual Mask Register" group.long 0x8E8++0x3 line.long 0x00 "CANFD0_RX_IMSK26,CANFD0 Receive Individual Mask Register" group.long 0x8EC++0x3 line.long 0x00 "CANFD0_RX_IMSK27,CANFD0 Receive Individual Mask Register" group.long 0x8F0++0x3 line.long 0x00 "CANFD0_RX_IMSK28,CANFD0 Receive Individual Mask Register" group.long 0x8F4++0x3 line.long 0x00 "CANFD0_RX_IMSK29,CANFD0 Receive Individual Mask Register" group.long 0x8F8++0x3 line.long 0x00 "CANFD0_RX_IMSK30,CANFD0 Receive Individual Mask Register" group.long 0x8FC++0x3 line.long 0x00 "CANFD0_RX_IMSK31,CANFD0 Receive Individual Mask Register" group.long 0x900++0x3 line.long 0x00 "CANFD0_RX_IMSK32,CANFD0 Receive Individual Mask Register" group.long 0x904++0x3 line.long 0x00 "CANFD0_RX_IMSK33,CANFD0 Receive Individual Mask Register" group.long 0x908++0x3 line.long 0x00 "CANFD0_RX_IMSK34,CANFD0 Receive Individual Mask Register" group.long 0x90C++0x3 line.long 0x00 "CANFD0_RX_IMSK35,CANFD0 Receive Individual Mask Register" group.long 0x910++0x3 line.long 0x00 "CANFD0_RX_IMSK36,CANFD0 Receive Individual Mask Register" group.long 0x914++0x3 line.long 0x00 "CANFD0_RX_IMSK37,CANFD0 Receive Individual Mask Register" group.long 0x918++0x3 line.long 0x00 "CANFD0_RX_IMSK38,CANFD0 Receive Individual Mask Register" group.long 0x91C++0x3 line.long 0x00 "CANFD0_RX_IMSK39,CANFD0 Receive Individual Mask Register" group.long 0x920++0x3 line.long 0x00 "CANFD0_RX_IMSK40,CANFD0 Receive Individual Mask Register" group.long 0x924++0x3 line.long 0x00 "CANFD0_RX_IMSK41,CANFD0 Receive Individual Mask Register" group.long 0x928++0x3 line.long 0x00 "CANFD0_RX_IMSK42,CANFD0 Receive Individual Mask Register" group.long 0x92C++0x3 line.long 0x00 "CANFD0_RX_IMSK43,CANFD0 Receive Individual Mask Register" group.long 0x930++0x3 line.long 0x00 "CANFD0_RX_IMSK44,CANFD0 Receive Individual Mask Register" group.long 0x934++0x3 line.long 0x00 "CANFD0_RX_IMSK45,CANFD0 Receive Individual Mask Register" group.long 0x938++0x3 line.long 0x00 "CANFD0_RX_IMSK46,CANFD0 Receive Individual Mask Register" group.long 0x93C++0x3 line.long 0x00 "CANFD0_RX_IMSK47,CANFD0 Receive Individual Mask Register" group.long 0x940++0x3 line.long 0x00 "CANFD0_RX_IMSK48,CANFD0 Receive Individual Mask Register" group.long 0x944++0x3 line.long 0x00 "CANFD0_RX_IMSK49,CANFD0 Receive Individual Mask Register" group.long 0x948++0x3 line.long 0x00 "CANFD0_RX_IMSK50,CANFD0 Receive Individual Mask Register" group.long 0x94C++0x3 line.long 0x00 "CANFD0_RX_IMSK51,CANFD0 Receive Individual Mask Register" group.long 0x950++0x3 line.long 0x00 "CANFD0_RX_IMSK52,CANFD0 Receive Individual Mask Register" group.long 0x954++0x3 line.long 0x00 "CANFD0_RX_IMSK53,CANFD0 Receive Individual Mask Register" group.long 0x958++0x3 line.long 0x00 "CANFD0_RX_IMSK54,CANFD0 Receive Individual Mask Register" group.long 0x95C++0x3 line.long 0x00 "CANFD0_RX_IMSK55,CANFD0 Receive Individual Mask Register" group.long 0x960++0x3 line.long 0x00 "CANFD0_RX_IMSK56,CANFD0 Receive Individual Mask Register" group.long 0x964++0x3 line.long 0x00 "CANFD0_RX_IMSK57,CANFD0 Receive Individual Mask Register" group.long 0x968++0x3 line.long 0x00 "CANFD0_RX_IMSK58,CANFD0 Receive Individual Mask Register" group.long 0x96C++0x3 line.long 0x00 "CANFD0_RX_IMSK59,CANFD0 Receive Individual Mask Register" group.long 0x970++0x3 line.long 0x00 "CANFD0_RX_IMSK60,CANFD0 Receive Individual Mask Register" group.long 0x974++0x3 line.long 0x00 "CANFD0_RX_IMSK61,CANFD0 Receive Individual Mask Register" group.long 0x978++0x3 line.long 0x00 "CANFD0_RX_IMSK62,CANFD0 Receive Individual Mask Register" group.long 0x97C++0x3 line.long 0x00 "CANFD0_RX_IMSK63,CANFD0 Receive Individual Mask Register" group.long 0xAE0++0x3 line.long 0x00 "CANFD0_MEC,CANFD0 Memory Error Control Register" bitfld.long 0x00 31. " ECRWRDIS ," "0,1" bitfld.long 0x00 19. " HNCIMSK ," "0,1" bitfld.long 0x00 18. " INCEMSK ," "0,1" newline bitfld.long 0x00 16. " CEIMSK ," "0,1" bitfld.long 0x00 15. " HAERRIEN ," "0,1" bitfld.long 0x00 14. " IAERRIEN ," "0,1" newline bitfld.long 0x00 13. " EXTERRIEN ," "0,1" bitfld.long 0x00 9. " RERDIS ," "0,1" bitfld.long 0x00 8. " ECCDIS ," "0,1" newline bitfld.long 0x00 7. " NCERRFRZEN ," "0,1" group.long 0xAE4++0x3 line.long 0x00 "CANFD0_ERR_IADDR,CANFD0 Error Injection Address Register" hexmask.long.word 0x00 0.--13. 1. " VALUE ," group.long 0xAE8++0x3 line.long 0x00 "CANFD0_ERR_IDP,CANFD0 Error Injection Data Pattern Register" group.long 0xAEC++0x3 line.long 0x00 "CANFD0_ERR_IPP,CANFD0 Error Injection Parity Pattern Register" bitfld.long 0x00 24.--28. " PFLIP3 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PFLIP2 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " PFLIP1 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. " PFLIP0 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAF0++0x3 line.long 0x00 "CANFD0_ERR_RADDR,CANFD0 Error Report Address Register" bitfld.long 0x00 24. " NCERR ," "0,1" bitfld.long 0x00 16.--18. " RDREQID ," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--13. 1. " VALUE ," group.long 0xAF4++0x3 line.long 0x00 "CANFD0_ERR_RDAT,CANFD0 Error Report Data Register" group.long 0xAF8++0x3 line.long 0x00 "CANFD0_ERR_RSYN,CANFD0 Error Report Syndrome Register" bitfld.long 0x00 31. " BEN3 ," "0,1" bitfld.long 0x00 24.--28. " SYND3 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " BEN2 ," "0,1" newline bitfld.long 0x00 16.--20. " SYND2 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " BEN1 ," "0,1" bitfld.long 0x00 8.--12. " SYND1 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7. " BEN0 ," "0,1" bitfld.long 0x00 0.--4. " SYND0 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAFC++0x3 line.long 0x00 "CANFD0_ERR_STAT,CANFD0 Error Status Register" bitfld.long 0x00 19. " HNCEI ," "0,1" bitfld.long 0x00 18. " INCEI ," "0,1" bitfld.long 0x00 16. " CEI ," "0,1" newline bitfld.long 0x00 3. " HNCEIOV ," "0,1" bitfld.long 0x00 2. " INCEIOV ," "0,1" bitfld.long 0x00 0. " CEIOV ," "0,1" group.long 0xB00++0x3 line.long 0x00 "CANFD0_PN_CTL1,CANFD0 Pretended Networking Control1 Register" bitfld.long 0x00 17. " WTOFMSK ," "0,1" bitfld.long 0x00 16. " WUMFMSK ," "0,1" hexmask.long.byte 0x00 8.--15. 1. " MATCHCNT ," newline bitfld.long 0x00 4.--5. " PLFSEL ," "0,1,2,3" bitfld.long 0x00 2.--3. " IDFSEL ," "0,1,2,3" bitfld.long 0x00 0.--1. " FCSEL ," "0,1,2,3" group.long 0xB04++0x3 line.long 0x00 "CANFD0_PN_CTL2,CANFD0 Pretended Networking Control2 Register" hexmask.long.word 0x00 0.--15. 1. " MATCHTO ," group.long 0xB08++0x3 line.long 0x00 "CANFD0_WUM,CANFD0 Pretended Networking Wakeup Match Register" bitfld.long 0x00 17. " WTOF ," "0,1" bitfld.long 0x00 16. " WUMF ," "0,1" hexmask.long.byte 0x00 8.--15. 1. " MCNT ," group.long 0xB0C++0x3 line.long 0x00 "CANFD0_FLTR_ID1,CANFD0 Pretended Networking ID Filter1 Register" bitfld.long 0x00 30. " IDE ," "0,1" bitfld.long 0x00 29. " RTR ," "0,1" hexmask.long 0x00 0.--28. 1. " VALUE ," group.long 0xB10++0x3 line.long 0x00 "CANFD0_FLTR_DLC,CANFD0 Pretended Networking DLC Filter Register" bitfld.long 0x00 16.--19. " LO ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HI ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB14++0x3 line.long 0x00 "CANFD0_FLTR_DATA1_LO,CANFD0 Pretended Networking Payload Low Filter1 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB18++0x3 line.long 0x00 "CANFD0_FLTR_DATA1_HI,CANFD0 Pretended Networking Payload Low Filter2 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB1C++0x3 line.long 0x00 "CANFD0_FLTR_ID2_IDMSK,CANFD0 Pretended Networking ID Filter2 / IDMask Register" bitfld.long 0x00 30. " IDE ," "0,1" bitfld.long 0x00 29. " RTR ," "0,1" hexmask.long 0x00 0.--28. 1. " VALUE ," group.long 0xB20++0x3 line.long 0x00 "CANFD0_FLTR_DATA2_DMSK_LO,CANFD0 Pretended Networking Payload Low Filter2 / Payload Low Mask Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB24++0x3 line.long 0x00 "CANFD0_FLTR_DATA2_DMSK_HI,CANFD0 Pretended Networking Payload High Filter2 High Order Bits / Payload High Mask Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB40++0x3 line.long 0x00 "CANFD0_WMB0_STAT,CANFD0 Wakeup Message Buffer Control/Status Register" bitfld.long 0x00 22. " SRR ," "0,1" bitfld.long 0x00 21. " IDE ," "0,1" bitfld.long 0x00 20. " RTR ," "0,1" newline bitfld.long 0x00 16.--19. " DLC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB44++0x3 line.long 0x00 "CANFD0_WMB0_ID,CANFD0 Wakeup Message ID Buffer Register" hexmask.long 0x00 0.--28. 1. " RCVID ," group.long 0xB48++0x3 line.long 0x00 "CANFD0_WMB0_DATA_LO,CANFD0 Wakeup Message Buffer Data 0-3 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB4C++0x3 line.long 0x00 "CANFD0_WMB0_DATA_HI,CANFD0 Wakeup Message Buffer Data 4-7 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB50++0x3 line.long 0x00 "CANFD0_WMB1_STAT,CANFD0 Wakeup Message Buffer Control/Status Register" bitfld.long 0x00 22. " SRR ," "0,1" bitfld.long 0x00 21. " IDE ," "0,1" bitfld.long 0x00 20. " RTR ," "0,1" newline bitfld.long 0x00 16.--19. " DLC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB54++0x3 line.long 0x00 "CANFD0_WMB1_ID,CANFD0 Wakeup Message ID Buffer Register" hexmask.long 0x00 0.--28. 1. " RCVID ," group.long 0xB58++0x3 line.long 0x00 "CANFD0_WMB1_DATA_LO,CANFD0 Wakeup Message Buffer Data 0-3 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB5C++0x3 line.long 0x00 "CANFD0_WMB1_DATA_HI,CANFD0 Wakeup Message Buffer Data 4-7 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB60++0x3 line.long 0x00 "CANFD0_WMB2_STAT,CANFD0 Wakeup Message Buffer Control/Status Register" bitfld.long 0x00 22. " SRR ," "0,1" bitfld.long 0x00 21. " IDE ," "0,1" bitfld.long 0x00 20. " RTR ," "0,1" newline bitfld.long 0x00 16.--19. " DLC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB64++0x3 line.long 0x00 "CANFD0_WMB2_ID,CANFD0 Wakeup Message ID Buffer Register" hexmask.long 0x00 0.--28. 1. " RCVID ," group.long 0xB68++0x3 line.long 0x00 "CANFD0_WMB2_DATA_LO,CANFD0 Wakeup Message Buffer Data 0-3 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB6C++0x3 line.long 0x00 "CANFD0_WMB2_DATA_HI,CANFD0 Wakeup Message Buffer Data 4-7 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB70++0x3 line.long 0x00 "CANFD0_WMB3_STAT,CANFD0 Wakeup Message Buffer Control/Status Register" bitfld.long 0x00 22. " SRR ," "0,1" bitfld.long 0x00 21. " IDE ," "0,1" bitfld.long 0x00 20. " RTR ," "0,1" newline bitfld.long 0x00 16.--19. " DLC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB74++0x3 line.long 0x00 "CANFD0_WMB3_ID,CANFD0 Wakeup Message ID Buffer Register" hexmask.long 0x00 0.--28. 1. " RCVID ," group.long 0xB78++0x3 line.long 0x00 "CANFD0_WMB3_DATA_LO,CANFD0 Wakeup Message Buffer Data 0-3 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB7C++0x3 line.long 0x00 "CANFD0_WMB3_DATA_HI,CANFD0 Wakeup Message Buffer Data 4-7 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xC00++0x3 line.long 0x00 "CANFD0_FD_CTL,CANFD0 CANFD Control Register" bitfld.long 0x00 31. " BRSEN ," "0,1" bitfld.long 0x00 25.--26. " MBDSIZR3 ," "0,1,2,3" bitfld.long 0x00 22.--23. " MBDSIZR2 ," "0,1,2,3" newline bitfld.long 0x00 19.--20. " MBDSIZR1 ," "0,1,2,3" bitfld.long 0x00 16.--17. " MBDSIZR0 ," "0,1,2,3" bitfld.long 0x00 15. " TDCOMPEN ," "0,1" newline bitfld.long 0x00 14. " TDCOMPFAIL ," "0,1" bitfld.long 0x00 8.--12. " TDCOMPOFF ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TDCOMPVAL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC04++0x3 line.long 0x00 "CANFD0_FD_TIMING,CANFD0 CANFD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ," bitfld.long 0x00 16.--18. " FRJW ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--14. " FPROPSEG ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--7. " FPSEG1 ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " FPSEG2 ," "0,1,2,3,4,5,6,7" group.long 0xC08++0x3 line.long 0x00 "CANFD0_FD_CRC,CANFD0 CANFD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " MB ," hexmask.long.tbyte 0x00 0.--20. 1. " TX ," tree.end tree "CANFD1" base ad:0x31047000 width 27. group.long 0x0++0x3 line.long 0x00 "CANFD1_CFG,CANFD1 Configuration Register" bitfld.long 0x00 31. " DIS ,Module Disable" "0,1" bitfld.long 0x00 30. " FRZ ,Freeze Mode Enable" "0,1" bitfld.long 0x00 29. " RFEN ,Rx FIFO Enable" "0,1" newline bitfld.long 0x00 28. " HALT ,Freeze Mode Enable" "0,1" bitfld.long 0x00 27. " NOTRDY ,FlexCAN Not Ready" "0,1" bitfld.long 0x00 26. " WAKMSK ,Wakeup Interrupt Mask" "0,1" newline bitfld.long 0x00 25. " SOFTRST ,Soft Reset" "0,1" bitfld.long 0x00 24. " FRZACK ,Freeze Mode Acknowledge" "0,1" bitfld.long 0x00 23. " SUPVEN ,Supervisor Mode" "0,1" newline bitfld.long 0x00 22. " SLFWAKEN ,Self Wakeup Enable" "0,1" bitfld.long 0x00 21. " WRNEN ,Warning Interrupt Enable" "0,1" bitfld.long 0x00 20. " LPMACK ,Low Power Mode Enable" "0,1" newline bitfld.long 0x00 19. " WSFLTREN ,Wakeup Source" "0,1" bitfld.long 0x00 18. " DOZEN ,Doze Mode Enable" "0,1" bitfld.long 0x00 17. " SRXDIS ,Self Reception Enable" "0,1" newline bitfld.long 0x00 16. " IRMQEN ,Rx Masking And Queue Enable" "0,1" bitfld.long 0x00 15. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 14. " PNETEN ,Pretended Networking Enable" "0,1" newline bitfld.long 0x00 13. " LPRIOEN ,Local Priority Enable" "0,1" bitfld.long 0x00 12. " ABORTEN ,Abort Enable" "0,1" bitfld.long 0x00 11. " FDEN ,CANFD Enable" "0,1" newline bitfld.long 0x00 8.--9. " IDAM ,ID Acceptance Mode" "0,1,2,3" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the Last Message Buffer" group.long 0x4++0x3 line.long 0x00 "CANFD1_CTL1,CANFD1 Control1 Register" hexmask.long.byte 0x00 24.--31. 1. " PRESDIV ," bitfld.long 0x00 22.--23. " RJW ," "0,1,2,3" bitfld.long 0x00 19.--21. " PSEG1 ," "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--18. " PSEG2 ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " BOFFMSK ," "0,1" bitfld.long 0x00 14. " ERRMSK ," "0,1" newline bitfld.long 0x00 13. " CLKSRC ," "0,1" bitfld.long 0x00 12. " LBEN ," "0,1" bitfld.long 0x00 11. " TWRNMSK ," "0,1" newline bitfld.long 0x00 10. " RWRNMSK ," "0,1" bitfld.long 0x00 7. " SMP ," "0,1" bitfld.long 0x00 6. " BOFFREC ," "0,1" newline bitfld.long 0x00 5. " TSYNEN ," "0,1" bitfld.long 0x00 4. " LBUF ," "0,1" bitfld.long 0x00 3. " LOMEN ," "0,1" newline bitfld.long 0x00 0.--2. " PROPSEG ," "0,1,2,3,4,5,6,7" group.long 0x8++0x3 line.long 0x00 "CANFD1_TMR,CANFD1 Timer Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ," group.long 0x10++0x3 line.long 0x00 "CANFD1_RX_MB_GMSK,CANFD1 Receive Mailbox Global Mask Register" bitfld.long 0x00 31. " MB31 ," "0,1" bitfld.long 0x00 30. " MB30 ," "0,1" bitfld.long 0x00 29. " MB29 ," "0,1" newline bitfld.long 0x00 28. " MB28 ," "0,1" bitfld.long 0x00 27. " MB27 ," "0,1" bitfld.long 0x00 26. " MB26 ," "0,1" newline bitfld.long 0x00 25. " MB25 ," "0,1" bitfld.long 0x00 24. " MB24 ," "0,1" bitfld.long 0x00 23. " MB23 ," "0,1" newline bitfld.long 0x00 22. " MB22 ," "0,1" bitfld.long 0x00 21. " MB21 ," "0,1" bitfld.long 0x00 20. " MB20 ," "0,1" newline bitfld.long 0x00 19. " MB19 ," "0,1" bitfld.long 0x00 18. " MB18 ," "0,1" bitfld.long 0x00 17. " MB17 ," "0,1" newline bitfld.long 0x00 16. " MB16 ," "0,1" bitfld.long 0x00 15. " MB15 ," "0,1" bitfld.long 0x00 14. " MB14 ," "0,1" newline bitfld.long 0x00 13. " MB13 ," "0,1" bitfld.long 0x00 12. " MB12 ," "0,1" bitfld.long 0x00 11. " MB11 ," "0,1" newline bitfld.long 0x00 10. " MB10 ," "0,1" bitfld.long 0x00 9. " MB09 ," "0,1" bitfld.long 0x00 8. " MB08 ," "0,1" newline bitfld.long 0x00 7. " MB07 ," "0,1" bitfld.long 0x00 6. " MB06 ," "0,1" bitfld.long 0x00 5. " MB05 ," "0,1" newline bitfld.long 0x00 4. " MB04 ," "0,1" bitfld.long 0x00 3. " MB03 ," "0,1" bitfld.long 0x00 2. " MB02 ," "0,1" newline bitfld.long 0x00 1. " MB01 ," "0,1" bitfld.long 0x00 0. " MB00 ," "0,1" group.long 0x14++0x3 line.long 0x00 "CANFD1_RX_14_MSK,CANFD1 Receive Mailbox14 Mask Register" group.long 0x18++0x3 line.long 0x00 "CANFD1_RX_15_MSK,CANFD1 Receive Mailbox15 Mask Register" group.long 0x1C++0x3 line.long 0x00 "CANFD1_ECR,CANFD1 Error Count Register" hexmask.long.byte 0x00 24.--31. 1. " RXERRCNTF ," hexmask.long.byte 0x00 16.--23. 1. " TXERRCNTF ," hexmask.long.byte 0x00 8.--15. 1. " RXERRCNT ," newline hexmask.long.byte 0x00 0.--7. 1. " TXERRCNT ," group.long 0x20++0x3 line.long 0x00 "CANFD1_ESR1,CANFD1 Error and Status1 Register" bitfld.long 0x00 31. " B1ERRF ," "0,1" bitfld.long 0x00 30. " B0ERRF ," "0,1" bitfld.long 0x00 28. " CRCERRF ," "0,1" newline bitfld.long 0x00 27. " FRMERRF ," "0,1" bitfld.long 0x00 26. " STFERRF ," "0,1" bitfld.long 0x00 21. " ERROVR ," "0,1" newline bitfld.long 0x00 20. " ERRINTF ," "0,1" bitfld.long 0x00 19. " BOFFDONEINT ," "0,1" bitfld.long 0x00 18. " SYNC ," "0,1" newline bitfld.long 0x00 17. " TXWRNINT ," "0,1" bitfld.long 0x00 16. " RXWRNINT ," "0,1" bitfld.long 0x00 15. " B1ERR ," "0,1" newline bitfld.long 0x00 14. " B0ERR ," "0,1" bitfld.long 0x00 13. " ACKERR ," "0,1" bitfld.long 0x00 12. " CRCERR ," "0,1" newline bitfld.long 0x00 11. " FRMERR ," "0,1" bitfld.long 0x00 10. " STFERR ," "0,1" bitfld.long 0x00 9. " TXWRN ," "0,1" newline bitfld.long 0x00 8. " RXWRN ," "0,1" bitfld.long 0x00 7. " IDLE ," "0,1" bitfld.long 0x00 6. " TXINPROG ," "0,1" newline bitfld.long 0x00 4.--5. " FLTCONF ," "0,1,2,3" bitfld.long 0x00 3. " RXINPROG ," "0,1" bitfld.long 0x00 2. " BOFFINT ," "0,1" newline bitfld.long 0x00 1. " ERRINT ," "0,1" bitfld.long 0x00 0. " WAKINT ," "0,1" group.long 0x24++0x3 line.long 0x00 "CANFD1_IMSK2,CANFD1 Mailbox Interrupt Mask2 Register" bitfld.long 0x00 31. " MB63 ,Message Buffer 63 Interrupt Mask" "0,1" bitfld.long 0x00 30. " MB62 ,Message Buffer 62 Interrupt Mask" "0,1" bitfld.long 0x00 29. " MB61 ,Message Buffer 61 Interrupt Mask" "0,1" newline bitfld.long 0x00 28. " MB60 ,Message Buffer 60 Interrupt Mask" "0,1" bitfld.long 0x00 27. " MB59 ,Message Buffer 59 Interrupt Mask" "0,1" bitfld.long 0x00 26. " MB58 ,Message Buffer 58 Interrupt Mask" "0,1" newline bitfld.long 0x00 25. " MB57 ,Message Buffer 57 Interrupt Mask" "0,1" bitfld.long 0x00 24. " MB56 ,Message Buffer 56 Interrupt Mask" "0,1" bitfld.long 0x00 23. " MB55 ,Message Buffer 55 Interrupt Mask" "0,1" newline bitfld.long 0x00 22. " MB54 ,Message Buffer 54 Interrupt Mask" "0,1" bitfld.long 0x00 21. " MB53 ,Message Buffer 53 Interrupt Mask" "0,1" bitfld.long 0x00 20. " MB52 ,Message Buffer 52 Interrupt Mask" "0,1" newline bitfld.long 0x00 19. " MB51 ,Message Buffer 51 Interrupt Mask" "0,1" bitfld.long 0x00 18. " MB50 ,Message Buffer 50 Interrupt Mask" "0,1" bitfld.long 0x00 17. " MB49 ,Message Buffer 49 Interrupt Mask" "0,1" newline bitfld.long 0x00 16. " MB48 ,Message Buffer 48 Interrupt Mask" "0,1" bitfld.long 0x00 15. " MB47 ,Message Buffer 47 Interrupt Mask" "0,1" bitfld.long 0x00 14. " MB46 ,Message Buffer 46 Interrupt Mask" "0,1" newline bitfld.long 0x00 13. " MB45 ,Message Buffer 45 Interrupt Mask" "0,1" bitfld.long 0x00 12. " MB44 ,Message Buffer 44 Interrupt Mask" "0,1" bitfld.long 0x00 11. " MB43 ,Message Buffer 43 Interrupt Mask" "0,1" newline bitfld.long 0x00 10. " MB42 ,Message Buffer 42 Interrupt Mask" "0,1" bitfld.long 0x00 9. " MB41 ,Message Buffer 41 Interrupt Mask" "0,1" bitfld.long 0x00 8. " MB40 ,Message Buffer 40 Interrupt Mask" "0,1" newline bitfld.long 0x00 7. " MB39 ,Message Buffer 39 Interrupt Mask" "0,1" bitfld.long 0x00 6. " MB38 ,Message Buffer 38 Interrupt Mask" "0,1" bitfld.long 0x00 5. " MB37 ,Message Buffer 37 Interrupt Mask" "0,1" newline bitfld.long 0x00 4. " MB36 ,Message Buffer 36 Interrupt Mask" "0,1" bitfld.long 0x00 3. " MB35 ,Message Buffer 35 Interrupt Mask" "0,1" bitfld.long 0x00 2. " MB34 ,Message Buffer 34 Interrupt Mask" "0,1" newline bitfld.long 0x00 1. " MB33 ,Message Buffer 33 Interrupt Mask" "0,1" bitfld.long 0x00 0. " MB32 ,Message Buffer 32 Interrupt Mask" "0,1" group.long 0x28++0x3 line.long 0x00 "CANFD1_IMSK1,CANFD1 Mailbox Interrupt Mask1 Register" bitfld.long 0x00 31. " MB31 ,Messge Buffer31 Interrupt Mask" "0,1" bitfld.long 0x00 30. " MB30 ,Messge Buffer30 Interrupt Mask" "0,1" bitfld.long 0x00 29. " MB29 ,Messge Buffer29 Interrupt Mask" "0,1" newline bitfld.long 0x00 28. " MB28 ,Messge Buffer28 Interrupt Mask" "0,1" bitfld.long 0x00 27. " MB27 ,Messge Buffer27 Interrupt Mask" "0,1" bitfld.long 0x00 26. " MB26 ,Messge Buffer26 Interrupt Mask" "0,1" newline bitfld.long 0x00 25. " MB25 ,Messge Buffer25 Interrupt Mask" "0,1" bitfld.long 0x00 24. " MB24 ,Messge Buffer24 Interrupt Mask" "0,1" bitfld.long 0x00 23. " MB23 ,Messge Buffer23 Interrupt Mask" "0,1" newline bitfld.long 0x00 22. " MB22 ,Messge Buffer22 Interrupt Mask" "0,1" bitfld.long 0x00 21. " MB21 ,Messge Buffer21 Interrupt Mask" "0,1" bitfld.long 0x00 20. " MB20 ,Messge Buffer20 Interrupt Mask" "0,1" newline bitfld.long 0x00 19. " MB19 ,Messge Buffer19 Interrupt Mask" "0,1" bitfld.long 0x00 18. " MB18 ,Messge Buffer18 Interrupt Mask" "0,1" bitfld.long 0x00 17. " MB17 ,Messge Buffer17 Interrupt Mask" "0,1" newline bitfld.long 0x00 16. " MB16 ,Messge Buffer16 Interrupt Mask" "0,1" bitfld.long 0x00 15. " MB15 ,Messge Buffer15 Interrupt Mask" "0,1" bitfld.long 0x00 14. " MB14 ,Messge Buffer14 Interrupt Mask" "0,1" newline bitfld.long 0x00 13. " MB13 ,Messge Buffer13 Interrupt Mask" "0,1" bitfld.long 0x00 12. " MB12 ,Messge Buffer12 Interrupt Mask" "0,1" bitfld.long 0x00 11. " MB11 ,Messge Buffer11 Interrupt Mask" "0,1" newline bitfld.long 0x00 10. " MB10 ,Messge Buffer10 Interrupt Mask" "0,1" bitfld.long 0x00 9. " MB09 ,Messge Buffer09 Interrupt Mask" "0,1" bitfld.long 0x00 8. " MB08 ,Messge Buffer08 Interrupt Mask" "0,1" newline bitfld.long 0x00 7. " MB07 ,Messge Buffer07 Interrupt Mask" "0,1" bitfld.long 0x00 6. " MB06 ,Messge Buffer06 Interrupt Mask" "0,1" bitfld.long 0x00 5. " MB05 ,Messge Buffer05 Interrupt Mask" "0,1" newline bitfld.long 0x00 4. " MB04 ,Messge Buffer04 Interrupt Mask" "0,1" bitfld.long 0x00 3. " MB03 ,Messge Buffer03 Interrupt Mask" "0,1" bitfld.long 0x00 2. " MB02 ,Messge Buffer02 Interrupt Mask" "0,1" newline bitfld.long 0x00 1. " MB01 ,Messge Buffer01 Interrupt Mask" "0,1" bitfld.long 0x00 0. " MB00 ,Messge Buffer00 Interrupt Mask" "0,1" group.long 0x2C++0x3 line.long 0x00 "CANFD1_IFLG2,CANFD1 Mailbox Interrupt Flag2 Register" bitfld.long 0x00 31. " MB63 ,Message Buffer 63 Interrupt Flag" "0,1" bitfld.long 0x00 30. " MB62 ,Message Buffer 62 Interrupt Flag" "0,1" bitfld.long 0x00 29. " MB61 ,Message Buffer 61 Interrupt Flag" "0,1" newline bitfld.long 0x00 28. " MB60 ,Message Buffer 60 Interrupt Flag" "0,1" bitfld.long 0x00 27. " MB59 ,Message Buffer 59 Interrupt Flag" "0,1" bitfld.long 0x00 26. " MB58 ,Message Buffer 58 Interrupt Flag" "0,1" newline bitfld.long 0x00 25. " MB57 ,Message Buffer 57 Interrupt Flag" "0,1" bitfld.long 0x00 24. " MB56 ,Message Buffer 56 Interrupt Flag" "0,1" bitfld.long 0x00 23. " MB55 ,Message Buffer 55 Interrupt Flag" "0,1" newline bitfld.long 0x00 22. " MB54 ,Message Buffer 54 Interrupt Flag" "0,1" bitfld.long 0x00 21. " MB53 ,Message Buffer 53 Interrupt Flag" "0,1" bitfld.long 0x00 20. " MB52 ,Message Buffer 52 Interrupt Flag" "0,1" newline bitfld.long 0x00 19. " MB51 ,Message Buffer 51 Interrupt Flag" "0,1" bitfld.long 0x00 18. " MB50 ,Message Buffer 50 Interrupt Flag" "0,1" bitfld.long 0x00 17. " MB49 ,Message Buffer 49 Interrupt Flag" "0,1" newline bitfld.long 0x00 16. " MB48 ,Message Buffer 48 Interrupt Flag" "0,1" bitfld.long 0x00 15. " MB47 ,Message Buffer 47 Interrupt Flag" "0,1" bitfld.long 0x00 14. " MB46 ,Message Buffer 46 Interrupt Flag" "0,1" newline bitfld.long 0x00 13. " MB45 ,Message Buffer 45 Interrupt Flag" "0,1" bitfld.long 0x00 12. " MB44 ,Message Buffer 44 Interrupt Flag" "0,1" bitfld.long 0x00 11. " MB43 ,Message Buffer 43 Interrupt Flag" "0,1" newline bitfld.long 0x00 10. " MB42 ,Message Buffer 42 Interrupt Flag" "0,1" bitfld.long 0x00 9. " MB41 ,Message Buffer 41 Interrupt Flag" "0,1" bitfld.long 0x00 8. " MB40 ,Message Buffer 40 Interrupt Flag" "0,1" newline bitfld.long 0x00 7. " MB39 ,Message Buffer 39 Interrupt Flag" "0,1" bitfld.long 0x00 6. " MB38 ,Message Buffer 38 Interrupt Flag" "0,1" bitfld.long 0x00 5. " MB37 ,Message Buffer 37 Interrupt Flag" "0,1" newline bitfld.long 0x00 4. " MB36 ,Message Buffer 36 Interrupt Flag" "0,1" bitfld.long 0x00 3. " MB35 ,Message Buffer 35 Interrupt Flag" "0,1" bitfld.long 0x00 2. " MB34 ,Message Buffer 34 Interrupt Flag" "0,1" newline bitfld.long 0x00 1. " MB33 ,Message Buffer 33 Interrupt Flag" "0,1" bitfld.long 0x00 0. " MB32 ,Message Buffer 32 Interrupt Flag" "0,1" group.long 0x30++0x3 line.long 0x00 "CANFD1_IFLG1,CANFD1 Mailbox Interrupt Flag1 Register" bitfld.long 0x00 31. " MB31 ,Message Buffer 31 Interrupt Flag" "0,1" bitfld.long 0x00 30. " MB30 ,Message Buffer 30 Interrupt Flag" "0,1" bitfld.long 0x00 29. " MB29 ,Message Buffer 29 Interrupt Flag" "0,1" newline bitfld.long 0x00 28. " MB28 ,Message Buffer 28 Interrupt Flag" "0,1" bitfld.long 0x00 27. " MB27 ,Message Buffer 27 Interrupt Flag" "0,1" bitfld.long 0x00 26. " MB26 ,Message Buffer 26 Interrupt Flag" "0,1" newline bitfld.long 0x00 25. " MB25 ,Message Buffer 25 Interrupt Flag" "0,1" bitfld.long 0x00 24. " MB24 ,Message Buffer 24 Interrupt Flag" "0,1" bitfld.long 0x00 23. " MB23 ,Message Buffer 23 Interrupt Flag" "0,1" newline bitfld.long 0x00 22. " MB22 ,Message Buffer 22 Interrupt Flag" "0,1" bitfld.long 0x00 21. " MB21 ,Message Buffer 21 Interrupt Flag" "0,1" bitfld.long 0x00 20. " MB20 ,Message Buffer 20 Interrupt Flag" "0,1" newline bitfld.long 0x00 19. " MB19 ,Message Buffer 19 Interrupt Flag" "0,1" bitfld.long 0x00 18. " MB18 ,Message Buffer 18 Interrupt Flag" "0,1" bitfld.long 0x00 17. " MB17 ,Message Buffer 17 Interrupt Flag" "0,1" newline bitfld.long 0x00 16. " MB16 ,Message Buffer 16 Interrupt Flag" "0,1" bitfld.long 0x00 15. " MB15 ,Message Buffer 15 Interrupt Flag" "0,1" bitfld.long 0x00 14. " MB14 ,Message Buffer 14 Interrupt Flag" "0,1" newline bitfld.long 0x00 13. " MB13 ,Message Buffer 13 Interrupt Flag" "0,1" bitfld.long 0x00 12. " MB12 ,Message Buffer 12 Interrupt Flag" "0,1" bitfld.long 0x00 11. " MB11 ,Message Buffer 11 Interrupt Flag" "0,1" newline bitfld.long 0x00 10. " MB10 ,Message Buffer 10 Interrupt Flag" "0,1" bitfld.long 0x00 9. " MB09 ,Message Buffer 9 Interrupt Flag" "0,1" bitfld.long 0x00 8. " MB08 ,Message Buffer 8 Interrupt Flag" "0,1" newline bitfld.long 0x00 7. " MB07 ,Message Buffer 7 Interrupt Flag" "0,1" bitfld.long 0x00 6. " MB06 ,Message Buffer 6 Interrupt Flag" "0,1" bitfld.long 0x00 5. " MB05 ,Message Buffer 5 Interrupt Flag" "0,1" newline bitfld.long 0x00 4. " MB04 ,Message Buffer 4 Interrupt Flag" "0,1" bitfld.long 0x00 3. " MB03 ,Message Buffer 3 Interrupt Flag" "0,1" bitfld.long 0x00 2. " MB02 ,Message Buffer 2 Interrupt Flag" "0,1" newline bitfld.long 0x00 1. " MB01 ,Message Buffer 1 Interrupt Flag" "0,1" bitfld.long 0x00 0. " MB00 ,Message Buffer 0 Interrupt Flag" "0,1" group.long 0x34++0x3 line.long 0x00 "CANFD1_CTL2,CANFD1 Control2 Register" bitfld.long 0x00 31. " ERRMSKF ," "0,1" bitfld.long 0x00 30. " BOFFDONEIMSK ," "0,1" bitfld.long 0x00 29. " ECRWREN ," "0,1" newline bitfld.long 0x00 28. " WRMFRZEN ," "0,1" bitfld.long 0x00 24.--27. " RFFNUM ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19.--23. " TXASDLY ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18. " MRPRIO ," "0,1" bitfld.long 0x00 17. " RRS ," "0,1" bitfld.long 0x00 16. " EACEN ," "0,1" newline bitfld.long 0x00 15. " TMRSRC_SEL ," "0,1" bitfld.long 0x00 14. " PREXEN ," "0,1" bitfld.long 0x00 12. " ISOFDEN ," "0,1" newline bitfld.long 0x00 11. " EDFLTDIS ," "0,1" group.long 0x38++0x3 line.long 0x00 "CANFD1_ESR2,CANFD1 Error and Status2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTXMB ," bitfld.long 0x00 14. " VPS ," "0,1" bitfld.long 0x00 13. " IMB ," "0,1" group.long 0x44++0x3 line.long 0x00 "CANFD1_CRC,CANFD1 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MB ," hexmask.long.word 0x00 0.--14. 1. " TX ," group.long 0x48++0x3 line.long 0x00 "CANFD1_RX_FIFO_GMSK,CANFD1 Receive FIFO Global Mask Register" bitfld.long 0x00 31. " VALUE31 ," "0,1" bitfld.long 0x00 30. " VALUE30 ," "0,1" bitfld.long 0x00 29. " VALUE29 ," "0,1" newline bitfld.long 0x00 28. " VALUE28 ," "0,1" bitfld.long 0x00 27. " VALUE27 ," "0,1" bitfld.long 0x00 26. " VALUE26 ," "0,1" newline bitfld.long 0x00 25. " VALUE25 ," "0,1" bitfld.long 0x00 24. " VALUE24 ," "0,1" bitfld.long 0x00 23. " VALUE23 ," "0,1" newline bitfld.long 0x00 22. " VALUE22 ," "0,1" bitfld.long 0x00 21. " VALUE21 ," "0,1" bitfld.long 0x00 20. " VALUE20 ," "0,1" newline bitfld.long 0x00 19. " VALUE19 ," "0,1" bitfld.long 0x00 18. " VALUE18 ," "0,1" bitfld.long 0x00 17. " VALUE17 ," "0,1" newline bitfld.long 0x00 16. " VALUE16 ," "0,1" bitfld.long 0x00 15. " VALUE15 ," "0,1" bitfld.long 0x00 14. " VALUE14 ," "0,1" newline bitfld.long 0x00 13. " VALUE13 ," "0,1" bitfld.long 0x00 12. " VALUE12 ," "0,1" bitfld.long 0x00 11. " VALUE11 ," "0,1" newline bitfld.long 0x00 10. " VALUE10 ," "0,1" bitfld.long 0x00 9. " VALUE9 ," "0,1" bitfld.long 0x00 8. " VALUE8 ," "0,1" newline bitfld.long 0x00 7. " VALUE7 ," "0,1" bitfld.long 0x00 6. " VALUE6 ," "0,1" bitfld.long 0x00 5. " VALUE5 ," "0,1" newline bitfld.long 0x00 4. " VALUE4 ," "0,1" bitfld.long 0x00 3. " VALUE3 ," "0,1" bitfld.long 0x00 2. " VALUE2 ," "0,1" newline bitfld.long 0x00 1. " VALUE1 ," "0,1" bitfld.long 0x00 0. " VALUE0 ," "0,1" group.long 0x4C++0x3 line.long 0x00 "CANFD1_RX_FIFO,CANFD1 Receive FIFO Information Register" hexmask.long.word 0x00 0.--8. 1. " IDHIT ," group.long 0x50++0x3 line.long 0x00 "CANFD1_TIMING,CANFD1 Can Bit Timing Register" bitfld.long 0x00 31. " BTF ," "0,1" hexmask.long.word 0x00 21.--30. 1. " EPRESDIV ," bitfld.long 0x00 16.--20. " ERJW ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--15. " EPROPSEG ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 5.--9. " EPSEG1 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " EPSEG2 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x880++0x3 line.long 0x00 "CANFD1_RX_IMSK0,CANFD1 Receive Individual Mask Register" group.long 0x884++0x3 line.long 0x00 "CANFD1_RX_IMSK1,CANFD1 Receive Individual Mask Register" group.long 0x888++0x3 line.long 0x00 "CANFD1_RX_IMSK2,CANFD1 Receive Individual Mask Register" group.long 0x88C++0x3 line.long 0x00 "CANFD1_RX_IMSK3,CANFD1 Receive Individual Mask Register" group.long 0x890++0x3 line.long 0x00 "CANFD1_RX_IMSK4,CANFD1 Receive Individual Mask Register" group.long 0x894++0x3 line.long 0x00 "CANFD1_RX_IMSK5,CANFD1 Receive Individual Mask Register" group.long 0x898++0x3 line.long 0x00 "CANFD1_RX_IMSK6,CANFD1 Receive Individual Mask Register" group.long 0x89C++0x3 line.long 0x00 "CANFD1_RX_IMSK7,CANFD1 Receive Individual Mask Register" group.long 0x8A0++0x3 line.long 0x00 "CANFD1_RX_IMSK8,CANFD1 Receive Individual Mask Register" group.long 0x8A4++0x3 line.long 0x00 "CANFD1_RX_IMSK9,CANFD1 Receive Individual Mask Register" group.long 0x8A8++0x3 line.long 0x00 "CANFD1_RX_IMSK10,CANFD1 Receive Individual Mask Register" group.long 0x8AC++0x3 line.long 0x00 "CANFD1_RX_IMSK11,CANFD1 Receive Individual Mask Register" group.long 0x8B0++0x3 line.long 0x00 "CANFD1_RX_IMSK12,CANFD1 Receive Individual Mask Register" group.long 0x8B4++0x3 line.long 0x00 "CANFD1_RX_IMSK13,CANFD1 Receive Individual Mask Register" group.long 0x8B8++0x3 line.long 0x00 "CANFD1_RX_IMSK14,CANFD1 Receive Individual Mask Register" group.long 0x8BC++0x3 line.long 0x00 "CANFD1_RX_IMSK15,CANFD1 Receive Individual Mask Register" group.long 0x8C0++0x3 line.long 0x00 "CANFD1_RX_IMSK16,CANFD1 Receive Individual Mask Register" group.long 0x8C4++0x3 line.long 0x00 "CANFD1_RX_IMSK17,CANFD1 Receive Individual Mask Register" group.long 0x8C8++0x3 line.long 0x00 "CANFD1_RX_IMSK18,CANFD1 Receive Individual Mask Register" group.long 0x8CC++0x3 line.long 0x00 "CANFD1_RX_IMSK19,CANFD1 Receive Individual Mask Register" group.long 0x8D0++0x3 line.long 0x00 "CANFD1_RX_IMSK20,CANFD1 Receive Individual Mask Register" group.long 0x8D4++0x3 line.long 0x00 "CANFD1_RX_IMSK21,CANFD1 Receive Individual Mask Register" group.long 0x8D8++0x3 line.long 0x00 "CANFD1_RX_IMSK22,CANFD1 Receive Individual Mask Register" group.long 0x8DC++0x3 line.long 0x00 "CANFD1_RX_IMSK23,CANFD1 Receive Individual Mask Register" group.long 0x8E0++0x3 line.long 0x00 "CANFD1_RX_IMSK24,CANFD1 Receive Individual Mask Register" group.long 0x8E4++0x3 line.long 0x00 "CANFD1_RX_IMSK25,CANFD1 Receive Individual Mask Register" group.long 0x8E8++0x3 line.long 0x00 "CANFD1_RX_IMSK26,CANFD1 Receive Individual Mask Register" group.long 0x8EC++0x3 line.long 0x00 "CANFD1_RX_IMSK27,CANFD1 Receive Individual Mask Register" group.long 0x8F0++0x3 line.long 0x00 "CANFD1_RX_IMSK28,CANFD1 Receive Individual Mask Register" group.long 0x8F4++0x3 line.long 0x00 "CANFD1_RX_IMSK29,CANFD1 Receive Individual Mask Register" group.long 0x8F8++0x3 line.long 0x00 "CANFD1_RX_IMSK30,CANFD1 Receive Individual Mask Register" group.long 0x8FC++0x3 line.long 0x00 "CANFD1_RX_IMSK31,CANFD1 Receive Individual Mask Register" group.long 0x900++0x3 line.long 0x00 "CANFD1_RX_IMSK32,CANFD1 Receive Individual Mask Register" group.long 0x904++0x3 line.long 0x00 "CANFD1_RX_IMSK33,CANFD1 Receive Individual Mask Register" group.long 0x908++0x3 line.long 0x00 "CANFD1_RX_IMSK34,CANFD1 Receive Individual Mask Register" group.long 0x90C++0x3 line.long 0x00 "CANFD1_RX_IMSK35,CANFD1 Receive Individual Mask Register" group.long 0x910++0x3 line.long 0x00 "CANFD1_RX_IMSK36,CANFD1 Receive Individual Mask Register" group.long 0x914++0x3 line.long 0x00 "CANFD1_RX_IMSK37,CANFD1 Receive Individual Mask Register" group.long 0x918++0x3 line.long 0x00 "CANFD1_RX_IMSK38,CANFD1 Receive Individual Mask Register" group.long 0x91C++0x3 line.long 0x00 "CANFD1_RX_IMSK39,CANFD1 Receive Individual Mask Register" group.long 0x920++0x3 line.long 0x00 "CANFD1_RX_IMSK40,CANFD1 Receive Individual Mask Register" group.long 0x924++0x3 line.long 0x00 "CANFD1_RX_IMSK41,CANFD1 Receive Individual Mask Register" group.long 0x928++0x3 line.long 0x00 "CANFD1_RX_IMSK42,CANFD1 Receive Individual Mask Register" group.long 0x92C++0x3 line.long 0x00 "CANFD1_RX_IMSK43,CANFD1 Receive Individual Mask Register" group.long 0x930++0x3 line.long 0x00 "CANFD1_RX_IMSK44,CANFD1 Receive Individual Mask Register" group.long 0x934++0x3 line.long 0x00 "CANFD1_RX_IMSK45,CANFD1 Receive Individual Mask Register" group.long 0x938++0x3 line.long 0x00 "CANFD1_RX_IMSK46,CANFD1 Receive Individual Mask Register" group.long 0x93C++0x3 line.long 0x00 "CANFD1_RX_IMSK47,CANFD1 Receive Individual Mask Register" group.long 0x940++0x3 line.long 0x00 "CANFD1_RX_IMSK48,CANFD1 Receive Individual Mask Register" group.long 0x944++0x3 line.long 0x00 "CANFD1_RX_IMSK49,CANFD1 Receive Individual Mask Register" group.long 0x948++0x3 line.long 0x00 "CANFD1_RX_IMSK50,CANFD1 Receive Individual Mask Register" group.long 0x94C++0x3 line.long 0x00 "CANFD1_RX_IMSK51,CANFD1 Receive Individual Mask Register" group.long 0x950++0x3 line.long 0x00 "CANFD1_RX_IMSK52,CANFD1 Receive Individual Mask Register" group.long 0x954++0x3 line.long 0x00 "CANFD1_RX_IMSK53,CANFD1 Receive Individual Mask Register" group.long 0x958++0x3 line.long 0x00 "CANFD1_RX_IMSK54,CANFD1 Receive Individual Mask Register" group.long 0x95C++0x3 line.long 0x00 "CANFD1_RX_IMSK55,CANFD1 Receive Individual Mask Register" group.long 0x960++0x3 line.long 0x00 "CANFD1_RX_IMSK56,CANFD1 Receive Individual Mask Register" group.long 0x964++0x3 line.long 0x00 "CANFD1_RX_IMSK57,CANFD1 Receive Individual Mask Register" group.long 0x968++0x3 line.long 0x00 "CANFD1_RX_IMSK58,CANFD1 Receive Individual Mask Register" group.long 0x96C++0x3 line.long 0x00 "CANFD1_RX_IMSK59,CANFD1 Receive Individual Mask Register" group.long 0x970++0x3 line.long 0x00 "CANFD1_RX_IMSK60,CANFD1 Receive Individual Mask Register" group.long 0x974++0x3 line.long 0x00 "CANFD1_RX_IMSK61,CANFD1 Receive Individual Mask Register" group.long 0x978++0x3 line.long 0x00 "CANFD1_RX_IMSK62,CANFD1 Receive Individual Mask Register" group.long 0x97C++0x3 line.long 0x00 "CANFD1_RX_IMSK63,CANFD1 Receive Individual Mask Register" group.long 0xAE0++0x3 line.long 0x00 "CANFD1_MEC,CANFD1 Memory Error Control Register" bitfld.long 0x00 31. " ECRWRDIS ," "0,1" bitfld.long 0x00 19. " HNCIMSK ," "0,1" bitfld.long 0x00 18. " INCEMSK ," "0,1" newline bitfld.long 0x00 16. " CEIMSK ," "0,1" bitfld.long 0x00 15. " HAERRIEN ," "0,1" bitfld.long 0x00 14. " IAERRIEN ," "0,1" newline bitfld.long 0x00 13. " EXTERRIEN ," "0,1" bitfld.long 0x00 9. " RERDIS ," "0,1" bitfld.long 0x00 8. " ECCDIS ," "0,1" newline bitfld.long 0x00 7. " NCERRFRZEN ," "0,1" group.long 0xAE4++0x3 line.long 0x00 "CANFD1_ERR_IADDR,CANFD1 Error Injection Address Register" hexmask.long.word 0x00 0.--13. 1. " VALUE ," group.long 0xAE8++0x3 line.long 0x00 "CANFD1_ERR_IDP,CANFD1 Error Injection Data Pattern Register" group.long 0xAEC++0x3 line.long 0x00 "CANFD1_ERR_IPP,CANFD1 Error Injection Parity Pattern Register" bitfld.long 0x00 24.--28. " PFLIP3 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--20. " PFLIP2 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--12. " PFLIP1 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. " PFLIP0 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAF0++0x3 line.long 0x00 "CANFD1_ERR_RADDR,CANFD1 Error Report Address Register" bitfld.long 0x00 24. " NCERR ," "0,1" bitfld.long 0x00 16.--18. " RDREQID ," "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--13. 1. " VALUE ," group.long 0xAF4++0x3 line.long 0x00 "CANFD1_ERR_RDAT,CANFD1 Error Report Data Register" group.long 0xAF8++0x3 line.long 0x00 "CANFD1_ERR_RSYN,CANFD1 Error Report Syndrome Register" bitfld.long 0x00 31. " BEN3 ," "0,1" bitfld.long 0x00 24.--28. " SYND3 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23. " BEN2 ," "0,1" newline bitfld.long 0x00 16.--20. " SYND2 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15. " BEN1 ," "0,1" bitfld.long 0x00 8.--12. " SYND1 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7. " BEN0 ," "0,1" bitfld.long 0x00 0.--4. " SYND0 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xAFC++0x3 line.long 0x00 "CANFD1_ERR_STAT,CANFD1 Error Status Register" bitfld.long 0x00 19. " HNCEI ," "0,1" bitfld.long 0x00 18. " INCEI ," "0,1" bitfld.long 0x00 16. " CEI ," "0,1" newline bitfld.long 0x00 3. " HNCEIOV ," "0,1" bitfld.long 0x00 2. " INCEIOV ," "0,1" bitfld.long 0x00 0. " CEIOV ," "0,1" group.long 0xB00++0x3 line.long 0x00 "CANFD1_PN_CTL1,CANFD1 Pretended Networking Control1 Register" bitfld.long 0x00 17. " WTOFMSK ," "0,1" bitfld.long 0x00 16. " WUMFMSK ," "0,1" hexmask.long.byte 0x00 8.--15. 1. " MATCHCNT ," newline bitfld.long 0x00 4.--5. " PLFSEL ," "0,1,2,3" bitfld.long 0x00 2.--3. " IDFSEL ," "0,1,2,3" bitfld.long 0x00 0.--1. " FCSEL ," "0,1,2,3" group.long 0xB04++0x3 line.long 0x00 "CANFD1_PN_CTL2,CANFD1 Pretended Networking Control2 Register" hexmask.long.word 0x00 0.--15. 1. " MATCHTO ," group.long 0xB08++0x3 line.long 0x00 "CANFD1_WUM,CANFD1 Pretended Networking Wakeup Match Register" bitfld.long 0x00 17. " WTOF ," "0,1" bitfld.long 0x00 16. " WUMF ," "0,1" hexmask.long.byte 0x00 8.--15. 1. " MCNT ," group.long 0xB0C++0x3 line.long 0x00 "CANFD1_FLTR_ID1,CANFD1 Pretended Networking ID Filter1 Register" bitfld.long 0x00 30. " IDE ," "0,1" bitfld.long 0x00 29. " RTR ," "0,1" hexmask.long 0x00 0.--28. 1. " VALUE ," group.long 0xB10++0x3 line.long 0x00 "CANFD1_FLTR_DLC,CANFD1 Pretended Networking DLC Filter Register" bitfld.long 0x00 16.--19. " LO ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HI ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB14++0x3 line.long 0x00 "CANFD1_FLTR_DATA1_LO,CANFD1 Pretended Networking Payload Low Filter1 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB18++0x3 line.long 0x00 "CANFD1_FLTR_DATA1_HI,CANFD1 Pretended Networking Payload Low Filter2 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB1C++0x3 line.long 0x00 "CANFD1_FLTR_ID2_IDMSK,CANFD1 Pretended Networking ID Filter2 / IDMask Register" bitfld.long 0x00 30. " IDE ," "0,1" bitfld.long 0x00 29. " RTR ," "0,1" hexmask.long 0x00 0.--28. 1. " VALUE ," group.long 0xB20++0x3 line.long 0x00 "CANFD1_FLTR_DATA2_DMSK_LO,CANFD1 Pretended Networking Payload Low Filter2 / Payload Low Mask Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB24++0x3 line.long 0x00 "CANFD1_FLTR_DATA2_DMSK_HI,CANFD1 Pretended Networking Payload High Filter2 High Order Bits / Payload High Mask Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB40++0x3 line.long 0x00 "CANFD1_WMB0_STAT,CANFD1 Wakeup Message Buffer Control/Status Register" bitfld.long 0x00 22. " SRR ," "0,1" bitfld.long 0x00 21. " IDE ," "0,1" bitfld.long 0x00 20. " RTR ," "0,1" newline bitfld.long 0x00 16.--19. " DLC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB44++0x3 line.long 0x00 "CANFD1_WMB0_ID,CANFD1 Wakeup Message ID Buffer Register" hexmask.long 0x00 0.--28. 1. " RCVID ," group.long 0xB48++0x3 line.long 0x00 "CANFD1_WMB0_DATA_LO,CANFD1 Wakeup Message Buffer Data 0-3 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB4C++0x3 line.long 0x00 "CANFD1_WMB0_DATA_HI,CANFD1 Wakeup Message Buffer Data 4-7 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB50++0x3 line.long 0x00 "CANFD1_WMB1_STAT,CANFD1 Wakeup Message Buffer Control/Status Register" bitfld.long 0x00 22. " SRR ," "0,1" bitfld.long 0x00 21. " IDE ," "0,1" bitfld.long 0x00 20. " RTR ," "0,1" newline bitfld.long 0x00 16.--19. " DLC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB54++0x3 line.long 0x00 "CANFD1_WMB1_ID,CANFD1 Wakeup Message ID Buffer Register" hexmask.long 0x00 0.--28. 1. " RCVID ," group.long 0xB58++0x3 line.long 0x00 "CANFD1_WMB1_DATA_LO,CANFD1 Wakeup Message Buffer Data 0-3 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB5C++0x3 line.long 0x00 "CANFD1_WMB1_DATA_HI,CANFD1 Wakeup Message Buffer Data 4-7 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB60++0x3 line.long 0x00 "CANFD1_WMB2_STAT,CANFD1 Wakeup Message Buffer Control/Status Register" bitfld.long 0x00 22. " SRR ," "0,1" bitfld.long 0x00 21. " IDE ," "0,1" bitfld.long 0x00 20. " RTR ," "0,1" newline bitfld.long 0x00 16.--19. " DLC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB64++0x3 line.long 0x00 "CANFD1_WMB2_ID,CANFD1 Wakeup Message ID Buffer Register" hexmask.long 0x00 0.--28. 1. " RCVID ," group.long 0xB68++0x3 line.long 0x00 "CANFD1_WMB2_DATA_LO,CANFD1 Wakeup Message Buffer Data 0-3 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB6C++0x3 line.long 0x00 "CANFD1_WMB2_DATA_HI,CANFD1 Wakeup Message Buffer Data 4-7 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xB70++0x3 line.long 0x00 "CANFD1_WMB3_STAT,CANFD1 Wakeup Message Buffer Control/Status Register" bitfld.long 0x00 22. " SRR ," "0,1" bitfld.long 0x00 21. " IDE ," "0,1" bitfld.long 0x00 20. " RTR ," "0,1" newline bitfld.long 0x00 16.--19. " DLC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB74++0x3 line.long 0x00 "CANFD1_WMB3_ID,CANFD1 Wakeup Message ID Buffer Register" hexmask.long 0x00 0.--28. 1. " RCVID ," group.long 0xB78++0x3 line.long 0x00 "CANFD1_WMB3_DATA_LO,CANFD1 Wakeup Message Buffer Data 0-3 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB0 ," hexmask.long.byte 0x00 16.--23. 1. " PDB1 ," hexmask.long.byte 0x00 8.--15. 1. " PDB2 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB3 ," group.long 0xB7C++0x3 line.long 0x00 "CANFD1_WMB3_DATA_HI,CANFD1 Wakeup Message Buffer Data 4-7 Register" hexmask.long.byte 0x00 24.--31. 1. " PDB4 ," hexmask.long.byte 0x00 16.--23. 1. " PDB5 ," hexmask.long.byte 0x00 8.--15. 1. " PDB6 ," newline hexmask.long.byte 0x00 0.--7. 1. " PDB7 ," group.long 0xC00++0x3 line.long 0x00 "CANFD1_FD_CTL,CANFD1 CANFD Control Register" bitfld.long 0x00 31. " BRSEN ," "0,1" bitfld.long 0x00 25.--26. " MBDSIZR3 ," "0,1,2,3" bitfld.long 0x00 22.--23. " MBDSIZR2 ," "0,1,2,3" newline bitfld.long 0x00 19.--20. " MBDSIZR1 ," "0,1,2,3" bitfld.long 0x00 16.--17. " MBDSIZR0 ," "0,1,2,3" bitfld.long 0x00 15. " TDCOMPEN ," "0,1" newline bitfld.long 0x00 14. " TDCOMPFAIL ," "0,1" bitfld.long 0x00 8.--12. " TDCOMPOFF ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--5. " TDCOMPVAL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC04++0x3 line.long 0x00 "CANFD1_FD_TIMING,CANFD1 CANFD Bit Timing Register" hexmask.long.word 0x00 20.--29. 1. " FPRESDIV ," bitfld.long 0x00 16.--18. " FRJW ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--14. " FPROPSEG ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--7. " FPSEG1 ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " FPSEG2 ," "0,1,2,3,4,5,6,7" group.long 0xC08++0x3 line.long 0x00 "CANFD1_FD_CRC,CANFD1 CANFD CRC Register" hexmask.long.byte 0x00 24.--30. 1. " MB ," hexmask.long.tbyte 0x00 0.--20. 1. " TX ," tree.end endif tree "CDU (Clock Distribution Unit)" base ad:0x3108F000 width 15. group.long 0x0++0x3 line.long 0x00 "CDU0_CFG0,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x4++0x3 line.long 0x00 "CDU0_CFG1,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x8++0x3 line.long 0x00 "CDU0_CFG2,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0xC++0x3 line.long 0x00 "CDU0_CFG3,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x10++0x3 line.long 0x00 "CDU0_CFG4,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x14++0x3 line.long 0x00 "CDU0_CFG5,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x18++0x3 line.long 0x00 "CDU0_CFG6,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x1C++0x3 line.long 0x00 "CDU0_CFG7,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x20++0x3 line.long 0x00 "CDU0_CFG8,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x24++0x3 line.long 0x00 "CDU0_CFG9,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x28++0x3 line.long 0x00 "CDU0_CFG10,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x2C++0x3 line.long 0x00 "CDU0_CFG11,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x30++0x3 line.long 0x00 "CDU0_CFG12,CDU0 CDU Configuration" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 1.--2. " SEL ,Select Clock Input" "0,1,2,3" bitfld.long 0x00 0. " EN ,Clock Output Enabled" "0,1" group.long 0x40++0x3 line.long 0x00 "CDU0_STAT,CDU0 CDU Status" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 12. " CLKO12 ,CDU_CLKO12 Status" "0,1" newline bitfld.long 0x00 11. " CLKO11 ,CDU_CLKO11 Status" "0,1" bitfld.long 0x00 10. " CLKO10 ,CDU_CLKO10 Status" "0,1" bitfld.long 0x00 9. " CLKO9 ,CDU_CLKO9 Status" "0,1" newline bitfld.long 0x00 8. " CLKO8 ,CDU_CLKO8 Status" "0,1" bitfld.long 0x00 7. " CLKO7 ,CDU_CLKO7 Status" "0,1" bitfld.long 0x00 6. " CLKO6 ,CDU_CLKO6 Status" "0,1" newline bitfld.long 0x00 5. " CLKO5 ,CDU_CLKO5 Status" "0,1" bitfld.long 0x00 4. " CLKO4 ,CDU_CLKO4 Status" "0,1" bitfld.long 0x00 3. " CLKO3 ,CDU_CLKO3 Status" "0,1" newline bitfld.long 0x00 2. " CLKO2 ,CDU_CLKO2 Status" "0,1" bitfld.long 0x00 1. " CLKO1 ,CDU_CLKO1 Status" "0,1" bitfld.long 0x00 0. " CLKO0 ,CDU_CLKO0 Status" "0,1" group.long 0x44++0x3 line.long 0x00 "CDU0_CLKINSEL,CDU0 CLKIN Select" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 0. " CGU1 ,CGU1 CLKINn Select" "0,1" group.long 0x48++0x3 line.long 0x00 "CDU0_REVID,CDU0 CDU Revision ID" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "CGU (Clock Generation Unit)" tree "CGU0" base ad:0x3108D000 width 16. group.long 0x0++0x3 line.long 0x00 "CGU0_CTL,CGU0 Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 30. " WFI ,Wait For Idle" "0,1" bitfld.long 0x00 17. " S1SELEXEN ,SCLK1 Extension Divider Enable" "0,1" newline hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier Select" bitfld.long 0x00 0. " DF ,Divide Frequency" "0,1" group.long 0x4++0x3 line.long 0x00 "CGU0_PLLCTL,CGU0 PLL Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 3. " PLLEN ,PLL Enable" "0,1" bitfld.long 0x00 2. " PLLDIS ,PLL Disable" "0,1" newline bitfld.long 0x00 1. " PLLBPCL ,PLL Bypass Clear" "0,1" bitfld.long 0x00 0. " PLLBPST ,PLL Bypass Set" "0,1" group.long 0x8++0x3 line.long 0x00 "CGU0_STAT,CGU0 Status Register" bitfld.long 0x00 21. " PCFGERR ,PLL Configuration Error" "0,1" bitfld.long 0x00 20. " WDIVERR ,Write to DIV Error" "0,1" bitfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL Error" "0,1" newline bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADDRERR ,Address Error" "0,1" bitfld.long 0x00 15. " OSCWDSTATF ,Oscillator Watchdog Status Fault" "0,1" newline bitfld.long 0x00 12.--14. " OSCWDSTATFC ,Oscillator Watchdog Status Fault Code" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CLKSALGN ,Clock Alignment" "0,1" bitfld.long 0x00 2. " PLOCK ,PLL Lock" "0,1" newline bitfld.long 0x00 1. " PLLBP ,PLL Bypass" "0,1" bitfld.long 0x00 0. " PLLEN ,PLL Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "CGU0_DIV,CGU0 Clocks Divisor Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 30. " UPDT ,Update Clock Divisors" "0,1" bitfld.long 0x00 29. " ALGN ,Align" "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OCLK Divisor" bitfld.long 0x00 16.--20. " DSEL ,DCLK Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 Divisor" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 Divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " CSEL ,CCLK Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10++0x3 line.long 0x00 "CGU0_CLKOUTSEL,CGU0 CLKOUT Select Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 0.--4. " CLKOUTSEL ,CLKOUT Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14++0x3 line.long 0x00 "CGU0_OSCWDCTL,CGU0 Oscillator Watchdog Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 23. " FAULTPINDIS ,Fault Pin disabled" "0,1" bitfld.long 0x00 15. " MONDIS ,Oscillator Watchdog Monitor functions disabled" "0,1" newline bitfld.long 0x00 14. " FAULTEN ,Fault enabled" "0,1" bitfld.long 0x00 13. " BOUEN ,Bad Oscillator Upper Frequency limit detection enabled" "0,1" bitfld.long 0x00 8.--12. " BOUF ,Bad Oscillator Upper Frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7. " CNGEN ,Clock not Good enabled" "0,1" bitfld.long 0x00 6. " HODEN ,Harmonic Oscillation Detection enabled" "0,1" bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x18++0x3 line.long 0x00 "CGU0_TSCTL,CGU0 Time Stamp Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 4.--7. " TSDIV ,Counter's Clock Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " LOAD ,Load Counter" "0,1" newline bitfld.long 0x00 0. " EN ,Counter Enable" "0,1" group.long 0x1C++0x3 line.long 0x00 "CGU0_TSVALUE0,CGU0 Time Stamp Counter Initial 32 LSB Value Register" group.long 0x20++0x3 line.long 0x00 "CGU0_TSVALUE1,CGU0 Time Stamp Counter Initial MSB Value Register" group.long 0x24++0x3 line.long 0x00 "CGU0_TSCOUNT0,CGU0 Time Stamp Counter 32 LSB Register" group.long 0x28++0x3 line.long 0x00 "CGU0_TSCOUNT1,CGU0 Time Stamp Counter 32 MSB Register" group.long 0x2C++0x3 line.long 0x00 "CGU0_CCBF_DIS,CGU0 Core Clock Buffer Disable Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 0. " CCBF0 ,Core Clock Buffer 0" "0,1" group.long 0x30++0x3 line.long 0x00 "CGU0_CCBF_STAT,CGU0 Core Clock Buffer Status Register" bitfld.long 0x00 0. " CCBF0 ,Core Clock Buffer 0" "0,1" group.long 0x38++0x3 line.long 0x00 "CGU0_SCBF_DIS,CGU0 System Clock Buffer Disable Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 3. " OUTCLKBF ,OCLK Buffer" "0,1" bitfld.long 0x00 2. " DCLKBF ,DCLK Buffer" "0,1" newline bitfld.long 0x00 1. " SCLK1BF ,SCLK1 Buffer" "0,1" bitfld.long 0x00 0. " SCLK0BF ,SCLK0 Buffer" "0,1" group.long 0x3C++0x3 line.long 0x00 "CGU0_SCBF_STAT,CGU0 System Clock Buffer Status Register" bitfld.long 0x00 3. " OCLKBF ,OCLK Buffer" "0,1" bitfld.long 0x00 2. " DCLKBF ,DCLK1 Buffer" "0,1" bitfld.long 0x00 1. " SCLK1BF ,SCLK1 Buffer" "0,1" newline bitfld.long 0x00 0. " SCLK0BF ,SCLK0 Buffer" "0,1" group.long 0x40++0x3 line.long 0x00 "CGU0_DIVEX,CGU0 DIV Register Extension" hexmask.long.byte 0x00 16.--23. 1. " S1SELEX ,SCLK 1 Extension Divisor" group.long 0x48++0x3 line.long 0x00 "CGU0_REVID,CGU0 Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "CGU1" base ad:0x3108E000 width 16. group.long 0x0++0x3 line.long 0x00 "CGU1_CTL,CGU1 Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 30. " WFI ,Wait For Idle" "0,1" bitfld.long 0x00 17. " S1SELEXEN ,SCLK1 Extension Divider Enable" "0,1" newline hexmask.long.byte 0x00 8.--14. 1. " MSEL ,Multiplier Select" bitfld.long 0x00 0. " DF ,Divide Frequency" "0,1" group.long 0x4++0x3 line.long 0x00 "CGU1_PLLCTL,CGU1 PLL Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 3. " PLLEN ,PLL Enable" "0,1" bitfld.long 0x00 2. " PLLDIS ,PLL Disable" "0,1" newline bitfld.long 0x00 1. " PLLBPCL ,PLL Bypass Clear" "0,1" bitfld.long 0x00 0. " PLLBPST ,PLL Bypass Set" "0,1" group.long 0x8++0x3 line.long 0x00 "CGU1_STAT,CGU1 Status Register" bitfld.long 0x00 21. " PCFGERR ,PLL Configuration Error" "0,1" bitfld.long 0x00 20. " WDIVERR ,Write to DIV Error" "0,1" bitfld.long 0x00 19. " WDFMSERR ,Write to DF or MSEL Error" "0,1" newline bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADDRERR ,Address Error" "0,1" bitfld.long 0x00 15. " OSCWDSTATF ,Oscillator Watchdog Status Fault" "0,1" newline bitfld.long 0x00 12.--14. " OSCWDSTATFC ,Oscillator Watchdog Status Fault Code" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CLKSALGN ,Clock Alignment" "0,1" bitfld.long 0x00 2. " PLOCK ,PLL Lock" "0,1" newline bitfld.long 0x00 1. " PLLBP ,PLL Bypass" "0,1" bitfld.long 0x00 0. " PLLEN ,PLL Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "CGU1_DIV,CGU1 Clocks Divisor Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 30. " UPDT ,Update Clock Divisors" "0,1" bitfld.long 0x00 29. " ALGN ,Align" "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " OSEL ,OCLK Divisor" bitfld.long 0x00 16.--20. " DSEL ,DCLK Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 13.--15. " S1SEL ,SCLK 1 Divisor" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--12. " SYSSEL ,SYSCLK Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--7. " S0SEL ,SCLK 0 Divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " CSEL ,CCLK Divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14++0x3 line.long 0x00 "CGU1_OSCWDCTL,CGU1 Oscillator Watchdog Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 23. " FAULTPINDIS ,Fault Pin disabled" "0,1" bitfld.long 0x00 15. " MONDIS ,Oscillator Watchdog Monitor functions disabled" "0,1" newline bitfld.long 0x00 14. " FAULTEN ,Fault enabled" "0,1" bitfld.long 0x00 13. " BOUEN ,Bad Oscillator Upper Frequency limit detection enabled" "0,1" bitfld.long 0x00 8.--12. " BOUF ,Bad Oscillator Upper Frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 7. " CNGEN ,Clock not Good enabled" "0,1" bitfld.long 0x00 6. " HODEN ,Harmonic Oscillation Detection enabled" "0,1" bitfld.long 0x00 0.--5. " HODF ,Watchdog lower frequency limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2C++0x3 line.long 0x00 "CGU1_CCBF_DIS,CGU1 Core Clock Buffer Disable Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 0. " CCBF0 ,Core Clock Buffer 0" "0,1" group.long 0x30++0x3 line.long 0x00 "CGU1_CCBF_STAT,CGU1 Core Clock Buffer Status Register" bitfld.long 0x00 0. " CCBF0 ,Core Clock Buffer 0" "0,1" group.long 0x38++0x3 line.long 0x00 "CGU1_SCBF_DIS,CGU1 System Clock Buffer Disable Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 3. " OUTCLKBF ,OCLK Buffer" "0,1" bitfld.long 0x00 2. " DCLKBF ,DCLK Buffer" "0,1" newline bitfld.long 0x00 1. " SCLK1BF ,SCLK1 Buffer" "0,1" bitfld.long 0x00 0. " SCLK0BF ,SCLK0 Buffer" "0,1" group.long 0x3C++0x3 line.long 0x00 "CGU1_SCBF_STAT,CGU1 System Clock Buffer Status Register" bitfld.long 0x00 3. " OCLKBF ,OCLK Buffer" "0,1" bitfld.long 0x00 2. " DCLKBF ,DCLK1 Buffer" "0,1" bitfld.long 0x00 1. " SCLK1BF ,SCLK1 Buffer" "0,1" newline bitfld.long 0x00 0. " SCLK0BF ,SCLK0 Buffer" "0,1" group.long 0x40++0x3 line.long 0x00 "CGU1_DIVEX,CGU1 DIV Register Extension" hexmask.long.byte 0x00 16.--23. 1. " S1SELEX ,SCLK 1 Extension Divisor" group.long 0x48++0x3 line.long 0x00 "CGU1_REVID,CGU1 Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree.end tree "CNT (General-Purpose Counter)" base ad:0x3100B000 width 13. group.long 0x0++0x3 line.long 0x00 "CNT0_CFG,CNT0 Configuration Register" bitfld.long 0x00 15. " INPDIS ,CUD and CDG Pin Input Disable" "0,1" bitfld.long 0x00 12.--13. " BNDMODE ,Boundary Register Mode" "0,1,2,3" bitfld.long 0x00 11. " ZMZC ,CZM Zeros Counter Enable" "0,1" newline bitfld.long 0x00 8.--10. " CNTMODE ,Counter Operating Mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. " CZMINV ,CZM Pin Polarity Invert" "0,1" bitfld.long 0x00 5. " CUDINV ,CUD Pin Polarity Invert" "0,1" newline bitfld.long 0x00 4. " CDGINV ,CDG Pin Polarity Invert" "0,1" bitfld.long 0x00 1. " DEBEN ,Debounce Enable" "0,1" bitfld.long 0x00 0. " EN ,Counter Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "CNT0_IMSK,CNT0 Interrupt Mask Register" bitfld.long 0x00 10. " CZMZ ,Counter Zeroed by Zero Marker Interrupt Enable" "0,1" bitfld.long 0x00 9. " CZME ,Zero Marker Error Interrupt Enable" "0,1" bitfld.long 0x00 8. " CZM ,CZM Pin/Pushbutton Interrupt Enable" "0,1" newline bitfld.long 0x00 7. " CZERO ,CNT_CNTR Counts To Zero Interrupt Enable" "0,1" bitfld.long 0x00 6. " COV15 ,Bit 15 Overflow Interrupt Enable" "0,1" bitfld.long 0x00 5. " COV31 ,Bit 31 Overflow Interrupt Enable" "0,1" newline bitfld.long 0x00 4. " MAXC ,Max Count Interrupt Enable" "0,1" bitfld.long 0x00 3. " MINC ,Min Count Interrupt Enable" "0,1" bitfld.long 0x00 2. " DC ,Downcount Interrupt Enable" "0,1" newline bitfld.long 0x00 1. " UC ,Upcount Interrupt Enable" "0,1" bitfld.long 0x00 0. " IC ,Illegal Gray/Binary Code Interrupt Enable" "0,1" group.long 0x8++0x3 line.long 0x00 "CNT0_STAT,CNT0 Status Register" bitfld.long 0x00 10. " CZMZ ,Counter Zeroed By Zero Marker Interrupt" "0,1" bitfld.long 0x00 9. " CZME ,Zero Marker Error Interrupt" "0,1" bitfld.long 0x00 8. " CZM ,CZM Pin/Pushbutton Interrupt" "0,1" newline bitfld.long 0x00 7. " CZERO ,CNT_CNTR Counts To Zero Interrupt" "0,1" bitfld.long 0x00 6. " COV15 ,Bit 15 Overflow Interrupt" "0,1" bitfld.long 0x00 5. " COV31 ,Bit 31 Overflow Interrupt" "0,1" newline bitfld.long 0x00 4. " MAXC ,Max Count Interrupt" "0,1" bitfld.long 0x00 3. " MINC ,Min Count Interrupt" "0,1" bitfld.long 0x00 2. " DC ,Down Count Interrupt" "0,1" newline bitfld.long 0x00 1. " UC ,Up Count Interrupt" "0,1" bitfld.long 0x00 0. " IC ,Illegal Gray/Binary Code Interrupt" "0,1" group.long 0xC++0x3 line.long 0x00 "CNT0_CMD,CNT0 Command Register" bitfld.long 0x00 12. " W1ZMONCE ,Write 1 Zero Marker Clear Once Enable" "0,1" bitfld.long 0x00 10. " W1LMAXMIN ,Write 1 MAX Copy from MIN" "0,1" bitfld.long 0x00 9. " W1LMAXCNT ,Write 1 MAX Capture from CNTR" "0,1" newline bitfld.long 0x00 8. " W1LMAXZERO ,Write 1 MAX to Zero" "0,1" bitfld.long 0x00 7. " W1LMINMAX ,Write 1 MIN Copy from MAX" "0,1" bitfld.long 0x00 5. " W1LMINCNT ,Write 1 MIN Capture from CNTR" "0,1" newline bitfld.long 0x00 4. " W1LMINZERO ,Write 1 MIN to Zero" "0,1" bitfld.long 0x00 3. " W1LCNTMAX ,Write 1 CNTR Load from MAX" "0,1" bitfld.long 0x00 2. " W1LCNTMIN ,Write 1 CNTR Load from MIN" "0,1" newline bitfld.long 0x00 0. " W1LCNTZERO ,Write 1 CNTR to Zero" "0,1" group.long 0x10++0x3 line.long 0x00 "CNT0_DEBNCE,CNT0 Debounce Register" bitfld.long 0x00 0.--4. " DPRESCALE ,Debounce Prescale" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x14++0x3 line.long 0x00 "CNT0_CNTR,CNT0 Counter Register" group.long 0x18++0x3 line.long 0x00 "CNT0_MAX,CNT0 Maximum Count Register" group.long 0x1C++0x3 line.long 0x00 "CNT0_MIN,CNT0 Minimum Count Register" tree.end tree "CRC (Cyclic Redundancy Check)" tree "CRC0" base ad:0x310A5000 width 17. group.long 0x0++0x3 line.long 0x00 "CRC0_CTL,CRC0 Control Register" bitfld.long 0x00 22. " CMPMIRR ,COMPARE Register Mirroring" "0,1" bitfld.long 0x00 21. " POLYMIRR ,Polynomial Register Mirroring" "0,1" bitfld.long 0x00 20. " RSLTMIRR ,Result Register Mirroring" "0,1" newline bitfld.long 0x00 19. " FDSEL ,FIFO Data Select" "0,1" bitfld.long 0x00 18. " W16SWP ,Word16 Swapping" "0,1" bitfld.long 0x00 17. " BYTMIRR ,Byte Mirroring" "0,1" newline bitfld.long 0x00 16. " BITMIRR ,Bit Mirroring" "0,1" bitfld.long 0x00 13. " IRRSTALL ,Intermediate Result Ready Stall" "0,1" bitfld.long 0x00 12. " OBRSTALL ,Output Buffer Ready Stall" "0,1" newline bitfld.long 0x00 9. " AUTOCLRF ,Auto Clear to One" "0,1" bitfld.long 0x00 8. " AUTOCLRZ ,Auto Clear to Zero" "0,1" bitfld.long 0x00 4.--7. " OPMODE ,Operation Mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " BLKEN ,Block Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "CRC0_DCNT,CRC0 Data Word Count Register" group.long 0x8++0x3 line.long 0x00 "CRC0_DCNTRLD,CRC0 Data Word Count Reload Register" group.long 0x14++0x3 line.long 0x00 "CRC0_COMP,CRC0 Data Compare Register" group.long 0x18++0x3 line.long 0x00 "CRC0_FILLVAL,CRC0 Fill Value Register" group.long 0x1C++0x3 line.long 0x00 "CRC0_DFIFO,CRC0 Data FIFO Register" group.long 0x20++0x3 line.long 0x00 "CRC0_INEN,CRC0 Interrupt Enable Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired (Status) Interrupt Enable" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Interrupt Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "CRC0_INEN_SET,CRC0 Interrupt Enable Set Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired (Status) Interrupt Enable Set" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Interrupt" "0,1" group.long 0x28++0x3 line.long 0x00 "CRC0_INEN_CLR,CRC0 Interrupt Enable Clear Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Clear" "0,1" group.long 0x2C++0x3 line.long 0x00 "CRC0_POLY,CRC0 Polynomial Register" group.long 0x40++0x3 line.long 0x00 "CRC0_STAT,CRC0 Status Register" bitfld.long 0x00 20.--22. " FSTAT ,FIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " LUTDONE ,Look-Up Table Done" "0,1" bitfld.long 0x00 18. " IRR ,Intermediate Result Ready" "0,1" newline bitfld.long 0x00 17. " OBR ,Output Buffer Ready" "0,1" bitfld.long 0x00 16. " IBR ,Input Buffer Ready" "0,1" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired" "0,1" newline bitfld.long 0x00 1. " CMPERR ,Compare Error" "0,1" group.long 0x44++0x3 line.long 0x00 "CRC0_DCNTCAP,CRC0 Data Count Capture Register" group.long 0x4C++0x3 line.long 0x00 "CRC0_RESULT_FIN,CRC0 CRC Final Result Register" group.long 0x50++0x3 line.long 0x00 "CRC0_RESULT_CUR,CRC0 CRC Current Result Register" tree.end tree "CRC1" base ad:0x310a6000 width 17. group.long 0x0++0x3 line.long 0x00 "CRC1_CTL,CRC1 Control Register" bitfld.long 0x00 22. " CMPMIRR ,COMPARE Register Mirroring" "0,1" bitfld.long 0x00 21. " POLYMIRR ,Polynomial Register Mirroring" "0,1" bitfld.long 0x00 20. " RSLTMIRR ,Result Register Mirroring" "0,1" newline bitfld.long 0x00 19. " FDSEL ,FIFO Data Select" "0,1" bitfld.long 0x00 18. " W16SWP ,Word16 Swapping" "0,1" bitfld.long 0x00 17. " BYTMIRR ,Byte Mirroring" "0,1" newline bitfld.long 0x00 16. " BITMIRR ,Bit Mirroring" "0,1" bitfld.long 0x00 13. " IRRSTALL ,Intermediate Result Ready Stall" "0,1" bitfld.long 0x00 12. " OBRSTALL ,Output Buffer Ready Stall" "0,1" newline bitfld.long 0x00 9. " AUTOCLRF ,Auto Clear to One" "0,1" bitfld.long 0x00 8. " AUTOCLRZ ,Auto Clear to Zero" "0,1" bitfld.long 0x00 4.--7. " OPMODE ,Operation Mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " BLKEN ,Block Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "CRC1_DCNT,CRC1 Data Word Count Register" group.long 0x8++0x3 line.long 0x00 "CRC1_DCNTRLD,CRC1 Data Word Count Reload Register" group.long 0x14++0x3 line.long 0x00 "CRC1_COMP,CRC1 Data Compare Register" group.long 0x18++0x3 line.long 0x00 "CRC1_FILLVAL,CRC1 Fill Value Register" group.long 0x1C++0x3 line.long 0x00 "CRC1_DFIFO,CRC1 Data FIFO Register" group.long 0x20++0x3 line.long 0x00 "CRC1_INEN,CRC1 Interrupt Enable Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired (Status) Interrupt Enable" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Interrupt Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "CRC1_INEN_SET,CRC1 Interrupt Enable Set Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired (Status) Interrupt Enable Set" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Interrupt" "0,1" group.long 0x28++0x3 line.long 0x00 "CRC1_INEN_CLR,CRC1 Interrupt Enable Clear Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Clear" "0,1" group.long 0x2C++0x3 line.long 0x00 "CRC1_POLY,CRC1 Polynomial Register" group.long 0x40++0x3 line.long 0x00 "CRC1_STAT,CRC1 Status Register" bitfld.long 0x00 20.--22. " FSTAT ,FIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " LUTDONE ,Look-Up Table Done" "0,1" bitfld.long 0x00 18. " IRR ,Intermediate Result Ready" "0,1" newline bitfld.long 0x00 17. " OBR ,Output Buffer Ready" "0,1" bitfld.long 0x00 16. " IBR ,Input Buffer Ready" "0,1" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired" "0,1" newline bitfld.long 0x00 1. " CMPERR ,Compare Error" "0,1" group.long 0x44++0x3 line.long 0x00 "CRC1_DCNTCAP,CRC1 Data Count Capture Register" group.long 0x4C++0x3 line.long 0x00 "CRC1_RESULT_FIN,CRC1 CRC Final Result Register" group.long 0x50++0x3 line.long 0x00 "CRC1_RESULT_CUR,CRC1 CRC Current Result Register" tree.end tree "CRC2" base ad:0x310AA000 width 17. group.long 0x0++0x3 line.long 0x00 "CRC2_CTL,CRC2 Control Register" bitfld.long 0x00 22. " CMPMIRR ,COMPARE Register Mirroring" "0,1" bitfld.long 0x00 21. " POLYMIRR ,Polynomial Register Mirroring" "0,1" bitfld.long 0x00 20. " RSLTMIRR ,Result Register Mirroring" "0,1" newline bitfld.long 0x00 19. " FDSEL ,FIFO Data Select" "0,1" bitfld.long 0x00 18. " W16SWP ,Word16 Swapping" "0,1" bitfld.long 0x00 17. " BYTMIRR ,Byte Mirroring" "0,1" newline bitfld.long 0x00 16. " BITMIRR ,Bit Mirroring" "0,1" bitfld.long 0x00 13. " IRRSTALL ,Intermediate Result Ready Stall" "0,1" bitfld.long 0x00 12. " OBRSTALL ,Output Buffer Ready Stall" "0,1" newline bitfld.long 0x00 9. " AUTOCLRF ,Auto Clear to One" "0,1" bitfld.long 0x00 8. " AUTOCLRZ ,Auto Clear to Zero" "0,1" bitfld.long 0x00 4.--7. " OPMODE ,Operation Mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " BLKEN ,Block Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "CRC2_DCNT,CRC2 Data Word Count Register" group.long 0x8++0x3 line.long 0x00 "CRC2_DCNTRLD,CRC2 Data Word Count Reload Register" group.long 0x14++0x3 line.long 0x00 "CRC2_COMP,CRC2 Data Compare Register" group.long 0x18++0x3 line.long 0x00 "CRC2_FILLVAL,CRC2 Fill Value Register" group.long 0x1C++0x3 line.long 0x00 "CRC2_DFIFO,CRC2 Data FIFO Register" group.long 0x20++0x3 line.long 0x00 "CRC2_INEN,CRC2 Interrupt Enable Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired (Status) Interrupt Enable" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Interrupt Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "CRC2_INEN_SET,CRC2 Interrupt Enable Set Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired (Status) Interrupt Enable Set" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Interrupt" "0,1" group.long 0x28++0x3 line.long 0x00 "CRC2_INEN_CLR,CRC2 Interrupt Enable Clear Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Clear" "0,1" group.long 0x2C++0x3 line.long 0x00 "CRC2_POLY,CRC2 Polynomial Register" group.long 0x40++0x3 line.long 0x00 "CRC2_STAT,CRC2 Status Register" bitfld.long 0x00 20.--22. " FSTAT ,FIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " LUTDONE ,Look-Up Table Done" "0,1" bitfld.long 0x00 18. " IRR ,Intermediate Result Ready" "0,1" newline bitfld.long 0x00 17. " OBR ,Output Buffer Ready" "0,1" bitfld.long 0x00 16. " IBR ,Input Buffer Ready" "0,1" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired" "0,1" newline bitfld.long 0x00 1. " CMPERR ,Compare Error" "0,1" group.long 0x44++0x3 line.long 0x00 "CRC2_DCNTCAP,CRC2 Data Count Capture Register" group.long 0x4C++0x3 line.long 0x00 "CRC2_RESULT_FIN,CRC2 CRC Final Result Register" group.long 0x50++0x3 line.long 0x00 "CRC2_RESULT_CUR,CRC2 CRC Current Result Register" tree.end tree "CRC3" base ad:0x310AB000 width 17. group.long 0x0++0x3 line.long 0x00 "CRC3_CTL,CRC3 Control Register" bitfld.long 0x00 22. " CMPMIRR ,COMPARE Register Mirroring" "0,1" bitfld.long 0x00 21. " POLYMIRR ,Polynomial Register Mirroring" "0,1" bitfld.long 0x00 20. " RSLTMIRR ,Result Register Mirroring" "0,1" newline bitfld.long 0x00 19. " FDSEL ,FIFO Data Select" "0,1" bitfld.long 0x00 18. " W16SWP ,Word16 Swapping" "0,1" bitfld.long 0x00 17. " BYTMIRR ,Byte Mirroring" "0,1" newline bitfld.long 0x00 16. " BITMIRR ,Bit Mirroring" "0,1" bitfld.long 0x00 13. " IRRSTALL ,Intermediate Result Ready Stall" "0,1" bitfld.long 0x00 12. " OBRSTALL ,Output Buffer Ready Stall" "0,1" newline bitfld.long 0x00 9. " AUTOCLRF ,Auto Clear to One" "0,1" bitfld.long 0x00 8. " AUTOCLRZ ,Auto Clear to Zero" "0,1" bitfld.long 0x00 4.--7. " OPMODE ,Operation Mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " BLKEN ,Block Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "CRC3_DCNT,CRC3 Data Word Count Register" group.long 0x8++0x3 line.long 0x00 "CRC3_DCNTRLD,CRC3 Data Word Count Reload Register" group.long 0x14++0x3 line.long 0x00 "CRC3_COMP,CRC3 Data Compare Register" group.long 0x18++0x3 line.long 0x00 "CRC3_FILLVAL,CRC3 Fill Value Register" group.long 0x1C++0x3 line.long 0x00 "CRC3_DFIFO,CRC3 Data FIFO Register" group.long 0x20++0x3 line.long 0x00 "CRC3_INEN,CRC3 Interrupt Enable Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired (Status) Interrupt Enable" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Interrupt Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "CRC3_INEN_SET,CRC3 Interrupt Enable Set Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired (Status) Interrupt Enable Set" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Interrupt" "0,1" group.long 0x28++0x3 line.long 0x00 "CRC3_INEN_CLR,CRC3 Interrupt Enable Clear Register" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired" "0,1" bitfld.long 0x00 1. " CMPERR ,Compare Error Clear" "0,1" group.long 0x2C++0x3 line.long 0x00 "CRC3_POLY,CRC3 Polynomial Register" group.long 0x40++0x3 line.long 0x00 "CRC3_STAT,CRC3 Status Register" bitfld.long 0x00 20.--22. " FSTAT ,FIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " LUTDONE ,Look-Up Table Done" "0,1" bitfld.long 0x00 18. " IRR ,Intermediate Result Ready" "0,1" newline bitfld.long 0x00 17. " OBR ,Output Buffer Ready" "0,1" bitfld.long 0x00 16. " IBR ,Input Buffer Ready" "0,1" bitfld.long 0x00 4. " DCNTEXP ,Data Count Expired" "0,1" newline bitfld.long 0x00 1. " CMPERR ,Compare Error" "0,1" group.long 0x44++0x3 line.long 0x00 "CRC3_DCNTCAP,CRC3 Data Count Capture Register" group.long 0x4C++0x3 line.long 0x00 "CRC3_RESULT_FIN,CRC3 CRC Final Result Register" group.long 0x50++0x3 line.long 0x00 "CRC3_RESULT_CUR,CRC3 CRC Current Result Register" tree.end tree.end tree "CSPFT0" base ad:0x31103000 width 19. group.long 0x0++0x3 line.long 0x00 "CSPFT0_CTL,CSPFT0 Main Control Register" bitfld.long 0x00 29. " RSENA ,Return Stack Enable" "0,1" bitfld.long 0x00 14.--15. " CIDSZ ,Context ID Size" "0,1,2,3" bitfld.long 0x00 10. " PB ,Programming Bit" "0,1" newline bitfld.long 0x00 8. " BBRAN ,Branch Broadcast" "0,1" group.long 0x4++0x3 line.long 0x00 "CSPFT0_HWFEAT,CSPFT0 Hardware Feature Register" bitfld.long 0x00 24.--25. " NCIDC ,Number of Context ID Comparators" "0,1,2,3" bitfld.long 0x00 20.--22. " NEXO ,Number of External Outputs" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " NEXI ,Number of External Inputs" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 13.--15. " NCNTR ,Number of Counters" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " NACMP ,Number of Pairs of Address Comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8++0x3 line.long 0x00 "CSPFT0_TRIGGER,CSPFT0 Trigger Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x10++0x3 line.long 0x00 "CSPFT0_STAT,CSPFT0 Status Register" bitfld.long 0x00 3. " TRIG ,Trigger Bit" "0,1" bitfld.long 0x00 2. " TSS ,Trace Start/Stop Bit Status" "0,1" bitfld.long 0x00 1. " PB ,Prog Bit Status" "0,1" newline bitfld.long 0x00 0. " OF ,Overflow" "0,1" group.long 0x18++0x3 line.long 0x00 "CSPFT0_TSSCTL,CSPFT0 TraceEnable Start/Stop Control Register" hexmask.long.word 0x00 16.--31. 1. " STOP ,Stop Address Comparator Select Bits" hexmask.long.word 0x00 0.--15. 1. " START ,Start Address Comparator Select Bits" group.long 0x20++0x3 line.long 0x00 "CSPFT0_TEEVENT,CSPFT0 TraceEnable Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x24++0x3 line.long 0x00 "CSPFT0_TECTL,CSPFT0 TraceEnable Control Register" bitfld.long 0x00 25. " TSSCENA ,Trace Start and Stop Control Enable" "0,1" bitfld.long 0x00 24. " EXCL ,Include and Exclude Control" "0,1" hexmask.long.byte 0x00 0.--7. 1. " ARCS ,Address Range Comparator Select Bits" group.long 0x40++0x3 line.long 0x00 "CSPFT0_ACVR0,CSPFT0 Address Comparator Value Register" group.long 0x44++0x3 line.long 0x00 "CSPFT0_ACVR1,CSPFT0 Address Comparator Value Register" group.long 0x48++0x3 line.long 0x00 "CSPFT0_ACVR2,CSPFT0 Address Comparator Value Register" group.long 0x4C++0x3 line.long 0x00 "CSPFT0_ACVR3,CSPFT0 Address Comparator Value Register" group.long 0x80++0x3 line.long 0x00 "CSPFT0_ACTR0,CSPFT0 Address Comparator Access Type Register" bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID Comparator Control" "0,1,2,3" group.long 0x84++0x3 line.long 0x00 "CSPFT0_ACTR1,CSPFT0 Address Comparator Access Type Register" bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID Comparator Control" "0,1,2,3" group.long 0x88++0x3 line.long 0x00 "CSPFT0_ACTR2,CSPFT0 Address Comparator Access Type Register" bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID Comparator Control" "0,1,2,3" group.long 0x8C++0x3 line.long 0x00 "CSPFT0_ACTR3,CSPFT0 Address Comparator Access Type Register" bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID Comparator Control" "0,1,2,3" group.long 0x140++0x3 line.long 0x00 "CSPFT0_CNTRLDVR0,CSPFT0 Counter Reload Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Counter Initial Value" group.long 0x144++0x3 line.long 0x00 "CSPFT0_CNTRLDVR1,CSPFT0 Counter Reload Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Counter Initial Value" group.long 0x150++0x3 line.long 0x00 "CSPFT0_CNTENR0,CSPFT0 Counter Enable Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x154++0x3 line.long 0x00 "CSPFT0_CNTENR1,CSPFT0 Counter Enable Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x160++0x3 line.long 0x00 "CSPFT0_CNTRLDEVR0,CSPFT0 Counter Reload Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x164++0x3 line.long 0x00 "CSPFT0_CNTRLDEVR1,CSPFT0 Counter Reload Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x170++0x3 line.long 0x00 "CSPFT0_CNTVR0,CSPFT0 Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Current Counter Value" group.long 0x174++0x3 line.long 0x00 "CSPFT0_CNTVR1,CSPFT0 Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Current Counter Value" group.long 0x1A0++0x3 line.long 0x00 "CSPFT0_EXTOUTEVR0,CSPFT0 External Output Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x1A4++0x3 line.long 0x00 "CSPFT0_EXTOUTEVR1,CSPFT0 External Output Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x1A8++0x3 line.long 0x00 "CSPFT0_EXTOUTEVR2,CSPFT0 External Output Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x1AC++0x3 line.long 0x00 "CSPFT0_EXTOUTEVR3,CSPFT0 External Output Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x1B0++0x3 line.long 0x00 "CSPFT0_CIDCVR0,CSPFT0 Context ID Comparator Value" group.long 0x1BC++0x3 line.long 0x00 "CSPFT0_CIDCMR,CSPFT0 Context ID Comparator Mask Register" group.long 0x1E0++0x3 line.long 0x00 "CSPFT0_SYNCFR,CSPFT0 Synchronization Frequency Register" hexmask.long.word 0x00 0.--11. 1. " SFREQ ,Synchronization frequency" group.long 0x1E8++0x3 line.long 0x00 "CSPFT0_CCER,CSPFT0 Configuration Code Extension Register" bitfld.long 0x00 26. " VEI ,Virtualization Extensions Implemented" "0,1" bitfld.long 0x00 23. " RSI ,Return Stack Implemented" "0,1" bitfld.long 0x00 22. " TSI ,Time Stamping Implemented" "0,1" group.long 0x200++0x3 line.long 0x00 "CSPFT0_TRACEIDR,CSPFT0 CoreSight Trace ID Register" hexmask.long.byte 0x00 0.--6. 1. " TID ,Trace ID" group.long 0xFA0++0x3 line.long 0x00 "CSPFT0_CLAIMSET,CSPFT0 Claim Tag Set Register" bitfld.long 0x00 0.--3. " TAGS ,Supported Tags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFA4++0x3 line.long 0x00 "CSPFT0_CLAIMCLR,CSPFT0 Claim Tag Clear Register" bitfld.long 0x00 0.--3. " TAGS ,Tags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFB0++0x3 line.long 0x00 "CSPFT0_LAR,CSPFT0 Lock Access Register" group.long 0xFB4++0x3 line.long 0x00 "CSPFT0_LSR,CSPFT0 Lock Status Register" bitfld.long 0x00 1. " LOCKED ,Lock Status" "0,1" bitfld.long 0x00 0. " LOCKEN ,Locking Supported" "0,1" group.long 0xFB8++0x3 line.long 0x00 "CSPFT0_AUTHSTATUS,CSPFT0 Authentication Status Register" bitfld.long 0x00 7. " ONE ,Always reads as one" "0,1" bitfld.long 0x00 6. " DBGEN ,Debug Enabled" "0,1" group.long 0xFCC++0x3 line.long 0x00 "CSPFT0_DEVTYPE,CSPFT0 Device Type Identifier Register" bitfld.long 0x00 4.--7. " STYPE ,Sub Type = DSP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TYPE ,Device Type = Trace Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFD0++0x3 line.long 0x00 "CSPFT0_PID4,CSPFT0 Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,Number of 4K Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " JEOP106CC ,JEOP106 continuation code (number of leading 0x7Fs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE0++0x3 line.long 0x00 "CSPFT0_PID0,CSPFT0 Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PARTNUM ,Part Number" group.long 0xFE4++0x3 line.long 0x00 "CSPFT0_PID1,CSPFT0 Peripheral ID1 Register" bitfld.long 0x00 4.--7. " JEP106 ,JEDEC JEP106 Manufacturer ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PARTNUM ,Part Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE8++0x3 line.long 0x00 "CSPFT0_PID2,CSPFT0 Peripheral ID2 Register" bitfld.long 0x00 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " JEDECASGN ,A JEDEC Assigned Value is Used" "0,1" bitfld.long 0x00 0.--2. " JEP106 ,JEDEC JEP106 Manufacturer ID code" "0,1,2,3,4,5,6,7" group.long 0xFEC++0x3 line.long 0x00 "CSPFT0_PID3,CSPFT0 Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Field to mark metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CUSTMOD ,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF0++0x3 line.long 0x00 "CSPFT0_CID0,CSPFT0 Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPID ,Component ID" group.long 0xFF4++0x3 line.long 0x00 "CSPFT0_CID1,CSPFT0 Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPID ,Component ID" group.long 0xFF8++0x3 line.long 0x00 "CSPFT0_CID2,CSPFT0 Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPID ,Component ID" group.long 0xFFC++0x3 line.long 0x00 "CSPFT0_CID3,CSPFT0 Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPID ,Component ID" tree.end tree "CSPFT1" base ad:0x31107000 width 19. group.long 0x0++0x3 line.long 0x00 "CSPFT1_CTL,CSPFT1 Main Control Register" bitfld.long 0x00 29. " RSENA ,Return Stack Enable" "0,1" bitfld.long 0x00 14.--15. " CIDSZ ,Context ID Size" "0,1,2,3" bitfld.long 0x00 10. " PB ,Programming Bit" "0,1" newline bitfld.long 0x00 8. " BBRAN ,Branch Broadcast" "0,1" group.long 0x4++0x3 line.long 0x00 "CSPFT1_HWFEAT,CSPFT1 Hardware Feature Register" bitfld.long 0x00 24.--25. " NCIDC ,Number of Context ID Comparators" "0,1,2,3" bitfld.long 0x00 20.--22. " NEXO ,Number of External Outputs" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " NEXI ,Number of External Inputs" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 13.--15. " NCNTR ,Number of Counters" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " NACMP ,Number of Pairs of Address Comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8++0x3 line.long 0x00 "CSPFT1_TRIGGER,CSPFT1 Trigger Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x10++0x3 line.long 0x00 "CSPFT1_STAT,CSPFT1 Status Register" bitfld.long 0x00 3. " TRIG ,Trigger Bit" "0,1" bitfld.long 0x00 2. " TSS ,Trace Start/Stop Bit Status" "0,1" bitfld.long 0x00 1. " PB ,Prog Bit Status" "0,1" newline bitfld.long 0x00 0. " OF ,Overflow" "0,1" group.long 0x18++0x3 line.long 0x00 "CSPFT1_TSSCTL,CSPFT1 TraceEnable Start/Stop Control Register" hexmask.long.word 0x00 16.--31. 1. " STOP ,Stop Address Comparator Select Bits" hexmask.long.word 0x00 0.--15. 1. " START ,Start Address Comparator Select Bits" group.long 0x20++0x3 line.long 0x00 "CSPFT1_TEEVENT,CSPFT1 TraceEnable Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x24++0x3 line.long 0x00 "CSPFT1_TECTL,CSPFT1 TraceEnable Control Register" bitfld.long 0x00 25. " TSSCENA ,Trace Start and Stop Control Enable" "0,1" bitfld.long 0x00 24. " EXCL ,Include and Exclude Control" "0,1" hexmask.long.byte 0x00 0.--7. 1. " ARCS ,Address Range Comparator Select Bits" group.long 0x40++0x3 line.long 0x00 "CSPFT1_ACVR0,CSPFT1 Address Comparator Value Register" group.long 0x44++0x3 line.long 0x00 "CSPFT1_ACVR1,CSPFT1 Address Comparator Value Register" group.long 0x48++0x3 line.long 0x00 "CSPFT1_ACVR2,CSPFT1 Address Comparator Value Register" group.long 0x4C++0x3 line.long 0x00 "CSPFT1_ACVR3,CSPFT1 Address Comparator Value Register" group.long 0x80++0x3 line.long 0x00 "CSPFT1_ACTR0,CSPFT1 Address Comparator Access Type Register" bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID Comparator Control" "0,1,2,3" group.long 0x84++0x3 line.long 0x00 "CSPFT1_ACTR1,CSPFT1 Address Comparator Access Type Register" bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID Comparator Control" "0,1,2,3" group.long 0x88++0x3 line.long 0x00 "CSPFT1_ACTR2,CSPFT1 Address Comparator Access Type Register" bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID Comparator Control" "0,1,2,3" group.long 0x8C++0x3 line.long 0x00 "CSPFT1_ACTR3,CSPFT1 Address Comparator Access Type Register" bitfld.long 0x00 8.--9. " CIDCTRL ,Context ID Comparator Control" "0,1,2,3" group.long 0x140++0x3 line.long 0x00 "CSPFT1_CNTRLDVR0,CSPFT1 Counter Reload Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Counter Initial Value" group.long 0x144++0x3 line.long 0x00 "CSPFT1_CNTRLDVR1,CSPFT1 Counter Reload Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Counter Initial Value" group.long 0x150++0x3 line.long 0x00 "CSPFT1_CNTENR0,CSPFT1 Counter Enable Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x154++0x3 line.long 0x00 "CSPFT1_CNTENR1,CSPFT1 Counter Enable Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x160++0x3 line.long 0x00 "CSPFT1_CNTRLDEVR0,CSPFT1 Counter Reload Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x164++0x3 line.long 0x00 "CSPFT1_CNTRLDEVR1,CSPFT1 Counter Reload Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x170++0x3 line.long 0x00 "CSPFT1_CNTVR0,CSPFT1 Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Current Counter Value" group.long 0x174++0x3 line.long 0x00 "CSPFT1_CNTVR1,CSPFT1 Counter Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Current Counter Value" group.long 0x1A0++0x3 line.long 0x00 "CSPFT1_EXTOUTEVR0,CSPFT1 External Output Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x1A4++0x3 line.long 0x00 "CSPFT1_EXTOUTEVR1,CSPFT1 External Output Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x1A8++0x3 line.long 0x00 "CSPFT1_EXTOUTEVR2,CSPFT1 External Output Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x1AC++0x3 line.long 0x00 "CSPFT1_EXTOUTEVR3,CSPFT1 External Output Event Register" bitfld.long 0x00 14.--16. " FUNC ,Function" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 7.--13. 1. " RESB ,Resource B" hexmask.long.byte 0x00 0.--6. 1. " RESA ,Resource A" group.long 0x1B0++0x3 line.long 0x00 "CSPFT1_CIDCVR0,CSPFT1 Context ID Comparator Value" group.long 0x1BC++0x3 line.long 0x00 "CSPFT1_CIDCMR,CSPFT1 Context ID Comparator Mask Register" group.long 0x1E0++0x3 line.long 0x00 "CSPFT1_SYNCFR,CSPFT1 Synchronization Frequency Register" hexmask.long.word 0x00 0.--11. 1. " SFREQ ,Synchronization frequency" group.long 0x1E8++0x3 line.long 0x00 "CSPFT1_CCER,CSPFT1 Configuration Code Extension Register" bitfld.long 0x00 26. " VEI ,Virtualization Extensions Implemented" "0,1" bitfld.long 0x00 23. " RSI ,Return Stack Implemented" "0,1" bitfld.long 0x00 22. " TSI ,Time Stamping Implemented" "0,1" group.long 0x200++0x3 line.long 0x00 "CSPFT1_TRACEIDR,CSPFT1 CoreSight Trace ID Register" hexmask.long.byte 0x00 0.--6. 1. " TID ,Trace ID" group.long 0xFA0++0x3 line.long 0x00 "CSPFT1_CLAIMSET,CSPFT1 Claim Tag Set Register" bitfld.long 0x00 0.--3. " TAGS ,Supported Tags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFA4++0x3 line.long 0x00 "CSPFT1_CLAIMCLR,CSPFT1 Claim Tag Clear Register" bitfld.long 0x00 0.--3. " TAGS ,Tags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFB0++0x3 line.long 0x00 "CSPFT1_LAR,CSPFT1 Lock Access Register" group.long 0xFB4++0x3 line.long 0x00 "CSPFT1_LSR,CSPFT1 Lock Status Register" bitfld.long 0x00 1. " LOCKED ,Lock Status" "0,1" bitfld.long 0x00 0. " LOCKEN ,Locking Supported" "0,1" group.long 0xFB8++0x3 line.long 0x00 "CSPFT1_AUTHSTATUS,CSPFT1 Authentication Status Register" bitfld.long 0x00 7. " ONE ,Always reads as one" "0,1" bitfld.long 0x00 6. " DBGEN ,Debug Enabled" "0,1" group.long 0xFCC++0x3 line.long 0x00 "CSPFT1_DEVTYPE,CSPFT1 Device Type Identifier Register" bitfld.long 0x00 4.--7. " STYPE ,Sub Type = DSP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TYPE ,Device Type = Trace Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFD0++0x3 line.long 0x00 "CSPFT1_PID4,CSPFT1 Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,Number of 4K Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " JEOP106CC ,JEOP106 continuation code (number of leading 0x7Fs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE0++0x3 line.long 0x00 "CSPFT1_PID0,CSPFT1 Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PARTNUM ,Part Number" group.long 0xFE4++0x3 line.long 0x00 "CSPFT1_PID1,CSPFT1 Peripheral ID1 Register" bitfld.long 0x00 4.--7. " JEP106 ,JEDEC JEP106 Manufacturer ID code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PARTNUM ,Part Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE8++0x3 line.long 0x00 "CSPFT1_PID2,CSPFT1 Peripheral ID2 Register" bitfld.long 0x00 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " JEDECASGN ,A JEDEC Assigned Value is Used" "0,1" bitfld.long 0x00 0.--2. " JEP106 ,JEDEC JEP106 Manufacturer ID code" "0,1,2,3,4,5,6,7" group.long 0xFEC++0x3 line.long 0x00 "CSPFT1_PID3,CSPFT1 Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Field to mark metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CUSTMOD ,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF0++0x3 line.long 0x00 "CSPFT1_CID0,CSPFT1 Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPID ,Component ID" group.long 0xFF4++0x3 line.long 0x00 "CSPFT1_CID1,CSPFT1 Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPID ,Component ID" group.long 0xFF8++0x3 line.long 0x00 "CSPFT1_CID2,CSPFT1 Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPID ,Component ID" group.long 0xFFC++0x3 line.long 0x00 "CSPFT1_CID3,CSPFT1 Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " COMPID ,Component ID" tree.end tree "CSTMC0" base ad:0x31109304 width 13. group.long 0x0++0x3 line.long 0x00 "CSTMC0_FFCR,CSTMC0 Formatter and Flush Control Register" bitfld.long 0x00 6. " FlushMan_R ,Manual Flush Completion Status" "0,1" tree.end tree "CSTMC1" base ad:0x3110A304 width 13. group.long 0x0++0x3 line.long 0x00 "CSTMC1_FFCR,CSTMC1 Formatter and Flush Control Register" bitfld.long 0x00 6. " FlushMan_R ,Manual Flush Completion Status" "0,1" tree.end tree "CTI (Capacitive Touch Interface)" tree "CTI0" base ad:0x31128000 width 23. group.long 0x0++0x3 line.long 0x00 "CTI0_CTICONTROL,CTI0 CTI Control Register" bitfld.long 0x00 0. " GLBEN ,Global CTI Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "CTI0_CTIINTACK,CTI0 CTI Interrupt Acknowledge Register" hexmask.long.byte 0x00 0.--7. 1. " INTACK ,Interrupt Acknowledge" group.long 0x14++0x3 line.long 0x00 "CTI0_CTIAPPSET,CTI0 CTI Application Trigger Set Register" bitfld.long 0x00 0.--3. " APPSET ,Set Channel Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "CTI0_CTIAPPCLEAR,CTI0 CTI Application Trigger Clear Register" bitfld.long 0x00 0.--3. " APPCLEAR ,Channel Clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "CTI0_CTIAPPPULSE,CTI0 CTI Application Pulse Register" bitfld.long 0x00 0.--3. " Bit_0APPULSE ,Channel Event Pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x00 "CTI0_CTIINEN0,CTI0 CTI Trigger 0 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "CTI0_CTIINEN1,CTI0 CTI Trigger 1 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x3 line.long 0x00 "CTI0_CTIINEN2,CTI0 CTI Trigger 2 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x3 line.long 0x00 "CTI0_CTIINEN3,CTI0 CTI Trigger 3 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x3 line.long 0x00 "CTI0_CTIINEN4,CTI0 CTI Trigger 4 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x3 line.long 0x00 "CTI0_CTIINEN5,CTI0 CTI Trigger 5 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "CTI0_CTIINEN6,CTI0 CTI Trigger 6 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "CTI0_CTIINEN7,CTI0 CTI Trigger 7 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "CTI0_CTIOUTEN0,CTI0 CTI Channel to Trigger 0 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA4++0x3 line.long 0x00 "CTI0_CTIOUTEN1,CTI0 CTI Channel to Trigger 1 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "CTI0_CTIOUTEN2,CTI0 CTI Channel to Trigger 2 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAC++0x3 line.long 0x00 "CTI0_CTIOUTEN3,CTI0 CTI Channel to Trigger 3 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x3 line.long 0x00 "CTI0_CTIOUTEN4,CTI0 CTI Channel to Trigger 4 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB4++0x3 line.long 0x00 "CTI0_CTIOUTEN5,CTI0 CTI Channel to Trigger 5 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x3 line.long 0x00 "CTI0_CTIOUTEN6,CTI0 CTI Channel to Trigger 6 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xBC++0x3 line.long 0x00 "CTI0_CTIOUTEN7,CTI0 CTI Channel to Trigger 7 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x3 line.long 0x00 "CTI0_CTITRIGINSTATUS,CTI0 CTI Trigger In Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGINSTATUS ,Trigger In Status" group.long 0x134++0x3 line.long 0x00 "CTI0_CTITRIGOUTSTATUS,CTI0 CTI Trigger Out Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGOUTSTATUS ,Trigger Output Status" group.long 0x138++0x3 line.long 0x00 "CTI0_CTICHINSTATUS,CTI0 CTI Channel In Status Register" bitfld.long 0x00 0.--3. " CTCHINSTATUS ,Channel Input Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x13C++0x3 line.long 0x00 "CTI0_CTICHOUTSTATUS,CTI0 CTI Channel Out Status Register" bitfld.long 0x00 0.--3. " CTCHOUTSTATUS ,Channel Out Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x140++0x3 line.long 0x00 "CTI0_CTIGATE,CTI0 Enable CTI Channel Gate Register" bitfld.long 0x00 3. " CTIGATEEN3 ,Enable CTICHOUT3" "0,1" bitfld.long 0x00 2. " CTIGATEEN2 ,Enable CTICHOUT2" "0,1" bitfld.long 0x00 1. " CTIGATEEN1 ,Enable CTICHOUT1" "0,1" newline bitfld.long 0x00 0. " CTIGATEEN0 ,Enable CTICHOUT0" "0,1" group.long 0x144++0x3 line.long 0x00 "CTI0_ASICCTL,CTI0 External Multiplexor Control Register" hexmask.long.byte 0x00 0.--7. 1. " ASICCTL ,ASIC Control" group.long 0xEDC++0x3 line.long 0x00 "CTI0_ITCHINACK,CTI0 ITCHINACK" bitfld.long 0x00 0.--3. " CTCHINACK ,Set the value of the CTCHINACK outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE0++0x3 line.long 0x00 "CTI0_ITTRIGINACK,CTI0 ITTRIGINACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGINACK ,Set the value of the CTTRIGINACK outputs" group.long 0xEE4++0x3 line.long 0x00 "CTI0_ITCHOUT,CTI0 ITCHOUT" bitfld.long 0x00 0.--3. " CTCHOUT ,Set the value of the CTCHOUT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE8++0x3 line.long 0x00 "CTI0_ITTRIGOUT,CTI0 ITTRIGOUT" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUT ,Set the value of the CTTRIGOUT outputs" group.long 0xEEC++0x3 line.long 0x00 "CTI0_ITCHOUTACK,CTI0 ITCHOUTACK" bitfld.long 0x00 0.--3. " CTCHOUTACK ,Read the values of the CTCHOUTACK inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF0++0x3 line.long 0x00 "CTI0_ITTRIGOUTACK,CTI0 ITTRIGOUTACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUTACK ,Read the values of the CTTRIGOUTACK inputs" group.long 0xEF4++0x3 line.long 0x00 "CTI0_ITCHIN,CTI0 ITCHIN" bitfld.long 0x00 0.--3. " CTCHIN ,Read the values of the CTCHIN inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF8++0x3 line.long 0x00 "CTI0_ITTRIGIN,CTI0 ITTRIGIN" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGIN ,Read the values of the CTTRIGIN inputs" group.long 0xF00++0x3 line.long 0x00 "CTI0_ITCTRL,CTI0 Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "0,1" group.long 0xFA0++0x3 line.long 0x00 "CTI0_CLAIMSET,CTI0 Claim Tag Set Register" bitfld.long 0x00 0.--3. " CLAIMSET ,Claim Tag Set Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFA4++0x3 line.long 0x00 "CTI0_CLAIMCLR,CTI0 Claim Tag Clear Register" bitfld.long 0x00 0.--3. " CLAIMCLR ,Claim Tag Clear Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFB0++0x3 line.long 0x00 "CTI0_LAR,CTI0 Lock Access Register" group.long 0xFB4++0x3 line.long 0x00 "CTI0_LSR,CTI0 Lock Status Register" bitfld.long 0x00 1. " ACCESS ,Access Blocked to Device" "0,1" bitfld.long 0x00 0. " LOCK ,Lock Exists for Device" "0,1" group.long 0xFB8++0x3 line.long 0x00 "CTI0_AUTHSTATUS,CTI0 Authentication Status" bitfld.long 0x00 3. " NDBG_EN ,Non-invasive Debug Enabled Status" "0,1" bitfld.long 0x00 2. " NDBG_CTL ,Non-invasive Debug Controlled" "0,1" bitfld.long 0x00 1. " IDBG_EN ,Invasive Debug Enable Status" "0,1" newline bitfld.long 0x00 0. " IDBG_CTL ,Invasive Debug Controlled" "0,1" group.long 0xFC8++0x3 line.long 0x00 "CTI0_DEVID,CTI0 Device ID" hexmask.long.tbyte 0x00 0.--19. 1. " DEVID ,Device ID Field" group.long 0xFCC++0x3 line.long 0x00 "CTI0_DEVTYPE,CTI0 Device Type" hexmask.long.byte 0x00 0.--7. 1. " DEVTYPE ,Device Type Field" group.long 0xFD0++0x3 line.long 0x00 "CTI0_PERIPHID4,CTI0 Peripheral ID4" hexmask.long.byte 0x00 0.--7. 1. " PID4 ,Peripheral ID4 Field" group.long 0xFD4++0x3 line.long 0x00 "CTI0_PERIPHID5,CTI0 Peripheral ID5" hexmask.long.byte 0x00 0.--7. 1. " PID5 ,Peripheral ID5 Field" group.long 0xFD8++0x3 line.long 0x00 "CTI0_PERIPHID6,CTI0 Peripheral ID6" hexmask.long.byte 0x00 0.--7. 1. " PID6 ,Peripheral ID6 Field" group.long 0xFDC++0x3 line.long 0x00 "CTI0_PERIPHID7,CTI0 Peripheral ID7" hexmask.long.byte 0x00 0.--7. 1. " PID7 ,Peripheral ID7 Field" group.long 0xFE0++0x3 line.long 0x00 "CTI0_PERIPHID0,CTI0 Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PID0 ,Peripheral ID0 Field" group.long 0xFE4++0x3 line.long 0x00 "CTI0_PERIPHID1,CTI0 Peripheral ID1" hexmask.long.byte 0x00 0.--7. 1. " PID1 ,Peripheral ID1 Field" group.long 0xFE8++0x3 line.long 0x00 "CTI0_PERIPHID2,CTI0 Peripheral ID2" hexmask.long.byte 0x00 0.--7. 1. " PID2 ,Peripheral ID2 Field" group.long 0xFEC++0x3 line.long 0x00 "CTI0_PERIPHID3,CTI0 Peripheral ID3" hexmask.long.byte 0x00 0.--7. 1. " PID3 ,Peripheral ID3 Field" group.long 0xFF0++0x3 line.long 0x00 "CTI0_COMPID0,CTI0 Component ID0" hexmask.long.byte 0x00 0.--7. 1. " ID0 ,Component ID0 Field" group.long 0xFF4++0x3 line.long 0x00 "CTI0_COMPID1,CTI0 Component ID1" hexmask.long.byte 0x00 0.--7. 1. " ID1 ,Component ID1 Field" group.long 0xFF8++0x3 line.long 0x00 "CTI0_COMPID2,CTI0 Component ID2" hexmask.long.byte 0x00 0.--7. 1. " ID2 ,Component ID2 Field" group.long 0xFFC++0x3 line.long 0x00 "CTI0_COMPID3,CTI0 Component ID3" hexmask.long.byte 0x00 0.--7. 1. " ID3 ,Component ID3 Field" tree.end tree "CTI1" base ad:0x31102000 width 23. group.long 0x0++0x3 line.long 0x00 "CTI1_CTICONTROL,CTI1 CTI Control Register" bitfld.long 0x00 0. " GLBEN ,Global CTI Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "CTI1_CTIINTACK,CTI1 CTI Interrupt Acknowledge Register" hexmask.long.byte 0x00 0.--7. 1. " INTACK ,Interrupt Acknowledge" group.long 0x14++0x3 line.long 0x00 "CTI1_CTIAPPSET,CTI1 CTI Application Trigger Set Register" bitfld.long 0x00 0.--3. " APPSET ,Set Channel Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "CTI1_CTIAPPCLEAR,CTI1 CTI Application Trigger Clear Register" bitfld.long 0x00 0.--3. " APPCLEAR ,Channel Clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "CTI1_CTIAPPPULSE,CTI1 CTI Application Pulse Register" bitfld.long 0x00 0.--3. " Bit_0APPULSE ,Channel Event Pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x00 "CTI1_CTIINEN0,CTI1 CTI Trigger 0 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "CTI1_CTIINEN1,CTI1 CTI Trigger 1 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x3 line.long 0x00 "CTI1_CTIINEN2,CTI1 CTI Trigger 2 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x3 line.long 0x00 "CTI1_CTIINEN3,CTI1 CTI Trigger 3 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x3 line.long 0x00 "CTI1_CTIINEN4,CTI1 CTI Trigger 4 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x3 line.long 0x00 "CTI1_CTIINEN5,CTI1 CTI Trigger 5 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "CTI1_CTIINEN6,CTI1 CTI Trigger 6 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "CTI1_CTIINEN7,CTI1 CTI Trigger 7 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "CTI1_CTIOUTEN0,CTI1 CTI Channel to Trigger 0 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA4++0x3 line.long 0x00 "CTI1_CTIOUTEN1,CTI1 CTI Channel to Trigger 1 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "CTI1_CTIOUTEN2,CTI1 CTI Channel to Trigger 2 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAC++0x3 line.long 0x00 "CTI1_CTIOUTEN3,CTI1 CTI Channel to Trigger 3 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x3 line.long 0x00 "CTI1_CTIOUTEN4,CTI1 CTI Channel to Trigger 4 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB4++0x3 line.long 0x00 "CTI1_CTIOUTEN5,CTI1 CTI Channel to Trigger 5 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x3 line.long 0x00 "CTI1_CTIOUTEN6,CTI1 CTI Channel to Trigger 6 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xBC++0x3 line.long 0x00 "CTI1_CTIOUTEN7,CTI1 CTI Channel to Trigger 7 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x3 line.long 0x00 "CTI1_CTITRIGINSTATUS,CTI1 CTI Trigger In Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGINSTATUS ,Trigger In Status" group.long 0x134++0x3 line.long 0x00 "CTI1_CTITRIGOUTSTATUS,CTI1 CTI Trigger Out Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGOUTSTATUS ,Trigger Output Status" group.long 0x138++0x3 line.long 0x00 "CTI1_CTICHINSTATUS,CTI1 CTI Channel In Status Register" bitfld.long 0x00 0.--3. " CTCHINSTATUS ,Channel Input Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x13C++0x3 line.long 0x00 "CTI1_CTICHOUTSTATUS,CTI1 CTI Channel Out Status Register" bitfld.long 0x00 0.--3. " CTCHOUTSTATUS ,Channel Out Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x140++0x3 line.long 0x00 "CTI1_CTIGATE,CTI1 Enable CTI Channel Gate Register" bitfld.long 0x00 3. " CTIGATEEN3 ,Enable CTICHOUT3" "0,1" bitfld.long 0x00 2. " CTIGATEEN2 ,Enable CTICHOUT2" "0,1" bitfld.long 0x00 1. " CTIGATEEN1 ,Enable CTICHOUT1" "0,1" newline bitfld.long 0x00 0. " CTIGATEEN0 ,Enable CTICHOUT0" "0,1" group.long 0x144++0x3 line.long 0x00 "CTI1_ASICCTL,CTI1 External Multiplexor Control Register" hexmask.long.byte 0x00 0.--7. 1. " ASICCTL ,ASIC Control" group.long 0xEDC++0x3 line.long 0x00 "CTI1_ITCHINACK,CTI1 ITCHINACK" bitfld.long 0x00 0.--3. " CTCHINACK ,Set the value of the CTCHINACK outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE0++0x3 line.long 0x00 "CTI1_ITTRIGINACK,CTI1 ITTRIGINACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGINACK ,Set the value of the CTTRIGINACK outputs" group.long 0xEE4++0x3 line.long 0x00 "CTI1_ITCHOUT,CTI1 ITCHOUT" bitfld.long 0x00 0.--3. " CTCHOUT ,Set the value of the CTCHOUT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE8++0x3 line.long 0x00 "CTI1_ITTRIGOUT,CTI1 ITTRIGOUT" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUT ,Set the value of the CTTRIGOUT outputs" group.long 0xEEC++0x3 line.long 0x00 "CTI1_ITCHOUTACK,CTI1 ITCHOUTACK" bitfld.long 0x00 0.--3. " CTCHOUTACK ,Read the values of the CTCHOUTACK inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF0++0x3 line.long 0x00 "CTI1_ITTRIGOUTACK,CTI1 ITTRIGOUTACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUTACK ,Read the values of the CTTRIGOUTACK inputs" group.long 0xEF4++0x3 line.long 0x00 "CTI1_ITCHIN,CTI1 ITCHIN" bitfld.long 0x00 0.--3. " CTCHIN ,Read the values of the CTCHIN inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF8++0x3 line.long 0x00 "CTI1_ITTRIGIN,CTI1 ITTRIGIN" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGIN ,Read the values of the CTTRIGIN inputs" group.long 0xF00++0x3 line.long 0x00 "CTI1_ITCTRL,CTI1 Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "0,1" group.long 0xFA0++0x3 line.long 0x00 "CTI1_CLAIMSET,CTI1 Claim Tag Set Register" bitfld.long 0x00 0.--3. " CLAIMSET ,Claim Tag Set Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFA4++0x3 line.long 0x00 "CTI1_CLAIMCLR,CTI1 Claim Tag Clear Register" bitfld.long 0x00 0.--3. " CLAIMCLR ,Claim Tag Clear Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFB0++0x3 line.long 0x00 "CTI1_LAR,CTI1 Lock Access Register" group.long 0xFB4++0x3 line.long 0x00 "CTI1_LSR,CTI1 Lock Status Register" bitfld.long 0x00 1. " ACCESS ,Access Blocked to Device" "0,1" bitfld.long 0x00 0. " LOCK ,Lock Exists for Device" "0,1" group.long 0xFB8++0x3 line.long 0x00 "CTI1_AUTHSTATUS,CTI1 Authentication Status" bitfld.long 0x00 3. " NDBG_EN ,Non-invasive Debug Enabled Status" "0,1" bitfld.long 0x00 2. " NDBG_CTL ,Non-invasive Debug Controlled" "0,1" bitfld.long 0x00 1. " IDBG_EN ,Invasive Debug Enable Status" "0,1" newline bitfld.long 0x00 0. " IDBG_CTL ,Invasive Debug Controlled" "0,1" group.long 0xFC8++0x3 line.long 0x00 "CTI1_DEVID,CTI1 Device ID" hexmask.long.tbyte 0x00 0.--19. 1. " DEVID ,Device ID Field" group.long 0xFCC++0x3 line.long 0x00 "CTI1_DEVTYPE,CTI1 Device Type" hexmask.long.byte 0x00 0.--7. 1. " DEVTYPE ,Device Type Field" group.long 0xFD0++0x3 line.long 0x00 "CTI1_PERIPHID4,CTI1 Peripheral ID4" hexmask.long.byte 0x00 0.--7. 1. " PID4 ,Peripheral ID4 Field" group.long 0xFD4++0x3 line.long 0x00 "CTI1_PERIPHID5,CTI1 Peripheral ID5" hexmask.long.byte 0x00 0.--7. 1. " PID5 ,Peripheral ID5 Field" group.long 0xFD8++0x3 line.long 0x00 "CTI1_PERIPHID6,CTI1 Peripheral ID6" hexmask.long.byte 0x00 0.--7. 1. " PID6 ,Peripheral ID6 Field" group.long 0xFDC++0x3 line.long 0x00 "CTI1_PERIPHID7,CTI1 Peripheral ID7" hexmask.long.byte 0x00 0.--7. 1. " PID7 ,Peripheral ID7 Field" group.long 0xFE0++0x3 line.long 0x00 "CTI1_PERIPHID0,CTI1 Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PID0 ,Peripheral ID0 Field" group.long 0xFE4++0x3 line.long 0x00 "CTI1_PERIPHID1,CTI1 Peripheral ID1" hexmask.long.byte 0x00 0.--7. 1. " PID1 ,Peripheral ID1 Field" group.long 0xFE8++0x3 line.long 0x00 "CTI1_PERIPHID2,CTI1 Peripheral ID2" hexmask.long.byte 0x00 0.--7. 1. " PID2 ,Peripheral ID2 Field" group.long 0xFEC++0x3 line.long 0x00 "CTI1_PERIPHID3,CTI1 Peripheral ID3" hexmask.long.byte 0x00 0.--7. 1. " PID3 ,Peripheral ID3 Field" group.long 0xFF0++0x3 line.long 0x00 "CTI1_COMPID0,CTI1 Component ID0" hexmask.long.byte 0x00 0.--7. 1. " ID0 ,Component ID0 Field" group.long 0xFF4++0x3 line.long 0x00 "CTI1_COMPID1,CTI1 Component ID1" hexmask.long.byte 0x00 0.--7. 1. " ID1 ,Component ID1 Field" group.long 0xFF8++0x3 line.long 0x00 "CTI1_COMPID2,CTI1 Component ID2" hexmask.long.byte 0x00 0.--7. 1. " ID2 ,Component ID2 Field" group.long 0xFFC++0x3 line.long 0x00 "CTI1_COMPID3,CTI1 Component ID3" hexmask.long.byte 0x00 0.--7. 1. " ID3 ,Component ID3 Field" tree.end tree "CTI2" base ad:0x31106000 width 23. group.long 0x0++0x3 line.long 0x00 "CTI2_CTICONTROL,CTI2 CTI Control Register" bitfld.long 0x00 0. " GLBEN ,Global CTI Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "CTI2_CTIINTACK,CTI2 CTI Interrupt Acknowledge Register" hexmask.long.byte 0x00 0.--7. 1. " INTACK ,Interrupt Acknowledge" group.long 0x14++0x3 line.long 0x00 "CTI2_CTIAPPSET,CTI2 CTI Application Trigger Set Register" bitfld.long 0x00 0.--3. " APPSET ,Set Channel Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "CTI2_CTIAPPCLEAR,CTI2 CTI Application Trigger Clear Register" bitfld.long 0x00 0.--3. " APPCLEAR ,Channel Clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "CTI2_CTIAPPPULSE,CTI2 CTI Application Pulse Register" bitfld.long 0x00 0.--3. " Bit_0APPULSE ,Channel Event Pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x00 "CTI2_CTIINEN0,CTI2 CTI Trigger 0 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "CTI2_CTIINEN1,CTI2 CTI Trigger 1 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x3 line.long 0x00 "CTI2_CTIINEN2,CTI2 CTI Trigger 2 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x3 line.long 0x00 "CTI2_CTIINEN3,CTI2 CTI Trigger 3 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x3 line.long 0x00 "CTI2_CTIINEN4,CTI2 CTI Trigger 4 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x3 line.long 0x00 "CTI2_CTIINEN5,CTI2 CTI Trigger 5 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "CTI2_CTIINEN6,CTI2 CTI Trigger 6 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "CTI2_CTIINEN7,CTI2 CTI Trigger 7 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "CTI2_CTIOUTEN0,CTI2 CTI Channel to Trigger 0 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA4++0x3 line.long 0x00 "CTI2_CTIOUTEN1,CTI2 CTI Channel to Trigger 1 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "CTI2_CTIOUTEN2,CTI2 CTI Channel to Trigger 2 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAC++0x3 line.long 0x00 "CTI2_CTIOUTEN3,CTI2 CTI Channel to Trigger 3 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x3 line.long 0x00 "CTI2_CTIOUTEN4,CTI2 CTI Channel to Trigger 4 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB4++0x3 line.long 0x00 "CTI2_CTIOUTEN5,CTI2 CTI Channel to Trigger 5 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x3 line.long 0x00 "CTI2_CTIOUTEN6,CTI2 CTI Channel to Trigger 6 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xBC++0x3 line.long 0x00 "CTI2_CTIOUTEN7,CTI2 CTI Channel to Trigger 7 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x3 line.long 0x00 "CTI2_CTITRIGINSTATUS,CTI2 CTI Trigger In Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGINSTATUS ,Trigger In Status" group.long 0x134++0x3 line.long 0x00 "CTI2_CTITRIGOUTSTATUS,CTI2 CTI Trigger Out Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGOUTSTATUS ,Trigger Output Status" group.long 0x138++0x3 line.long 0x00 "CTI2_CTICHINSTATUS,CTI2 CTI Channel In Status Register" bitfld.long 0x00 0.--3. " CTCHINSTATUS ,Channel Input Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x13C++0x3 line.long 0x00 "CTI2_CTICHOUTSTATUS,CTI2 CTI Channel Out Status Register" bitfld.long 0x00 0.--3. " CTCHOUTSTATUS ,Channel Out Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x140++0x3 line.long 0x00 "CTI2_CTIGATE,CTI2 Enable CTI Channel Gate Register" bitfld.long 0x00 3. " CTIGATEEN3 ,Enable CTICHOUT3" "0,1" bitfld.long 0x00 2. " CTIGATEEN2 ,Enable CTICHOUT2" "0,1" bitfld.long 0x00 1. " CTIGATEEN1 ,Enable CTICHOUT1" "0,1" newline bitfld.long 0x00 0. " CTIGATEEN0 ,Enable CTICHOUT0" "0,1" group.long 0x144++0x3 line.long 0x00 "CTI2_ASICCTL,CTI2 External Multiplexor Control Register" hexmask.long.byte 0x00 0.--7. 1. " ASICCTL ,ASIC Control" group.long 0xEDC++0x3 line.long 0x00 "CTI2_ITCHINACK,CTI2 ITCHINACK" bitfld.long 0x00 0.--3. " CTCHINACK ,Set the value of the CTCHINACK outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE0++0x3 line.long 0x00 "CTI2_ITTRIGINACK,CTI2 ITTRIGINACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGINACK ,Set the value of the CTTRIGINACK outputs" group.long 0xEE4++0x3 line.long 0x00 "CTI2_ITCHOUT,CTI2 ITCHOUT" bitfld.long 0x00 0.--3. " CTCHOUT ,Set the value of the CTCHOUT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE8++0x3 line.long 0x00 "CTI2_ITTRIGOUT,CTI2 ITTRIGOUT" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUT ,Set the value of the CTTRIGOUT outputs" group.long 0xEEC++0x3 line.long 0x00 "CTI2_ITCHOUTACK,CTI2 ITCHOUTACK" bitfld.long 0x00 0.--3. " CTCHOUTACK ,Read the values of the CTCHOUTACK inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF0++0x3 line.long 0x00 "CTI2_ITTRIGOUTACK,CTI2 ITTRIGOUTACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUTACK ,Read the values of the CTTRIGOUTACK inputs" group.long 0xEF4++0x3 line.long 0x00 "CTI2_ITCHIN,CTI2 ITCHIN" bitfld.long 0x00 0.--3. " CTCHIN ,Read the values of the CTCHIN inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF8++0x3 line.long 0x00 "CTI2_ITTRIGIN,CTI2 ITTRIGIN" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGIN ,Read the values of the CTTRIGIN inputs" group.long 0xF00++0x3 line.long 0x00 "CTI2_ITCTRL,CTI2 Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "0,1" group.long 0xFA0++0x3 line.long 0x00 "CTI2_CLAIMSET,CTI2 Claim Tag Set Register" bitfld.long 0x00 0.--3. " CLAIMSET ,Claim Tag Set Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFA4++0x3 line.long 0x00 "CTI2_CLAIMCLR,CTI2 Claim Tag Clear Register" bitfld.long 0x00 0.--3. " CLAIMCLR ,Claim Tag Clear Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFB0++0x3 line.long 0x00 "CTI2_LAR,CTI2 Lock Access Register" group.long 0xFB4++0x3 line.long 0x00 "CTI2_LSR,CTI2 Lock Status Register" bitfld.long 0x00 1. " ACCESS ,Access Blocked to Device" "0,1" bitfld.long 0x00 0. " LOCK ,Lock Exists for Device" "0,1" group.long 0xFB8++0x3 line.long 0x00 "CTI2_AUTHSTATUS,CTI2 Authentication Status" bitfld.long 0x00 3. " NDBG_EN ,Non-invasive Debug Enabled Status" "0,1" bitfld.long 0x00 2. " NDBG_CTL ,Non-invasive Debug Controlled" "0,1" bitfld.long 0x00 1. " IDBG_EN ,Invasive Debug Enable Status" "0,1" newline bitfld.long 0x00 0. " IDBG_CTL ,Invasive Debug Controlled" "0,1" group.long 0xFC8++0x3 line.long 0x00 "CTI2_DEVID,CTI2 Device ID" hexmask.long.tbyte 0x00 0.--19. 1. " DEVID ,Device ID Field" group.long 0xFCC++0x3 line.long 0x00 "CTI2_DEVTYPE,CTI2 Device Type" hexmask.long.byte 0x00 0.--7. 1. " DEVTYPE ,Device Type Field" group.long 0xFD0++0x3 line.long 0x00 "CTI2_PERIPHID4,CTI2 Peripheral ID4" hexmask.long.byte 0x00 0.--7. 1. " PID4 ,Peripheral ID4 Field" group.long 0xFD4++0x3 line.long 0x00 "CTI2_PERIPHID5,CTI2 Peripheral ID5" hexmask.long.byte 0x00 0.--7. 1. " PID5 ,Peripheral ID5 Field" group.long 0xFD8++0x3 line.long 0x00 "CTI2_PERIPHID6,CTI2 Peripheral ID6" hexmask.long.byte 0x00 0.--7. 1. " PID6 ,Peripheral ID6 Field" group.long 0xFDC++0x3 line.long 0x00 "CTI2_PERIPHID7,CTI2 Peripheral ID7" hexmask.long.byte 0x00 0.--7. 1. " PID7 ,Peripheral ID7 Field" group.long 0xFE0++0x3 line.long 0x00 "CTI2_PERIPHID0,CTI2 Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PID0 ,Peripheral ID0 Field" group.long 0xFE4++0x3 line.long 0x00 "CTI2_PERIPHID1,CTI2 Peripheral ID1" hexmask.long.byte 0x00 0.--7. 1. " PID1 ,Peripheral ID1 Field" group.long 0xFE8++0x3 line.long 0x00 "CTI2_PERIPHID2,CTI2 Peripheral ID2" hexmask.long.byte 0x00 0.--7. 1. " PID2 ,Peripheral ID2 Field" group.long 0xFEC++0x3 line.long 0x00 "CTI2_PERIPHID3,CTI2 Peripheral ID3" hexmask.long.byte 0x00 0.--7. 1. " PID3 ,Peripheral ID3 Field" group.long 0xFF0++0x3 line.long 0x00 "CTI2_COMPID0,CTI2 Component ID0" hexmask.long.byte 0x00 0.--7. 1. " ID0 ,Component ID0 Field" group.long 0xFF4++0x3 line.long 0x00 "CTI2_COMPID1,CTI2 Component ID1" hexmask.long.byte 0x00 0.--7. 1. " ID1 ,Component ID1 Field" group.long 0xFF8++0x3 line.long 0x00 "CTI2_COMPID2,CTI2 Component ID2" hexmask.long.byte 0x00 0.--7. 1. " ID2 ,Component ID2 Field" group.long 0xFFC++0x3 line.long 0x00 "CTI2_COMPID3,CTI2 Component ID3" hexmask.long.byte 0x00 0.--7. 1. " ID3 ,Component ID3 Field" tree.end tree "CTI3" base ad:0x3110D000 width 23. group.long 0x0++0x3 line.long 0x00 "CTI3_CTICONTROL,CTI3 CTI Control Register" bitfld.long 0x00 0. " GLBEN ,Global CTI Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "CTI3_CTIINTACK,CTI3 CTI Interrupt Acknowledge Register" hexmask.long.byte 0x00 0.--7. 1. " INTACK ,Interrupt Acknowledge" group.long 0x14++0x3 line.long 0x00 "CTI3_CTIAPPSET,CTI3 CTI Application Trigger Set Register" bitfld.long 0x00 0.--3. " APPSET ,Set Channel Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "CTI3_CTIAPPCLEAR,CTI3 CTI Application Trigger Clear Register" bitfld.long 0x00 0.--3. " APPCLEAR ,Channel Clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "CTI3_CTIAPPPULSE,CTI3 CTI Application Pulse Register" bitfld.long 0x00 0.--3. " Bit_0APPULSE ,Channel Event Pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x00 "CTI3_CTIINEN0,CTI3 CTI Trigger 0 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "CTI3_CTIINEN1,CTI3 CTI Trigger 1 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x3 line.long 0x00 "CTI3_CTIINEN2,CTI3 CTI Trigger 2 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x3 line.long 0x00 "CTI3_CTIINEN3,CTI3 CTI Trigger 3 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x3 line.long 0x00 "CTI3_CTIINEN4,CTI3 CTI Trigger 4 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x3 line.long 0x00 "CTI3_CTIINEN5,CTI3 CTI Trigger 5 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "CTI3_CTIINEN6,CTI3 CTI Trigger 6 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "CTI3_CTIINEN7,CTI3 CTI Trigger 7 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "CTI3_CTIOUTEN0,CTI3 CTI Channel to Trigger 0 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA4++0x3 line.long 0x00 "CTI3_CTIOUTEN1,CTI3 CTI Channel to Trigger 1 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "CTI3_CTIOUTEN2,CTI3 CTI Channel to Trigger 2 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAC++0x3 line.long 0x00 "CTI3_CTIOUTEN3,CTI3 CTI Channel to Trigger 3 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x3 line.long 0x00 "CTI3_CTIOUTEN4,CTI3 CTI Channel to Trigger 4 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB4++0x3 line.long 0x00 "CTI3_CTIOUTEN5,CTI3 CTI Channel to Trigger 5 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x3 line.long 0x00 "CTI3_CTIOUTEN6,CTI3 CTI Channel to Trigger 6 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xBC++0x3 line.long 0x00 "CTI3_CTIOUTEN7,CTI3 CTI Channel to Trigger 7 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x3 line.long 0x00 "CTI3_CTITRIGINSTATUS,CTI3 CTI Trigger In Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGINSTATUS ,Trigger In Status" group.long 0x134++0x3 line.long 0x00 "CTI3_CTITRIGOUTSTATUS,CTI3 CTI Trigger Out Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGOUTSTATUS ,Trigger Output Status" group.long 0x138++0x3 line.long 0x00 "CTI3_CTICHINSTATUS,CTI3 CTI Channel In Status Register" bitfld.long 0x00 0.--3. " CTCHINSTATUS ,Channel Input Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x13C++0x3 line.long 0x00 "CTI3_CTICHOUTSTATUS,CTI3 CTI Channel Out Status Register" bitfld.long 0x00 0.--3. " CTCHOUTSTATUS ,Channel Out Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x140++0x3 line.long 0x00 "CTI3_CTIGATE,CTI3 Enable CTI Channel Gate Register" bitfld.long 0x00 3. " CTIGATEEN3 ,Enable CTICHOUT3" "0,1" bitfld.long 0x00 2. " CTIGATEEN2 ,Enable CTICHOUT2" "0,1" bitfld.long 0x00 1. " CTIGATEEN1 ,Enable CTICHOUT1" "0,1" newline bitfld.long 0x00 0. " CTIGATEEN0 ,Enable CTICHOUT0" "0,1" group.long 0x144++0x3 line.long 0x00 "CTI3_ASICCTL,CTI3 External Multiplexor Control Register" hexmask.long.byte 0x00 0.--7. 1. " ASICCTL ,ASIC Control" group.long 0xEDC++0x3 line.long 0x00 "CTI3_ITCHINACK,CTI3 ITCHINACK" bitfld.long 0x00 0.--3. " CTCHINACK ,Set the value of the CTCHINACK outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE0++0x3 line.long 0x00 "CTI3_ITTRIGINACK,CTI3 ITTRIGINACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGINACK ,Set the value of the CTTRIGINACK outputs" group.long 0xEE4++0x3 line.long 0x00 "CTI3_ITCHOUT,CTI3 ITCHOUT" bitfld.long 0x00 0.--3. " CTCHOUT ,Set the value of the CTCHOUT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE8++0x3 line.long 0x00 "CTI3_ITTRIGOUT,CTI3 ITTRIGOUT" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUT ,Set the value of the CTTRIGOUT outputs" group.long 0xEEC++0x3 line.long 0x00 "CTI3_ITCHOUTACK,CTI3 ITCHOUTACK" bitfld.long 0x00 0.--3. " CTCHOUTACK ,Read the values of the CTCHOUTACK inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF0++0x3 line.long 0x00 "CTI3_ITTRIGOUTACK,CTI3 ITTRIGOUTACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUTACK ,Read the values of the CTTRIGOUTACK inputs" group.long 0xEF4++0x3 line.long 0x00 "CTI3_ITCHIN,CTI3 ITCHIN" bitfld.long 0x00 0.--3. " CTCHIN ,Read the values of the CTCHIN inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF8++0x3 line.long 0x00 "CTI3_ITTRIGIN,CTI3 ITTRIGIN" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGIN ,Read the values of the CTTRIGIN inputs" group.long 0xF00++0x3 line.long 0x00 "CTI3_ITCTRL,CTI3 Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "0,1" group.long 0xFA0++0x3 line.long 0x00 "CTI3_CLAIMSET,CTI3 Claim Tag Set Register" bitfld.long 0x00 0.--3. " CLAIMSET ,Claim Tag Set Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFA4++0x3 line.long 0x00 "CTI3_CLAIMCLR,CTI3 Claim Tag Clear Register" bitfld.long 0x00 0.--3. " CLAIMCLR ,Claim Tag Clear Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFB0++0x3 line.long 0x00 "CTI3_LAR,CTI3 Lock Access Register" group.long 0xFB4++0x3 line.long 0x00 "CTI3_LSR,CTI3 Lock Status Register" bitfld.long 0x00 1. " ACCESS ,Access Blocked to Device" "0,1" bitfld.long 0x00 0. " LOCK ,Lock Exists for Device" "0,1" group.long 0xFB8++0x3 line.long 0x00 "CTI3_AUTHSTATUS,CTI3 Authentication Status" bitfld.long 0x00 3. " NDBG_EN ,Non-invasive Debug Enabled Status" "0,1" bitfld.long 0x00 2. " NDBG_CTL ,Non-invasive Debug Controlled" "0,1" bitfld.long 0x00 1. " IDBG_EN ,Invasive Debug Enable Status" "0,1" newline bitfld.long 0x00 0. " IDBG_CTL ,Invasive Debug Controlled" "0,1" group.long 0xFC8++0x3 line.long 0x00 "CTI3_DEVID,CTI3 Device ID" hexmask.long.tbyte 0x00 0.--19. 1. " DEVID ,Device ID Field" group.long 0xFCC++0x3 line.long 0x00 "CTI3_DEVTYPE,CTI3 Device Type" hexmask.long.byte 0x00 0.--7. 1. " DEVTYPE ,Device Type Field" group.long 0xFD0++0x3 line.long 0x00 "CTI3_PERIPHID4,CTI3 Peripheral ID4" hexmask.long.byte 0x00 0.--7. 1. " PID4 ,Peripheral ID4 Field" group.long 0xFD4++0x3 line.long 0x00 "CTI3_PERIPHID5,CTI3 Peripheral ID5" hexmask.long.byte 0x00 0.--7. 1. " PID5 ,Peripheral ID5 Field" group.long 0xFD8++0x3 line.long 0x00 "CTI3_PERIPHID6,CTI3 Peripheral ID6" hexmask.long.byte 0x00 0.--7. 1. " PID6 ,Peripheral ID6 Field" group.long 0xFDC++0x3 line.long 0x00 "CTI3_PERIPHID7,CTI3 Peripheral ID7" hexmask.long.byte 0x00 0.--7. 1. " PID7 ,Peripheral ID7 Field" group.long 0xFE0++0x3 line.long 0x00 "CTI3_PERIPHID0,CTI3 Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PID0 ,Peripheral ID0 Field" group.long 0xFE4++0x3 line.long 0x00 "CTI3_PERIPHID1,CTI3 Peripheral ID1" hexmask.long.byte 0x00 0.--7. 1. " PID1 ,Peripheral ID1 Field" group.long 0xFE8++0x3 line.long 0x00 "CTI3_PERIPHID2,CTI3 Peripheral ID2" hexmask.long.byte 0x00 0.--7. 1. " PID2 ,Peripheral ID2 Field" group.long 0xFEC++0x3 line.long 0x00 "CTI3_PERIPHID3,CTI3 Peripheral ID3" hexmask.long.byte 0x00 0.--7. 1. " PID3 ,Peripheral ID3 Field" group.long 0xFF0++0x3 line.long 0x00 "CTI3_COMPID0,CTI3 Component ID0" hexmask.long.byte 0x00 0.--7. 1. " ID0 ,Component ID0 Field" group.long 0xFF4++0x3 line.long 0x00 "CTI3_COMPID1,CTI3 Component ID1" hexmask.long.byte 0x00 0.--7. 1. " ID1 ,Component ID1 Field" group.long 0xFF8++0x3 line.long 0x00 "CTI3_COMPID2,CTI3 Component ID2" hexmask.long.byte 0x00 0.--7. 1. " ID2 ,Component ID2 Field" group.long 0xFFC++0x3 line.long 0x00 "CTI3_COMPID3,CTI3 Component ID3" hexmask.long.byte 0x00 0.--7. 1. " ID3 ,Component ID3 Field" tree.end tree "CTI4" base ad:0x3110C000 width 23. group.long 0x0++0x3 line.long 0x00 "CTI4_CTICONTROL,CTI4 CTI Control Register" bitfld.long 0x00 0. " GLBEN ,Global CTI Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "CTI4_CTIINTACK,CTI4 CTI Interrupt Acknowledge Register" hexmask.long.byte 0x00 0.--7. 1. " INTACK ,Interrupt Acknowledge" group.long 0x14++0x3 line.long 0x00 "CTI4_CTIAPPSET,CTI4 CTI Application Trigger Set Register" bitfld.long 0x00 0.--3. " APPSET ,Set Channel Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18++0x3 line.long 0x00 "CTI4_CTIAPPCLEAR,CTI4 CTI Application Trigger Clear Register" bitfld.long 0x00 0.--3. " APPCLEAR ,Channel Clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C++0x3 line.long 0x00 "CTI4_CTIAPPPULSE,CTI4 CTI Application Pulse Register" bitfld.long 0x00 0.--3. " Bit_0APPULSE ,Channel Event Pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x00 "CTI4_CTIINEN0,CTI4 CTI Trigger 0 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "CTI4_CTIINEN1,CTI4 CTI Trigger 1 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28++0x3 line.long 0x00 "CTI4_CTIINEN2,CTI4 CTI Trigger 2 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C++0x3 line.long 0x00 "CTI4_CTIINEN3,CTI4 CTI Trigger 3 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x3 line.long 0x00 "CTI4_CTIINEN4,CTI4 CTI Trigger 4 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x3 line.long 0x00 "CTI4_CTIINEN5,CTI4 CTI Trigger 5 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38++0x3 line.long 0x00 "CTI4_CTIINEN6,CTI4 CTI Trigger 6 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x3 line.long 0x00 "CTI4_CTIINEN7,CTI4 CTI Trigger 7 to Channel Enable Register" bitfld.long 0x00 0.--3. " TRIGINEN ,Channel Trigger Input Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "CTI4_CTIOUTEN0,CTI4 CTI Channel to Trigger 0 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA4++0x3 line.long 0x00 "CTI4_CTIOUTEN1,CTI4 CTI Channel to Trigger 1 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA8++0x3 line.long 0x00 "CTI4_CTIOUTEN2,CTI4 CTI Channel to Trigger 2 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xAC++0x3 line.long 0x00 "CTI4_CTIOUTEN3,CTI4 CTI Channel to Trigger 3 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x3 line.long 0x00 "CTI4_CTIOUTEN4,CTI4 CTI Channel to Trigger 4 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB4++0x3 line.long 0x00 "CTI4_CTIOUTEN5,CTI4 CTI Channel to Trigger 5 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB8++0x3 line.long 0x00 "CTI4_CTIOUTEN6,CTI4 CTI Channel to Trigger 6 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xBC++0x3 line.long 0x00 "CTI4_CTIOUTEN7,CTI4 CTI Channel to Trigger 7 Enable Register" bitfld.long 0x00 0.--3. " TRIGOUTEN ,Channel Trigger Output Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x3 line.long 0x00 "CTI4_CTITRIGINSTATUS,CTI4 CTI Trigger In Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGINSTATUS ,Trigger In Status" group.long 0x134++0x3 line.long 0x00 "CTI4_CTITRIGOUTSTATUS,CTI4 CTI Trigger Out Status Register" hexmask.long.byte 0x00 0.--7. 1. " TRIGOUTSTATUS ,Trigger Output Status" group.long 0x138++0x3 line.long 0x00 "CTI4_CTICHINSTATUS,CTI4 CTI Channel In Status Register" bitfld.long 0x00 0.--3. " CTCHINSTATUS ,Channel Input Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x13C++0x3 line.long 0x00 "CTI4_CTICHOUTSTATUS,CTI4 CTI Channel Out Status Register" bitfld.long 0x00 0.--3. " CTCHOUTSTATUS ,Channel Out Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x140++0x3 line.long 0x00 "CTI4_CTIGATE,CTI4 Enable CTI Channel Gate Register" bitfld.long 0x00 3. " CTIGATEEN3 ,Enable CTICHOUT3" "0,1" bitfld.long 0x00 2. " CTIGATEEN2 ,Enable CTICHOUT2" "0,1" bitfld.long 0x00 1. " CTIGATEEN1 ,Enable CTICHOUT1" "0,1" newline bitfld.long 0x00 0. " CTIGATEEN0 ,Enable CTICHOUT0" "0,1" group.long 0x144++0x3 line.long 0x00 "CTI4_ASICCTL,CTI4 External Multiplexor Control Register" hexmask.long.byte 0x00 0.--7. 1. " ASICCTL ,ASIC Control" group.long 0xEDC++0x3 line.long 0x00 "CTI4_ITCHINACK,CTI4 ITCHINACK" bitfld.long 0x00 0.--3. " CTCHINACK ,Set the value of the CTCHINACK outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE0++0x3 line.long 0x00 "CTI4_ITTRIGINACK,CTI4 ITTRIGINACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGINACK ,Set the value of the CTTRIGINACK outputs" group.long 0xEE4++0x3 line.long 0x00 "CTI4_ITCHOUT,CTI4 ITCHOUT" bitfld.long 0x00 0.--3. " CTCHOUT ,Set the value of the CTCHOUT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEE8++0x3 line.long 0x00 "CTI4_ITTRIGOUT,CTI4 ITTRIGOUT" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUT ,Set the value of the CTTRIGOUT outputs" group.long 0xEEC++0x3 line.long 0x00 "CTI4_ITCHOUTACK,CTI4 ITCHOUTACK" bitfld.long 0x00 0.--3. " CTCHOUTACK ,Read the values of the CTCHOUTACK inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF0++0x3 line.long 0x00 "CTI4_ITTRIGOUTACK,CTI4 ITTRIGOUTACK" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGOUTACK ,Read the values of the CTTRIGOUTACK inputs" group.long 0xEF4++0x3 line.long 0x00 "CTI4_ITCHIN,CTI4 ITCHIN" bitfld.long 0x00 0.--3. " CTCHIN ,Read the values of the CTCHIN inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xEF8++0x3 line.long 0x00 "CTI4_ITTRIGIN,CTI4 ITTRIGIN" hexmask.long.byte 0x00 0.--7. 1. " CTTRIGIN ,Read the values of the CTTRIGIN inputs" group.long 0xF00++0x3 line.long 0x00 "CTI4_ITCTRL,CTI4 Integration Mode Control Register" bitfld.long 0x00 0. " INTEGRATION_MODE ,Integration Mode Enable" "0,1" group.long 0xFA0++0x3 line.long 0x00 "CTI4_CLAIMSET,CTI4 Claim Tag Set Register" bitfld.long 0x00 0.--3. " CLAIMSET ,Claim Tag Set Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFA4++0x3 line.long 0x00 "CTI4_CLAIMCLR,CTI4 Claim Tag Clear Register" bitfld.long 0x00 0.--3. " CLAIMCLR ,Claim Tag Clear Register Bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFB0++0x3 line.long 0x00 "CTI4_LAR,CTI4 Lock Access Register" group.long 0xFB4++0x3 line.long 0x00 "CTI4_LSR,CTI4 Lock Status Register" bitfld.long 0x00 1. " ACCESS ,Access Blocked to Device" "0,1" bitfld.long 0x00 0. " LOCK ,Lock Exists for Device" "0,1" group.long 0xFB8++0x3 line.long 0x00 "CTI4_AUTHSTATUS,CTI4 Authentication Status" bitfld.long 0x00 3. " NDBG_EN ,Non-invasive Debug Enabled Status" "0,1" bitfld.long 0x00 2. " NDBG_CTL ,Non-invasive Debug Controlled" "0,1" bitfld.long 0x00 1. " IDBG_EN ,Invasive Debug Enable Status" "0,1" newline bitfld.long 0x00 0. " IDBG_CTL ,Invasive Debug Controlled" "0,1" group.long 0xFC8++0x3 line.long 0x00 "CTI4_DEVID,CTI4 Device ID" hexmask.long.tbyte 0x00 0.--19. 1. " DEVID ,Device ID Field" group.long 0xFCC++0x3 line.long 0x00 "CTI4_DEVTYPE,CTI4 Device Type" hexmask.long.byte 0x00 0.--7. 1. " DEVTYPE ,Device Type Field" group.long 0xFD0++0x3 line.long 0x00 "CTI4_PERIPHID4,CTI4 Peripheral ID4" hexmask.long.byte 0x00 0.--7. 1. " PID4 ,Peripheral ID4 Field" group.long 0xFD4++0x3 line.long 0x00 "CTI4_PERIPHID5,CTI4 Peripheral ID5" hexmask.long.byte 0x00 0.--7. 1. " PID5 ,Peripheral ID5 Field" group.long 0xFD8++0x3 line.long 0x00 "CTI4_PERIPHID6,CTI4 Peripheral ID6" hexmask.long.byte 0x00 0.--7. 1. " PID6 ,Peripheral ID6 Field" group.long 0xFDC++0x3 line.long 0x00 "CTI4_PERIPHID7,CTI4 Peripheral ID7" hexmask.long.byte 0x00 0.--7. 1. " PID7 ,Peripheral ID7 Field" group.long 0xFE0++0x3 line.long 0x00 "CTI4_PERIPHID0,CTI4 Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " PID0 ,Peripheral ID0 Field" group.long 0xFE4++0x3 line.long 0x00 "CTI4_PERIPHID1,CTI4 Peripheral ID1" hexmask.long.byte 0x00 0.--7. 1. " PID1 ,Peripheral ID1 Field" group.long 0xFE8++0x3 line.long 0x00 "CTI4_PERIPHID2,CTI4 Peripheral ID2" hexmask.long.byte 0x00 0.--7. 1. " PID2 ,Peripheral ID2 Field" group.long 0xFEC++0x3 line.long 0x00 "CTI4_PERIPHID3,CTI4 Peripheral ID3" hexmask.long.byte 0x00 0.--7. 1. " PID3 ,Peripheral ID3 Field" group.long 0xFF0++0x3 line.long 0x00 "CTI4_COMPID0,CTI4 Component ID0" hexmask.long.byte 0x00 0.--7. 1. " ID0 ,Component ID0 Field" group.long 0xFF4++0x3 line.long 0x00 "CTI4_COMPID1,CTI4 Component ID1" hexmask.long.byte 0x00 0.--7. 1. " ID1 ,Component ID1 Field" group.long 0xFF8++0x3 line.long 0x00 "CTI4_COMPID2,CTI4 Component ID2" hexmask.long.byte 0x00 0.--7. 1. " ID2 ,Component ID2 Field" group.long 0xFFC++0x3 line.long 0x00 "CTI4_COMPID3,CTI4 Component ID3" hexmask.long.byte 0x00 0.--7. 1. " ID3 ,Component ID3 Field" tree.end tree.end tree "DAI (Digital Audio Interface)" tree "DAI0" base ad:0x310C9000 width 17. group.long 0x0++0x3 line.long 0x00 "DAI0_EXTD_CLK0,DAI0 Extended Clock Routing Control Register 0" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0x4++0x3 line.long 0x00 "DAI0_EXTD_CLK1,DAI0 Extended Clock Routing Control Register 1" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "DAI0_EXTD_CLK2,DAI0 Extended Clock Routing Control Register 2" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" newline bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0xC++0x3 line.long 0x00 "DAI0_EXTD_CLK3,DAI0 Extended Clock Routing Control Register 3" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 0" "0,1,2,3" group.long 0x10++0x3 line.long 0x00 "DAI0_EXTD_CLK4,DAI0 Extended Clock Routing Control Register 4" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0x14++0x3 line.long 0x00 "DAI0_EXTD_CLK5,DAI0 Extended Clock Routing Control Register 5" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0x18++0x3 line.long 0x00 "DAI0_EXTD_DAT0,DAI0 Extended Serial Data Routing Control Register 0" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" newline bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x1C++0x3 line.long 0x00 "DAI0_EXTD_DAT1,DAI0 Extended Serial Data Routing Control Register 1" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" newline bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x20++0x3 line.long 0x00 "DAI0_EXTD_DAT2,DAI0 Extended Serial Data Routing Control Register 2" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" newline bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x24++0x3 line.long 0x00 "DAI0_EXTD_DAT3,DAI0 Extended Serial Data Routing Control Register 3" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" newline bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x28++0x3 line.long 0x00 "DAI0_EXTD_DAT4,DAI0 Extended Serial Data Routing Control Register 4" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x2C++0x3 line.long 0x00 "DAI0_EXTD_DAT5,DAI0 Extended Serial Data Routing Control Register 5" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" group.long 0x30++0x3 line.long 0x00 "DAI0_EXTD_DAT6,DAI0 Extended Serial Data Routing Control Register 6" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" newline bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x34++0x3 line.long 0x00 "DAI0_EXTD_FS0,DAI0 Extended Frame Sync Routing Control Register 0" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Frame Sync 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Frame Sync 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Frame Sync 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Frame Sync 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Frame Sync 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Frame Sync 0" "0,1,2,3" group.long 0x38++0x3 line.long 0x00 "DAI0_EXTD_FS1,DAI0 Extended Frame Sync Routing Control Register 1" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Frame Sync 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Frame Sync 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Frame Sync 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Frame Sync 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Frame Sync 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Frame Sync 0" "0,1,2,3" group.long 0x3C++0x3 line.long 0x00 "DAI0_EXTD_FS2,DAI0 Extended Frame Sync Routing Control Register 2" bitfld.long 0x00 8.--9. " IN2 ,Extended Input Frame Sync 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Frame Sync 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Frame Sync 0" "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "DAI0_EXTD_FS4,DAI0 Extended Frame Sync Routing Control Register 4" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Frame Sync 3" "0,1,2,3" bitfld.long 0x00 8.--9. " IN2 ,Extended Input Frame Sync 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Frame Sync 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " IN0 ,Extended Input Frame Sync 0" "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "DAI0_EXTD_PIN0,DAI0 Extended Pin Buffer Assignment Register 0" bitfld.long 0x00 13. " PB04 ,Extended Pin Buffer 4 Input" "0,1" bitfld.long 0x00 9. " PB03 ,Extended Pin Buffer 3 Input" "0,1" bitfld.long 0x00 5. " PB02 ,Extended Pin Buffer 2 Input" "0,1" newline bitfld.long 0x00 1. " PB01 ,Extended Pin Buffer 1 Input" "0,1" group.long 0x4C++0x3 line.long 0x00 "DAI0_EXTD_PIN1,DAI0 Extended Pin Buffer Assignment Register 1" bitfld.long 0x00 13. " PB08 ,Extended Pin Buffer 8 Input" "0,1" bitfld.long 0x00 9. " PB07 ,Extended Pin Buffer 7 Input" "0,1" bitfld.long 0x00 5. " PB06 ,Extended Pin Buffer 6 Input" "0,1" newline bitfld.long 0x00 1. " PB05 ,Extended Pin Buffer 5 Input" "0,1" group.long 0x50++0x3 line.long 0x00 "DAI0_EXTD_PIN2,DAI0 Extended Pin Buffer Assignment Register 2" bitfld.long 0x00 13. " PB12 ,Extended Pin Buffer 12 Input" "0,1" bitfld.long 0x00 9. " PB11 ,Extended Pin Buffer 11 Input" "0,1" bitfld.long 0x00 5. " PB10 ,Extended Pin Buffer 10 Input" "0,1" newline bitfld.long 0x00 1. " PB09 ,Extended Pin Buffer 9 Input" "0,1" group.long 0x54++0x3 line.long 0x00 "DAI0_EXTD_PIN3,DAI0 Extended Pin Buffer Assignment Register 3" bitfld.long 0x00 13. " PB16 ,Extended Pin Buffer 16 Input" "0,1" bitfld.long 0x00 9. " PB15 ,Extended Pin Buffer 15 Input" "0,1" bitfld.long 0x00 5. " PB14 ,Extended Pin Buffer 14 Input" "0,1" newline bitfld.long 0x00 1. " PB13 ,Extended Pin Buffer 13 Input" "0,1" group.long 0x58++0x3 line.long 0x00 "DAI0_EXTD_PIN4,DAI0 Extended Pin Buffer Assignment Register 4" bitfld.long 0x00 13. " PB20 ,Extended Pin Buffer 20 Input" "0,1" bitfld.long 0x00 9. " PB19 ,Extended Pin Buffer 19 Input" "0,1" bitfld.long 0x00 5. " PB18 ,Extended Pin Buffer 18 Input" "0,1" newline bitfld.long 0x00 1. " PB17 ,Extended Pin Buffer 17 Input" "0,1" group.long 0x5C++0x3 line.long 0x00 "DAI0_EXTD_MISC0,DAI0 Extended Miscellaneous Control Register 0" bitfld.long 0x00 20.--21. " IN11 ,Extended Input 11" "0,1,2,3" bitfld.long 0x00 16.--17. " IN10 ,Extended Input 10" "0,1,2,3" bitfld.long 0x00 12.--13. " IN9 ,Extended Input 9" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN8 ,Extended Input 8" "0,1,2,3" bitfld.long 0x00 4.--5. " IN7 ,Extended Input 7" "0,1,2,3" bitfld.long 0x00 0.--1. " IN6 ,Extended Input 6" "0,1,2,3" group.long 0x60++0x3 line.long 0x00 "DAI0_EXTD_MISC1,DAI0 Extended Miscellaneous Control Register 1" bitfld.long 0x00 20.--21. " IN5 ,Extended Input 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input 0" "0,1,2,3" group.long 0x64++0x3 line.long 0x00 "DAI0_EXTD_MISC2,DAI0 Extended Miscellaneous Control Register 2" bitfld.long 0x00 12.--13. " IN3 ,Extended Input 3" "0,1,2,3" bitfld.long 0x00 8.--9. " IN2 ,Extended Input 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " IN0 ,Extended Input 0" "0,1,2,3" group.long 0x68++0x3 line.long 0x00 "DAI0_EXTD_PBEN0,DAI0 Extended Pin Buffer Enable Register 0" bitfld.long 0x00 17. " PB05 ,Extended Pin Buffer Enable 5" "0,1" bitfld.long 0x00 13. " PB04 ,Extended Pin Buffer Enable 4" "0,1" bitfld.long 0x00 9. " PB03 ,Extended Pin Buffer Enable 3" "0,1" newline bitfld.long 0x00 5. " PB02 ,Extended Pin Buffer Enable 2" "0,1" bitfld.long 0x00 1. " PB01 ,Extended Pin Buffer Enable 1" "0,1" group.long 0x6C++0x3 line.long 0x00 "DAI0_EXTD_PBEN1,DAI0 Extended Pin Buffer Enable Register 1" bitfld.long 0x00 17. " PB10 ,Extended Pin Buffer Enable 10" "0,1" bitfld.long 0x00 13. " PB09 ,Extended Pin Buffer Enable 9" "0,1" bitfld.long 0x00 9. " PB08 ,Extended Pin Buffer Enable 8" "0,1" newline bitfld.long 0x00 5. " PB07 ,Extended Pin Buffer Enable 7" "0,1" bitfld.long 0x00 1. " PB06 ,Extended Pin Buffer Enable 6" "0,1" group.long 0x70++0x3 line.long 0x00 "DAI0_EXTD_PBEN2,DAI0 Extended Pin Buffer Enable Register 2" bitfld.long 0x00 17. " PB15 ,Extended Pin Buffer Enable 15" "0,1" bitfld.long 0x00 13. " PB14 ,Extended Pin Buffer Enable 14" "0,1" bitfld.long 0x00 9. " PB13 ,Extended Pin Buffer Enable 13" "0,1" newline bitfld.long 0x00 5. " PB12 ,Extended Pin Buffer Enable 12" "0,1" bitfld.long 0x00 1. " PB11 ,Extended Pin Buffer Enable 11" "0,1" group.long 0x74++0x3 line.long 0x00 "DAI0_EXTD_PBEN3,DAI0 Extended Pin Buffer Enable Register 3" bitfld.long 0x00 17. " PB20 ,Extended Pin Buffer Enable 20" "0,1" bitfld.long 0x00 13. " PB19 ,Extended Pin Buffer Enable 19" "0,1" bitfld.long 0x00 9. " PB18 ,Extended Pin Buffer Enable 18" "0,1" newline bitfld.long 0x00 5. " PB17 ,Extended Pin Buffer Enable 17" "0,1" bitfld.long 0x00 1. " PB16 ,Extended Pin Buffer Enable 16" "0,1" group.long 0xC0++0x3 line.long 0x00 "DAI0_CLK0,DAI0 Clock Routing Control Register 0" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Clock 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC4++0x3 line.long 0x00 "DAI0_CLK1,DAI0 Clock Routing Control Register 1" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Clock 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC8++0x3 line.long 0x00 "DAI0_CLK2,DAI0 Clock Routing Control Register 2" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " IN2 ,Input Clock 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xCC++0x3 line.long 0x00 "DAI0_CLK3,DAI0 Clock Routing Control Register 3" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD0++0x3 line.long 0x00 "DAI0_CLK4,DAI0 Clock Routing Control Register 4" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD4++0x3 line.long 0x00 "DAI0_CLK5,DAI0 Clock Routing Control Register 5" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Clock 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x3 line.long 0x00 "DAI0_DAT0,DAI0 Serial Data Routing Control Register 0" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x104++0x3 line.long 0x00 "DAI0_DAT1,DAI0 Serial Data Routing Control Register 1" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x108++0x3 line.long 0x00 "DAI0_DAT2,DAI0 Serial Data Routing Control Register 2" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10C++0x3 line.long 0x00 "DAI0_DAT3,DAI0 Serial Data Routing Control Register 3" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x110++0x3 line.long 0x00 "DAI0_DAT4,DAI0 Serial Data Routing Control Register 4" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x114++0x3 line.long 0x00 "DAI0_DAT5,DAI0 Serial Data Routing Control Register 5" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x118++0x3 line.long 0x00 "DAI0_DAT6,DAI0 Serial Data Routing Control Register 6" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x140++0x3 line.long 0x00 "DAI0_FS0,DAI0 Frame Sync Routing Control Register 0" bitfld.long 0x00 25.--29. " IN5 ,Input Frame Sync 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Frame Sync 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Frame Sync 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Frame Sync 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Frame Sync 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Frame Sync 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x144++0x3 line.long 0x00 "DAI0_FS1,DAI0 Frame Sync Routing Control Register 1" bitfld.long 0x00 25.--29. " IN5 ,Input Frame Sync 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Frame Sync 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Frame Sync 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Frame Sync 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Frame Sync 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Frame Sync 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x148++0x3 line.long 0x00 "DAI0_FS2,DAI0 Frame Sync Routing Control Register 2" bitfld.long 0x00 10.--14. " IN2 ,Input Frame Sync 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Frame Sync 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Frame Sync 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x150++0x3 line.long 0x00 "DAI0_FS4,DAI0 Frame Sync Routing Control Register 4" bitfld.long 0x00 15.--19. " IN3 ,Input Frame Sync 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " IN2 ,Input Frame Sync 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Frame Sync 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. " IN0 ,Input Frame Sync 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x180++0x3 line.long 0x00 "DAI0_PIN0,DAI0 Pin Buffer Assignment Register 0" hexmask.long.byte 0x00 21.--27. 1. " PB04 ,Pin Buffer 4 Input" hexmask.long.byte 0x00 14.--20. 1. " PB03 ,Pin Buffer 3 Input" hexmask.long.byte 0x00 7.--13. 1. " PB02 ,Pin Buffer 2 Input" newline hexmask.long.byte 0x00 0.--6. 1. " PB01 ,Pin Buffer 1 Input" group.long 0x184++0x3 line.long 0x00 "DAI0_PIN1,DAI0 Pin Buffer Assignment Register 1" hexmask.long.byte 0x00 21.--27. 1. " PB08 ,Pin Buffer 8 Input" hexmask.long.byte 0x00 14.--20. 1. " PB07 ,Pin Buffer 7 Input" hexmask.long.byte 0x00 7.--13. 1. " PB06 ,Pin Buffer 6 Input" newline hexmask.long.byte 0x00 0.--6. 1. " PB05 ,Pin Buffer 5 Input" group.long 0x188++0x3 line.long 0x00 "DAI0_PIN2,DAI0 Pin Buffer Assignment Register 2" hexmask.long.byte 0x00 21.--27. 1. " PB12 ,Pin Buffer 12 Input" hexmask.long.byte 0x00 14.--20. 1. " PB11 ,Pin Buffer 11 Input" hexmask.long.byte 0x00 7.--13. 1. " PB10 ,Pin Buffer 10 Input" newline hexmask.long.byte 0x00 0.--6. 1. " PB09 ,Pin Buffer 9 Input" group.long 0x18C++0x3 line.long 0x00 "DAI0_PIN3,DAI0 Pin Buffer Assignment Register 3" hexmask.long.byte 0x00 21.--27. 1. " PB16 ,Pin Buffer 16 Input" hexmask.long.byte 0x00 14.--20. 1. " PB15 ,Pin Buffer 15 Input" hexmask.long.byte 0x00 7.--13. 1. " PB14 ,Pin Buffer 14 Input" newline hexmask.long.byte 0x00 0.--6. 1. " PB13 ,Pin Buffer 13 Input" group.long 0x190++0x3 line.long 0x00 "DAI0_PIN4,DAI0 Pin Buffer Assignment Register 4" bitfld.long 0x00 29. " INV20 ,Pin Buffer 20 Invert" "0,1" bitfld.long 0x00 28. " INV19 ,Pin Buffer 19 Invert" "0,1" hexmask.long.byte 0x00 21.--27. 1. " PB20 ,Pin Buffer 20 Input" newline hexmask.long.byte 0x00 14.--20. 1. " PB19 ,Pin Buffer 19 Input" hexmask.long.byte 0x00 7.--13. 1. " PB18 ,Pin Buffer 18 Input" hexmask.long.byte 0x00 0.--6. 1. " PB17 ,Pin Buffer 17 Input" group.long 0x1C0++0x3 line.long 0x00 "DAI0_MISC0,DAI0 Miscellaneous Control Register 0" bitfld.long 0x00 31. " INV11 ,Invert 11" "0,1" bitfld.long 0x00 30. " INV10 ,Invert 10" "0,1" bitfld.long 0x00 25.--29. " IN11 ,Input 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--24. " IN10 ,Input 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN9 ,Input 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " IN8 ,Input 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. " IN7 ,Input 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN6 ,Input 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C4++0x3 line.long 0x00 "DAI0_MISC1,DAI0 Miscellaneous Control Register 1" bitfld.long 0x00 25.--29. " IN5 ,Input 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C8++0x3 line.long 0x00 "DAI0_MISC2,DAI0 Miscellaneous Control Register 1" bitfld.long 0x00 15.--19. " IN3 ,Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " IN2 ,Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. " IN0 ,Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1E0++0x3 line.long 0x00 "DAI0_PBEN0,DAI0 Pin Buffer Enable Register 0" bitfld.long 0x00 24.--29. " PB05 ,Pin Buffer Enable 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " PB04 ,Pin Buffer Enable 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " PB03 ,Pin Buffer Enable 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " PB02 ,Pin Buffer Enable 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PB01 ,Pin Buffer Enable 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E4++0x3 line.long 0x00 "DAI0_PBEN1,DAI0 Pin Buffer Enable Register 1" bitfld.long 0x00 24.--29. " PB10 ,Pin Buffer Enable 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " PB09 ,Pin Buffer Enable 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " PB08 ,Pin Buffer Enable 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " PB07 ,Pin Buffer Enable 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PB06 ,Pin Buffer Enable 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E8++0x3 line.long 0x00 "DAI0_PBEN2,DAI0 Pin Buffer Enable Register 2" bitfld.long 0x00 24.--29. " PB15 ,Pin Buffer Enable 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " PB14 ,Pin Buffer Enable 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " PB13 ,Pin Buffer Enable 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " PB12 ,Pin Buffer Enable 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PB11 ,Pin Buffer Enable 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1EC++0x3 line.long 0x00 "DAI0_PBEN3,DAI0 Pin Buffer Enable Register 3" bitfld.long 0x00 24.--29. " PB20 ,Pin Buffer Enable 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " PB19 ,Pin Buffer Enable 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " PB18 ,Pin Buffer Enable 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " PB17 ,Pin Buffer Enable 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PB16 ,Pin Buffer Enable 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x3 line.long 0x00 "DAI0_IMSK_FE,DAI0 Falling-Edge Interrupt Mask Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x204++0x3 line.long 0x00 "DAI0_IMSK_RE,DAI0 Rising-Edge Interrupt Mask Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x210++0x3 line.long 0x00 "DAI0_IMSK_PRI,DAI0 Core Interrupt Priority Assignment Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receiver Non-Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x220++0x3 line.long 0x00 "DAI0_IRPTL_H,DAI0 High Priority Interrupt Latch Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change Indication" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x224++0x3 line.long 0x00 "DAI0_IRPTL_L,DAI0 Low Priority Interrupt Latch Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x230++0x3 line.long 0x00 "DAI0_IRPTL_HS,DAI0 Shadow High Priority Interrupt Latch Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x234++0x3 line.long 0x00 "DAI0_IRPTL_LS,DAI0 Shadow Low Priority Interrupt Latch Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receiver Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Emphasis Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Error Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x2E4++0x3 line.long 0x00 "DAI0_PIN_STAT,DAI0 Pin Status Register" bitfld.long 0x00 19. " PB20 ,Pin Buffer 20 Status" "0,1" bitfld.long 0x00 18. " PB19 ,Pin Buffer 19 Status" "0,1" bitfld.long 0x00 17. " PB18 ,Pin Buffer 18 Status" "0,1" newline bitfld.long 0x00 16. " PB17 ,Pin Buffer 17 Status" "0,1" bitfld.long 0x00 15. " PB16 ,Pin Buffer 16 Status" "0,1" bitfld.long 0x00 14. " PB15 ,Pin Buffer 15 Status" "0,1" newline bitfld.long 0x00 13. " PB14 ,Pin Buffer 14 Status" "0,1" bitfld.long 0x00 12. " PB13 ,Pin Buffer 13 Status" "0,1" bitfld.long 0x00 11. " PB12 ,Pin Buffer 12 Status" "0,1" newline bitfld.long 0x00 10. " PB11 ,Pin Buffer 11 Status" "0,1" bitfld.long 0x00 9. " PB10 ,Pin Buffer 10 Status" "0,1" bitfld.long 0x00 8. " PB09 ,Pin Buffer 09 Status" "0,1" newline bitfld.long 0x00 7. " PB08 ,Pin Buffer 08 Status" "0,1" bitfld.long 0x00 6. " PB07 ,Pin Buffer 07 Status" "0,1" bitfld.long 0x00 5. " PB06 ,Pin Buffer 06 Status" "0,1" newline bitfld.long 0x00 4. " PB05 ,Pin Buffer 05 Status" "0,1" bitfld.long 0x00 3. " PB04 ,Pin Buffer 04 Status" "0,1" bitfld.long 0x00 2. " PB03 ,Pin Buffer 03 Status" "0,1" newline bitfld.long 0x00 1. " PB02 ,Pin Buffer 02 Status" "0,1" bitfld.long 0x00 0. " PB01 ,Pin Buffer 01 Status" "0,1" group.long 0x2E8++0x3 line.long 0x00 "DAI0_GBL_SP_EN,DAI0 Global SPORT Enable Register" bitfld.long 0x00 19. " GBL_SP3B_SC_EN ,SPORT3 B Secondary Channel Select" "0,1" bitfld.long 0x00 18. " GBL_SP3B_PC_EN ,SPORT3 B Primary Channel Select" "0,1" bitfld.long 0x00 17. " GBL_SP3A_SC_EN ,SPORT3 A Secondary Channel Select" "0,1" newline bitfld.long 0x00 16. " GBL_SP3A_PC_EN ,SPORT3 A Primary Channel Select" "0,1" bitfld.long 0x00 15. " GBL_SP2B_SC_EN ,SPORT2 B Secondary Channel Select" "0,1" bitfld.long 0x00 14. " GBL_SP2B_PC_EN ,SPORT2 B Primary Channel Select" "0,1" newline bitfld.long 0x00 13. " GBL_SP2A_SC_EN ,SPORT2 A Secondary Channel Select" "0,1" bitfld.long 0x00 12. " GBL_SP2A_PC_EN ,SPORT2 A Primary Channel Select" "0,1" bitfld.long 0x00 11. " GBL_SP1B_SC_EN ,SPORT1 B Secondary Channel Select" "0,1" newline bitfld.long 0x00 10. " GBL_SP1B_PC_EN ,SPORT1 B Primary Channel Select" "0,1" bitfld.long 0x00 9. " GBL_SP1A_SC_EN ,SPORT1 A Secondary Channel Select" "0,1" bitfld.long 0x00 8. " GBL_SP1A_PC_EN ,SPORT1 A Primary Channel Select" "0,1" newline bitfld.long 0x00 7. " GBL_SP0B_SC_EN ,SPORT0 B Secondary Channel Select" "0,1" bitfld.long 0x00 6. " GBL_SP0B_PC_EN ,SPORT0 B Primary Channel Select" "0,1" bitfld.long 0x00 5. " GBL_SP0A_SC_EN ,SPORT0 A Secondary Channel Select" "0,1" newline bitfld.long 0x00 4. " GBL_SP0A_PC_EN ,SPORT0 A Primary Channel Select" "0,1" bitfld.long 0x00 3. " GBL_SPEN_GRP1 ,Group 1 SPORT Subgroup Select" "0,1" bitfld.long 0x00 2. " GBL_SPEN_GRP0 ,Group 0 SPORT Subgroup Select" "0,1" newline bitfld.long 0x00 1. " GBL_SPEN_DAIX ,DAI SPORTs Enable" "0,1" bitfld.long 0x00 0. " GBL_SP_EN ,Global SPORTs Enable" "0,1" group.long 0x2EC++0x3 line.long 0x00 "DAI0_GBL_INT_EN,DAI0 Global SPORT Interrupt Grouping Register" bitfld.long 0x00 21. " GRP1_ERR_EN ,Enable Error For Group1" "0,1" bitfld.long 0x00 20. " GRP0_ERR_EN ,Enable Error For Group0" "0,1" bitfld.long 0x00 19. " GRP1_TRG_EN ,Group 1 Trigger Enable" "0,1" newline bitfld.long 0x00 18. " GRP0_TRG_EN ,Group 0 Trigger Enable" "0,1" bitfld.long 0x00 17. " GRP1_INT_EN ,Group 1 Interrupt Enable" "0,1" bitfld.long 0x00 16. " GRP0_INT_EN ,Group 0 Interrupt Enable" "0,1" newline bitfld.long 0x00 15. " GRP1_SP3BINT_EN ,SP3B Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 14. " GRP1_SP3AINT_EN ,SP3A Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 13. " GRP1_SP2BINT_EN ,SP2B Interrupt/Trigger Group 1 Enable" "0,1" newline bitfld.long 0x00 12. " GRP1_SP2AINT_EN ,SP2A Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 11. " GRP1_SP1BINT_EN ,SP1B Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 10. " GRP1_SP1AINT_EN ,SP1A Interrupt/Trigger Group 1 Enable" "0,1" newline bitfld.long 0x00 9. " GRP1_SP0BINT_EN ,SP0B Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 8. " GRP1_SP0AINT_EN ,SP0A Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 7. " GRP0_SP3BINT_EN ,SP3B Interrupt/Trigger Group 0 Enable" "0,1" newline bitfld.long 0x00 6. " GRP0_SP3AINT_EN ,SP3A Interrupt/Trigger Group 0 Enable" "0,1" bitfld.long 0x00 5. " GRP0_SP2BINT_EN ,SP2B Interrupt/Trigger Group 0 Enable" "0,1" bitfld.long 0x00 4. " GRP0_SP2AINT_EN ,SP2A Interrupt/Trigger Group 0 Enable" "0,1" newline bitfld.long 0x00 3. " GRP0_SP1BINT_EN ,SP1B Interrupt/Trigger Group 0 Enable" "0,1" bitfld.long 0x00 2. " GRP0_SP1AINT_EN ,SP1A Interrupt/Trigger Group 0 Enable" "0,1" bitfld.long 0x00 1. " GRP0_SP0BINT_EN ,SP0B Interrupt/Trigger Group 0 Enable" "0,1" newline bitfld.long 0x00 0. " GRP0_SP0AINT_EN ,SP0A Interrupt/Trigger Group 0 Enable" "0,1" group.long 0x2F0++0x3 line.long 0x00 "DAI0_GBL_PCG_EN,DAI0 Global PCG Enable Control Register" bitfld.long 0x00 23. " GBL_PCGH_FS_EN ,PCG-H Frame Sync Enable" "0,1" bitfld.long 0x00 22. " GBL_PCGH_CLK_EN ,PCG-H Clock Enable" "0,1" bitfld.long 0x00 21. " GBL_PCGG_FS_EN ,PCG-G Frame Sync Enable" "0,1" newline bitfld.long 0x00 20. " GBL_PCGG_CLK_EN ,PCG-G Clock Enable" "0,1" bitfld.long 0x00 19. " GBL_PCGD_FS_EN ,PCG-D Frame Sync Enable" "0,1" bitfld.long 0x00 18. " GBL_PCGD_CLK_EN ,PCG-D Clock Enable" "0,1" newline bitfld.long 0x00 17. " GBL_PCGC_FS_EN ,PCG-C Frame Sync Enable" "0,1" bitfld.long 0x00 16. " GBL_PCGC_CLK_EN ,PCG-C Clock Enable" "0,1" bitfld.long 0x00 15. " GBL_PCGF_FS_EN ,PCG-F Frame Sync Enable" "0,1" newline bitfld.long 0x00 14. " GBL_PCGF_CLK_EN ,PCG-F Clock Enable" "0,1" bitfld.long 0x00 13. " GBL_PCGE_FS_EN ,PCG-E Frame Sync Enable" "0,1" bitfld.long 0x00 12. " GBL_PCGE_CLK_EN ,PCG-E Clock Enable" "0,1" newline bitfld.long 0x00 11. " GBL_PCGB_FS_EN ,PCG-B Frame Sync Enable" "0,1" bitfld.long 0x00 10. " GBL_PCGB_CLK_EN ,PCG-B Clock Enable" "0,1" bitfld.long 0x00 9. " GBL_PCGA_FS_EN ,PCG-A Frame Sync Enable" "0,1" newline bitfld.long 0x00 8. " GBL_PCGA_CLK_EN ,PCG-A Clock Enable" "0,1" bitfld.long 0x00 2. " GBL_PCG_CDGH_EN ,PCG C/D/G/H Enable" "0,1" bitfld.long 0x00 1. " GBL_PCG_ABEF_EN ,PCG A/B/E/F Enable" "0,1" newline bitfld.long 0x00 0. " GBL_PCG_EN ,Global PCG Enable" "0,1" tree.end tree "DAI1" base ad:0x310CA000 width 17. group.long 0x0++0x3 line.long 0x00 "DAI1_EXTD_CLK0,DAI1 Extended Clock Routing Control Register 0" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0x4++0x3 line.long 0x00 "DAI1_EXTD_CLK1,DAI1 Extended Clock Routing Control Register 1" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0x8++0x3 line.long 0x00 "DAI1_EXTD_CLK2,DAI1 Extended Clock Routing Control Register 2" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" newline bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0xC++0x3 line.long 0x00 "DAI1_EXTD_CLK3,DAI1 Extended Clock Routing Control Register 3" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 0" "0,1,2,3" group.long 0x10++0x3 line.long 0x00 "DAI1_EXTD_CLK4,DAI1 Extended Clock Routing Control Register 4" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0x14++0x3 line.long 0x00 "DAI1_EXTD_CLK5,DAI1 Extended Clock Routing Control Register 5" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Clock 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Clock 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Clock 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Clock 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Clock 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Clock 0" "0,1,2,3" group.long 0x18++0x3 line.long 0x00 "DAI1_EXTD_DAT0,DAI1 Extended Serial Data Routing Control Register 0" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" newline bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x1C++0x3 line.long 0x00 "DAI1_EXTD_DAT1,DAI1 Extended Serial Data Routing Control Register 1" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" newline bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x20++0x3 line.long 0x00 "DAI1_EXTD_DAT2,DAI1 Extended Serial Data Routing Control Register 2" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" newline bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x24++0x3 line.long 0x00 "DAI1_EXTD_DAT3,DAI1 Extended Serial Data Routing Control Register 3" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" newline bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x28++0x3 line.long 0x00 "DAI1_EXTD_DAT4,DAI1 Extended Serial Data Routing Control Register 4" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x2C++0x3 line.long 0x00 "DAI1_EXTD_DAT5,DAI1 Extended Serial Data Routing Control Register 5" bitfld.long 0x00 17. " IN4 ,Extended Input Data 4" "0,1" group.long 0x30++0x3 line.long 0x00 "DAI1_EXTD_DAT6,DAI1 Extended Serial Data Routing Control Register 6" bitfld.long 0x00 13. " IN3 ,Extended Input Data 3" "0,1" bitfld.long 0x00 9. " IN2 ,Extended Input Data 2" "0,1" bitfld.long 0x00 5. " IN1 ,Extended Input Data 1" "0,1" newline bitfld.long 0x00 1. " IN0 ,Extended Input Data 0" "0,1" group.long 0x34++0x3 line.long 0x00 "DAI1_EXTD_FS0,DAI1 Extended Frame Sync Routing Control Register 0" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Frame Sync 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Frame Sync 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Frame Sync 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Frame Sync 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Frame Sync 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Frame Sync 0" "0,1,2,3" group.long 0x38++0x3 line.long 0x00 "DAI1_EXTD_FS1,DAI1 Extended Frame Sync Routing Control Register 1" bitfld.long 0x00 20.--21. " IN5 ,Extended Input Frame Sync 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input Frame Sync 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Frame Sync 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input Frame Sync 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Frame Sync 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Frame Sync 0" "0,1,2,3" group.long 0x3C++0x3 line.long 0x00 "DAI1_EXTD_FS2,DAI1 Extended Frame Sync Routing Control Register 2" bitfld.long 0x00 8.--9. " IN2 ,Extended Input Frame Sync 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Frame Sync 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input Frame Sync 0" "0,1,2,3" group.long 0x44++0x3 line.long 0x00 "DAI1_EXTD_FS4,DAI1 Extended Frame Sync Routing Control Register 4" bitfld.long 0x00 12.--13. " IN3 ,Extended Input Frame Sync 3" "0,1,2,3" bitfld.long 0x00 8.--9. " IN2 ,Extended Input Frame Sync 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input Frame Sync 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " IN0 ,Extended Input Frame Sync 0" "0,1,2,3" group.long 0x48++0x3 line.long 0x00 "DAI1_EXTD_PIN0,DAI1 Extended Pin Buffer Assignment Register 0" bitfld.long 0x00 13. " PB04 ,Extended Pin Buffer 4 Input" "0,1" bitfld.long 0x00 9. " PB03 ,Extended Pin Buffer 3 Input" "0,1" bitfld.long 0x00 5. " PB02 ,Extended Pin Buffer 2 Input" "0,1" newline bitfld.long 0x00 1. " PB01 ,Extended Pin Buffer 1 Input" "0,1" group.long 0x4C++0x3 line.long 0x00 "DAI1_EXTD_PIN1,DAI1 Extended Pin Buffer Assignment Register 1" bitfld.long 0x00 13. " PB08 ,Extended Pin Buffer 8 Input" "0,1" bitfld.long 0x00 9. " PB07 ,Extended Pin Buffer 7 Input" "0,1" bitfld.long 0x00 5. " PB06 ,Extended Pin Buffer 6 Input" "0,1" newline bitfld.long 0x00 1. " PB05 ,Extended Pin Buffer 5 Input" "0,1" group.long 0x50++0x3 line.long 0x00 "DAI1_EXTD_PIN2,DAI1 Extended Pin Buffer Assignment Register 2" bitfld.long 0x00 13. " PB12 ,Extended Pin Buffer 12 Input" "0,1" bitfld.long 0x00 9. " PB11 ,Extended Pin Buffer 11 Input" "0,1" bitfld.long 0x00 5. " PB10 ,Extended Pin Buffer 10 Input" "0,1" newline bitfld.long 0x00 1. " PB09 ,Extended Pin Buffer 9 Input" "0,1" group.long 0x54++0x3 line.long 0x00 "DAI1_EXTD_PIN3,DAI1 Extended Pin Buffer Assignment Register 3" bitfld.long 0x00 13. " PB16 ,Extended Pin Buffer 16 Input" "0,1" bitfld.long 0x00 9. " PB15 ,Extended Pin Buffer 15 Input" "0,1" bitfld.long 0x00 5. " PB14 ,Extended Pin Buffer 14 Input" "0,1" newline bitfld.long 0x00 1. " PB13 ,Extended Pin Buffer 13 Input" "0,1" group.long 0x58++0x3 line.long 0x00 "DAI1_EXTD_PIN4,DAI1 Extended Pin Buffer Assignment Register 4" bitfld.long 0x00 13. " PB20 ,Extended Pin Buffer 20 Input" "0,1" bitfld.long 0x00 9. " PB19 ,Extended Pin Buffer 19 Input" "0,1" bitfld.long 0x00 5. " PB18 ,Extended Pin Buffer 18 Input" "0,1" newline bitfld.long 0x00 1. " PB17 ,Extended Pin Buffer 17 Input" "0,1" group.long 0x5C++0x3 line.long 0x00 "DAI1_EXTD_MISC0,DAI1 Extended Miscellaneous Control Register 0" bitfld.long 0x00 20.--21. " IN11 ,Extended Input 11" "0,1,2,3" bitfld.long 0x00 16.--17. " IN10 ,Extended Input 10" "0,1,2,3" bitfld.long 0x00 12.--13. " IN9 ,Extended Input 9" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN8 ,Extended Input 8" "0,1,2,3" bitfld.long 0x00 4.--5. " IN7 ,Extended Input 7" "0,1,2,3" bitfld.long 0x00 0.--1. " IN6 ,Extended Input 6" "0,1,2,3" group.long 0x60++0x3 line.long 0x00 "DAI1_EXTD_MISC1,DAI1 Extended Miscellaneous Control Register 1" bitfld.long 0x00 20.--21. " IN5 ,Extended Input 5" "0,1,2,3" bitfld.long 0x00 16.--17. " IN4 ,Extended Input 4" "0,1,2,3" bitfld.long 0x00 12.--13. " IN3 ,Extended Input 3" "0,1,2,3" newline bitfld.long 0x00 8.--9. " IN2 ,Extended Input 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input 1" "0,1,2,3" bitfld.long 0x00 0.--1. " IN0 ,Extended Input 0" "0,1,2,3" group.long 0x64++0x3 line.long 0x00 "DAI1_EXTD_MISC2,DAI1 Extended Miscellaneous Control Register 2" bitfld.long 0x00 12.--13. " IN3 ,Extended Input 3" "0,1,2,3" bitfld.long 0x00 8.--9. " IN2 ,Extended Input 2" "0,1,2,3" bitfld.long 0x00 4.--5. " IN1 ,Extended Input 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " IN0 ,Extended Input 0" "0,1,2,3" group.long 0x68++0x3 line.long 0x00 "DAI1_EXTD_PBEN0,DAI1 Extended Pin Buffer Enable Register 0" bitfld.long 0x00 17. " PB05 ,Extended Pin Buffer Enable 5" "0,1" bitfld.long 0x00 13. " PB04 ,Extended Pin Buffer Enable 4" "0,1" bitfld.long 0x00 9. " PB03 ,Extended Pin Buffer Enable 3" "0,1" newline bitfld.long 0x00 5. " PB02 ,Extended Pin Buffer Enable 2" "0,1" bitfld.long 0x00 1. " PB01 ,Extended Pin Buffer Enable 1" "0,1" group.long 0x6C++0x3 line.long 0x00 "DAI1_EXTD_PBEN1,DAI1 Extended Pin Buffer Enable Register 1" bitfld.long 0x00 17. " PB10 ,Extended Pin Buffer Enable 10" "0,1" bitfld.long 0x00 13. " PB09 ,Extended Pin Buffer Enable 9" "0,1" bitfld.long 0x00 9. " PB08 ,Extended Pin Buffer Enable 8" "0,1" newline bitfld.long 0x00 5. " PB07 ,Extended Pin Buffer Enable 7" "0,1" bitfld.long 0x00 1. " PB06 ,Extended Pin Buffer Enable 6" "0,1" group.long 0x70++0x3 line.long 0x00 "DAI1_EXTD_PBEN2,DAI1 Extended Pin Buffer Enable Register 2" bitfld.long 0x00 17. " PB15 ,Extended Pin Buffer Enable 15" "0,1" bitfld.long 0x00 13. " PB14 ,Extended Pin Buffer Enable 14" "0,1" bitfld.long 0x00 9. " PB13 ,Extended Pin Buffer Enable 13" "0,1" newline bitfld.long 0x00 5. " PB12 ,Extended Pin Buffer Enable 12" "0,1" bitfld.long 0x00 1. " PB11 ,Extended Pin Buffer Enable 11" "0,1" group.long 0x74++0x3 line.long 0x00 "DAI1_EXTD_PBEN3,DAI1 Extended Pin Buffer Enable Register 3" bitfld.long 0x00 17. " PB20 ,Extended Pin Buffer Enable 20" "0,1" bitfld.long 0x00 13. " PB19 ,Extended Pin Buffer Enable 19" "0,1" bitfld.long 0x00 9. " PB18 ,Extended Pin Buffer Enable 18" "0,1" newline bitfld.long 0x00 5. " PB17 ,Extended Pin Buffer Enable 17" "0,1" bitfld.long 0x00 1. " PB16 ,Extended Pin Buffer Enable 16" "0,1" group.long 0xC0++0x3 line.long 0x00 "DAI1_CLK0,DAI1 Clock Routing Control Register 0" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Clock 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC4++0x3 line.long 0x00 "DAI1_CLK1,DAI1 Clock Routing Control Register 1" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Clock 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xC8++0x3 line.long 0x00 "DAI1_CLK2,DAI1 Clock Routing Control Register 2" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " IN2 ,Input Clock 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xCC++0x3 line.long 0x00 "DAI1_CLK3,DAI1 Clock Routing Control Register 3" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD0++0x3 line.long 0x00 "DAI1_CLK4,DAI1 Clock Routing Control Register 4" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0xD4++0x3 line.long 0x00 "DAI1_CLK5,DAI1 Clock Routing Control Register 5" bitfld.long 0x00 25.--29. " IN5 ,Input Clock 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Clock 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Clock 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Clock 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Clock 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Clock 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x3 line.long 0x00 "DAI1_DAT0,DAI1 Serial Data Routing Control Register 0" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x104++0x3 line.long 0x00 "DAI1_DAT1,DAI1 Serial Data Routing Control Register 1" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x108++0x3 line.long 0x00 "DAI1_DAT2,DAI1 Serial Data Routing Control Register 2" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10C++0x3 line.long 0x00 "DAI1_DAT3,DAI1 Serial Data Routing Control Register 3" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x110++0x3 line.long 0x00 "DAI1_DAT4,DAI1 Serial Data Routing Control Register 4" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x114++0x3 line.long 0x00 "DAI1_DAT5,DAI1 Serial Data Routing Control Register 5" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x118++0x3 line.long 0x00 "DAI1_DAT6,DAI1 Serial Data Routing Control Register 6" bitfld.long 0x00 24.--29. " IN4 ,Input Data 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " IN3 ,Input Data 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " IN2 ,Input Data 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " IN1 ,Input Data 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " IN0 ,Input Data 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x140++0x3 line.long 0x00 "DAI1_FS0,DAI1 Frame Sync Routing Control Register 0" bitfld.long 0x00 25.--29. " IN5 ,Input Frame Sync 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Frame Sync 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Frame Sync 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Frame Sync 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Frame Sync 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Frame Sync 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x144++0x3 line.long 0x00 "DAI1_FS1,DAI1 Frame Sync Routing Control Register 1" bitfld.long 0x00 25.--29. " IN5 ,Input Frame Sync 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input Frame Sync 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input Frame Sync 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input Frame Sync 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Frame Sync 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Frame Sync 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x148++0x3 line.long 0x00 "DAI1_FS2,DAI1 Frame Sync Routing Control Register 2" bitfld.long 0x00 10.--14. " IN2 ,Input Frame Sync 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Frame Sync 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input Frame Sync 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x150++0x3 line.long 0x00 "DAI1_FS4,DAI1 Frame Sync Routing Control Register 4" bitfld.long 0x00 15.--19. " IN3 ,Input Frame Sync 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " IN2 ,Input Frame Sync 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input Frame Sync 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. " IN0 ,Input Frame Sync 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x180++0x3 line.long 0x00 "DAI1_PIN0,DAI1 Pin Buffer Assignment Register 0" hexmask.long.byte 0x00 21.--27. 1. " PB04 ,Pin Buffer 4 Input" hexmask.long.byte 0x00 14.--20. 1. " PB03 ,Pin Buffer 3 Input" hexmask.long.byte 0x00 7.--13. 1. " PB02 ,Pin Buffer 2 Input" newline hexmask.long.byte 0x00 0.--6. 1. " PB01 ,Pin Buffer 1 Input" group.long 0x184++0x3 line.long 0x00 "DAI1_PIN1,DAI1 Pin Buffer Assignment Register 1" hexmask.long.byte 0x00 21.--27. 1. " PB08 ,Pin Buffer 8 Input" hexmask.long.byte 0x00 14.--20. 1. " PB07 ,Pin Buffer 7 Input" hexmask.long.byte 0x00 7.--13. 1. " PB06 ,Pin Buffer 6 Input" newline hexmask.long.byte 0x00 0.--6. 1. " PB05 ,Pin Buffer 5 Input" group.long 0x188++0x3 line.long 0x00 "DAI1_PIN2,DAI1 Pin Buffer Assignment Register 2" hexmask.long.byte 0x00 21.--27. 1. " PB12 ,Pin Buffer 12 Input" hexmask.long.byte 0x00 14.--20. 1. " PB11 ,Pin Buffer 11 Input" hexmask.long.byte 0x00 7.--13. 1. " PB10 ,Pin Buffer 10 Input" newline hexmask.long.byte 0x00 0.--6. 1. " PB09 ,Pin Buffer 9 Input" group.long 0x18C++0x3 line.long 0x00 "DAI1_PIN3,DAI1 Pin Buffer Assignment Register 3" hexmask.long.byte 0x00 21.--27. 1. " PB16 ,Pin Buffer 16 Input" hexmask.long.byte 0x00 14.--20. 1. " PB15 ,Pin Buffer 15 Input" hexmask.long.byte 0x00 7.--13. 1. " PB14 ,Pin Buffer 14 Input" newline hexmask.long.byte 0x00 0.--6. 1. " PB13 ,Pin Buffer 13 Input" group.long 0x190++0x3 line.long 0x00 "DAI1_PIN4,DAI1 Pin Buffer Assignment Register 4" bitfld.long 0x00 29. " INV20 ,Pin Buffer 20 Invert" "0,1" bitfld.long 0x00 28. " INV19 ,Pin Buffer 19 Invert" "0,1" hexmask.long.byte 0x00 21.--27. 1. " PB20 ,Pin Buffer 20 Input" newline hexmask.long.byte 0x00 14.--20. 1. " PB19 ,Pin Buffer 19 Input" hexmask.long.byte 0x00 7.--13. 1. " PB18 ,Pin Buffer 18 Input" hexmask.long.byte 0x00 0.--6. 1. " PB17 ,Pin Buffer 17 Input" group.long 0x1C0++0x3 line.long 0x00 "DAI1_MISC0,DAI1 Miscellaneous Control Register 0" bitfld.long 0x00 31. " INV11 ,Invert 11" "0,1" bitfld.long 0x00 30. " INV10 ,Invert 10" "0,1" bitfld.long 0x00 25.--29. " IN11 ,Input 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 20.--24. " IN10 ,Input 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN9 ,Input 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " IN8 ,Input 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5.--9. " IN7 ,Input 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN6 ,Input 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C4++0x3 line.long 0x00 "DAI1_MISC1,DAI1 Miscellaneous Control Register 1" bitfld.long 0x00 25.--29. " IN5 ,Input 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20.--24. " IN4 ,Input 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 15.--19. " IN3 ,Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 10.--14. " IN2 ,Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " IN0 ,Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C8++0x3 line.long 0x00 "DAI1_MISC2,DAI1 Miscellaneous Control Register 1" bitfld.long 0x00 15.--19. " IN3 ,Input 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10.--14. " IN2 ,Input 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5.--9. " IN1 ,Input 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 0.--4. " IN0 ,Input 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1E0++0x3 line.long 0x00 "DAI1_PBEN0,DAI1 Pin Buffer Enable Register 0" bitfld.long 0x00 24.--29. " PB05 ,Pin Buffer Enable 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " PB04 ,Pin Buffer Enable 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " PB03 ,Pin Buffer Enable 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " PB02 ,Pin Buffer Enable 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PB01 ,Pin Buffer Enable 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E4++0x3 line.long 0x00 "DAI1_PBEN1,DAI1 Pin Buffer Enable Register 1" bitfld.long 0x00 24.--29. " PB10 ,Pin Buffer Enable 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " PB09 ,Pin Buffer Enable 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " PB08 ,Pin Buffer Enable 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " PB07 ,Pin Buffer Enable 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PB06 ,Pin Buffer Enable 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1E8++0x3 line.long 0x00 "DAI1_PBEN2,DAI1 Pin Buffer Enable Register 2" bitfld.long 0x00 24.--29. " PB15 ,Pin Buffer Enable 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " PB14 ,Pin Buffer Enable 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " PB13 ,Pin Buffer Enable 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " PB12 ,Pin Buffer Enable 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PB11 ,Pin Buffer Enable 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1EC++0x3 line.long 0x00 "DAI1_PBEN3,DAI1 Pin Buffer Enable Register 3" bitfld.long 0x00 24.--29. " PB20 ,Pin Buffer Enable 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 18.--23. " PB19 ,Pin Buffer Enable 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--17. " PB18 ,Pin Buffer Enable 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--11. " PB17 ,Pin Buffer Enable 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " PB16 ,Pin Buffer Enable 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x3 line.long 0x00 "DAI1_IMSK_FE,DAI1 Falling-Edge Interrupt Mask Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x204++0x3 line.long 0x00 "DAI1_IMSK_RE,DAI1 Rising-Edge Interrupt Mask Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x210++0x3 line.long 0x00 "DAI1_IMSK_PRI,DAI1 Core Interrupt Priority Assignment Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receiver Non-Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x220++0x3 line.long 0x00 "DAI1_IRPTL_H,DAI1 High Priority Interrupt Latch Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change Indication" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x224++0x3 line.long 0x00 "DAI1_IRPTL_L,DAI1 Low Priority Interrupt Latch Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x230++0x3 line.long 0x00 "DAI1_IRPTL_HS,DAI1 Shadow High Priority Interrupt Latch Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receive Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x234++0x3 line.long 0x00 "DAI1_IRPTL_LS,DAI1 Shadow Low Priority Interrupt Latch Register" bitfld.long 0x00 31. " MISCINT9 ,Miscellaneous Interrupt 9" "0,1" bitfld.long 0x00 30. " MISCINT8 ,Miscellaneous Interrupt 8" "0,1" bitfld.long 0x00 29. " MISCINT7 ,Miscellaneous Interrupt 7" "0,1" newline bitfld.long 0x00 28. " MISCINT6 ,Miscellaneous Interrupt 6" "0,1" bitfld.long 0x00 27. " MISCINT5 ,Miscellaneous Interrupt 5" "0,1" bitfld.long 0x00 26. " MISCINT4 ,Miscellaneous Interrupt 4" "0,1" newline bitfld.long 0x00 25. " MISCINT3 ,Miscellaneous Interrupt 3" "0,1" bitfld.long 0x00 24. " MISCINT2 ,Miscellaneous Interrupt 2" "0,1" bitfld.long 0x00 23. " MISCINT1 ,Miscellaneous Interrupt 1" "0,1" newline bitfld.long 0x00 22. " MISCINT0 ,Miscellaneous Interrupt 0" "0,1" bitfld.long 0x00 21. " SRC3MUTE ,SRC3 Mute" "0,1" bitfld.long 0x00 20. " SRC2MUTE ,SRC2 Mute" "0,1" newline bitfld.long 0x00 19. " SRC1MUTE ,SRC1 Mute" "0,1" bitfld.long 0x00 18. " SRC0MUTE ,SRC0 Mute" "0,1" bitfld.long 0x00 7. " RXCHSCH ,SPDIF Rx Channel Status Change" "0,1" newline bitfld.long 0x00 4. " RXNONAUDIO ,Receiver Non Audio" "0,1" bitfld.long 0x00 2. " RXLOSSOFLOCK ,Receive Emphasis Loss of Lock" "0,1" bitfld.long 0x00 1. " RXLOCK ,Receive Error Lock" "0,1" newline bitfld.long 0x00 0. " RXVALID ,Receive Valid" "0,1" group.long 0x2E4++0x3 line.long 0x00 "DAI1_PIN_STAT,DAI1 Pin Status Register" bitfld.long 0x00 19. " PB20 ,Pin Buffer 20 Status" "0,1" bitfld.long 0x00 18. " PB19 ,Pin Buffer 19 Status" "0,1" bitfld.long 0x00 17. " PB18 ,Pin Buffer 18 Status" "0,1" newline bitfld.long 0x00 16. " PB17 ,Pin Buffer 17 Status" "0,1" bitfld.long 0x00 15. " PB16 ,Pin Buffer 16 Status" "0,1" bitfld.long 0x00 14. " PB15 ,Pin Buffer 15 Status" "0,1" newline bitfld.long 0x00 13. " PB14 ,Pin Buffer 14 Status" "0,1" bitfld.long 0x00 12. " PB13 ,Pin Buffer 13 Status" "0,1" bitfld.long 0x00 11. " PB12 ,Pin Buffer 12 Status" "0,1" newline bitfld.long 0x00 10. " PB11 ,Pin Buffer 11 Status" "0,1" bitfld.long 0x00 9. " PB10 ,Pin Buffer 10 Status" "0,1" bitfld.long 0x00 8. " PB09 ,Pin Buffer 09 Status" "0,1" newline bitfld.long 0x00 7. " PB08 ,Pin Buffer 08 Status" "0,1" bitfld.long 0x00 6. " PB07 ,Pin Buffer 07 Status" "0,1" bitfld.long 0x00 5. " PB06 ,Pin Buffer 06 Status" "0,1" newline bitfld.long 0x00 4. " PB05 ,Pin Buffer 05 Status" "0,1" bitfld.long 0x00 3. " PB04 ,Pin Buffer 04 Status" "0,1" bitfld.long 0x00 2. " PB03 ,Pin Buffer 03 Status" "0,1" newline bitfld.long 0x00 1. " PB02 ,Pin Buffer 02 Status" "0,1" bitfld.long 0x00 0. " PB01 ,Pin Buffer 01 Status" "0,1" group.long 0x2E8++0x3 line.long 0x00 "DAI1_GBL_SP_EN,DAI1 Global SPORT Enable Register" bitfld.long 0x00 19. " GBL_SP3B_SC_EN ,SPORT3 B Secondary Channel Select" "0,1" bitfld.long 0x00 18. " GBL_SP3B_PC_EN ,SPORT3 B Primary Channel Select" "0,1" bitfld.long 0x00 17. " GBL_SP3A_SC_EN ,SPORT3 A Secondary Channel Select" "0,1" newline bitfld.long 0x00 16. " GBL_SP3A_PC_EN ,SPORT3 A Primary Channel Select" "0,1" bitfld.long 0x00 15. " GBL_SP2B_SC_EN ,SPORT2 B Secondary Channel Select" "0,1" bitfld.long 0x00 14. " GBL_SP2B_PC_EN ,SPORT2 B Primary Channel Select" "0,1" newline bitfld.long 0x00 13. " GBL_SP2A_SC_EN ,SPORT2 A Secondary Channel Select" "0,1" bitfld.long 0x00 12. " GBL_SP2A_PC_EN ,SPORT2 A Primary Channel Select" "0,1" bitfld.long 0x00 11. " GBL_SP1B_SC_EN ,SPORT1 B Secondary Channel Select" "0,1" newline bitfld.long 0x00 10. " GBL_SP1B_PC_EN ,SPORT1 B Primary Channel Select" "0,1" bitfld.long 0x00 9. " GBL_SP1A_SC_EN ,SPORT1 A Secondary Channel Select" "0,1" bitfld.long 0x00 8. " GBL_SP1A_PC_EN ,SPORT1 A Primary Channel Select" "0,1" newline bitfld.long 0x00 7. " GBL_SP0B_SC_EN ,SPORT0 B Secondary Channel Select" "0,1" bitfld.long 0x00 6. " GBL_SP0B_PC_EN ,SPORT0 B Primary Channel Select" "0,1" bitfld.long 0x00 5. " GBL_SP0A_SC_EN ,SPORT0 A Secondary Channel Select" "0,1" newline bitfld.long 0x00 4. " GBL_SP0A_PC_EN ,SPORT0 A Primary Channel Select" "0,1" bitfld.long 0x00 3. " GBL_SPEN_GRP1 ,Group 1 SPORT Subgroup Select" "0,1" bitfld.long 0x00 2. " GBL_SPEN_GRP0 ,Group 0 SPORT Subgroup Select" "0,1" newline bitfld.long 0x00 1. " GBL_SPEN_DAIX ,DAI SPORTs Enable" "0,1" bitfld.long 0x00 0. " GBL_SP_EN ,Global SPORTs Enable" "0,1" group.long 0x2EC++0x3 line.long 0x00 "DAI1_GBL_INT_EN,DAI1 Global SPORT Interrupt Grouping Register" bitfld.long 0x00 21. " GRP1_ERR_EN ,Enable Error For Group1" "0,1" bitfld.long 0x00 20. " GRP0_ERR_EN ,Enable Error For Group0" "0,1" bitfld.long 0x00 19. " GRP1_TRG_EN ,Group 1 Trigger Enable" "0,1" newline bitfld.long 0x00 18. " GRP0_TRG_EN ,Group 0 Trigger Enable" "0,1" bitfld.long 0x00 17. " GRP1_INT_EN ,Group 1 Interrupt Enable" "0,1" bitfld.long 0x00 16. " GRP0_INT_EN ,Group 0 Interrupt Enable" "0,1" newline bitfld.long 0x00 15. " GRP1_SP3BINT_EN ,SP3B Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 14. " GRP1_SP3AINT_EN ,SP3A Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 13. " GRP1_SP2BINT_EN ,SP2B Interrupt/Trigger Group 1 Enable" "0,1" newline bitfld.long 0x00 12. " GRP1_SP2AINT_EN ,SP2A Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 11. " GRP1_SP1BINT_EN ,SP1B Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 10. " GRP1_SP1AINT_EN ,SP1A Interrupt/Trigger Group 1 Enable" "0,1" newline bitfld.long 0x00 9. " GRP1_SP0BINT_EN ,SP0B Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 8. " GRP1_SP0AINT_EN ,SP0A Interrupt/Trigger Group 1 Enable" "0,1" bitfld.long 0x00 7. " GRP0_SP3BINT_EN ,SP3B Interrupt/Trigger Group 0 Enable" "0,1" newline bitfld.long 0x00 6. " GRP0_SP3AINT_EN ,SP3A Interrupt/Trigger Group 0 Enable" "0,1" bitfld.long 0x00 5. " GRP0_SP2BINT_EN ,SP2B Interrupt/Trigger Group 0 Enable" "0,1" bitfld.long 0x00 4. " GRP0_SP2AINT_EN ,SP2A Interrupt/Trigger Group 0 Enable" "0,1" newline bitfld.long 0x00 3. " GRP0_SP1BINT_EN ,SP1B Interrupt/Trigger Group 0 Enable" "0,1" bitfld.long 0x00 2. " GRP0_SP1AINT_EN ,SP1A Interrupt/Trigger Group 0 Enable" "0,1" bitfld.long 0x00 1. " GRP0_SP0BINT_EN ,SP0B Interrupt/Trigger Group 0 Enable" "0,1" newline bitfld.long 0x00 0. " GRP0_SP0AINT_EN ,SP0A Interrupt/Trigger Group 0 Enable" "0,1" tree.end tree.end tree "DAPROM0" base ad:0x31100000 width 20. group.long 0x0++0x3 line.long 0x00 "DAPROM0_ROMENTRY00,DAPROM0 ROM Entry 00" group.long 0x4++0x3 line.long 0x00 "DAPROM0_ROMENTRY01,DAPROM0 ROM Entry 01" group.long 0x8++0x3 line.long 0x00 "DAPROM0_ROMENTRY02,DAPROM0 ROM Entry 02" group.long 0xC++0x3 line.long 0x00 "DAPROM0_ROMENTRY03,DAPROM0 ROM Entry 03" group.long 0x10++0x3 line.long 0x00 "DAPROM0_ROMENTRY04,DAPROM0 ROM Entry 04" group.long 0x14++0x3 line.long 0x00 "DAPROM0_ROMENTRY05,DAPROM0 ROM Entry 05" group.long 0x18++0x3 line.long 0x00 "DAPROM0_ROMENTRY06,DAPROM0 ROM Entry 06" group.long 0x1C++0x3 line.long 0x00 "DAPROM0_ROMENTRY07,DAPROM0 ROM Entry 07" group.long 0x20++0x3 line.long 0x00 "DAPROM0_ROMENTRY08,DAPROM0 ROM Entry 08" group.long 0x24++0x3 line.long 0x00 "DAPROM0_ROMENTRY09,DAPROM0 ROM Entry 09" group.long 0x28++0x3 line.long 0x00 "DAPROM0_ROMENTRY10,DAPROM0 ROM Entry 10" group.long 0x2C++0x3 line.long 0x00 "DAPROM0_ROMENTRY11,DAPROM0 ROM Entry 11" group.long 0x30++0x3 line.long 0x00 "DAPROM0_ROMENTRY12,DAPROM0 ROM Entry 12" group.long 0x34++0x3 line.long 0x00 "DAPROM0_ROMENTRY13,DAPROM0 ROM Entry 13" tree.end tree "DMA (Direct Memory Access)" tree "DMA0" base ad:0x31022000 width 17. group.long 0x0++0x3 line.long 0x00 "DMA0_DSCPTR_NXT,DMA0 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA0_ADDRSTART,DMA0 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA0_CFG,DMA0 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA0_XCNT,DMA0 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA0_XMOD,DMA0 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA0_YCNT,DMA0 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA0_YMOD,DMA0 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA0_DSCPTR_CUR,DMA0 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA0_DSCPTR_PRV,DMA0 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA0_ADDR_CUR,DMA0 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA0_STAT,DMA0 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA0_XCNT_CUR,DMA0 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA0_YCNT_CUR,DMA0 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA0_BWLCNT,DMA0 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA0_BWLCNT_CUR,DMA0 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA0_BWMCNT,DMA0 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA0_BWMCNT_CUR,DMA0 Bandwidth Monitor Count Current Register" tree.end tree "DMA1" base ad:0x31022080 width 17. group.long 0x0++0x3 line.long 0x00 "DMA1_DSCPTR_NXT,DMA1 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA1_ADDRSTART,DMA1 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA1_CFG,DMA1 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA1_XCNT,DMA1 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA1_XMOD,DMA1 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA1_YCNT,DMA1 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA1_YMOD,DMA1 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA1_DSCPTR_CUR,DMA1 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA1_DSCPTR_PRV,DMA1 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA1_ADDR_CUR,DMA1 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA1_STAT,DMA1 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA1_XCNT_CUR,DMA1 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA1_YCNT_CUR,DMA1 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA1_BWLCNT,DMA1 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA1_BWLCNT_CUR,DMA1 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA1_BWMCNT,DMA1 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA1_BWMCNT_CUR,DMA1 Bandwidth Monitor Count Current Register" tree.end tree "DMA10" base ad:0x31023000 width 18. group.long 0x0++0x3 line.long 0x00 "DMA10_DSCPTR_NXT,DMA10 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA10_ADDRSTART,DMA10 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA10_CFG,DMA10 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA10_XCNT,DMA10 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA10_XMOD,DMA10 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA10_YCNT,DMA10 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA10_YMOD,DMA10 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA10_DSCPTR_CUR,DMA10 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA10_DSCPTR_PRV,DMA10 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA10_ADDR_CUR,DMA10 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA10_STAT,DMA10 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA10_XCNT_CUR,DMA10 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA10_YCNT_CUR,DMA10 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA10_BWLCNT,DMA10 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA10_BWLCNT_CUR,DMA10 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA10_BWMCNT,DMA10 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA10_BWMCNT_CUR,DMA10 Bandwidth Monitor Count Current Register" tree.end tree "DMA11" base ad:0x31023080 width 18. group.long 0x0++0x3 line.long 0x00 "DMA11_DSCPTR_NXT,DMA11 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA11_ADDRSTART,DMA11 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA11_CFG,DMA11 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA11_XCNT,DMA11 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA11_XMOD,DMA11 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA11_YCNT,DMA11 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA11_YMOD,DMA11 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA11_DSCPTR_CUR,DMA11 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA11_DSCPTR_PRV,DMA11 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA11_ADDR_CUR,DMA11 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA11_STAT,DMA11 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA11_XCNT_CUR,DMA11 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA11_YCNT_CUR,DMA11 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA11_BWLCNT,DMA11 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA11_BWLCNT_CUR,DMA11 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA11_BWMCNT,DMA11 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA11_BWMCNT_CUR,DMA11 Bandwidth Monitor Count Current Register" tree.end tree "DMA12" base ad:0x31023100 width 18. group.long 0x0++0x3 line.long 0x00 "DMA12_DSCPTR_NXT,DMA12 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA12_ADDRSTART,DMA12 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA12_CFG,DMA12 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA12_XCNT,DMA12 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA12_XMOD,DMA12 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA12_YCNT,DMA12 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA12_YMOD,DMA12 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA12_DSCPTR_CUR,DMA12 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA12_DSCPTR_PRV,DMA12 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA12_ADDR_CUR,DMA12 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA12_STAT,DMA12 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA12_XCNT_CUR,DMA12 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA12_YCNT_CUR,DMA12 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA12_BWLCNT,DMA12 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA12_BWLCNT_CUR,DMA12 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA12_BWMCNT,DMA12 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA12_BWMCNT_CUR,DMA12 Bandwidth Monitor Count Current Register" tree.end tree "DMA13" base ad:0x31023180 width 18. group.long 0x0++0x3 line.long 0x00 "DMA13_DSCPTR_NXT,DMA13 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA13_ADDRSTART,DMA13 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA13_CFG,DMA13 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA13_XCNT,DMA13 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA13_XMOD,DMA13 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA13_YCNT,DMA13 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA13_YMOD,DMA13 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA13_DSCPTR_CUR,DMA13 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA13_DSCPTR_PRV,DMA13 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA13_ADDR_CUR,DMA13 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA13_STAT,DMA13 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA13_XCNT_CUR,DMA13 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA13_YCNT_CUR,DMA13 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA13_BWLCNT,DMA13 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA13_BWLCNT_CUR,DMA13 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA13_BWMCNT,DMA13 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA13_BWMCNT_CUR,DMA13 Bandwidth Monitor Count Current Register" tree.end tree "DMA14" base ad:0x31023200 width 18. group.long 0x0++0x3 line.long 0x00 "DMA14_DSCPTR_NXT,DMA14 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA14_ADDRSTART,DMA14 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA14_CFG,DMA14 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA14_XCNT,DMA14 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA14_XMOD,DMA14 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA14_YCNT,DMA14 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA14_YMOD,DMA14 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA14_DSCPTR_CUR,DMA14 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA14_DSCPTR_PRV,DMA14 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA14_ADDR_CUR,DMA14 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA14_STAT,DMA14 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA14_XCNT_CUR,DMA14 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA14_YCNT_CUR,DMA14 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA14_BWLCNT,DMA14 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA14_BWLCNT_CUR,DMA14 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA14_BWMCNT,DMA14 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA14_BWMCNT_CUR,DMA14 Bandwidth Monitor Count Current Register" tree.end tree "DMA15" base ad:0x31023280 width 18. group.long 0x0++0x3 line.long 0x00 "DMA15_DSCPTR_NXT,DMA15 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA15_ADDRSTART,DMA15 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA15_CFG,DMA15 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA15_XCNT,DMA15 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA15_XMOD,DMA15 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA15_YCNT,DMA15 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA15_YMOD,DMA15 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA15_DSCPTR_CUR,DMA15 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA15_DSCPTR_PRV,DMA15 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA15_ADDR_CUR,DMA15 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA15_STAT,DMA15 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA15_XCNT_CUR,DMA15 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA15_YCNT_CUR,DMA15 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA15_BWLCNT,DMA15 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA15_BWLCNT_CUR,DMA15 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA15_BWMCNT,DMA15 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA15_BWMCNT_CUR,DMA15 Bandwidth Monitor Count Current Register" tree.end tree "DMA16" base ad:0x31023300 width 18. group.long 0x0++0x3 line.long 0x00 "DMA16_DSCPTR_NXT,DMA16 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA16_ADDRSTART,DMA16 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA16_CFG,DMA16 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA16_XCNT,DMA16 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA16_XMOD,DMA16 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA16_YCNT,DMA16 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA16_YMOD,DMA16 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA16_DSCPTR_CUR,DMA16 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA16_DSCPTR_PRV,DMA16 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA16_ADDR_CUR,DMA16 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA16_STAT,DMA16 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA16_XCNT_CUR,DMA16 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA16_YCNT_CUR,DMA16 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA16_BWLCNT,DMA16 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA16_BWLCNT_CUR,DMA16 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA16_BWMCNT,DMA16 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA16_BWMCNT_CUR,DMA16 Bandwidth Monitor Count Current Register" tree.end tree "DMA17" base ad:0x31023380 width 18. group.long 0x0++0x3 line.long 0x00 "DMA17_DSCPTR_NXT,DMA17 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA17_ADDRSTART,DMA17 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA17_CFG,DMA17 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA17_XCNT,DMA17 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA17_XMOD,DMA17 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA17_YCNT,DMA17 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA17_YMOD,DMA17 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA17_DSCPTR_CUR,DMA17 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA17_DSCPTR_PRV,DMA17 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA17_ADDR_CUR,DMA17 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA17_STAT,DMA17 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA17_XCNT_CUR,DMA17 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA17_YCNT_CUR,DMA17 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA17_BWLCNT,DMA17 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA17_BWLCNT_CUR,DMA17 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA17_BWMCNT,DMA17 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA17_BWMCNT_CUR,DMA17 Bandwidth Monitor Count Current Register" tree.end tree "DMA18" base ad:0x310A7100 width 18. group.long 0x0++0x3 line.long 0x00 "DMA18_DSCPTR_NXT,DMA18 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA18_ADDRSTART,DMA18 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA18_CFG,DMA18 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA18_XCNT,DMA18 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA18_XMOD,DMA18 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA18_YCNT,DMA18 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA18_YMOD,DMA18 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA18_DSCPTR_CUR,DMA18 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA18_DSCPTR_PRV,DMA18 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA18_ADDR_CUR,DMA18 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA18_STAT,DMA18 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA18_XCNT_CUR,DMA18 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA18_YCNT_CUR,DMA18 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA18_BWLCNT,DMA18 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA18_BWLCNT_CUR,DMA18 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA18_BWMCNT,DMA18 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA18_BWMCNT_CUR,DMA18 Bandwidth Monitor Count Current Register" tree.end tree "DMA19" base ad:0x310A7180 width 18. group.long 0x0++0x3 line.long 0x00 "DMA19_DSCPTR_NXT,DMA19 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA19_ADDRSTART,DMA19 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA19_CFG,DMA19 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA19_XCNT,DMA19 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA19_XMOD,DMA19 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA19_YCNT,DMA19 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA19_YMOD,DMA19 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA19_DSCPTR_CUR,DMA19 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA19_DSCPTR_PRV,DMA19 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA19_ADDR_CUR,DMA19 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA19_STAT,DMA19 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA19_XCNT_CUR,DMA19 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA19_YCNT_CUR,DMA19 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA19_BWLCNT,DMA19 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA19_BWLCNT_CUR,DMA19 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA19_BWMCNT,DMA19 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA19_BWMCNT_CUR,DMA19 Bandwidth Monitor Count Current Register" tree.end tree "DMA2" base ad:0x31022100 width 17. group.long 0x0++0x3 line.long 0x00 "DMA2_DSCPTR_NXT,DMA2 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA2_ADDRSTART,DMA2 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA2_CFG,DMA2 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA2_XCNT,DMA2 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA2_XMOD,DMA2 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA2_YCNT,DMA2 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA2_YMOD,DMA2 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA2_DSCPTR_CUR,DMA2 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA2_DSCPTR_PRV,DMA2 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA2_ADDR_CUR,DMA2 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA2_STAT,DMA2 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA2_XCNT_CUR,DMA2 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA2_YCNT_CUR,DMA2 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA2_BWLCNT,DMA2 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA2_BWLCNT_CUR,DMA2 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA2_BWMCNT,DMA2 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA2_BWMCNT_CUR,DMA2 Bandwidth Monitor Count Current Register" tree.end tree "DMA20" base ad:0x31026080 width 18. group.long 0x0++0x3 line.long 0x00 "DMA20_DSCPTR_NXT,DMA20 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA20_ADDRSTART,DMA20 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA20_CFG,DMA20 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA20_XCNT,DMA20 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA20_XMOD,DMA20 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA20_YCNT,DMA20 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA20_YMOD,DMA20 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA20_DSCPTR_CUR,DMA20 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA20_DSCPTR_PRV,DMA20 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA20_ADDR_CUR,DMA20 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA20_STAT,DMA20 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA20_XCNT_CUR,DMA20 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA20_YCNT_CUR,DMA20 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA20_BWLCNT,DMA20 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA20_BWLCNT_CUR,DMA20 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA20_BWMCNT,DMA20 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA20_BWMCNT_CUR,DMA20 Bandwidth Monitor Count Current Register" tree.end tree "DMA21" base ad:0x31026000 width 18. group.long 0x0++0x3 line.long 0x00 "DMA21_DSCPTR_NXT,DMA21 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA21_ADDRSTART,DMA21 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA21_CFG,DMA21 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA21_XCNT,DMA21 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA21_XMOD,DMA21 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA21_YCNT,DMA21 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA21_YMOD,DMA21 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA21_DSCPTR_CUR,DMA21 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA21_DSCPTR_PRV,DMA21 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA21_ADDR_CUR,DMA21 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA21_STAT,DMA21 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA21_XCNT_CUR,DMA21 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA21_YCNT_CUR,DMA21 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA21_BWLCNT,DMA21 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA21_BWLCNT_CUR,DMA21 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA21_BWMCNT,DMA21 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA21_BWMCNT_CUR,DMA21 Bandwidth Monitor Count Current Register" tree.end tree "DMA22" base ad:0x3102D000 width 18. group.long 0x0++0x3 line.long 0x00 "DMA22_DSCPTR_NXT,DMA22 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA22_ADDRSTART,DMA22 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA22_CFG,DMA22 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA22_XCNT,DMA22 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA22_XMOD,DMA22 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA22_YCNT,DMA22 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA22_YMOD,DMA22 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA22_DSCPTR_CUR,DMA22 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA22_DSCPTR_PRV,DMA22 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA22_ADDR_CUR,DMA22 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA22_STAT,DMA22 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA22_XCNT_CUR,DMA22 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA22_YCNT_CUR,DMA22 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA22_BWLCNT,DMA22 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA22_BWLCNT_CUR,DMA22 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA22_BWMCNT,DMA22 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA22_BWMCNT_CUR,DMA22 Bandwidth Monitor Count Current Register" tree.end tree "DMA23" base ad:0x3102D080 width 18. group.long 0x0++0x3 line.long 0x00 "DMA23_DSCPTR_NXT,DMA23 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA23_ADDRSTART,DMA23 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA23_CFG,DMA23 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA23_XCNT,DMA23 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA23_XMOD,DMA23 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA23_YCNT,DMA23 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA23_YMOD,DMA23 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA23_DSCPTR_CUR,DMA23 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA23_DSCPTR_PRV,DMA23 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA23_ADDR_CUR,DMA23 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA23_STAT,DMA23 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA23_XCNT_CUR,DMA23 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA23_YCNT_CUR,DMA23 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA23_BWLCNT,DMA23 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA23_BWLCNT_CUR,DMA23 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA23_BWMCNT,DMA23 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA23_BWMCNT_CUR,DMA23 Bandwidth Monitor Count Current Register" tree.end tree "DMA24" base ad:0x3102D100 width 18. group.long 0x0++0x3 line.long 0x00 "DMA24_DSCPTR_NXT,DMA24 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA24_ADDRSTART,DMA24 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA24_CFG,DMA24 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA24_XCNT,DMA24 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA24_XMOD,DMA24 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA24_YCNT,DMA24 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA24_YMOD,DMA24 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA24_DSCPTR_CUR,DMA24 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA24_DSCPTR_PRV,DMA24 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA24_ADDR_CUR,DMA24 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA24_STAT,DMA24 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA24_XCNT_CUR,DMA24 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA24_YCNT_CUR,DMA24 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA24_BWLCNT,DMA24 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA24_BWLCNT_CUR,DMA24 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA24_BWMCNT,DMA24 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA24_BWMCNT_CUR,DMA24 Bandwidth Monitor Count Current Register" tree.end tree "DMA25" base ad:0x3102D180 width 18. group.long 0x0++0x3 line.long 0x00 "DMA25_DSCPTR_NXT,DMA25 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA25_ADDRSTART,DMA25 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA25_CFG,DMA25 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA25_XCNT,DMA25 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA25_XMOD,DMA25 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA25_YCNT,DMA25 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA25_YMOD,DMA25 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA25_DSCPTR_CUR,DMA25 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA25_DSCPTR_PRV,DMA25 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA25_ADDR_CUR,DMA25 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA25_STAT,DMA25 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA25_XCNT_CUR,DMA25 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA25_YCNT_CUR,DMA25 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA25_BWLCNT,DMA25 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA25_BWLCNT_CUR,DMA25 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA25_BWMCNT,DMA25 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA25_BWMCNT_CUR,DMA25 Bandwidth Monitor Count Current Register" tree.end tree "DMA26" base ad:0x3102D200 width 18. group.long 0x0++0x3 line.long 0x00 "DMA26_DSCPTR_NXT,DMA26 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA26_ADDRSTART,DMA26 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA26_CFG,DMA26 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA26_XCNT,DMA26 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA26_XMOD,DMA26 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA26_YCNT,DMA26 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA26_YMOD,DMA26 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA26_DSCPTR_CUR,DMA26 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA26_DSCPTR_PRV,DMA26 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA26_ADDR_CUR,DMA26 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA26_STAT,DMA26 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA26_XCNT_CUR,DMA26 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA26_YCNT_CUR,DMA26 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA26_BWLCNT,DMA26 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA26_BWLCNT_CUR,DMA26 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA26_BWMCNT,DMA26 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA26_BWMCNT_CUR,DMA26 Bandwidth Monitor Count Current Register" tree.end tree "DMA27" base ad:0x3102D280 width 18. group.long 0x0++0x3 line.long 0x00 "DMA27_DSCPTR_NXT,DMA27 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA27_ADDRSTART,DMA27 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA27_CFG,DMA27 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA27_XCNT,DMA27 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA27_XMOD,DMA27 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA27_YCNT,DMA27 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA27_YMOD,DMA27 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA27_DSCPTR_CUR,DMA27 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA27_DSCPTR_PRV,DMA27 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA27_ADDR_CUR,DMA27 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA27_STAT,DMA27 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA27_XCNT_CUR,DMA27 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA27_YCNT_CUR,DMA27 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA27_BWLCNT,DMA27 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA27_BWLCNT_CUR,DMA27 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA27_BWMCNT,DMA27 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA27_BWMCNT_CUR,DMA27 Bandwidth Monitor Count Current Register" tree.end tree "DMA28" base ad:0x31026400 width 18. group.long 0x0++0x3 line.long 0x00 "DMA28_DSCPTR_NXT,DMA28 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA28_ADDRSTART,DMA28 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA28_CFG,DMA28 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA28_XCNT,DMA28 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA28_XMOD,DMA28 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA28_YCNT,DMA28 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA28_YMOD,DMA28 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA28_DSCPTR_CUR,DMA28 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA28_DSCPTR_PRV,DMA28 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA28_ADDR_CUR,DMA28 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA28_STAT,DMA28 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA28_XCNT_CUR,DMA28 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA28_YCNT_CUR,DMA28 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA28_BWLCNT,DMA28 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA28_BWLCNT_CUR,DMA28 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA28_BWMCNT,DMA28 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA28_BWMCNT_CUR,DMA28 Bandwidth Monitor Count Current Register" tree.end tree "DMA29" base ad:0x31026480 width 18. group.long 0x0++0x3 line.long 0x00 "DMA29_DSCPTR_NXT,DMA29 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA29_ADDRSTART,DMA29 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA29_CFG,DMA29 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA29_XCNT,DMA29 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA29_XMOD,DMA29 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA29_YCNT,DMA29 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA29_YMOD,DMA29 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA29_DSCPTR_CUR,DMA29 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA29_DSCPTR_PRV,DMA29 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA29_ADDR_CUR,DMA29 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA29_STAT,DMA29 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA29_XCNT_CUR,DMA29 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA29_YCNT_CUR,DMA29 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA29_BWLCNT,DMA29 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA29_BWLCNT_CUR,DMA29 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA29_BWMCNT,DMA29 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA29_BWMCNT_CUR,DMA29 Bandwidth Monitor Count Current Register" tree.end tree "DMA3" base ad:0x31022180 width 17. group.long 0x0++0x3 line.long 0x00 "DMA3_DSCPTR_NXT,DMA3 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA3_ADDRSTART,DMA3 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA3_CFG,DMA3 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA3_XCNT,DMA3 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA3_XMOD,DMA3 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA3_YCNT,DMA3 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA3_YMOD,DMA3 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA3_DSCPTR_CUR,DMA3 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA3_DSCPTR_PRV,DMA3 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA3_ADDR_CUR,DMA3 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA3_STAT,DMA3 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA3_XCNT_CUR,DMA3 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA3_YCNT_CUR,DMA3 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA3_BWLCNT,DMA3 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA3_BWLCNT_CUR,DMA3 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA3_BWMCNT,DMA3 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA3_BWMCNT_CUR,DMA3 Bandwidth Monitor Count Current Register" tree.end tree "DMA30" base ad:0x30FFF000 width 18. group.long 0x0++0x3 line.long 0x00 "DMA30_DSCPTR_NXT,DMA30 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA30_ADDRSTART,DMA30 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA30_CFG,DMA30 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA30_XCNT,DMA30 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA30_XMOD,DMA30 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA30_YCNT,DMA30 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA30_YMOD,DMA30 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA30_DSCPTR_CUR,DMA30 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA30_DSCPTR_PRV,DMA30 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA30_ADDR_CUR,DMA30 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA30_STAT,DMA30 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA30_XCNT_CUR,DMA30 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA30_YCNT_CUR,DMA30 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA30_BWLCNT,DMA30 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA30_BWLCNT_CUR,DMA30 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA30_BWMCNT,DMA30 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA30_BWMCNT_CUR,DMA30 Bandwidth Monitor Count Current Register" tree.end tree "DMA34" base ad:0x31026180 width 18. group.long 0x0++0x3 line.long 0x00 "DMA34_DSCPTR_NXT,DMA34 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA34_ADDRSTART,DMA34 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA34_CFG,DMA34 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA34_XCNT,DMA34 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA34_XMOD,DMA34 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA34_YCNT,DMA34 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA34_YMOD,DMA34 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA34_DSCPTR_CUR,DMA34 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA34_DSCPTR_PRV,DMA34 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA34_ADDR_CUR,DMA34 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA34_STAT,DMA34 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA34_XCNT_CUR,DMA34 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA34_YCNT_CUR,DMA34 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA34_BWLCNT,DMA34 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA34_BWLCNT_CUR,DMA34 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA34_BWMCNT,DMA34 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA34_BWMCNT_CUR,DMA34 Bandwidth Monitor Count Current Register" tree.end tree "DMA35" base ad:0x31026100 width 18. group.long 0x0++0x3 line.long 0x00 "DMA35_DSCPTR_NXT,DMA35 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA35_ADDRSTART,DMA35 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA35_CFG,DMA35 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA35_XCNT,DMA35 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA35_XMOD,DMA35 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA35_YCNT,DMA35 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA35_YMOD,DMA35 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA35_DSCPTR_CUR,DMA35 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA35_DSCPTR_PRV,DMA35 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA35_ADDR_CUR,DMA35 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA35_STAT,DMA35 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA35_XCNT_CUR,DMA35 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA35_YCNT_CUR,DMA35 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA35_BWLCNT,DMA35 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA35_BWLCNT_CUR,DMA35 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA35_BWMCNT,DMA35 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA35_BWMCNT_CUR,DMA35 Bandwidth Monitor Count Current Register" tree.end tree "DMA36" base ad:0x30FFF080 width 18. group.long 0x0++0x3 line.long 0x00 "DMA36_DSCPTR_NXT,DMA36 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA36_ADDRSTART,DMA36 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA36_CFG,DMA36 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA36_XCNT,DMA36 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA36_XMOD,DMA36 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA36_YCNT,DMA36 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA36_YMOD,DMA36 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA36_DSCPTR_CUR,DMA36 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA36_DSCPTR_PRV,DMA36 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA36_ADDR_CUR,DMA36 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA36_STAT,DMA36 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA36_XCNT_CUR,DMA36 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA36_YCNT_CUR,DMA36 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA36_BWLCNT,DMA36 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA36_BWLCNT_CUR,DMA36 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA36_BWMCNT,DMA36 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA36_BWMCNT_CUR,DMA36 Bandwidth Monitor Count Current Register" tree.end tree "DMA37" base ad:0x31026280 width 18. group.long 0x0++0x3 line.long 0x00 "DMA37_DSCPTR_NXT,DMA37 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA37_ADDRSTART,DMA37 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA37_CFG,DMA37 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA37_XCNT,DMA37 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA37_XMOD,DMA37 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA37_YCNT,DMA37 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA37_YMOD,DMA37 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA37_DSCPTR_CUR,DMA37 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA37_DSCPTR_PRV,DMA37 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA37_ADDR_CUR,DMA37 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA37_STAT,DMA37 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA37_XCNT_CUR,DMA37 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA37_YCNT_CUR,DMA37 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA37_BWLCNT,DMA37 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA37_BWLCNT_CUR,DMA37 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA37_BWMCNT,DMA37 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA37_BWMCNT_CUR,DMA37 Bandwidth Monitor Count Current Register" tree.end tree "DMA38" base ad:0x31026200 width 18. group.long 0x0++0x3 line.long 0x00 "DMA38_DSCPTR_NXT,DMA38 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA38_ADDRSTART,DMA38 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA38_CFG,DMA38 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA38_XCNT,DMA38 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA38_XMOD,DMA38 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA38_YCNT,DMA38 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA38_YMOD,DMA38 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA38_DSCPTR_CUR,DMA38 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA38_DSCPTR_PRV,DMA38 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA38_ADDR_CUR,DMA38 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA38_STAT,DMA38 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA38_XCNT_CUR,DMA38 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA38_YCNT_CUR,DMA38 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA38_BWLCNT,DMA38 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA38_BWLCNT_CUR,DMA38 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA38_BWMCNT,DMA38 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA38_BWMCNT_CUR,DMA38 Bandwidth Monitor Count Current Register" tree.end tree "DMA39" base ad:0x3109A000 width 18. group.long 0x0++0x3 line.long 0x00 "DMA39_DSCPTR_NXT,DMA39 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA39_ADDRSTART,DMA39 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA39_CFG,DMA39 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA39_XCNT,DMA39 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA39_XMOD,DMA39 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA39_YCNT,DMA39 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA39_YMOD,DMA39 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA39_DSCPTR_CUR,DMA39 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA39_DSCPTR_PRV,DMA39 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA39_ADDR_CUR,DMA39 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA39_STAT,DMA39 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA39_XCNT_CUR,DMA39 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA39_YCNT_CUR,DMA39 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA39_BWLCNT,DMA39 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA39_BWLCNT_CUR,DMA39 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA39_BWMCNT,DMA39 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA39_BWMCNT_CUR,DMA39 Bandwidth Monitor Count Current Register" tree.end tree "DMA4" base ad:0x31022200 width 17. group.long 0x0++0x3 line.long 0x00 "DMA4_DSCPTR_NXT,DMA4 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA4_ADDRSTART,DMA4 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA4_CFG,DMA4 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA4_XCNT,DMA4 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA4_XMOD,DMA4 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA4_YCNT,DMA4 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA4_YMOD,DMA4 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA4_DSCPTR_CUR,DMA4 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA4_DSCPTR_PRV,DMA4 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA4_ADDR_CUR,DMA4 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA4_STAT,DMA4 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA4_XCNT_CUR,DMA4 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA4_YCNT_CUR,DMA4 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA4_BWLCNT,DMA4 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA4_BWLCNT_CUR,DMA4 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA4_BWMCNT,DMA4 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA4_BWMCNT_CUR,DMA4 Bandwidth Monitor Count Current Register" tree.end tree "DMA40" base ad:0x3109A080 width 18. group.long 0x0++0x3 line.long 0x00 "DMA40_DSCPTR_NXT,DMA40 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA40_ADDRSTART,DMA40 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA40_CFG,DMA40 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA40_XCNT,DMA40 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA40_XMOD,DMA40 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA40_YCNT,DMA40 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA40_YMOD,DMA40 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA40_DSCPTR_CUR,DMA40 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA40_DSCPTR_PRV,DMA40 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA40_ADDR_CUR,DMA40 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA40_STAT,DMA40 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA40_XCNT_CUR,DMA40 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA40_YCNT_CUR,DMA40 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA40_BWLCNT,DMA40 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA40_BWLCNT_CUR,DMA40 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA40_BWMCNT,DMA40 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA40_BWMCNT_CUR,DMA40 Bandwidth Monitor Count Current Register" tree.end tree "DMA43" base ad:0x3109B000 width 18. group.long 0x0++0x3 line.long 0x00 "DMA43_DSCPTR_NXT,DMA43 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA43_ADDRSTART,DMA43 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA43_CFG,DMA43 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA43_XCNT,DMA43 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA43_XMOD,DMA43 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA43_YCNT,DMA43 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA43_YMOD,DMA43 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA43_DSCPTR_CUR,DMA43 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA43_DSCPTR_PRV,DMA43 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA43_ADDR_CUR,DMA43 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA43_STAT,DMA43 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA43_XCNT_CUR,DMA43 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA43_YCNT_CUR,DMA43 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA43_BWLCNT,DMA43 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA43_BWLCNT_CUR,DMA43 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA43_BWMCNT,DMA43 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA43_BWMCNT_CUR,DMA43 Bandwidth Monitor Count Current Register" tree.end tree "DMA44" base ad:0x3109B080 width 18. group.long 0x0++0x3 line.long 0x00 "DMA44_DSCPTR_NXT,DMA44 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA44_ADDRSTART,DMA44 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA44_CFG,DMA44 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA44_XCNT,DMA44 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA44_XMOD,DMA44 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA44_YCNT,DMA44 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA44_YMOD,DMA44 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA44_DSCPTR_CUR,DMA44 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA44_DSCPTR_PRV,DMA44 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA44_ADDR_CUR,DMA44 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA44_STAT,DMA44 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA44_XCNT_CUR,DMA44 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA44_YCNT_CUR,DMA44 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA44_BWLCNT,DMA44 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA44_BWLCNT_CUR,DMA44 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA44_BWMCNT,DMA44 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA44_BWMCNT_CUR,DMA44 Bandwidth Monitor Count Current Register" tree.end tree "DMA45" base ad:0x310A7200 width 18. group.long 0x0++0x3 line.long 0x00 "DMA45_DSCPTR_NXT,DMA45 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA45_ADDRSTART,DMA45 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA45_CFG,DMA45 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA45_XCNT,DMA45 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA45_XMOD,DMA45 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA45_YCNT,DMA45 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA45_YMOD,DMA45 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA45_DSCPTR_CUR,DMA45 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA45_DSCPTR_PRV,DMA45 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA45_ADDR_CUR,DMA45 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA45_STAT,DMA45 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA45_XCNT_CUR,DMA45 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA45_YCNT_CUR,DMA45 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA45_BWLCNT,DMA45 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA45_BWLCNT_CUR,DMA45 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA45_BWMCNT,DMA45 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA45_BWMCNT_CUR,DMA45 Bandwidth Monitor Count Current Register" tree.end tree "DMA46" base ad:0x310A7280 width 18. group.long 0x0++0x3 line.long 0x00 "DMA46_DSCPTR_NXT,DMA46 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA46_ADDRSTART,DMA46 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA46_CFG,DMA46 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA46_XCNT,DMA46 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA46_XMOD,DMA46 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA46_YCNT,DMA46 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA46_YMOD,DMA46 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA46_DSCPTR_CUR,DMA46 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA46_DSCPTR_PRV,DMA46 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA46_ADDR_CUR,DMA46 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA46_STAT,DMA46 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA46_XCNT_CUR,DMA46 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA46_YCNT_CUR,DMA46 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA46_BWLCNT,DMA46 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA46_BWLCNT_CUR,DMA46 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA46_BWMCNT,DMA46 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA46_BWMCNT_CUR,DMA46 Bandwidth Monitor Count Current Register" tree.end tree "DMA47" base ad:0x310A7300 width 18. group.long 0x0++0x3 line.long 0x00 "DMA47_DSCPTR_NXT,DMA47 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA47_ADDRSTART,DMA47 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA47_CFG,DMA47 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA47_XCNT,DMA47 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA47_XMOD,DMA47 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA47_YCNT,DMA47 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA47_YMOD,DMA47 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA47_DSCPTR_CUR,DMA47 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA47_DSCPTR_PRV,DMA47 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA47_ADDR_CUR,DMA47 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA47_STAT,DMA47 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA47_XCNT_CUR,DMA47 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA47_YCNT_CUR,DMA47 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA47_BWLCNT,DMA47 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA47_BWLCNT_CUR,DMA47 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA47_BWMCNT,DMA47 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA47_BWMCNT_CUR,DMA47 Bandwidth Monitor Count Current Register" tree.end tree "DMA48" base ad:0x310A7380 width 18. group.long 0x0++0x3 line.long 0x00 "DMA48_DSCPTR_NXT,DMA48 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA48_ADDRSTART,DMA48 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA48_CFG,DMA48 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA48_XCNT,DMA48 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA48_XMOD,DMA48 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA48_YCNT,DMA48 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA48_YMOD,DMA48 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA48_DSCPTR_CUR,DMA48 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA48_DSCPTR_PRV,DMA48 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA48_ADDR_CUR,DMA48 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA48_STAT,DMA48 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA48_XCNT_CUR,DMA48 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA48_YCNT_CUR,DMA48 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA48_BWLCNT,DMA48 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA48_BWLCNT_CUR,DMA48 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA48_BWMCNT,DMA48 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA48_BWMCNT_CUR,DMA48 Bandwidth Monitor Count Current Register" tree.end tree "DMA49" base ad:0x310AC000 width 18. group.long 0x0++0x3 line.long 0x00 "DMA49_DSCPTR_NXT,DMA49 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA49_ADDRSTART,DMA49 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA49_CFG,DMA49 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA49_XCNT,DMA49 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA49_XMOD,DMA49 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA49_YCNT,DMA49 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA49_YMOD,DMA49 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA49_DSCPTR_CUR,DMA49 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA49_DSCPTR_PRV,DMA49 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA49_ADDR_CUR,DMA49 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA49_STAT,DMA49 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA49_XCNT_CUR,DMA49 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA49_YCNT_CUR,DMA49 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA49_BWLCNT,DMA49 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA49_BWLCNT_CUR,DMA49 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA49_BWMCNT,DMA49 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA49_BWMCNT_CUR,DMA49 Bandwidth Monitor Count Current Register" tree.end tree "DMA5" base ad:0x31022280 width 17. group.long 0x0++0x3 line.long 0x00 "DMA5_DSCPTR_NXT,DMA5 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA5_ADDRSTART,DMA5 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA5_CFG,DMA5 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA5_XCNT,DMA5 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA5_XMOD,DMA5 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA5_YCNT,DMA5 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA5_YMOD,DMA5 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA5_DSCPTR_CUR,DMA5 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA5_DSCPTR_PRV,DMA5 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA5_ADDR_CUR,DMA5 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA5_STAT,DMA5 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA5_XCNT_CUR,DMA5 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA5_YCNT_CUR,DMA5 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA5_BWLCNT,DMA5 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA5_BWLCNT_CUR,DMA5 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA5_BWMCNT,DMA5 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA5_BWMCNT_CUR,DMA5 Bandwidth Monitor Count Current Register" tree.end tree "DMA50" base ad:0x310AC080 width 18. group.long 0x0++0x3 line.long 0x00 "DMA50_DSCPTR_NXT,DMA50 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA50_ADDRSTART,DMA50 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA50_CFG,DMA50 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA50_XCNT,DMA50 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA50_XMOD,DMA50 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA50_YCNT,DMA50 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA50_YMOD,DMA50 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA50_DSCPTR_CUR,DMA50 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA50_DSCPTR_PRV,DMA50 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA50_ADDR_CUR,DMA50 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA50_STAT,DMA50 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA50_XCNT_CUR,DMA50 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA50_YCNT_CUR,DMA50 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA50_BWLCNT,DMA50 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA50_BWLCNT_CUR,DMA50 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA50_BWMCNT,DMA50 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA50_BWMCNT_CUR,DMA50 Bandwidth Monitor Count Current Register" tree.end tree "DMA51" base ad:0x3109C000 width 18. group.long 0x0++0x3 line.long 0x00 "DMA51_DSCPTR_NXT,DMA51 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA51_ADDRSTART,DMA51 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA51_CFG,DMA51 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA51_XCNT,DMA51 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA51_XMOD,DMA51 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA51_YCNT,DMA51 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA51_YMOD,DMA51 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA51_DSCPTR_CUR,DMA51 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA51_DSCPTR_PRV,DMA51 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA51_ADDR_CUR,DMA51 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA51_STAT,DMA51 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA51_XCNT_CUR,DMA51 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA51_YCNT_CUR,DMA51 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA51_BWLCNT,DMA51 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA51_BWLCNT_CUR,DMA51 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA51_BWMCNT,DMA51 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA51_BWMCNT_CUR,DMA51 Bandwidth Monitor Count Current Register" tree.end tree "DMA52" base ad:0x3109C080 width 18. group.long 0x0++0x3 line.long 0x00 "DMA52_DSCPTR_NXT,DMA52 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA52_ADDRSTART,DMA52 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA52_CFG,DMA52 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA52_XCNT,DMA52 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA52_XMOD,DMA52 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA52_YCNT,DMA52 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA52_YMOD,DMA52 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA52_DSCPTR_CUR,DMA52 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA52_DSCPTR_PRV,DMA52 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA52_ADDR_CUR,DMA52 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA52_STAT,DMA52 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA52_XCNT_CUR,DMA52 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA52_YCNT_CUR,DMA52 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA52_BWLCNT,DMA52 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA52_BWLCNT_CUR,DMA52 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA52_BWMCNT,DMA52 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA52_BWMCNT_CUR,DMA52 Bandwidth Monitor Count Current Register" tree.end tree "DMA53" base ad:0x31026380 width 18. group.long 0x0++0x3 line.long 0x00 "DMA53_DSCPTR_NXT,DMA53 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA53_ADDRSTART,DMA53 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA53_CFG,DMA53 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA53_XCNT,DMA53 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA53_XMOD,DMA53 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA53_YCNT,DMA53 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA53_YMOD,DMA53 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA53_DSCPTR_CUR,DMA53 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA53_DSCPTR_PRV,DMA53 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA53_ADDR_CUR,DMA53 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA53_STAT,DMA53 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA53_XCNT_CUR,DMA53 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA53_YCNT_CUR,DMA53 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA53_BWLCNT,DMA53 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA53_BWLCNT_CUR,DMA53 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA53_BWMCNT,DMA53 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA53_BWMCNT_CUR,DMA53 Bandwidth Monitor Count Current Register" tree.end tree "DMA54" base ad:0x31026300 width 18. group.long 0x0++0x3 line.long 0x00 "DMA54_DSCPTR_NXT,DMA54 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA54_ADDRSTART,DMA54 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA54_CFG,DMA54 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA54_XCNT,DMA54 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA54_XMOD,DMA54 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA54_YCNT,DMA54 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA54_YMOD,DMA54 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA54_DSCPTR_CUR,DMA54 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA54_DSCPTR_PRV,DMA54 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA54_ADDR_CUR,DMA54 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA54_STAT,DMA54 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA54_XCNT_CUR,DMA54 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA54_YCNT_CUR,DMA54 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA54_BWLCNT,DMA54 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA54_BWLCNT_CUR,DMA54 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA54_BWMCNT,DMA54 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA54_BWMCNT_CUR,DMA54 Bandwidth Monitor Count Current Register" tree.end tree "DMA55" base ad:0x3102D300 width 18. group.long 0x0++0x3 line.long 0x00 "DMA55_DSCPTR_NXT,DMA55 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA55_ADDRSTART,DMA55 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA55_CFG,DMA55 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA55_XCNT,DMA55 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA55_XMOD,DMA55 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA55_YCNT,DMA55 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA55_YMOD,DMA55 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA55_DSCPTR_CUR,DMA55 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA55_DSCPTR_PRV,DMA55 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA55_ADDR_CUR,DMA55 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA55_STAT,DMA55 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA55_XCNT_CUR,DMA55 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA55_YCNT_CUR,DMA55 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA55_BWLCNT,DMA55 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA55_BWLCNT_CUR,DMA55 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA55_BWMCNT,DMA55 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA55_BWMCNT_CUR,DMA55 Bandwidth Monitor Count Current Register" tree.end tree "DMA56" base ad:0x3102D380 width 18. group.long 0x0++0x3 line.long 0x00 "DMA56_DSCPTR_NXT,DMA56 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA56_ADDRSTART,DMA56 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA56_CFG,DMA56 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA56_XCNT,DMA56 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA56_XMOD,DMA56 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA56_YCNT,DMA56 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA56_YMOD,DMA56 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA56_DSCPTR_CUR,DMA56 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA56_DSCPTR_PRV,DMA56 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA56_ADDR_CUR,DMA56 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA56_STAT,DMA56 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA56_XCNT_CUR,DMA56 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA56_YCNT_CUR,DMA56 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA56_BWLCNT,DMA56 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA56_BWLCNT_CUR,DMA56 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA56_BWMCNT,DMA56 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA56_BWMCNT_CUR,DMA56 Bandwidth Monitor Count Current Register" tree.end tree "DMA6" base ad:0x31022300 width 17. group.long 0x0++0x3 line.long 0x00 "DMA6_DSCPTR_NXT,DMA6 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA6_ADDRSTART,DMA6 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA6_CFG,DMA6 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA6_XCNT,DMA6 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA6_XMOD,DMA6 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA6_YCNT,DMA6 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA6_YMOD,DMA6 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA6_DSCPTR_CUR,DMA6 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA6_DSCPTR_PRV,DMA6 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA6_ADDR_CUR,DMA6 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA6_STAT,DMA6 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA6_XCNT_CUR,DMA6 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA6_YCNT_CUR,DMA6 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA6_BWLCNT,DMA6 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA6_BWLCNT_CUR,DMA6 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA6_BWMCNT,DMA6 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA6_BWMCNT_CUR,DMA6 Bandwidth Monitor Count Current Register" tree.end tree "DMA7" base ad:0x31022380 width 17. group.long 0x0++0x3 line.long 0x00 "DMA7_DSCPTR_NXT,DMA7 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA7_ADDRSTART,DMA7 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA7_CFG,DMA7 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA7_XCNT,DMA7 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA7_XMOD,DMA7 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA7_YCNT,DMA7 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA7_YMOD,DMA7 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA7_DSCPTR_CUR,DMA7 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA7_DSCPTR_PRV,DMA7 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA7_ADDR_CUR,DMA7 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA7_STAT,DMA7 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA7_XCNT_CUR,DMA7 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA7_YCNT_CUR,DMA7 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA7_BWLCNT,DMA7 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA7_BWLCNT_CUR,DMA7 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA7_BWMCNT,DMA7 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA7_BWMCNT_CUR,DMA7 Bandwidth Monitor Count Current Register" tree.end tree "DMA8" base ad:0x310A7000 width 17. group.long 0x0++0x3 line.long 0x00 "DMA8_DSCPTR_NXT,DMA8 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA8_ADDRSTART,DMA8 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA8_CFG,DMA8 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA8_XCNT,DMA8 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA8_XMOD,DMA8 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA8_YCNT,DMA8 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA8_YMOD,DMA8 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA8_DSCPTR_CUR,DMA8 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA8_DSCPTR_PRV,DMA8 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA8_ADDR_CUR,DMA8 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA8_STAT,DMA8 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA8_XCNT_CUR,DMA8 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA8_YCNT_CUR,DMA8 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA8_BWLCNT,DMA8 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA8_BWLCNT_CUR,DMA8 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA8_BWMCNT,DMA8 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA8_BWMCNT_CUR,DMA8 Bandwidth Monitor Count Current Register" tree.end tree "DMA9" base ad:0x310A7080 width 17. group.long 0x0++0x3 line.long 0x00 "DMA9_DSCPTR_NXT,DMA9 Pointer to Next Initial Descriptor Register" group.long 0x4++0x3 line.long 0x00 "DMA9_ADDRSTART,DMA9 Start Address of Current Buffer Register" group.long 0x8++0x3 line.long 0x00 "DMA9_CFG,DMA9 Configuration Register" bitfld.long 0x00 28. " PDRF ,Peripheral Data Request Forward" "0,1" bitfld.long 0x00 26. " TWOD ,Two Dimension Addressing Enable" "0,1" bitfld.long 0x00 25. " DESCIDCPY ,Descriptor ID Copy Control" "0,1" newline bitfld.long 0x00 24. " TOVEN ,Trigger Overrun Error Enable" "0,1" bitfld.long 0x00 22.--23. " TRIG ,Generate Outgoing Trigger" "0,1,2,3" bitfld.long 0x00 20.--21. " INT ,Generate Interrupt Request" "0,1,2,3" newline bitfld.long 0x00 16.--18. " NDSIZE ,Next Descriptor Set Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 12.--14. " FLOW ,Next Operation" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. " MSIZE ,Memory Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " PSIZE ,Peripheral Transfer Word Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " CADDR ,Use Current Address" "0,1" newline bitfld.long 0x00 2. " SYNC ,Synchronize Work Unit Transitions" "0,1" bitfld.long 0x00 1. " WNR ,Write/Read Channel Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Channel Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "DMA9_XCNT,DMA9 Inner Loop Count Start Value Register" group.long 0x10++0x3 line.long 0x00 "DMA9_XMOD,DMA9 Inner Loop Address Increment Register" group.long 0x14++0x3 line.long 0x00 "DMA9_YCNT,DMA9 Outer Loop Count Start Value (2D only) Register" group.long 0x18++0x3 line.long 0x00 "DMA9_YMOD,DMA9 Outer Loop Address Increment (2D only) Register" group.long 0x24++0x3 line.long 0x00 "DMA9_DSCPTR_CUR,DMA9 Current Descriptor Pointer Register" group.long 0x28++0x3 line.long 0x00 "DMA9_DSCPTR_PRV,DMA9 Previous Initial Descriptor Pointer Register" hexmask.long 0x00 2.--31. 1. " DESCPPREV ,Descriptor Pointer for Previous Element" bitfld.long 0x00 0. " PDPO ,Previous Descriptor Pointer Overrun" "0,1" group.long 0x2C++0x3 line.long 0x00 "DMA9_ADDR_CUR,DMA9 Current Address Register" group.long 0x30++0x3 line.long 0x00 "DMA9_STAT,DMA9 Status Register" bitfld.long 0x00 20. " TWAIT ,Trigger Wait Status" "0,1" bitfld.long 0x00 16.--18. " FIFOFILL ,FIFO Fill Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " MBWID ,Memory Bus Width" "0,1,2,3" newline bitfld.long 0x00 12.--13. " PBWID ,Peripheral Bus Width" "0,1,2,3" bitfld.long 0x00 8.--10. " RUN ,Run Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. " ERRC ,Error Cause" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 2. " PIRQ ,Peripheral Interrupt Request" "0,1" bitfld.long 0x00 1. " IRQERR ,Error Interrupt Request" "0,1" bitfld.long 0x00 0. " IRQDONE ,Work Unit/Row Done Interrupt" "0,1" group.long 0x34++0x3 line.long 0x00 "DMA9_XCNT_CUR,DMA9 Current Count (1D) or Intra-row XCNT (2D) Register" group.long 0x38++0x3 line.long 0x00 "DMA9_YCNT_CUR,DMA9 Current Row Count (2D only) Register" group.long 0x40++0x3 line.long 0x00 "DMA9_BWLCNT,DMA9 Bandwidth Limit Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count" group.long 0x44++0x3 line.long 0x00 "DMA9_BWLCNT_CUR,DMA9 Bandwidth Limit Count Current Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Bandwidth Limit Count Current" group.long 0x48++0x3 line.long 0x00 "DMA9_BWMCNT,DMA9 Bandwidth Monitor Count Register" group.long 0x4C++0x3 line.long 0x00 "DMA9_BWMCNT_CUR,DMA9 Bandwidth Monitor Count Current Register" tree.end tree.end tree "DMC (Dynamic Memory Controller)" base ad:0x31070004 width 26. group.long 0x0++0x3 line.long 0x00 "DMC0_CTL,DMC0 Control Register" bitfld.long 0x00 27. " AL_EN ,AL_EN" "0,1" bitfld.long 0x00 26. " RL_DQS ,RL_DQS" "0,1" bitfld.long 0x00 25. " ZQCL ,ZQ Calibration Long" "0,1" newline bitfld.long 0x00 24. " ZQCS ,ZQ Calibration Short" "0,1" bitfld.long 0x00 13. " DLLCAL ,DLL Calibration Start" "0,1" bitfld.long 0x00 12. " PPREF ,Postpone Refresh" "0,1" newline bitfld.long 0x00 9.--11. " RDTOWR ,Read-to-Write Cycle" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8. " ADDRMODE ,Addressing (Page/Bank) Mode" "0,1" bitfld.long 0x00 7. " RESET ,Reset SDRAM" "0,1" newline bitfld.long 0x00 6. " PREC ,Precharge" "0,1" bitfld.long 0x00 4. " PDREQ ,Power Down Request" "0,1" bitfld.long 0x00 3. " SRREQ ,Self-Refresh Request" "0,1" newline bitfld.long 0x00 2. " INIT ,Initialize DRAM Start" "0,1" bitfld.long 0x00 0. " DDR3EN ,DDR3 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "DMC0_STAT,DMC0 Status Register" bitfld.long 0x00 25. " ZQCLDONE ,ZQ Calibration Long Done" "0,1" bitfld.long 0x00 24. " ZQCSDONE ,ZQ Calibration Short Done" "0,1" bitfld.long 0x00 20.--23. " PHYRDPHASE ,PHY Read Phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. " PENDREF ,Pending Refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13. " DLLCALDONE ,DLL Calibration Done" "0,1" bitfld.long 0x00 7. " RESETDONE ,Reset Done" "0,1" newline bitfld.long 0x00 4. " PDACK ,Power-Down Acknowledge" "0,1" bitfld.long 0x00 3. " SRACK ,Self-Refresh Acknowledge" "0,1" bitfld.long 0x00 2. " INITDONE ,Initialization Done" "0,1" newline bitfld.long 0x00 0. " IDLE ,Idle State" "0,1" group.long 0x8++0x3 line.long 0x00 "DMC0_EFFCTL,DMC0 Efficiency Control Register" bitfld.long 0x00 20.--23. " IDLECYC ,Idle Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " NUMREF ,Number of Refresh Commands" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " PRECBANK7 ,Precharge Bank 7" "0,1" newline bitfld.long 0x00 14. " PRECBANK6 ,Precharge Bank 6" "0,1" bitfld.long 0x00 13. " PRECBANK5 ,Precharge Bank 5" "0,1" bitfld.long 0x00 12. " PRECBANK4 ,Precharge Bank 4" "0,1" newline bitfld.long 0x00 11. " PRECBANK3 ,Precharge Bank 3" "0,1" bitfld.long 0x00 10. " PRECBANK2 ,Precharge Bank 2" "0,1" bitfld.long 0x00 9. " PRECBANK1 ,Precharge Bank 1" "0,1" newline bitfld.long 0x00 8. " PRECBANK0 ,Precharge Bank 0" "0,1" group.long 0xC++0x3 line.long 0x00 "DMC0_PRIO,DMC0 Priority ID Register 1" group.long 0x10++0x3 line.long 0x00 "DMC0_PRIOMSK,DMC0 Priority ID Mask Register 1" group.long 0x14++0x3 line.long 0x00 "DMC0_PRIO2,DMC0 Priority ID Register 2" group.long 0x18++0x3 line.long 0x00 "DMC0_PRIOMSK2,DMC0 Priority ID Mask Register 2" group.long 0x3C++0x3 line.long 0x00 "DMC0_CFG,DMC0 Configuration Register" bitfld.long 0x00 12.--15. " EXTBANK ,External Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " SDRSIZE ,SDRAM Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " SDRWID ,SDRAM Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " IFWID ,Interface Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x3 line.long 0x00 "DMC0_TR0,DMC0 Timing 0 Register" bitfld.long 0x00 28.--31. " TMRD ,Timing Mode Register Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--25. " TRC ,Timing Row Cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12.--16. " TRAS ,Timing Row Active Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--11. " TRP ,Timing RAS Precharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " TWTR ,Timing Write to Read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " TRCD ,Timing RAS to CAS Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x44++0x3 line.long 0x00 "DMC0_TR1,DMC0 Timing 1 Register" bitfld.long 0x00 28.--30. " TRRD ,Timing Read-Read Delay" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 16.--24. 1. " TRFC ,Timing Refresh-to-Command" hexmask.long.word 0x00 0.--13. 1. " TREF ,Timing Refresh Interval" group.long 0x48++0x3 line.long 0x00 "DMC0_TR2,DMC0 Timing 2 Register" bitfld.long 0x00 20.--23. " TCKE ,Timing Clock Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " TXP ,Timing Exit Power Down" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " TRTP ,Timing Read-to-Precharge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. " TFAW5 ,Extended Timing Four-Active Window Bit 5" "0,1" bitfld.long 0x00 0.--4. " TFAW ,Timing Four-Activated-Window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x58++0x3 line.long 0x00 "DMC0_MSK,DMC0 Mask (Mode Register Shadow) Register" bitfld.long 0x00 11. " EMR3 ,Shadow EMR3 Unmask" "0,1" bitfld.long 0x00 10. " MR2 ,Shadow MR2 Unmask" "0,1" bitfld.long 0x00 9. " MR1 ,Shadow MR1 Unmask" "0,1" newline bitfld.long 0x00 8. " MR ,Shadow MR Unmask" "0,1" group.long 0x5C++0x3 line.long 0x00 "DMC0_MR,DMC0 Shadow MR0 Register (DDR3)" bitfld.long 0x00 12. " PD ,Active Power Down Mode" "0,1" bitfld.long 0x00 9.--11. " WRRECOV ,Write Recovery" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8. " DLLRST ,DLL Reset" "0,1" newline bitfld.long 0x00 4.--6. " CL ,CAS Latency" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. " CL0 ,CAS Latency 0" "0,1" bitfld.long 0x00 0.--1. " BLEN ,Burst Length" "0,1,2,3" group.long 0x60++0x3 line.long 0x00 "DMC0_MR1,DMC0 Shadow MR1 Register (DDR3)" bitfld.long 0x00 12. " QOFF ,Output Buffer Enable" "0,1" bitfld.long 0x00 11. " TDQS ,Termination Data Strobe" "0,1" bitfld.long 0x00 9. " RTT2 ,Rtt_nom" "0,1" newline bitfld.long 0x00 7. " WL ,Write Leveling Enable." "0,1" bitfld.long 0x00 6. " RTT1 ,Rtt_nom" "0,1" bitfld.long 0x00 5. " DIC1 ,Output Driver Impedance Control" "0,1" newline bitfld.long 0x00 3.--4. " AL ,Additive Latency" "0,1,2,3" bitfld.long 0x00 2. " RTT0 ,Rtt_nom" "0,1" bitfld.long 0x00 1. " DIC0 ,Output Driver Impedance control" "0,1" newline bitfld.long 0x00 0. " DLLEN ,DLL Enable" "0,1" group.long 0x64++0x3 line.long 0x00 "DMC0_MR2,DMC0 Shadow MR2 Register (DDR3)" bitfld.long 0x00 7. " SRT ,Self Refresh Temperature Range" "0,1" bitfld.long 0x00 6. " ASR ,Auto Self Refresh" "0,1" bitfld.long 0x00 3.--5. " CWL ,CAS Write Latency" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " PASR ,Partial Array Self refresh" "0,1,2,3,4,5,6,7" group.long 0x68++0x3 line.long 0x00 "DMC0_EMR3,DMC0 Shadow EMR3 Register" bitfld.long 0x00 2. " MPR ,Multi Purpose Read Enable (Read Leveling)" "0,1" bitfld.long 0x00 0.--1. " MPR_LOC ,Hardcoded to '00'. Reads a pre-defined pattern on MPR Read" "0,1,2,3" group.long 0x7C++0x3 line.long 0x00 "DMC0_DLLCTL,DMC0 DLL Control Register" bitfld.long 0x00 8.--11. " DATACYC ,Data Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " DLLCALRDCNT ,DLL Calibration RD Count" group.long 0x8C++0x3 line.long 0x00 "DMC0_DT_CALIB_ADDR,DMC0 Data Calibration Address Register" group.long 0x90++0x3 line.long 0x00 "DMC0_DT_DATA_CALIB_DATA0,DMC0 Data Calibration Data 0 Register" group.long 0x94++0x3 line.long 0x00 "DMC0_DT_DATA_CALIB_DATA1,DMC0 Data Calibration Data 1 Register" group.long 0xFC++0x3 line.long 0x00 "DMC0_RDDATABUFID1,DMC0 DMC Read Data Buffer ID Register 1" group.long 0x100++0x3 line.long 0x00 "DMC0_RDDATABUFMSK1,DMC0 DMC Read Data Buffer Mask Register 1" group.long 0x104++0x3 line.long 0x00 "DMC0_RDDATABUFID2,DMC0 DMC Read Data Buffer ID Register 2" group.long 0x108++0x3 line.long 0x00 "DMC0_RDDATABUFMSK2,DMC0 DMC Read Data Buffer Mask Register 2" group.long 0xFFC++0x3 line.long 0x00 "DMC0_DDR_LANE0_CTL0,DMC0 Data Lane 0 Control Register 0" bitfld.long 0x00 27. " CB_RSTDAT ,Reset the Data Pads" "0,1" bitfld.long 0x00 12.--15. " BYPCODE ,Used to select from four levels of duty cycle adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " BYPSELP ,Duty Cycle Offset Direction Select" "0,1" newline bitfld.long 0x00 10. " BYPENB ,DQS Duty Cycle Offset Adjustment Enable" "0,1" bitfld.long 0x00 8. " CB_RSTDLL ,Reset the Lane DLL" "0,1" bitfld.long 0x00 5.--6. " MF_SEL ,SPI Master Frequency Divider Select" "0,1,2,3" newline bitfld.long 0x00 1.--2. " DDR_MODE ,DDR Mode" "0,1,2,3" bitfld.long 0x00 0. " LANE_DIS ,Clock Gate Data Lane" "0,1" group.long 0x1000++0x3 line.long 0x00 "DMC0_DDR_LANE0_CTL1,DMC0 Data Lane 0 Control Register 1" bitfld.long 0x00 15. " BYPDELCHAINEN ,Bypass enable for delay chain controlling extra delay on DATA pins" "0,1" bitfld.long 0x00 10.--14. " BYPCODE ,Bypass Code for extra delay on DATA pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " COMP_DCYCLE ,Compute Datacycle" "0,1" group.long 0x1008++0x3 line.long 0x00 "DMC0_DDR_LANE1_CTL0,DMC0 Data Lane 1 Control Register 0" bitfld.long 0x00 27. " CB_RSTDAT ,Reset the Data Pads" "0,1" bitfld.long 0x00 12.--15. " BYPCODE ,Used to select from four levels of duty cycle adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " BYPSELP ,Duty Cycle Offset Direction Select" "0,1" newline bitfld.long 0x00 10. " BYPENB ,DQS Duty Cycle Offset Adjustment Enable" "0,1" bitfld.long 0x00 8. " CB_RSTDLL ,Reset the Lane DLL" "0,1" bitfld.long 0x00 5.--6. " MF_SEL ,SPI Master Frequency Divider Select" "0,1,2,3" newline bitfld.long 0x00 1.--2. " DDR_MODE ,DDR Mode" "0,1,2,3" bitfld.long 0x00 0. " LANE_DIS ,Clock Gate Data Lane" "0,1" group.long 0x100C++0x3 line.long 0x00 "DMC0_DDR_LANE1_CTL1,DMC0 Data Lane 1 Control Register 1" bitfld.long 0x00 15. " BYPDELCHAINEN ,Bypass enable for delay chain controlling extra delay on DATA pins" "0,1" bitfld.long 0x00 10.--14. " BYPCODE ,Bypass Code for extra delay on DATA pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " COMP_DCYCLE ,Compute Datacycle" "0,1" group.long 0x1014++0x3 line.long 0x00 "DMC0_DDR_ROOT_CTL,DMC0 DDR ROOT Module Control Register" bitfld.long 0x00 21. " TRIG_RD_XFER_ALL ,All Lane Read Status" "0,1" bitfld.long 0x00 18. " TRIG_WR_XFER_L1 ,Write Transfer from Root to Lane1" "0,1" bitfld.long 0x00 17. " TRIG_WR_XFER_L0 ,Write Transfer from Root to Lane 0" "0,1" newline bitfld.long 0x00 16. " TRIG_WR_XFER_CA ,Write Transfer from Root to CA Lane" "0,1" bitfld.long 0x00 14.--15. " MF_SEL ,SPI Master Frequency Divider Select" "0,1,2,3" bitfld.long 0x00 13. " SW_REFRESH ,Refresh Lane DLL Code" "0,1" newline bitfld.long 0x00 10.--12. " PIPE_OFSTDCYCLE ,Pipeline offset for PHYC_DATACYCLE" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--9. " CPHY_DCYCLE_VAL ,Bypass Value for CPHY_DATACYCLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " CPHY_DCYCLE_BYP ,Bypass Enable for CPHY_DATACYCLE" "0,1" newline bitfld.long 0x00 1.--4. " PHYC_DCYCLE_VAL ,Bypass Value for PHYC_DATACYCLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " PHYC_DCYCLE_BYP ,Bypass Enable for PHYC_DATACYCLE" "0,1" group.long 0x1030++0x3 line.long 0x00 "DMC0_DDR_ZQ_CTL0,DMC0 DDR Calibration Control Register 0" hexmask.long.byte 0x00 16.--23. 1. " IMPRTT ,Data/DQS ODT" hexmask.long.byte 0x00 8.--15. 1. " IMPWRDQ ,Data/DQS/DM/CLK Drive Strength" hexmask.long.byte 0x00 0.--7. 1. " IMPWRADD ,Address/Command Drive Strength" group.long 0x1034++0x3 line.long 0x00 "DMC0_DDR_ZQ_CTL1,DMC0 DDR Calibration Control Register 1" bitfld.long 0x00 22. " USEFNBUS ,BSCAN Mode" "0,1" bitfld.long 0x00 12. " PDCAL ,Calibration Pad Power Down" "0,1" bitfld.long 0x00 6.--11. " BYPRDPD ,Pull-down Termination Bypass Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 0.--5. " BYPRDPU ,Pull-up Termination Bypass Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1038++0x3 line.long 0x00 "DMC0_DDR_ZQ_CTL2,DMC0 DDR Calibration Control Register 2" bitfld.long 0x00 31. " RTTCALEN ,Pad ODT Strength Calibration Enable" "0,1" bitfld.long 0x00 30. " PDCALEN ,Driver Pull-down Strength Calibration Enable" "0,1" bitfld.long 0x00 29. " PUCALEN ,Driver Pull-up Strength Calibration Enable" "0,1" newline bitfld.long 0x00 28. " CALSTRT ,New Impedance Calibration Enable" "0,1" bitfld.long 0x00 27. " CALTYPE ,Calibration Type" "0,1" bitfld.long 0x00 21.--26. " BYPPDDQ ,Bypass Code for DQ,DQS,CLK,DM Pull-down Driver Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 15.--20. " BYPPUDQ ,Bypass Code for DQ,DQS,CLK,DM Pull-up Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9.--14. " BYPPDADD ,Address/Command Bypass Pull-down Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 3.--8. " BYPPUADD ,Address/Command Bypass Pull-up Codes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 2. " BYPIMRD ,Bypass Termination Code Enable" "0,1" bitfld.long 0x00 1. " BYPIMDQ ,DQ/DQS/CLK/DM Bypass Driver Code Enable" "0,1" bitfld.long 0x00 0. " BYPIMAD ,Address/Command Bypass Code Enable" "0,1" group.long 0x1064++0x3 line.long 0x00 "DMC0_DDR_CA_CTL,DMC0 DDR CA Lane Control Register" bitfld.long 0x00 26.--30. " SLAVE_ID ,SW Slave Read/Write Slave ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 23.--24. " BYPCODE1 ,Duty Cycle Level Select" "0,1,2,3" bitfld.long 0x00 19.--20. " BYPCODE0 ,Duty Cycle Level Select" "0,1,2,3" newline bitfld.long 0x00 18. " BYPSELP ,Duty Cycle Offset Direction Select" "0,1" bitfld.long 0x00 17. " BYPENB ,CLK Duty Cycle Offset Adjustment Enable" "0,1" bitfld.long 0x00 15.--16. " MF_SEL ,SPI Master Frequency Divider Select" "0,1,2,3" newline bitfld.long 0x00 14. " SW_REFRESH ,Refresh Lane DLL Code" "0,1" tree.end tree "DPM (Dynamic Power Management)" base ad:0x31090000 width 15. group.long 0x0++0x3 line.long 0x00 "DPM0_CTL,DPM0 Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" group.long 0x4++0x3 line.long 0x00 "DPM0_STAT,DPM0 Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADDRERR ,Address Error" "0,1" bitfld.long 0x00 4.--7. " PRVMODE ,Previous Mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. " CURMODE ,Current Mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x70++0x3 line.long 0x00 "DPM0_PER_DIS0,DPM0 Peripherals Disable Register 0" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Peripheral Disable" group.long 0x74++0x3 line.long 0x00 "DPM0_PER_DIS1,DPM0 Peripherals Disable Register 1" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" hexmask.long.tbyte 0x00 0.--18. 1. " VALUE ,Peripheral Disable" group.long 0x84++0x3 line.long 0x00 "DPM0_REVID,DPM0 Revision ID" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "EMAC (Ethernet Media Access Controller)" tree "EMAC0" base ad:0x31040000 width 26. group.long 0x0++0x3 line.long 0x00 "EMAC0_MACCFG,EMAC0 MAC Configuration Register" bitfld.long 0x00 28.--30. " SARC ,Source Address Insertion or Replacement Control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TWOKPE ,Support for 2K packets" "0,1" bitfld.long 0x00 25. " CST ,CRC Stripping" "0,1" newline bitfld.long 0x00 24. " TC ,Transmit Configuration in RGMII, SGMII or SMII" "0,1" bitfld.long 0x00 23. " WD ,Watch Dog Disable" "0,1" bitfld.long 0x00 22. " JB ,Jabber Disable" "0,1" newline bitfld.long 0x00 21. " BE ,Frame Burst Enable" "0,1" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "0,1" bitfld.long 0x00 17.--19. " IFG ,Inter-Frame Gap" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense" "0,1" bitfld.long 0x00 15. " PS ,Port Select" "0,1" bitfld.long 0x00 14. " FES ,Speed of Operation" "0,1" newline bitfld.long 0x00 13. " DO ,Disable Receive Own" "0,1" bitfld.long 0x00 12. " LM ,Loopback Mode" "0,1" bitfld.long 0x00 11. " DM ,Duplex Mode" "0,1" newline bitfld.long 0x00 10. " IPC ,IP Checksum" "0,1" bitfld.long 0x00 9. " DR ,Disable Retry" "0,1" bitfld.long 0x00 8. " LUD ,Link Up or Down" "0,1" newline bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "0,1" bitfld.long 0x00 5.--6. " BL ,Back Off Limit" "0,1,2,3" bitfld.long 0x00 4. " DC ,Deferral Check" "0,1" newline bitfld.long 0x00 3. " TE ,Transmitter Enable" "0,1" bitfld.long 0x00 2. " RE ,Receiver Enable" "0,1" bitfld.long 0x00 0.--1. " PRELEN ,Preamble Length for Transmit Frames" "0,1,2,3" group.long 0x4++0x3 line.long 0x00 "EMAC0_MACFRMFILT,EMAC0 MAC Rx Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive All Frames" "0,1" bitfld.long 0x00 21. " DNTU ,Drop non-TCP/UDP over IP Frames" "0,1" bitfld.long 0x00 20. " IPFE ,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x00 16. " VTFE ,VAN Tag Filter Enable" "0,1" bitfld.long 0x00 10. " HPF ,Hash or Perfect Filter" "0,1" bitfld.long 0x00 9. " SAF ,Source Address Filter Enable" "0,1" newline bitfld.long 0x00 8. " SAIF ,Source Address Inverse Filtering" "0,1" bitfld.long 0x00 6.--7. " PCF ,Pass Control Frames" "0,1,2,3" bitfld.long 0x00 5. " DBF ,Disable Broadcast Frames" "0,1" newline bitfld.long 0x00 4. " PM ,Pass All Multicast Frames" "0,1" bitfld.long 0x00 3. " DAIF ,Destination Address Inverse Filtering" "0,1" bitfld.long 0x00 2. " HMC ,Hash Multicast" "0,1" newline bitfld.long 0x00 1. " HUC ,Hash Unicast" "0,1" bitfld.long 0x00 0. " PR ,Promiscuous Mode" "0,1" group.long 0x8++0x3 line.long 0x00 "EMAC0_HASHTBL_HI,EMAC0 Hash Table High Register" group.long 0xC++0x3 line.long 0x00 "EMAC0_HASHTBL_LO,EMAC0 Hash Table Low Register" group.long 0x10++0x3 line.long 0x00 "EMAC0_SMI_ADDR,EMAC0 SMI Address Register" bitfld.long 0x00 11.--15. " PA ,Physical Layer Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--10. " SMIR ,SMI Register Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--5. " CR ,Clock Range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " SMIW ,SMI Write" "0,1" bitfld.long 0x00 0. " SMIB ,SMI Busy" "0,1" group.long 0x14++0x3 line.long 0x00 "EMAC0_SMI_DATA,EMAC0 SMI Data Register" hexmask.long.word 0x00 0.--15. 1. " SMID ,SMI Data" group.long 0x18++0x3 line.long 0x00 "EMAC0_FLOWCTL,EMAC0 FLow Control Register" hexmask.long.word 0x00 16.--31. 1. " PT ,Pause Time" bitfld.long 0x00 7. " DZPQ ,Disable Zero-Quanta Pause" "0,1" bitfld.long 0x00 4.--5. " PLT ,Pause Low Threshold" "0,1,2,3" newline bitfld.long 0x00 3. " UP ,Unicast Pause Frame Detect" "0,1" bitfld.long 0x00 2. " RFE ,Receive Flow Control Enable" "0,1" bitfld.long 0x00 1. " TFE ,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x00 0. " FCBBPA ,Initiate Pause Control Frame" "0,1" group.long 0x1C++0x3 line.long 0x00 "EMAC0_VLANTAG,EMAC0 VLAN Tag Register" bitfld.long 0x00 19. " VTHM ,VLAN Tag Hash Table Match Enable" "0,1" bitfld.long 0x00 18. " ESVL ,Enable S-VLAN" "0,1" bitfld.long 0x00 17. " VTIM ,VLAN Tag Inverse Match Enable" "0,1" newline bitfld.long 0x00 16. " ETV ,Enable Tag VLAN Comparison" "0,1" hexmask.long.word 0x00 0.--15. 1. " VL ,VLAN Tag Id Receive Frames" group.long 0x24++0x3 line.long 0x00 "EMAC0_DBG,EMAC0 Debug Register" bitfld.long 0x00 25. " TXFIFOFULL ,Tx FIFO Full" "0,1" bitfld.long 0x00 24. " TXFIFONE ,Tx FIFO Not Empty" "0,1" bitfld.long 0x00 22. " TXFIFOACT ,Tx FIFO Active" "0,1" newline bitfld.long 0x00 20.--21. " TXFIFOCTLST ,Tx FIFO Controller State" "0,1,2,3" bitfld.long 0x00 19. " TXPAUSE ,Tx Paused" "0,1" bitfld.long 0x00 17.--18. " TXFRCTL ,Tx Frame Controller State" "0,1,2,3" newline bitfld.long 0x00 16. " MMTEA ,MM Tx Engine Active" "0,1" bitfld.long 0x00 8.--9. " RXFIFOST ,Rx FIFO State" "0,1,2,3" bitfld.long 0x00 5.--6. " RXFIFOCTLST ,Rx FIFO Controller State" "0,1,2,3" newline bitfld.long 0x00 4. " RXFIFOACT ,Rx FIFO Active" "0,1" bitfld.long 0x00 1.--2. " SFIFOST ,Small FIFO State" "0,1,2,3" bitfld.long 0x00 0. " MMREA ,MM Rx Engine Active" "0,1" group.long 0x30++0x3 line.long 0x00 "EMAC0_LPI_CTLSTAT,EMAC0 Low Power Idle Control and Status Register" bitfld.long 0x00 19. " LPITXA ,LPI Mode Transmit Behavior" "0,1" bitfld.long 0x00 18. " PLSEN ,LPI Link Status Enable" "0,1" bitfld.long 0x00 17. " PLS ,PHY Link Status" "0,1" newline bitfld.long 0x00 16. " LPIEN ,LPI Enable" "0,1" bitfld.long 0x00 9. " RLPIST ,Receive LPI Status" "0,1" bitfld.long 0x00 8. " TLPIST ,Transmit LPI Status" "0,1" newline bitfld.long 0x00 3. " RLPIEX ,Receiver LPI State Exit Status" "0,1" bitfld.long 0x00 2. " RLPIEN ,Receiver LPI State Enable Status" "0,1" bitfld.long 0x00 1. " TLPIEX ,Transmitter LPI State Exit Status" "0,1" newline bitfld.long 0x00 0. " TLPIEN ,Transmitter LPI State Enable Status" "0,1" group.long 0x34++0x3 line.long 0x00 "EMAC0_LPI_TMRSCTL,EMAC0 Low Power Idle Timeout Register" hexmask.long.word 0x00 16.--25. 1. " LST ,Link Status Timer" hexmask.long.word 0x00 0.--15. 1. " TWT ,Timer Wait Time" group.long 0x38++0x3 line.long 0x00 "EMAC0_ISTAT,EMAC0 Interrupt Status Register" bitfld.long 0x00 10. " LPIIS ,LPI Interrupt Status" "0,1" bitfld.long 0x00 9. " TS ,Time Stamp Interrupt Status" "0,1" bitfld.long 0x00 7. " MMCRC ,MMC Receive Checksum Offload Interrupt Status" "0,1" newline bitfld.long 0x00 6. " MMCTX ,MMC Transmit Interrupt Status" "0,1" bitfld.long 0x00 5. " MMCRX ,MMC Receive Interrupt Status" "0,1" bitfld.long 0x00 4. " MMC ,MMC Interrupt Status" "0,1" newline bitfld.long 0x00 0. " RGMIIIS ,RGMII or SMII Interrupt Status" "0,1" group.long 0x3C++0x3 line.long 0x00 "EMAC0_IMSK,EMAC0 Interrupt Mask Register" bitfld.long 0x00 10. " LPIIM ,LPI Interrupt Mask" "0,1" bitfld.long 0x00 9. " TS ,Time Stamp Interrupt Mask" "0,1" bitfld.long 0x00 0. " RGMIIIM ,RGMII or SMII Interrupt Mask" "0,1" group.long 0x40++0x3 line.long 0x00 "EMAC0_ADDR0_HI,EMAC0 MAC Address 0 High Register" hexmask.long.word 0x00 0.--15. 1. " ADDR ,Address" group.long 0x44++0x3 line.long 0x00 "EMAC0_ADDR0_LO,EMAC0 MAC Address 0 Low Register" group.long 0x48++0x3 line.long 0x00 "EMAC0_ADDR1_HI,EMAC0 MAC Address 1 High Register" bitfld.long 0x00 31. " AE ,Address Enable" "0,1" bitfld.long 0x00 30. " SA ,Source Address" "0,1" bitfld.long 0x00 24.--29. " MBC ,Mask byte control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--15. 1. " ADDRHI ,Mac address" group.long 0x4C++0x3 line.long 0x00 "EMAC0_ADDR1_LO,EMAC0 MAC Address 1 Low Register" group.long 0xD8++0x3 line.long 0x00 "EMAC0_GIGE_CTLSTAT,EMAC0 RGMII Control and Status Register" bitfld.long 0x00 3. " LNKSTS ,Link Status" "0,1" bitfld.long 0x00 1.--2. " LNKSPEED ,Link Speed" "0,1,2,3" bitfld.long 0x00 0. " LNKMOD ,Link Mode" "0,1" group.long 0xDC++0x3 line.long 0x00 "EMAC0_WDOG_TIMOUT,EMAC0 Watchdog Timeout Register" bitfld.long 0x00 16. " PWE ,Programmable Watchdog Enable" "0,1" hexmask.long.word 0x00 0.--13. 1. " WTO ,Watchdog Timeout" group.long 0x100++0x3 line.long 0x00 "EMAC0_MMC_CTL,EMAC0 MMC Control Register" bitfld.long 0x00 5. " FULLPSET ,Full Preset" "0,1" bitfld.long 0x00 4. " CNTRPSET ,Counter Reset/Preset" "0,1" bitfld.long 0x00 3. " CNTRFRZ ,Counter Freeze" "0,1" newline bitfld.long 0x00 2. " RDRST ,Read Reset" "0,1" bitfld.long 0x00 1. " NOROLL ,No Rollover" "0,1" bitfld.long 0x00 0. " RST ,Reset" "0,1" group.long 0x104++0x3 line.long 0x00 "EMAC0_MMC_RXINT,EMAC0 MMC Rx Interrupt Register" bitfld.long 0x00 25. " RXCTLFIS ,Rx Control Frame Counter Interrupt Status" "0,1" bitfld.long 0x00 24. " RXRCVERRFIS ,Rx Error Frame Counter Interrupt Status" "0,1" bitfld.long 0x00 23. " WDOGERR ,Rx Watch Dog Error Count Half/Full" "0,1" newline bitfld.long 0x00 22. " VLANFRGB ,Rx VLAN Frames (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 21. " FIFOOVF ,Rx FIFO Overflow Count Half/Full" "0,1" bitfld.long 0x00 20. " PAUSEFR ,Rx Pause Frames Count Half/Full" "0,1" newline bitfld.long 0x00 19. " OUTRANGE ,Rx Out Of Range Type Count Half/Full" "0,1" bitfld.long 0x00 18. " LENERR ,Rx Length Error Count Half/Full" "0,1" bitfld.long 0x00 17. " UCASTG ,Rx Unicast Frames (Good) Count Half/Full" "0,1" newline bitfld.long 0x00 16. " R1024TOMAX ,Rx 1024-to-max Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 15. " R512TO1023 ,Rx 512-to-1023 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 14. " R256TO511 ,Rx 255-to-511 Octets (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 13. " R128TO255 ,Rx 128-to-255 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 12. " R65TO127 ,Rx 65-to-127 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 11. " R64 ,Rx 64 Octets (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 10. " OSIZEG ,Rx Oversize (Good) Count Half/Full" "0,1" bitfld.long 0x00 9. " USIZEG ,Rx Undersize (Good) Count Half/Full" "0,1" bitfld.long 0x00 8. " JABERR ,Rx Jabber Error Count Half/Full" "0,1" newline bitfld.long 0x00 7. " RUNTERR ,Rx Runt Error Count Half/Full" "0,1" bitfld.long 0x00 6. " ALIGNERR ,Rx Alignment Error Count Half/Full" "0,1" bitfld.long 0x00 5. " CRCERR ,Rx CRC Error Counter Half/Full" "0,1" newline bitfld.long 0x00 4. " MCASTG ,Rx Multicast Count (Good) Half/Full" "0,1" bitfld.long 0x00 3. " BCASTG ,Rx Broadcast Count (Good) Half/Full" "0,1" bitfld.long 0x00 2. " OCTCNTG ,Octet Count (Good) Half/Full" "0,1" newline bitfld.long 0x00 1. " OCTCNTGB ,Octet Count (Good/Bad) Half/Full" "0,1" bitfld.long 0x00 0. " FRCNTGB ,Frame Count (Good/Bad) Half/Full" "0,1" group.long 0x108++0x3 line.long 0x00 "EMAC0_MMC_TXINT,EMAC0 MMC Tx Interrupt Register" bitfld.long 0x00 25. " TXOSIZEGFIS ,Tx Oversize Good Frame Count Interrupt Status" "0,1" bitfld.long 0x00 24. " VLANFRGB ,Tx VLAN Frames (Good) Count Half/Full" "0,1" bitfld.long 0x00 23. " PAUSEFRM ,Tx Pause Frames Count Half/Full" "0,1" newline bitfld.long 0x00 22. " EXCESSDEF ,Tx Excess Deferred Count Half/Full" "0,1" bitfld.long 0x00 21. " FRCNTG ,Tx Frame Count (Good) Count Half/Full" "0,1" bitfld.long 0x00 20. " OCTCNTG ,Tx Octet Count (Good) Count Half/Full" "0,1" newline bitfld.long 0x00 19. " CARRERR ,Tx Carrier Error Count Half/Full" "0,1" bitfld.long 0x00 18. " EXCESSCOL ,Tx Excess Collision Count Half/Full" "0,1" bitfld.long 0x00 17. " LATECOL ,Tx Late Collision Count Half/Full" "0,1" newline bitfld.long 0x00 16. " DEFERRED ,Tx Deferred Count Half/Full" "0,1" bitfld.long 0x00 15. " MULTCOLG ,Tx Multiple collision (Good) Count Half/Full" "0,1" bitfld.long 0x00 14. " SNGCOLG ,Tx Single Collision (Good) Count Half/Full" "0,1" newline bitfld.long 0x00 13. " UNDERR ,Tx Underflow Error Count Half/Full" "0,1" bitfld.long 0x00 12. " BCASTGB ,Tx Broadcast Frames (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 11. " MCASTGB ,Tx Multicast Frames (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 10. " UCASTGB ,Tx Unicast Frames (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 9. " T1024TOMAX ,Tx 1024-to-max Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 8. " T512TO1023 ,Tx 512-to-1023 Octets (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 7. " T256TO511 ,Tx 256-to-511 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 6. " T128TO255 ,Tx 128-to-255 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 5. " T65TO127 ,Tx 65-to-127 Octets (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 4. " T64 ,Tx 64 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 3. " MCASTG ,Tx Multicast Frames (Good) Count Half/Full" "0,1" bitfld.long 0x00 2. " BCASTG ,Tx Broadcast Frames (Good) Count Half/Full" "0,1" newline bitfld.long 0x00 1. " FRCNTGB ,Tx Frame Count (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 0. " OCTCNTGB ,Tx Octet Count (Good/Bad) Count Half/Full" "0,1" group.long 0x10C++0x3 line.long 0x00 "EMAC0_MMC_RXIMSK,EMAC0 MMC Rx Interrupt Mask Register" bitfld.long 0x00 25. " CTLFIM ,Rx Control Frame Counter Interrupt Mask" "0,1" bitfld.long 0x00 24. " RCVERRFIM ,Rx Error Frame Counter Interrupt Mask" "0,1" bitfld.long 0x00 23. " WATCHERR ,Rx Watch Dog Error Count Half/Full Mask" "0,1" newline bitfld.long 0x00 22. " VLANFRGB ,Rx VLAN Frames (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 21. " FIFOOV ,Rx FIFO Overflow Count Half/Full Mask" "0,1" bitfld.long 0x00 20. " PAUSEFRM ,Rx Pause Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 19. " OUTRANGE ,Rx Out Of Range Type Count Half/Full Mask" "0,1" bitfld.long 0x00 18. " LENERR ,Rx Length Error Count Half/Full Mask" "0,1" bitfld.long 0x00 17. " UCASTG ,Rx Unicast Frames (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 16. " R1024TOMAX ,Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 15. " R512TO1023 ,Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 14. " R256TO511 ,Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 13. " R128TO255 ,Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 12. " R65TO127 ,Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 11. " R64 ,Rx 64 Octets (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 10. " OSIZEG ,Rx Oversize (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 9. " USIZEG ,Rx Undersize (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 8. " JABERR ,Rx Jabber Error Count Half/Full Mask" "0,1" newline bitfld.long 0x00 7. " RUNTERR ,Rx Runt Error Count Half/Full Mask" "0,1" bitfld.long 0x00 6. " ALIGNERR ,Rx Alignment Error Count Half/Full Mask" "0,1" bitfld.long 0x00 5. " CRCERR ,Rx CRC Error Count Half/Full Mask" "0,1" newline bitfld.long 0x00 4. " MCASTG ,Rx Multicast Frames (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 3. " BCASTG ,Rx Broadcast Frames (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 2. " OCTCNTG ,Rx Octet Count (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 1. " OCTCNTGB ,Rx Octet Count (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 0. " FRCNTGB ,Rx Frame Count (Good/Bad) Count Half/Full Mask" "0,1" group.long 0x110++0x3 line.long 0x00 "EMAC0_MMC_TXIMSK,EMAC0 MMC TX Interrupt Mask Register" bitfld.long 0x00 25. " OSZGFIM ,Tx Oversize Good Frame Count Interrupt Mask" "0,1" bitfld.long 0x00 24. " VLANFRG ,Tx VLAN Frames (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 23. " PAUSEFRM ,Tx Pause Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 22. " EXCESSDEF ,Tx Excess Deferred Count Half/Full Mask" "0,1" bitfld.long 0x00 21. " FRCNTG ,Tx Frame Count (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 20. " OCTCNTG ,Tx Octet Count (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 19. " CARRERR ,Tx Carrier Error Count Half/Full Mask" "0,1" bitfld.long 0x00 18. " EXCESSCOL ,Tx Excess collision Count Half/Full Mask" "0,1" bitfld.long 0x00 17. " LATECOL ,Tx Late Collision Count Half/Full Mask" "0,1" newline bitfld.long 0x00 16. " DEFERRED ,Tx Deferred Count Half/Full Mask" "0,1" bitfld.long 0x00 15. " MULTCOLG ,Tx Multiple Collisions (Good) Count Mask" "0,1" bitfld.long 0x00 14. " SNGCOLG ,Tx Single Collision (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 13. " UNDERR ,Tx Underflow Error Count Half/Full Mask" "0,1" bitfld.long 0x00 12. " BCASTGB ,Tx Broadcast Frames (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 11. " MCASTGB ,Tx Multicast Frames (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 10. " UCASTGB ,Tx Unicast Frames (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 9. " T1024TOMAX ,Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 8. " T512TO1023 ,Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 7. " T256TO511 ,Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 6. " T128TO255 ,Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 5. " T65TO127 ,Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 4. " T64 ,Tx 64 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 3. " MCASTG ,Tx Multicast Frames (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 2. " BCASTG ,Tx Broadcast Frames (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 1. " FRCNTGB ,Tx Frame Count (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 0. " OCTCNTGB ,Tx Octet Count (Good/Bad) Count Half/Full Mask" "0,1" group.long 0x114++0x3 line.long 0x00 "EMAC0_TXOCTCNT_GB,EMAC0 Tx OCT Count (Good/Bad) Register" group.long 0x118++0x3 line.long 0x00 "EMAC0_TXFRMCNT_GB,EMAC0 Tx Frame Count (Good/Bad) Register" group.long 0x11C++0x3 line.long 0x00 "EMAC0_TXBCASTFRM_G,EMAC0 Tx Broadcast Frames (Good) Register" group.long 0x120++0x3 line.long 0x00 "EMAC0_TXMCASTFRM_G,EMAC0 Tx Multicast Frames (Good) Register" group.long 0x124++0x3 line.long 0x00 "EMAC0_TX64_GB,EMAC0 Tx 64-Byte Frames (Good/Bad) Register" group.long 0x128++0x3 line.long 0x00 "EMAC0_TX65TO127_GB,EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register" group.long 0x12C++0x3 line.long 0x00 "EMAC0_TX128TO255_GB,EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register" group.long 0x130++0x3 line.long 0x00 "EMAC0_TX256TO511_GB,EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register" group.long 0x134++0x3 line.long 0x00 "EMAC0_TX512TO1023_GB,EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register" group.long 0x138++0x3 line.long 0x00 "EMAC0_TX1024TOMAX_GB,EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register" group.long 0x13C++0x3 line.long 0x00 "EMAC0_TXUCASTFRM_GB,EMAC0 Tx Unicast Frames (Good/Bad) Register" group.long 0x140++0x3 line.long 0x00 "EMAC0_TXMCASTFRM_GB,EMAC0 Tx Multicast Frames (Good/Bad) Register" group.long 0x144++0x3 line.long 0x00 "EMAC0_TXBCASTFRM_GB,EMAC0 Tx Broadcast Frames (Good/Bad) Register" group.long 0x148++0x3 line.long 0x00 "EMAC0_TXUNDR_ERR,EMAC0 Tx Underflow Error Register" group.long 0x14C++0x3 line.long 0x00 "EMAC0_TXSNGCOL_G,EMAC0 Tx Single Collision (Good) Register" group.long 0x150++0x3 line.long 0x00 "EMAC0_TXMULTCOL_G,EMAC0 Tx Multiple Collision (Good) Register" group.long 0x154++0x3 line.long 0x00 "EMAC0_TXDEFERRED,EMAC0 Tx Deferred Register" group.long 0x158++0x3 line.long 0x00 "EMAC0_TXLATECOL,EMAC0 Tx Late Collision Register" group.long 0x15C++0x3 line.long 0x00 "EMAC0_TXEXCESSCOL,EMAC0 Tx Excess Collision Register" group.long 0x160++0x3 line.long 0x00 "EMAC0_TXCARR_ERR,EMAC0 Tx Carrier Error Register" group.long 0x164++0x3 line.long 0x00 "EMAC0_TXOCTCNT_G,EMAC0 Tx Octet Count (Good) Register" group.long 0x168++0x3 line.long 0x00 "EMAC0_TXFRMCNT_G,EMAC0 Tx Frame Count (Good) Register" group.long 0x16C++0x3 line.long 0x00 "EMAC0_TXEXCESSDEF,EMAC0 Tx Excess Deferral Register" group.long 0x170++0x3 line.long 0x00 "EMAC0_TXPAUSEFRM,EMAC0 Tx Pause Frame Register" group.long 0x174++0x3 line.long 0x00 "EMAC0_TXVLANFRM_G,EMAC0 Tx VLAN Frames (Good) Register" group.long 0x178++0x3 line.long 0x00 "EMAC0_TXOVRSIZE_G,EMAC0 Number of Tx Frames (Good) greater than maxsize" group.long 0x180++0x3 line.long 0x00 "EMAC0_RXFRMCNT_GB,EMAC0 Rx Frame Count (Good/Bad) Register" group.long 0x184++0x3 line.long 0x00 "EMAC0_RXOCTCNT_GB,EMAC0 Rx Octet Count (Good/Bad) Register" group.long 0x188++0x3 line.long 0x00 "EMAC0_RXOCTCNT_G,EMAC0 Rx Octet Count (Good) Register" group.long 0x18C++0x3 line.long 0x00 "EMAC0_RXBCASTFRM_G,EMAC0 Rx Broadcast Frames (Good) Register" group.long 0x190++0x3 line.long 0x00 "EMAC0_RXMCASTFRM_G,EMAC0 Rx Multicast Frames (Good) Register" group.long 0x194++0x3 line.long 0x00 "EMAC0_RXCRC_ERR,EMAC0 Rx CRC Error Register" group.long 0x198++0x3 line.long 0x00 "EMAC0_RXALIGN_ERR,EMAC0 Rx alignment Error Register" group.long 0x19C++0x3 line.long 0x00 "EMAC0_RXRUNT_ERR,EMAC0 Rx Runt Error Register" group.long 0x1A0++0x3 line.long 0x00 "EMAC0_RXJAB_ERR,EMAC0 Rx Jab Error Register" group.long 0x1A4++0x3 line.long 0x00 "EMAC0_RXUSIZE_G,EMAC0 Rx Undersize (Good) Register" group.long 0x1A8++0x3 line.long 0x00 "EMAC0_RXOSIZE_G,EMAC0 Rx Oversize (Good) Register" group.long 0x1AC++0x3 line.long 0x00 "EMAC0_RX64_GB,EMAC0 Rx 64-Byte Frames (Good/Bad) Register" group.long 0x1B0++0x3 line.long 0x00 "EMAC0_RX65TO127_GB,EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register" group.long 0x1B4++0x3 line.long 0x00 "EMAC0_RX128TO255_GB,EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register" group.long 0x1B8++0x3 line.long 0x00 "EMAC0_RX256TO511_GB,EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register" group.long 0x1BC++0x3 line.long 0x00 "EMAC0_RX512TO1023_GB,EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register" group.long 0x1C0++0x3 line.long 0x00 "EMAC0_RX1024TOMAX_GB,EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register" group.long 0x1C4++0x3 line.long 0x00 "EMAC0_RXUCASTFRM_G,EMAC0 Rx Unicast Frames (Good) Register" group.long 0x1C8++0x3 line.long 0x00 "EMAC0_RXLEN_ERR,EMAC0 Rx Length Error Register" group.long 0x1CC++0x3 line.long 0x00 "EMAC0_RXOORTYPE,EMAC0 Rx Out Of Range Type Register" group.long 0x1D0++0x3 line.long 0x00 "EMAC0_RXPAUSEFRM,EMAC0 Rx Pause Frames Register" group.long 0x1D4++0x3 line.long 0x00 "EMAC0_RXFIFO_OVF,EMAC0 Rx FIFO Overflow Register" group.long 0x1D8++0x3 line.long 0x00 "EMAC0_RXVLANFRM_GB,EMAC0 Rx VLAN Frames (Good/Bad) Register" group.long 0x1DC++0x3 line.long 0x00 "EMAC0_RXWDOG_ERR,EMAC0 Rx Watch Dog Error Register" group.long 0x1E0++0x3 line.long 0x00 "EMAC0_RXRCV_ERR,EMAC0 Rx Error Frames Received Register" group.long 0x1E4++0x3 line.long 0x00 "EMAC0_RXCTLFRM_G,EMAC0 Rx Good Control Frames Register" group.long 0x200++0x3 line.long 0x00 "EMAC0_IPC_RXIMSK,EMAC0 MMC IPC Rx Interrupt Mask Register" bitfld.long 0x00 29. " ICMPERROCT ,Rx ICMP Error Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 28. " ICMPGOCT ,Rx ICMP (Good) Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 27. " TCPERROCT ,Rx TCP Error Octets Count Half/Full Mask" "0,1" newline bitfld.long 0x00 26. " TCPGOCT ,Rx TCP (Good) Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 25. " UDPERROCT ,Rx UDP Error Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 24. " UDPGOCT ,Rx UDP (Good) Octets Count Half/Full Mask" "0,1" newline bitfld.long 0x00 23. " V6NOPAYOCT ,Rx IPv6 No Payload Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 22. " V6HDERROCT ,Rx IPv6 Header Error Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 21. " V6GOCT ,Rx IPv6 (Good) Octets Count Half/Full Mask" "0,1" newline bitfld.long 0x00 20. " V4UDSBLOCT ,Rx IPv4 UDS Disable Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 19. " V4FRAGOCT ,Rx IPv4 Fragmented Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 18. " V4NOPAYOCT ,Rx IPv4 No Payload Octets Count Half/Full Mask" "0,1" newline bitfld.long 0x00 17. " V4HDERROCT ,Rx IPv4 Header Error Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 16. " V4GOCT ,Rx IPv4 (Good) Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 13. " ICMPERRFRM ,Rx ICMP Error Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 12. " ICMPGFRM ,Rx ICMP (Good) Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 11. " TCPERRFRM ,Rx TCP Error Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 10. " TCPGFRM ,Rx TCP (Good) Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 9. " UDPERRFRM ,Rx UDP Error Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 8. " UDPGFRM ,Rx UDP (Good) Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 7. " V6NOPAYFRM ,Rx IPv6 No Payload Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 6. " V6HDERRFRM ,Rx IPv6 Header Error Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 5. " V6GFRM ,Rx IPv6 (Good) Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 4. " V4UDSBLFRM ,Rx IPv4 UDS Disable Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 3. " V4FRAGFRM ,Rx IPv4 Fragmented Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 2. " V4NOPAYFRM ,Rx IPv4 No Payload Frame Count Half/Full Mask" "0,1" bitfld.long 0x00 1. " V4HDERRFRM ,Rx IPv4 Header Error Frame Count Half/Full Mask" "0,1" newline bitfld.long 0x00 0. " V4GFRM ,Rx IPv4 (Good) Frames Count Half/Full Mask" "0,1" group.long 0x208++0x3 line.long 0x00 "EMAC0_IPC_RXINT,EMAC0 MMC IPC Rx Interrupt Register" bitfld.long 0x00 29. " ICMPERROCT ,Rx ICMP Error Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 28. " ICMPGOCT ,Rx ICMP (Good) Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 27. " TCPERROCT ,Rx TCP Error Octets Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 26. " TCPGOCT ,Rx TCP (Good) Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 25. " UDPERROCT ,Rx UDP Error Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 24. " UDPGOCT ,Rx UDP (Good) Octets Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 23. " V6NOPAYOCT ,Rx IPv6 No Payload Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 22. " V6HDERROCT ,Rx IPv6 Header Error Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 21. " V6GOCT ,Rx IPv6 (Good) Octets Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 20. " V4UDSBLOCT ,Rx IPv4 UDS Disable Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 19. " V4FRAGOCT ,Rx IPv4 Fragmented Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 18. " V4NOPAYOCT ,Rx IPv4 No Payload Octets Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 17. " V4HDERROCT ,Rx IPv4 Header Error Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 16. " V4GOCT ,Rx IPv4 (Good) Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 13. " ICMPERRFRM ,Rx ICMP Error Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 12. " ICMPGFRM ,Rx ICMP (Good) Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 11. " TCPERRFRM ,Rx TCP Error Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 10. " TCPGFRM ,Rx TCP (Good) Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 9. " UDPERRFRM ,Rx IDP Error Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 8. " UDPGFRM ,Rx UDP (Good) Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 7. " V6NOPAYFRM ,Rx IPv6 No Payload Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 6. " V6HDERRFRM ,Rx IPv6 Header Error Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 5. " V6GFRM ,Rx IPv6 (Good) Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 4. " V4UDSBLFRM ,Rx IPv4 UDS Disable Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 3. " V4FRAGFRM ,Rx IPv4 Fragmented Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 2. " V4NOPAYFRM ,Rx IPv4 No Payload Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 1. " V4HDERRFRM ,Rx IPv4 Header Error Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 0. " V4GFRM ,Rx IPv4 (Good) Frames Count Half/Full Interrupt" "0,1" group.long 0x210++0x3 line.long 0x00 "EMAC0_RXIPV4_GD_FRM,EMAC0 Rx IPv4 Datagrams (Good) Register" group.long 0x214++0x3 line.long 0x00 "EMAC0_RXIPV4_HDR_ERR_FRM,EMAC0 Rx IPv4 Datagrams Header Errors Register" group.long 0x218++0x3 line.long 0x00 "EMAC0_RXIPV4_NOPAY_FRM,EMAC0 Rx IPv4 Datagrams No Payload Frame Register" group.long 0x21C++0x3 line.long 0x00 "EMAC0_RXIPV4_FRAG_FRM,EMAC0 Rx IPv4 Datagrams Fragmented Frames Register" group.long 0x220++0x3 line.long 0x00 "EMAC0_RXIPV4_UDSBL_FRM,EMAC0 Rx IPv4 UDP Disabled Frames Register" group.long 0x224++0x3 line.long 0x00 "EMAC0_RXIPV6_GD_FRM,EMAC0 Rx IPv6 Datagrams Good Frames Register" group.long 0x228++0x3 line.long 0x00 "EMAC0_RXIPV6_HDR_ERR_FRM,EMAC0 Rx IPv6 Datagrams Header Error Frames Register" group.long 0x22C++0x3 line.long 0x00 "EMAC0_RXIPV6_NOPAY_FRM,EMAC0 Rx IPv6 Datagrams No Payload Frames Register" group.long 0x230++0x3 line.long 0x00 "EMAC0_RXUDP_GD_FRM,EMAC0 Rx UDP Good Frames Register" group.long 0x234++0x3 line.long 0x00 "EMAC0_RXUDP_ERR_FRM,EMAC0 Rx UDP Error Frames Register" group.long 0x238++0x3 line.long 0x00 "EMAC0_RXTCP_GD_FRM,EMAC0 Rx TCP Good Frames Register" group.long 0x23C++0x3 line.long 0x00 "EMAC0_RXTCP_ERR_FRM,EMAC0 Rx TCP Error Frames Register" group.long 0x240++0x3 line.long 0x00 "EMAC0_RXICMP_GD_FRM,EMAC0 Rx ICMP Good Frames Register" group.long 0x244++0x3 line.long 0x00 "EMAC0_RXICMP_ERR_FRM,EMAC0 Rx ICMP Error Frames Register" group.long 0x250++0x3 line.long 0x00 "EMAC0_RXIPV4_GD_OCT,EMAC0 Rx IPv4 Datagrams Good Octets Register" group.long 0x254++0x3 line.long 0x00 "EMAC0_RXIPV4_HDR_ERR_OCT,EMAC0 Rx IPv4 Datagrams Header Errors Register" group.long 0x258++0x3 line.long 0x00 "EMAC0_RXIPV4_NOPAY_OCT,EMAC0 Rx IPv4 Datagrams No Payload Octets Register" group.long 0x25C++0x3 line.long 0x00 "EMAC0_RXIPV4_FRAG_OCT,EMAC0 Rx IPv4 Datagrams Fragmented Octets Register" group.long 0x260++0x3 line.long 0x00 "EMAC0_RXIPV4_UDSBL_OCT,EMAC0 Rx IPv4 UDP Disabled Octets Register" group.long 0x264++0x3 line.long 0x00 "EMAC0_RXIPV6_GD_OCT,EMAC0 Rx IPv6 Good Octets Register" group.long 0x268++0x3 line.long 0x00 "EMAC0_RXIPV6_HDR_ERR_OCT,EMAC0 Rx IPv6 Header Errors Register" group.long 0x26C++0x3 line.long 0x00 "EMAC0_RXIPV6_NOPAY_OCT,EMAC0 Rx IPv6 No Payload Octets Register" group.long 0x270++0x3 line.long 0x00 "EMAC0_RXUDP_GD_OCT,EMAC0 Rx UDP Good Octets Register" group.long 0x274++0x3 line.long 0x00 "EMAC0_RXUDP_ERR_OCT,EMAC0 Rx UDP Error Octets Register" group.long 0x278++0x3 line.long 0x00 "EMAC0_RXTCP_GD_OCT,EMAC0 Rx TCP Good Octets Register" group.long 0x27C++0x3 line.long 0x00 "EMAC0_RXTCP_ERR_OCT,EMAC0 Rx TCP Error Octets Register" group.long 0x280++0x3 line.long 0x00 "EMAC0_RXICMP_GD_OCT,EMAC0 Rx ICMP Good Octets Register" group.long 0x284++0x3 line.long 0x00 "EMAC0_RXICMP_ERR_OCT,EMAC0 Rx ICMP Error Octets Register" group.long 0x400++0x3 line.long 0x00 "EMAC0_L3L4_CTL,EMAC0 Layer3 and Layer4 Control Register" bitfld.long 0x00 21. " L4DPIM ,Layer 4 Destination Port Inverse Matching" "0,1" bitfld.long 0x00 20. " L4DPM ,Layer 4 Destination Port Matching" "0,1" bitfld.long 0x00 19. " L4SPIM ,Layer 4 Source Port Inverse Matching" "0,1" newline bitfld.long 0x00 18. " L4SPM ,Layer 4 Source Port Matching" "0,1" bitfld.long 0x00 16. " L4PEN ,Layer 4 Filtering Enable" "0,1" bitfld.long 0x00 11.--15. " L3HDBM ,Layer 3 Destination Address Bits Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--10. " L3HSBM ,Layer 3 Source Address Bits Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " L3DAIM ,Layer 3 Destination Address Inverse Matching" "0,1" bitfld.long 0x00 4. " L3DAM ,Layer 3 Destination Address Matching" "0,1" newline bitfld.long 0x00 3. " L3SAIM ,Layer 3 Source Address Inverse Matching" "0,1" bitfld.long 0x00 2. " L3SAM ,Layer 3 Source Address Matching" "0,1" bitfld.long 0x00 0. " L3PEN ,Layer 3 Enabled" "0,1" group.long 0x404++0x3 line.long 0x00 "EMAC0_L4_ADDR,EMAC0 Layer 4 Address Register" hexmask.long.word 0x00 16.--31. 1. " L4DP ,Layer 4 Destination Port" hexmask.long.word 0x00 0.--15. 1. " L4SP ,Layer 4 Source Port" group.long 0x410++0x3 line.long 0x00 "EMAC0_L3_ADDR0,EMAC0 Layer 3 Address0 Register" group.long 0x414++0x3 line.long 0x00 "EMAC0_L3_ADDR1,EMAC0 Layer 3 Address1 Register" group.long 0x418++0x3 line.long 0x00 "EMAC0_L3_ADDR2,EMAC0 Layer 3 Address2 Register" group.long 0x41C++0x3 line.long 0x00 "EMAC0_L3_ADDR3,EMAC0 Layer 3 Address3 Register" group.long 0x584++0x3 line.long 0x00 "EMAC0_VLAN_INCL,EMAC0 VLAN Tag Inclusion or Replacement Register" bitfld.long 0x00 19. " CSVL ,C-VLAN or S-VLAN" "0,1" bitfld.long 0x00 18. " VLP ,VLAN Priority Control" "0,1" bitfld.long 0x00 16.--17. " VLC ,VLAN Tag Control in Transmit Frames" "0,1,2,3" newline hexmask.long.word 0x00 0.--15. 1. " VLT ,VLAN Tag for Transmit Frames" group.long 0x588++0x3 line.long 0x00 "EMAC0_VLAN_HSHTBL,EMAC0 VLAN Hash Table Register" hexmask.long.word 0x00 0.--15. 1. " VLHT ,VLAN Hash Table" group.long 0x700++0x3 line.long 0x00 "EMAC0_TM_CTL,EMAC0 Time Stamp Control Register" bitfld.long 0x00 28. " ATSEN3 ,Auxiliary Snapshot 3 Enable" "0,1" bitfld.long 0x00 27. " ATSEN2 ,Auxiliary Snapshot 2 Enable" "0,1" bitfld.long 0x00 26. " ATSEN1 ,Auxiliary Snapshot 1 Enable" "0,1" newline bitfld.long 0x00 25. " ATSEN0 ,Auxiliary Snapshot 0 Enable" "0,1" bitfld.long 0x00 24. " ATSFC ,Auxiliary Time Stamp FIFO Clear" "0,1" bitfld.long 0x00 18. " TSENMACADDR ,Time Stamp Enable MAC Address" "0,1" newline bitfld.long 0x00 16.--17. " SNAPTYPSEL ,Snapshot Type Select" "0,1,2,3" bitfld.long 0x00 15. " TSMSTRENA ,Time Stamp Master (Frames) Enable" "0,1" bitfld.long 0x00 14. " TSEVNTENA ,Time Stamp Event (PTP Frames) Enable" "0,1" newline bitfld.long 0x00 13. " TSIPV4ENA ,Time Stamp IPV4 (PTP Frames) Enable" "0,1" bitfld.long 0x00 12. " TSIPV6ENA ,Time Stamp IPV6 (PTP Frames) Enable" "0,1" bitfld.long 0x00 11. " TSIPENA ,Time Stamp IP Enable" "0,1" newline bitfld.long 0x00 10. " TSVER2ENA ,Time Stamp VER2 (Snooping) Enable" "0,1" bitfld.long 0x00 9. " TSCTRLSSR ,Time Stamp Control Nanosecond Rollover" "0,1" bitfld.long 0x00 8. " TSENALL ,Time Stamp Enable All (Frames)" "0,1" newline bitfld.long 0x00 5. " TSADDREG ,Time Stamp Addend Register Update" "0,1" bitfld.long 0x00 4. " TSTRIG ,Time Stamp (Target Time) Trigger Enable" "0,1" bitfld.long 0x00 3. " TSUPDT ,Time Stamp (System Time) Update" "0,1" newline bitfld.long 0x00 2. " TSINIT ,Time Stamp (System Time) Initialize" "0,1" bitfld.long 0x00 1. " TSCFUPDT ,Time Stamp (System Time) Fine/Coarse Update" "0,1" bitfld.long 0x00 0. " TSENA ,Time Stamp (PTP) Enable" "0,1" group.long 0x704++0x3 line.long 0x00 "EMAC0_TM_SUBSEC,EMAC0 Time Stamp Sub Second Increment Register" hexmask.long.byte 0x00 0.--7. 1. " SSINC ,Sub-Second Increment Value" group.long 0x708++0x3 line.long 0x00 "EMAC0_TM_SEC,EMAC0 Time Stamp Low Seconds Register" group.long 0x70C++0x3 line.long 0x00 "EMAC0_TM_NSEC,EMAC0 Time Stamp Nanoseconds Register" hexmask.long 0x00 0.--30. 1. " TSSS ,Time Stamp Nanoseconds" group.long 0x710++0x3 line.long 0x00 "EMAC0_TM_SECUPDT,EMAC0 Time Stamp Seconds Update Register" group.long 0x714++0x3 line.long 0x00 "EMAC0_TM_NSECUPDT,EMAC0 Time Stamp Nanoseconds Update Register" bitfld.long 0x00 31. " ADDSUB ,Add or Subtract the Time" "0,1" hexmask.long 0x00 0.--30. 1. " TSSS ,Time Stamp Sub Second Initialize/Increment" group.long 0x718++0x3 line.long 0x00 "EMAC0_TM_ADDEND,EMAC0 Time Stamp Addend Register" group.long 0x71C++0x3 line.long 0x00 "EMAC0_TM_PPS0TGTM,EMAC0 Time Stamp Target Time Seconds Register" group.long 0x720++0x3 line.long 0x00 "EMAC0_TM_PPS0NTGTM,EMAC0 Time Stamp Target Time Nanoseconds Register" bitfld.long 0x00 31. " TSTRBUSY ,Target Time Register Busy" "0,1" hexmask.long 0x00 0.--30. 1. " TSTR ,Target Time Nano Seconds" group.long 0x724++0x3 line.long 0x00 "EMAC0_TM_HISEC,EMAC0 Time Stamp High Second Register" hexmask.long.word 0x00 0.--15. 1. " TSHWR ,Time Stamp Higher Word Seconds Register" group.long 0x728++0x3 line.long 0x00 "EMAC0_TM_STMPSTAT,EMAC0 Time Stamp Status Register" bitfld.long 0x00 25.--27. " ATSNS ,Auxiliary Time Stamp Number of Snapshots" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. " ATSSTM ,Auxiliary Time Stamp Snapshot Trigger Missed" "0,1" bitfld.long 0x00 16.--19. " ATSSTN ,Auxiliary Timestamp Snapshot Trigger Identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 9. " TSTRGTERR3 ,Timestamp Target Time Error 3" "0,1" bitfld.long 0x00 8. " TSTARGT3 ,Timestamp Target Time Reached for Target Time PPS3" "0,1" bitfld.long 0x00 7. " TSTRGTERR2 ,Timestamp Target Time Error 2" "0,1" newline bitfld.long 0x00 6. " TSTARGT2 ,Timestamp Target Time Reached for Target Time PPS2" "0,1" bitfld.long 0x00 5. " TSTRGTERR1 ,Timestamp Target Time Error 1" "0,1" bitfld.long 0x00 4. " TSTARGT1 ,Timestamp Target Time Reached for Target Time PPS1" "0,1" newline bitfld.long 0x00 3. " TSTRGTERR0 ,Time Stamp Target Time Programming Error" "0,1" bitfld.long 0x00 2. " ATSTS ,Auxiliary Time Stamp Trigger Snapshot" "0,1" bitfld.long 0x00 1. " TSTARGT0 ,Time Stamp Target Time Reached" "0,1" newline bitfld.long 0x00 0. " TSSOVF ,Time Stamp Seconds Overflow" "0,1" group.long 0x72C++0x3 line.long 0x00 "EMAC0_TM_PPSCTL,EMAC0 PPS Control Register" bitfld.long 0x00 29.--30. " TRGTMODSEL3 ,Target Time Register Mode for PPS3" "0,1,2,3" bitfld.long 0x00 24.--26. " PPSCMD3 ,Flexible PPS3 Output Control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--22. " TRGTMODSEL2 ,Target Time Register Mode for PPS2" "0,1,2,3" newline bitfld.long 0x00 16.--18. " PPSCMD2 ,Flexible PPS2 Output Control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13.--14. " TRGTMODSEL1 ,Target Time Register Mode for PPS1" "0,1,2,3" bitfld.long 0x00 8.--10. " PPSCMD1 ,Flexible PPS1 Output Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5.--6. " TRGTMODSEL0 ,Target Time Register Mode" "0,1,2,3" bitfld.long 0x00 4. " PPSEN ,Enable the flexible PPS output mode" "0,1" bitfld.long 0x00 0.--3. " PPSCTL0 ,PPS Frequency Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x730++0x3 line.long 0x00 "EMAC0_TM_AUXSTMP_NSEC,EMAC0 Time Stamp Auxiliary TS Nano Seconds Register" group.long 0x734++0x3 line.long 0x00 "EMAC0_TM_AUXSTMP_SEC,EMAC0 Time Stamp Auxiliary TM Seconds Register" group.long 0x738++0x3 line.long 0x00 "EMAC0_MAC_AVCTL,EMAC0 AV MAC Control Register" bitfld.long 0x00 24.--25. " PTPCH ,Channel for Queuing the PTP Packets" "0,1,2,3" bitfld.long 0x00 21.--22. " AVCH ,Channel for Queuing AV Control Packets" "0,1,2,3" bitfld.long 0x00 20. " AVCD ,AV Channel Disable" "0,1" newline bitfld.long 0x00 19. " VQE ,VLAN Tagged non-AV packets queuing enable" "0,1" bitfld.long 0x00 16.--18. " AVP ,AV Priority for Queuing" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. " AVT ,AV Ether Type Value" group.long 0x760++0x3 line.long 0x00 "EMAC0_TM_PPS0INTVL,EMAC0 Time Stamp PPS Interval Register" group.long 0x764++0x3 line.long 0x00 "EMAC0_TM_PPS0WIDTH,EMAC0 PPS Width Register" group.long 0x780++0x3 line.long 0x00 "EMAC0_TM_PPS1TGTM,EMAC0 PPS 1 Target Time Seconds Register" group.long 0x784++0x3 line.long 0x00 "EMAC0_TM_PPS1NTGTM,EMAC0 PPS 1 Target Time Nanoseconds Register" bitfld.long 0x00 31. " TSTRBUSY ,Target-Time Register" "0,1" hexmask.long 0x00 0.--30. 1. " TSTR ,Target-Time Low Register" group.long 0x788++0x3 line.long 0x00 "EMAC0_TM_PPS1INTVL,EMAC0 PPS 1 Interval Register" group.long 0x78C++0x3 line.long 0x00 "EMAC0_TM_PPS1WIDTH,EMAC0 PPS 1 Width Register" group.long 0x7A0++0x3 line.long 0x00 "EMAC0_TM_PPS2TGTM,EMAC0 PPS 2 Target Time Seconds Register" group.long 0x7A4++0x3 line.long 0x00 "EMAC0_TM_PPS2NTGTM,EMAC0 PPS 2 Target Time Nanoseconds Register" bitfld.long 0x00 31. " TSTRBUSY ,Target time register" "0,1" hexmask.long 0x00 0.--30. 1. " TSTR ,Target Time Low Register" group.long 0x7A8++0x3 line.long 0x00 "EMAC0_TM_PPS2INTVL,EMAC0 PPS 2 Interval Register" group.long 0x7AC++0x3 line.long 0x00 "EMAC0_TM_PPS2WIDTH,EMAC0 PPS 2 Width Register" group.long 0x7C0++0x3 line.long 0x00 "EMAC0_TM_PPS3TGTM,EMAC0 PPS 3 Target Time Seconds Register" group.long 0x7C4++0x3 line.long 0x00 "EMAC0_TM_PPS3NTGTM,EMAC0 PPS 3 Target Time Nanoseconds Register" bitfld.long 0x00 31. " TSTRBUSY ,Target Time Register" "0,1" hexmask.long 0x00 0.--30. 1. " TSTR ,Target Time Low Register" group.long 0x7C8++0x3 line.long 0x00 "EMAC0_TM_PPS3INTVL,EMAC0 PPS 3 Interval Register" group.long 0x7CC++0x3 line.long 0x00 "EMAC0_TM_PPS3WIDTH,EMAC0 PPS 3 Width Register" group.long 0x1000++0x3 line.long 0x00 "EMAC0_DMA0_BUSMODE,EMAC0 DMA Bus Mode Register" bitfld.long 0x00 25. " AAL ,Address Aligned Bursts" "0,1" bitfld.long 0x00 24. " PBL8 ,PBL * 8" "0,1" bitfld.long 0x00 23. " USP ,Use Separate PBL" "0,1" newline bitfld.long 0x00 17.--22. " RPBL ,Receive Programmable Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16. " FB ,Fixed Burst" "0,1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "0,1" bitfld.long 0x00 2.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " SWR ,Software Reset" "0,1" group.long 0x1004++0x3 line.long 0x00 "EMAC0_DMA0_TXPOLL,EMAC0 DMA Tx Poll Demand Register" group.long 0x1008++0x3 line.long 0x00 "EMAC0_DMA0_RXPOLL,EMAC0 DMA Rx Poll Demand register" group.long 0x100C++0x3 line.long 0x00 "EMAC0_DMA0_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register" group.long 0x1010++0x3 line.long 0x00 "EMAC0_DMA0_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register" group.long 0x1014++0x3 line.long 0x00 "EMAC0_DMA0_STAT,EMAC0 DMA Status Register" bitfld.long 0x00 30. " GLPII ,GMAC LPI Interrupt" "0,1" bitfld.long 0x00 29. " TTI ,Time Stamp Trigger Interrupt" "0,1" bitfld.long 0x00 27. " MCI ,MAC MMC Interrupt" "0,1" newline bitfld.long 0x00 26. " GLI ,Line Interface Interrupt" "0,1" bitfld.long 0x00 23.--25. " EB ,Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " TS ,Tx Process State" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17.--19. " RS ,Rx Process State" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16. " NIS ,Normal Interrupt Summary" "0,1" bitfld.long 0x00 15. " AIS ,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x00 14. " ERI ,Early Receive Interrupt" "0,1" bitfld.long 0x00 13. " FBI ,Fatal Bus Error Interrupt" "0,1" bitfld.long 0x00 10. " ETI ,Early Transmit Interrupt" "0,1" newline bitfld.long 0x00 9. " RWT ,Receive WatchDog Timeout" "0,1" bitfld.long 0x00 8. " RPS ,Receive Process Stopped" "0,1" bitfld.long 0x00 7. " RU ,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x00 6. " RI ,Receive Interrupt" "0,1" bitfld.long 0x00 5. " UNF ,Transmit Buffer Underflow" "0,1" bitfld.long 0x00 4. " OVF ,Receive Buffer Overflow" "0,1" newline bitfld.long 0x00 3. " TJT ,Transmit Jabber Timeout" "0,1" bitfld.long 0x00 2. " TU ,Transmit Buffer Unavailable" "0,1" bitfld.long 0x00 1. " TPS ,Transmit Process Stopped" "0,1" newline bitfld.long 0x00 0. " TI ,Transmit Interrupt" "0,1" group.long 0x1018++0x3 line.long 0x00 "EMAC0_DMA0_OPMODE,EMAC0 DMA Operation Mode Register" bitfld.long 0x00 26. " DT ,Disable Dropping TCP/IP Errors" "0,1" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "0,1" bitfld.long 0x00 24. " DFF ,Disable Flushing of received Frames" "0,1" newline bitfld.long 0x00 21. " TSF ,Transmit Store and Forward" "0,1" bitfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "0,1" bitfld.long 0x00 14.--16. " TTC ,Transmit Threshold Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 13. " ST ,Start/Stop Transmission" "0,1" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "0,1" bitfld.long 0x00 6. " FUF ,Forward Undersized good Frames" "0,1" newline bitfld.long 0x00 5. " DGF ,Drop Gaint Frames" "0,1" bitfld.long 0x00 3.--4. " RTC ,Receive Threshold Control" "0,1,2,3" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "0,1" newline bitfld.long 0x00 1. " SR ,Start/Stop Receive" "0,1" group.long 0x101C++0x3 line.long 0x00 "EMAC0_DMA0_IEN,EMAC0 DMA Interrupt Enable Register" bitfld.long 0x00 16. " NIE ,Normal Interrupt Summary Enable" "0,1" bitfld.long 0x00 15. " AIE ,Abnormal Interrupt Summary Enable" "0,1" bitfld.long 0x00 14. " ERE ,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 13. " FBE ,Fatal Bus Error Enable" "0,1" bitfld.long 0x00 10. " ETE ,Early Transmit Interrupt Enable" "0,1" bitfld.long 0x00 9. " RWE ,Receive WatchdogTimeout Enable" "0,1" newline bitfld.long 0x00 8. " RSE ,Receive Stopped Enable" "0,1" bitfld.long 0x00 7. " RUE ,Receive Buffer Unavailable Enable" "0,1" bitfld.long 0x00 6. " RIE ,Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 5. " UNE ,Underflow Interrupt Enable" "0,1" bitfld.long 0x00 4. " OVE ,Overflow Interrupt Enable" "0,1" bitfld.long 0x00 3. " TJE ,Transmit Jabber Timeout Enable" "0,1" newline bitfld.long 0x00 2. " TUE ,Transmit Buffer Unavailable Enable" "0,1" bitfld.long 0x00 1. " TSE ,Transmit Stopped Enable" "0,1" bitfld.long 0x00 0. " TIE ,Transmit Interrupt Enable" "0,1" group.long 0x1020++0x3 line.long 0x00 "EMAC0_DMA0_MISS_FRM,EMAC0 DMA Missed Frame Register" bitfld.long 0x00 28. " OVFFIFO ,Overflow bit for FIFO Overflow Counter" "0,1" hexmask.long.word 0x00 17.--27. 1. " MISSFROV ,Missed Frames Buffer Overflow" bitfld.long 0x00 16. " OVFMISS ,Overflow bit for Missed Frame Counter" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " MISSFRUN ,Missed Frames Unavailable Buffer" group.long 0x1024++0x3 line.long 0x00 "EMAC0_DMA0_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register" hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI WatchDog Timer Count" group.long 0x1028++0x3 line.long 0x00 "EMAC0_DMA0_BMMODE,EMAC0 DMA SCB Bus Mode Register" bitfld.long 0x00 31. " ENLPI ,Enable Low Power Interface" "0,1" bitfld.long 0x00 20.--22. " WROSRLMT ,SCB Maximum Write Outstanding Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " RDOSRLMT ,SCB Maximum Read Outstanding Request" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 13. " ONEKBBE ,1K Boundary Crossing Enable" "0,1" bitfld.long 0x00 12. " AAL ,Address Aligned Beats" "0,1" bitfld.long 0x00 3. " BLEN16 ,SCB Burst Length 16" "0,1" newline bitfld.long 0x00 2. " BLEN8 ,SCB Burst Length 8" "0,1" bitfld.long 0x00 1. " BLEN4 ,SCB Burst Length 4" "0,1" bitfld.long 0x00 0. " UNDEF ,SCB Undefined Burst Length" "0,1" group.long 0x102C++0x3 line.long 0x00 "EMAC0_DMA0_BMSTAT,EMAC0 DMA SCB Status Register" bitfld.long 0x00 1. " BUSRD ,Bus (SCB master) Read Active" "0,1" bitfld.long 0x00 0. " BUSWR ,Bus (SCB master) Write Active" "0,1" group.long 0x1048++0x3 line.long 0x00 "EMAC0_DMA0_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register" group.long 0x104C++0x3 line.long 0x00 "EMAC0_DMA0_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register" group.long 0x1050++0x3 line.long 0x00 "EMAC0_DMA0_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register" group.long 0x1054++0x3 line.long 0x00 "EMAC0_DMA0_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register" group.long 0x1100++0x3 line.long 0x00 "EMAC0_DMA1_BUSMODE,EMAC0 DMA Bus Mode Register" bitfld.long 0x00 25. " AAL ,Address Aligned Bursts" "0,1" bitfld.long 0x00 24. " PBL8 ,PBL * 8" "0,1" bitfld.long 0x00 23. " USP ,Use Separate PBL" "0,1" newline bitfld.long 0x00 17.--22. " RPBL ,Receive Programmable Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16. " FB ,Fixed Burst" "0,1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "0,1" bitfld.long 0x00 2.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1104++0x3 line.long 0x00 "EMAC0_DMA1_TXPOLL,EMAC0 DMA Tx Poll Demand Register" group.long 0x1108++0x3 line.long 0x00 "EMAC0_DMA1_RXPOLL,EMAC0 DMA Rx Poll Demand Register" group.long 0x110C++0x3 line.long 0x00 "EMAC0_DMA1_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register" group.long 0x1110++0x3 line.long 0x00 "EMAC0_DMA1_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register" group.long 0x1114++0x3 line.long 0x00 "EMAC0_DMA1_STAT,EMAC0 DMA Status Register" bitfld.long 0x00 30. " GTMSI ,MAC TMS Interrupt" "0,1" bitfld.long 0x00 29. " TTI ,Time Stamp Trigger Interrupt" "0,1" bitfld.long 0x00 27. " MCI ,MAC MMC Interrupt" "0,1" newline bitfld.long 0x00 26. " GLI ,Line Interface Interrupt" "0,1" bitfld.long 0x00 23.--25. " EB ,Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " TS ,Tx Process State" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17.--19. " RS ,Rx Process State" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16. " NIS ,Normal Interrupt Summary" "0,1" bitfld.long 0x00 15. " AIS ,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x00 14. " ERI ,Early Receive Interrupt" "0,1" bitfld.long 0x00 13. " FBI ,Fatal Bus Error Interrupt" "0,1" bitfld.long 0x00 10. " ETI ,Early Transmit Interrupt" "0,1" newline bitfld.long 0x00 9. " RWT ,Receive WatchDog Timeout" "0,1" bitfld.long 0x00 8. " RPS ,Receive Process Stopped" "0,1" bitfld.long 0x00 7. " RU ,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x00 6. " RI ,Receive Interrupt" "0,1" bitfld.long 0x00 5. " UNF ,Transmit Buffer Underflow" "0,1" bitfld.long 0x00 4. " OVF ,Receive Buffer Overflow" "0,1" newline bitfld.long 0x00 3. " TJT ,Transmit Jabber Timeout" "0,1" bitfld.long 0x00 2. " TU ,Transmit Buffer Unavailable" "0,1" bitfld.long 0x00 1. " TPS ,Transmit Process Stopped" "0,1" newline bitfld.long 0x00 0. " TI ,Transmit Interrupt" "0,1" group.long 0x1118++0x3 line.long 0x00 "EMAC0_DMA1_OPMODE,EMAC0 DMA Operation Mode Register" bitfld.long 0x00 26. " DT ,Disable Dropping TCP/IP Errors" "0,1" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "0,1" bitfld.long 0x00 24. " DFF ,Disable Flushing of received Frames" "0,1" newline bitfld.long 0x00 21. " TSF ,Transmit Store and Forward" "0,1" bitfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "0,1" bitfld.long 0x00 14.--16. " TTC ,Transmit Threshold Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 13. " ST ,Start/Stop Transmission" "0,1" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "0,1" bitfld.long 0x00 6. " FUF ,Forward Undersized Good Frames" "0,1" newline bitfld.long 0x00 5. " DGF ,Drop Giant Frames" "0,1" bitfld.long 0x00 3.--4. " RTC ,Receive Threshold Control" "0,1,2,3" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "0,1" newline bitfld.long 0x00 1. " SR ,Start/Stop Receive" "0,1" group.long 0x111C++0x3 line.long 0x00 "EMAC0_DMA1_IEN,EMAC0 DMA Interrupt Enable Register" bitfld.long 0x00 16. " NIE ,Normal Interrupt Summary Enable" "0,1" bitfld.long 0x00 15. " AIE ,Abnormal Interrupt Summary Enable" "0,1" bitfld.long 0x00 14. " ERE ,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 13. " FBE ,Fatal Bus Error Enable" "0,1" bitfld.long 0x00 10. " ETE ,Early Transmit Interrupt Enable" "0,1" bitfld.long 0x00 9. " RWE ,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0x00 8. " RSE ,Receive Stopped Enable" "0,1" bitfld.long 0x00 7. " RUE ,Receive Buffer Unavailable Enable" "0,1" bitfld.long 0x00 6. " RIE ,Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 5. " UNE ,Underflow Interrupt Enable" "0,1" bitfld.long 0x00 4. " OVE ,Overflow Interrupt Enable" "0,1" bitfld.long 0x00 3. " TJE ,Transmit Jabber Timeout Enable" "0,1" newline bitfld.long 0x00 2. " TUE ,Transmit Buffer Unavailable Enable" "0,1" bitfld.long 0x00 1. " TSE ,Transmit Stopped Enable" "0,1" bitfld.long 0x00 0. " TIE ,Transmit Interrupt Enable" "0,1" group.long 0x1120++0x3 line.long 0x00 "EMAC0_DMA1_MISS_FRM,EMAC0 DMA Missed Frame Register" bitfld.long 0x00 28. " OVFFIFO ,Overflow bit for FIFO Overflow Counter" "0,1" hexmask.long.word 0x00 17.--27. 1. " MISSFROV ,Missed Frames Buffer Overflow" bitfld.long 0x00 16. " OVFMISS ,Overflow bit for Missed Frame Counter" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " MISSFRUN ,Missed Frames Unavailable Buffer" group.long 0x1124++0x3 line.long 0x00 "EMAC0_DMA1_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register" hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI Watch Dog Timer Count" group.long 0x1130++0x3 line.long 0x00 "EMAC0_DMA1_CHSFCS,EMAC0 Channel 1 Control Bits for Slot Function Register" bitfld.long 0x00 16.--19. " RSN ,Reference Slot Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " ASC ,Advance Slot Check" "0,1" bitfld.long 0x00 0. " ESC ,Enable Slot Comparison" "0,1" group.long 0x1148++0x3 line.long 0x00 "EMAC0_DMA1_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register" group.long 0x114C++0x3 line.long 0x00 "EMAC0_DMA1_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register" group.long 0x1150++0x3 line.long 0x00 "EMAC0_DMA1_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register" group.long 0x1154++0x3 line.long 0x00 "EMAC0_DMA1_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register" group.long 0x1160++0x3 line.long 0x00 "EMAC0_DMA1_CHCBSCTL,EMAC0 Channel 1 Credit Shaping Control Register" bitfld.long 0x00 17. " ABPSSIE ,Average Bits Per Slot Interrupt Enable" "0,1" bitfld.long 0x00 4.--6. " SLC ,Slot Count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " CC ,Credit Control" "0,1" newline bitfld.long 0x00 0. " CBSD ,Credit based shaper disable" "0,1" group.long 0x1164++0x3 line.long 0x00 "EMAC0_DMA1_CHCBSSTAT,EMAC0 Channel 1 Average Traffic Transmitted Register" bitfld.long 0x00 17. " ABSU ,ABS Updated" "0,1" hexmask.long.tbyte 0x00 0.--16. 1. " ABS ,Average Bits Per Slot" group.long 0x1168++0x3 line.long 0x00 "EMAC0_DMA1_CHISC,EMAC0 Channel 1 Idle Slope Credit Value Register" hexmask.long.word 0x00 0.--13. 1. " ISC ,Idle Slope Credit" group.long 0x116C++0x3 line.long 0x00 "EMAC0_DMA1_CHSSC,EMAC0 Channel 1 Send Slope Credit Value Register" hexmask.long.word 0x00 0.--13. 1. " SSC ,Send Slope Credit" group.long 0x1170++0x3 line.long 0x00 "EMAC0_DMA1_CHHIC,EMAC0 Channel 1 High Credit Value Register" hexmask.long 0x00 0.--28. 1. " HC ,High Credit" group.long 0x1174++0x3 line.long 0x00 "EMAC0_DMA1_CHLOC,EMAC0 Channel 1 Low Credit Value Register" hexmask.long 0x00 0.--28. 1. " LC ,Low Credit" group.long 0x1200++0x3 line.long 0x00 "EMAC0_DMA2_BUSMODE,EMAC0 DMA Bus Mode Register" bitfld.long 0x00 25. " AAL ,Address Aligned Bursts" "0,1" bitfld.long 0x00 24. " PBL8 ,PBL * 8" "0,1" bitfld.long 0x00 23. " USP ,Use Separate PBL" "0,1" newline bitfld.long 0x00 17.--22. " RPBL ,Receive Programmable Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16. " FB ,Fixed Burst" "0,1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "0,1" bitfld.long 0x00 2.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " SWR ,Software Reset" "0,1" group.long 0x1204++0x3 line.long 0x00 "EMAC0_DMA2_TXPOLL,EMAC0 DMA Tx Poll Demand Register" group.long 0x1208++0x3 line.long 0x00 "EMAC0_DMA2_RXPOLL,EMAC0 DMA Rx Poll Demand register" group.long 0x120C++0x3 line.long 0x00 "EMAC0_DMA2_RXDSC_ADDR,EMAC0 DMA Rx Descriptor List Address Register" group.long 0x1210++0x3 line.long 0x00 "EMAC0_DMA2_TXDSC_ADDR,EMAC0 DMA Tx Descriptor List Address Register" group.long 0x1214++0x3 line.long 0x00 "EMAC0_DMA2_STAT,EMAC0 DMA Status Register" bitfld.long 0x00 30. " GTMSI ,MAC TMS Interrupt" "0,1" bitfld.long 0x00 29. " TTI ,Time Stamp Trigger Interrupt" "0,1" bitfld.long 0x00 27. " MCI ,MAC MMC Interrupt" "0,1" newline bitfld.long 0x00 26. " GLI ,Line Interface Interrupt" "0,1" bitfld.long 0x00 23.--25. " EB ,Error Bits" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. " TS ,Tx Process State" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 17.--19. " RS ,Rx Process State" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16. " NIS ,Normal Interrupt Summary" "0,1" bitfld.long 0x00 15. " AIS ,Abnormal Interrupt Summary" "0,1" newline bitfld.long 0x00 14. " ERI ,Early Receive Interrupt" "0,1" bitfld.long 0x00 13. " FBI ,Fatal Bus Error Interrupt" "0,1" bitfld.long 0x00 10. " ETI ,Early Transmit Interrupt" "0,1" newline bitfld.long 0x00 9. " RWT ,Receive WatchDog Timeout" "0,1" bitfld.long 0x00 8. " RPS ,Receive Process Stopped" "0,1" bitfld.long 0x00 7. " RU ,Receive Buffer Unavailable" "0,1" newline bitfld.long 0x00 6. " RI ,Receive Interrupt" "0,1" bitfld.long 0x00 5. " UNF ,Transmit Buffer Underflow" "0,1" bitfld.long 0x00 4. " OVF ,Receive Buffer Overflow" "0,1" newline bitfld.long 0x00 3. " TJT ,Transmit Jabber Timeout" "0,1" bitfld.long 0x00 2. " TU ,Transmit Buffer Unavailable" "0,1" bitfld.long 0x00 1. " TPS ,Transmit Process Stopped" "0,1" newline bitfld.long 0x00 0. " TI ,Transmit Interrupt" "0,1" group.long 0x1218++0x3 line.long 0x00 "EMAC0_DMA2_OPMODE,EMAC0 DMA Operation Mode Register" bitfld.long 0x00 26. " DT ,Disable Dropping TCP/IP Errors" "0,1" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "0,1" bitfld.long 0x00 24. " DFF ,Disable Flushing of Received Frames" "0,1" newline bitfld.long 0x00 21. " TSF ,Transmit Store and Forward" "0,1" bitfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "0,1" bitfld.long 0x00 14.--16. " TTC ,Transmit Threshold Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 13. " ST ,Start/Stop Transmission" "0,1" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "0,1" bitfld.long 0x00 6. " FUF ,Forward Undersized good Frames" "0,1" newline bitfld.long 0x00 5. " DGF ,Drop Giant Frames" "0,1" bitfld.long 0x00 3.--4. " RTC ,Receive Threshold Control" "0,1,2,3" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "0,1" newline bitfld.long 0x00 1. " SR ,Start/Stop Receive" "0,1" group.long 0x121C++0x3 line.long 0x00 "EMAC0_DMA2_IEN,EMAC0 DMA Interrupt Enable Register" bitfld.long 0x00 16. " NIE ,Normal Interrupt Summary Enable" "0,1" bitfld.long 0x00 15. " AIE ,Abnormal Interrupt Summary Enable" "0,1" bitfld.long 0x00 14. " ERE ,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 13. " FBE ,Fatal Bus Error Enable" "0,1" bitfld.long 0x00 10. " ETE ,Early Transmit Interrupt Enable" "0,1" bitfld.long 0x00 9. " RWE ,Receive Watchdog Timeout Enable" "0,1" newline bitfld.long 0x00 8. " RSE ,Receive Stopped Enable" "0,1" bitfld.long 0x00 7. " RUE ,Receive Buffer Unavailable Enable" "0,1" bitfld.long 0x00 6. " RIE ,Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 5. " UNE ,Underflow Interrupt Enable" "0,1" bitfld.long 0x00 4. " OVE ,Overflow Interrupt Enable" "0,1" bitfld.long 0x00 3. " TJE ,Transmit Jabber Timeout Enable" "0,1" newline bitfld.long 0x00 2. " TUE ,Transmit Buffer Unavailable Enable" "0,1" bitfld.long 0x00 1. " TSE ,Transmit Stopped Enable" "0,1" bitfld.long 0x00 0. " TIE ,Transmit Interrupt Enable" "0,1" group.long 0x1220++0x3 line.long 0x00 "EMAC0_DMA2_MISS_FRM,EMAC0 DMA Missed Frame Register" bitfld.long 0x00 28. " OVFFIFO ,Overflow bit for FIFO Overflow Counter" "0,1" hexmask.long.word 0x00 17.--27. 1. " MISSFROV ,Missed Frames Buffer Overflow" bitfld.long 0x00 16. " OVFMISS ,Overflow bit for Missed Frame Counter" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " MISSFRUN ,Missed Frames Unavailable Buffer" group.long 0x1224++0x3 line.long 0x00 "EMAC0_DMA2_RXIWDOG,EMAC0 DMA Rx Interrupt Watch Dog Register" hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI WatchDog Timer Count" group.long 0x1230++0x3 line.long 0x00 "EMAC0_DMA2_CHSFCS,EMAC0 Channel 2 Control Bits for Slot Function Register" bitfld.long 0x00 16.--19. " RSN ,Reference Slot number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " ASC ,Advance Slot Check" "0,1" bitfld.long 0x00 0. " ESC ,Enable Slot Comparison" "0,1" group.long 0x1248++0x3 line.long 0x00 "EMAC0_DMA2_TXDSC_CUR,EMAC0 DMA Tx Descriptor Current Register" group.long 0x124C++0x3 line.long 0x00 "EMAC0_DMA2_RXDSC_CUR,EMAC0 DMA Rx Descriptor Current Register" group.long 0x1250++0x3 line.long 0x00 "EMAC0_DMA2_TXBUF_CUR,EMAC0 DMA Tx Buffer Current Register" group.long 0x1254++0x3 line.long 0x00 "EMAC0_DMA2_RXBUF_CUR,EMAC0 DMA Rx Buffer Current Register" group.long 0x1260++0x3 line.long 0x00 "EMAC0_DMA2_CHCBSCTL,EMAC0 Channel 2 Credit Shaping Control Register" bitfld.long 0x00 17. " ABPSSIE ,Average bits per slot Interrupt Enable" "0,1" bitfld.long 0x00 4.--6. " SLC ,Slot Count" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. " CC ,Credit Control" "0,1" newline bitfld.long 0x00 0. " CBSD ,Credit Based Shaper Disable" "0,1" group.long 0x1264++0x3 line.long 0x00 "EMAC0_DMA2_CHCBSSTAT,EMAC0 Channel 2 Avg Traffic Transmitted Status Register" bitfld.long 0x00 17. " ABSU ,ABS Updated" "0,1" hexmask.long.tbyte 0x00 0.--16. 1. " ABS ,Average Bits per Slot" group.long 0x1268++0x3 line.long 0x00 "EMAC0_DMA2_CHISC,EMAC0 Channel 2 Idle Slope Credit Value Register" hexmask.long.word 0x00 0.--13. 1. " ISC ,Idle Slope Credit" group.long 0x126C++0x3 line.long 0x00 "EMAC0_DMA2_CHSSC,EMAC0 Channel 2 Send Slope Credit Value Register" hexmask.long.word 0x00 0.--13. 1. " SSC ,Send Slope Credit" group.long 0x1270++0x3 line.long 0x00 "EMAC0_DMA2_CHHIC,EMAC0 Channel 2 High Credit Value Register" hexmask.long 0x00 0.--28. 1. " HC ,High Credit" group.long 0x1274++0x3 line.long 0x00 "EMAC0_DMA2_CHLOC,EMAC0 Channel 2 Low Credit Value Register" hexmask.long 0x00 0.--28. 1. " LC ,Low Credit" tree.end tree "EMAC1" base ad:0x31042000 width 26. group.long 0x0++0x3 line.long 0x00 "EMAC1_MACCFG,EMAC1 MAC Configuration Register" bitfld.long 0x00 28.--30. " SARC ,Source Address Insertion or Replacement Control" "0,1,2,3,4,5,6,7" bitfld.long 0x00 27. " TWOKPE ,Support for 2K packets" "0,1" bitfld.long 0x00 25. " CST ,CRC Stripping" "0,1" newline bitfld.long 0x00 23. " WD ,Watch Dog Disable" "0,1" bitfld.long 0x00 22. " JB ,Jabber Disable" "0,1" bitfld.long 0x00 20. " JE ,Jumbo Frame Enable" "0,1" newline bitfld.long 0x00 17.--19. " IFG ,Inter-Frame Gap" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16. " DCRS ,Disable Carrier Sense" "0,1" bitfld.long 0x00 14. " FES ,Speed of Operation" "0,1" newline bitfld.long 0x00 13. " DO ,Disable Receive Own" "0,1" bitfld.long 0x00 12. " LM ,Loopback Mode" "0,1" bitfld.long 0x00 11. " DM ,Duplex Mode" "0,1" newline bitfld.long 0x00 10. " IPC ,IP Checksum" "0,1" bitfld.long 0x00 9. " DR ,Disable Retry" "0,1" bitfld.long 0x00 7. " ACS ,Automatic Pad/CRC Stripping" "0,1" newline bitfld.long 0x00 5.--6. " BL ,Back Off Limit" "0,1,2,3" bitfld.long 0x00 4. " DC ,Deferral Check" "0,1" bitfld.long 0x00 3. " TE ,Transmitter Enable" "0,1" newline bitfld.long 0x00 2. " RE ,Receiver Enable" "0,1" bitfld.long 0x00 0.--1. " PRELEN ,Preamble Length for Transmit Frames" "0,1,2,3" group.long 0x4++0x3 line.long 0x00 "EMAC1_MACFRMFILT,EMAC1 MAC Rx Frame Filter Register" bitfld.long 0x00 31. " RA ,Receive All Frames" "0,1" bitfld.long 0x00 21. " DNTU ,Drop non-TCP/UDP over IP Frames" "0,1" bitfld.long 0x00 20. " IPFE ,Layer 3 and Layer 4 Filter Enable" "0,1" newline bitfld.long 0x00 16. " VTFE ,VAN Tag Filter Enable" "0,1" bitfld.long 0x00 10. " HPF ,Hash or Perfect Filter" "0,1" bitfld.long 0x00 9. " SAF ,Source Address Filter Enable" "0,1" newline bitfld.long 0x00 8. " SAIF ,Source Address Inverse Filtering" "0,1" bitfld.long 0x00 6.--7. " PCF ,Pass Control Frames" "0,1,2,3" bitfld.long 0x00 5. " DBF ,Disable Broadcast Frames" "0,1" newline bitfld.long 0x00 4. " PM ,Pass All Multicast Frames" "0,1" bitfld.long 0x00 3. " DAIF ,Destination Address Inverse Filtering" "0,1" bitfld.long 0x00 2. " HMC ,Hash Multicast" "0,1" newline bitfld.long 0x00 1. " HUC ,Hash Unicast" "0,1" bitfld.long 0x00 0. " PR ,Promiscuous Mode" "0,1" group.long 0x8++0x3 line.long 0x00 "EMAC1_HASHTBL_HI,EMAC1 Hash Table High Register" group.long 0xC++0x3 line.long 0x00 "EMAC1_HASHTBL_LO,EMAC1 Hash Table Low Register" group.long 0x10++0x3 line.long 0x00 "EMAC1_SMI_ADDR,EMAC1 SMI Address Register" bitfld.long 0x00 11.--15. " PA ,Physical Layer Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6.--10. " SMIR ,SMI Register Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 2.--5. " CR ,Clock Range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. " SMIW ,SMI Write" "0,1" bitfld.long 0x00 0. " SMIB ,SMI Busy" "0,1" group.long 0x14++0x3 line.long 0x00 "EMAC1_SMI_DATA,EMAC1 SMI Data Register" hexmask.long.word 0x00 0.--15. 1. " SMID ,SMI Data" group.long 0x18++0x3 line.long 0x00 "EMAC1_FLOWCTL,EMAC1 FLow Control Register" hexmask.long.word 0x00 16.--31. 1. " PT ,Pause Time" bitfld.long 0x00 7. " DZPQ ,Disable Zero-Quanta Pause" "0,1" bitfld.long 0x00 4.--5. " PLT ,Pause Low Threshold" "0,1,2,3" newline bitfld.long 0x00 3. " UP ,Unicast Pause Frame Detect" "0,1" bitfld.long 0x00 2. " RFE ,Receive Flow Control Enable" "0,1" bitfld.long 0x00 1. " TFE ,Transmit Flow Control Enable" "0,1" newline bitfld.long 0x00 0. " FCBBPA ,Initiate Pause Control Frame" "0,1" group.long 0x1C++0x3 line.long 0x00 "EMAC1_VLANTAG,EMAC1 VLAN Tag Register" bitfld.long 0x00 19. " VTHM ,VLAN Tag Hash Table Match Enable" "0,1" bitfld.long 0x00 18. " ESVL ,Enable S-VLAN" "0,1" bitfld.long 0x00 17. " VTIM ,VLAN Tag Inverse Match Enable" "0,1" newline bitfld.long 0x00 16. " ETV ,Enable Tag VLAN Comparison" "0,1" hexmask.long.word 0x00 0.--15. 1. " VL ,VLAN Tag Id Receive Frames" group.long 0x24++0x3 line.long 0x00 "EMAC1_DBG,EMAC1 Debug Register" bitfld.long 0x00 25. " TXFIFOFULL ,Tx FIFO Full" "0,1" bitfld.long 0x00 24. " TXFIFONE ,Tx FIFO Not Empty" "0,1" bitfld.long 0x00 22. " TXFIFOACT ,Tx FIFO Active" "0,1" newline bitfld.long 0x00 20.--21. " TXFIFOCTLST ,Tx FIFO Controller State" "0,1,2,3" bitfld.long 0x00 19. " TXPAUSE ,Tx Paused" "0,1" bitfld.long 0x00 17.--18. " TXFRCTL ,Tx Frame Controller State" "0,1,2,3" newline bitfld.long 0x00 16. " MMTEA ,MM Tx Engine Active" "0,1" bitfld.long 0x00 8.--9. " RXFIFOST ,Rx FIFO State" "0,1,2,3" bitfld.long 0x00 5.--6. " RXFIFOCTLST ,Rx FIFO Controller State" "0,1,2,3" newline bitfld.long 0x00 4. " RXFIFOACT ,Rx FIFO Active" "0,1" bitfld.long 0x00 1.--2. " SFIFOST ,Small FIFO State" "0,1,2,3" bitfld.long 0x00 0. " MMREA ,MM Rx Engine Active" "0,1" group.long 0x38++0x3 line.long 0x00 "EMAC1_ISTAT,EMAC1 Interrupt Status Register" bitfld.long 0x00 9. " TS ,Time Stamp Interrupt Status" "0,1" bitfld.long 0x00 7. " MMCRC ,MMC Receive Checksum Offload Interrupt Status" "0,1" bitfld.long 0x00 6. " MMCTX ,MMC Transmit Interrupt Status" "0,1" newline bitfld.long 0x00 5. " MMCRX ,MMC Receive Interrupt Status" "0,1" bitfld.long 0x00 4. " MMC ,MMC Interrupt Status" "0,1" group.long 0x3C++0x3 line.long 0x00 "EMAC1_IMSK,EMAC1 Interrupt Mask Register" bitfld.long 0x00 9. " TS ,Time Stamp Interrupt Mask" "0,1" group.long 0x40++0x3 line.long 0x00 "EMAC1_ADDR0_HI,EMAC1 MAC Address 0 High Register" hexmask.long.word 0x00 0.--15. 1. " ADDR ,Address" group.long 0x44++0x3 line.long 0x00 "EMAC1_ADDR0_LO,EMAC1 MAC Address 0 Low Register" group.long 0x48++0x3 line.long 0x00 "EMAC1_ADDR1_HI,EMAC1 MAC Address 1 High Register" bitfld.long 0x00 31. " AE ,Address Enable" "0,1" bitfld.long 0x00 30. " SA ,Source Address" "0,1" bitfld.long 0x00 24.--29. " MBC ,Mask byte control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline hexmask.long.word 0x00 0.--15. 1. " ADDRHI ,Mac address" group.long 0x4C++0x3 line.long 0x00 "EMAC1_ADDR1_LO,EMAC1 MAC Address 1 Low Register" group.long 0xDC++0x3 line.long 0x00 "EMAC1_WDOG_TIMOUT,EMAC1 Watchdog Timeout Register" bitfld.long 0x00 16. " PWE ,Programmable Watchdog Enable" "0,1" hexmask.long.word 0x00 0.--13. 1. " WTO ,Watchdog Timeout" group.long 0x100++0x3 line.long 0x00 "EMAC1_MMC_CTL,EMAC1 MMC Control Register" bitfld.long 0x00 5. " FULLPSET ,Full Preset" "0,1" bitfld.long 0x00 4. " CNTRPSET ,Counter Reset/Preset" "0,1" bitfld.long 0x00 3. " CNTRFRZ ,Counter Freeze" "0,1" newline bitfld.long 0x00 2. " RDRST ,Read Reset" "0,1" bitfld.long 0x00 1. " NOROLL ,No Rollover" "0,1" bitfld.long 0x00 0. " RST ,Reset" "0,1" group.long 0x104++0x3 line.long 0x00 "EMAC1_MMC_RXINT,EMAC1 MMC Rx Interrupt Register" bitfld.long 0x00 25. " RXCTLFIS ,Rx Control Frame Counter Interrupt Status" "0,1" bitfld.long 0x00 24. " RXRCVERRFIS ,Rx Error Frame Counter Interrupt Status" "0,1" bitfld.long 0x00 23. " WDOGERR ,Rx Watch Dog Error Count Half/Full" "0,1" newline bitfld.long 0x00 22. " VLANFRGB ,Rx VLAN Frames (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 21. " FIFOOVF ,Rx FIFO Overflow Count Half/Full" "0,1" bitfld.long 0x00 20. " PAUSEFR ,Rx Pause Frames Count Half/Full" "0,1" newline bitfld.long 0x00 19. " OUTRANGE ,Rx Out Of Range Type Count Half/Full" "0,1" bitfld.long 0x00 18. " LENERR ,Rx Length Error Count Half/Full" "0,1" bitfld.long 0x00 17. " UCASTG ,Rx Unicast Frames (Good) Count Half/Full" "0,1" newline bitfld.long 0x00 16. " R1024TOMAX ,Rx 1024-to-max Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 15. " R512TO1023 ,Rx 512-to-1023 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 14. " R256TO511 ,Rx 255-to-511 Octets (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 13. " R128TO255 ,Rx 128-to-255 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 12. " R65TO127 ,Rx 65-to-127 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 11. " R64 ,Rx 64 Octets (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 10. " OSIZEG ,Rx Oversize (Good) Count Half/Full" "0,1" bitfld.long 0x00 9. " USIZEG ,Rx Undersize (Good) Count Half/Full" "0,1" bitfld.long 0x00 8. " JABERR ,Rx Jabber Error Count Half/Full" "0,1" newline bitfld.long 0x00 7. " RUNTERR ,Rx Runt Error Count Half/Full" "0,1" bitfld.long 0x00 6. " ALIGNERR ,Rx Alignment Error Count Half/Full" "0,1" bitfld.long 0x00 5. " CRCERR ,Rx CRC Error Counter Half/Full" "0,1" newline bitfld.long 0x00 4. " MCASTG ,Rx Multicast Count (Good) Half/Full" "0,1" bitfld.long 0x00 3. " BCASTG ,Rx Broadcast Count (Good) Half/Full" "0,1" bitfld.long 0x00 2. " OCTCNTG ,Octet Count (Good) Half/Full" "0,1" newline bitfld.long 0x00 1. " OCTCNTGB ,Octet Count (Good/Bad) Half/Full" "0,1" bitfld.long 0x00 0. " FRCNTGB ,Frame Count (Good/Bad) Half/Full" "0,1" group.long 0x108++0x3 line.long 0x00 "EMAC1_MMC_TXINT,EMAC1 MMC Tx Interrupt Register" bitfld.long 0x00 25. " TXOSIZEGFIS ,Tx Oversize Good Frame Count Interrupt Status" "0,1" bitfld.long 0x00 24. " VLANFRGB ,Tx VLAN Frames (Good) Count Half/Full" "0,1" bitfld.long 0x00 23. " PAUSEFRM ,Tx Pause Frames Count Half/Full" "0,1" newline bitfld.long 0x00 22. " EXCESSDEF ,Tx Excess Deferred Count Half/Full" "0,1" bitfld.long 0x00 21. " FRCNTG ,Tx Frame Count (Good) Count Half/Full" "0,1" bitfld.long 0x00 20. " OCTCNTG ,Tx Octet Count (Good) Count Half/Full" "0,1" newline bitfld.long 0x00 19. " CARRERR ,Tx Carrier Error Count Half/Full" "0,1" bitfld.long 0x00 18. " EXCESSCOL ,Tx Excess Collision Count Half/Full" "0,1" bitfld.long 0x00 17. " LATECOL ,Tx Late Collision Count Half/Full" "0,1" newline bitfld.long 0x00 16. " DEFERRED ,Tx Deferred Count Half/Full" "0,1" bitfld.long 0x00 15. " MULTCOLG ,Tx Multiple collision (Good) Count Half/Full" "0,1" bitfld.long 0x00 14. " SNGCOLG ,Tx Single Collision (Good) Count Half/Full" "0,1" newline bitfld.long 0x00 13. " UNDERR ,Tx Underflow Error Count Half/Full" "0,1" bitfld.long 0x00 12. " BCASTGB ,Tx Broadcast Frames (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 11. " MCASTGB ,Tx Multicast Frames (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 10. " UCASTGB ,Tx Unicast Frames (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 9. " T1024TOMAX ,Tx 1024-to-max Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 8. " T512TO1023 ,Tx 512-to-1023 Octets (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 7. " T256TO511 ,Tx 256-to-511 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 6. " T128TO255 ,Tx 128-to-255 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 5. " T65TO127 ,Tx 65-to-127 Octets (Good/Bad) Count Half/Full" "0,1" newline bitfld.long 0x00 4. " T64 ,Tx 64 Octets (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 3. " MCASTG ,Tx Multicast Frames (Good) Count Half/Full" "0,1" bitfld.long 0x00 2. " BCASTG ,Tx Broadcast Frames (Good) Count Half/Full" "0,1" newline bitfld.long 0x00 1. " FRCNTGB ,Tx Frame Count (Good/Bad) Count Half/Full" "0,1" bitfld.long 0x00 0. " OCTCNTGB ,Tx Octet Count (Good/Bad) Count Half/Full" "0,1" group.long 0x10C++0x3 line.long 0x00 "EMAC1_MMC_RXIMSK,EMAC1 MMC Rx Interrupt Mask Register" bitfld.long 0x00 25. " CTLFIM ,Rx Control Frame Counter Interrupt Mask" "0,1" bitfld.long 0x00 24. " RCVERRFIM ,Rx Error Frame Counter Interrupt Mask" "0,1" bitfld.long 0x00 23. " WATCHERR ,Rx Watch Dog Error Count Half/Full Mask" "0,1" newline bitfld.long 0x00 22. " VLANFRGB ,Rx VLAN Frames (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 21. " FIFOOV ,Rx FIFO Overflow Count Half/Full Mask" "0,1" bitfld.long 0x00 20. " PAUSEFRM ,Rx Pause Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 19. " OUTRANGE ,Rx Out Of Range Type Count Half/Full Mask" "0,1" bitfld.long 0x00 18. " LENERR ,Rx Length Error Count Half/Full Mask" "0,1" bitfld.long 0x00 17. " UCASTG ,Rx Unicast Frames (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 16. " R1024TOMAX ,Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 15. " R512TO1023 ,Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 14. " R256TO511 ,Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 13. " R128TO255 ,Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 12. " R65TO127 ,Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 11. " R64 ,Rx 64 Octets (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 10. " OSIZEG ,Rx Oversize (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 9. " USIZEG ,Rx Undersize (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 8. " JABERR ,Rx Jabber Error Count Half/Full Mask" "0,1" newline bitfld.long 0x00 7. " RUNTERR ,Rx Runt Error Count Half/Full Mask" "0,1" bitfld.long 0x00 6. " ALIGNERR ,Rx Alignment Error Count Half/Full Mask" "0,1" bitfld.long 0x00 5. " CRCERR ,Rx CRC Error Count Half/Full Mask" "0,1" newline bitfld.long 0x00 4. " MCASTG ,Rx Multicast Frames (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 3. " BCASTG ,Rx Broadcast Frames (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 2. " OCTCNTG ,Rx Octet Count (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 1. " OCTCNTGB ,Rx Octet Count (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 0. " FRCNTGB ,Rx Frame Count (Good/Bad) Count Half/Full Mask" "0,1" group.long 0x110++0x3 line.long 0x00 "EMAC1_MMC_TXIMSK,EMAC1 MMC TX Interrupt Mask Register" bitfld.long 0x00 25. " OSZGFIM ,Tx Oversize Good Frame Count Interrupt Mask" "0,1" bitfld.long 0x00 24. " VLANFRG ,Tx VLAN Frames (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 23. " PAUSEFRM ,Tx Pause Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 22. " EXCESSDEF ,Tx Excess Deferred Count Half/Full Mask" "0,1" bitfld.long 0x00 21. " FRCNTG ,Tx Frame Count (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 20. " OCTCNTG ,Tx Octet Count (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 19. " CARRERR ,Tx Carrier Error Count Half/Full Mask" "0,1" bitfld.long 0x00 18. " EXCESSCOL ,Tx Excess collision Count Half/Full Mask" "0,1" bitfld.long 0x00 17. " LATECOL ,Tx Late Collision Count Half/Full Mask" "0,1" newline bitfld.long 0x00 16. " DEFERRED ,Tx Deferred Count Half/Full Mask" "0,1" bitfld.long 0x00 15. " MULTCOLG ,Tx Multiple Collisions (Good) Count Mask" "0,1" bitfld.long 0x00 14. " SNGCOLG ,Tx Single Collision (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 13. " UNDERR ,Tx Underflow Error Count Half/Full Mask" "0,1" bitfld.long 0x00 12. " BCASTGB ,Tx Broadcast Frames (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 11. " MCASTGB ,Tx Multicast Frames (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 10. " UCASTGB ,Tx Unicast Frames (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 9. " T1024TOMAX ,Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 8. " T512TO1023 ,Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 7. " T256TO511 ,Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 6. " T128TO255 ,Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 5. " T65TO127 ,Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 4. " T64 ,Tx 64 Octets (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 3. " MCASTG ,Tx Multicast Frames (Good) Count Half/Full Mask" "0,1" bitfld.long 0x00 2. " BCASTG ,Tx Broadcast Frames (Good) Count Half/Full Mask" "0,1" newline bitfld.long 0x00 1. " FRCNTGB ,Tx Frame Count (Good/Bad) Count Half/Full Mask" "0,1" bitfld.long 0x00 0. " OCTCNTGB ,Tx Octet Count (Good/Bad) Count Half/Full Mask" "0,1" group.long 0x114++0x3 line.long 0x00 "EMAC1_TXOCTCNT_GB,EMAC1 Tx OCT Count (Good/Bad) Register" group.long 0x118++0x3 line.long 0x00 "EMAC1_TXFRMCNT_GB,EMAC1 Tx Frame Count (Good/Bad) Register" group.long 0x11C++0x3 line.long 0x00 "EMAC1_TXBCASTFRM_G,EMAC1 Tx Broadcast Frames (Good) Register" group.long 0x120++0x3 line.long 0x00 "EMAC1_TXMCASTFRM_G,EMAC1 Tx Multicast Frames (Good) Register" group.long 0x124++0x3 line.long 0x00 "EMAC1_TX64_GB,EMAC1 Tx 64-Byte Frames (Good/Bad) Register" group.long 0x128++0x3 line.long 0x00 "EMAC1_TX65TO127_GB,EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register" group.long 0x12C++0x3 line.long 0x00 "EMAC1_TX128TO255_GB,EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register" group.long 0x130++0x3 line.long 0x00 "EMAC1_TX256TO511_GB,EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register" group.long 0x134++0x3 line.long 0x00 "EMAC1_TX512TO1023_GB,EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register" group.long 0x138++0x3 line.long 0x00 "EMAC1_TX1024TOMAX_GB,EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register" group.long 0x13C++0x3 line.long 0x00 "EMAC1_TXUCASTFRM_GB,EMAC1 Tx Unicast Frames (Good/Bad) Register" group.long 0x140++0x3 line.long 0x00 "EMAC1_TXMCASTFRM_GB,EMAC1 Tx Multicast Frames (Good/Bad) Register" group.long 0x144++0x3 line.long 0x00 "EMAC1_TXBCASTFRM_GB,EMAC1 Tx Broadcast Frames (Good/Bad) Register" group.long 0x148++0x3 line.long 0x00 "EMAC1_TXUNDR_ERR,EMAC1 Tx Underflow Error Register" group.long 0x14C++0x3 line.long 0x00 "EMAC1_TXSNGCOL_G,EMAC1 Tx Single Collision (Good) Register" group.long 0x150++0x3 line.long 0x00 "EMAC1_TXMULTCOL_G,EMAC1 Tx Multiple Collision (Good) Register" group.long 0x154++0x3 line.long 0x00 "EMAC1_TXDEFERRED,EMAC1 Tx Deferred Register" group.long 0x158++0x3 line.long 0x00 "EMAC1_TXLATECOL,EMAC1 Tx Late Collision Register" group.long 0x15C++0x3 line.long 0x00 "EMAC1_TXEXCESSCOL,EMAC1 Tx Excess Collision Register" group.long 0x160++0x3 line.long 0x00 "EMAC1_TXCARR_ERR,EMAC1 Tx Carrier Error Register" group.long 0x164++0x3 line.long 0x00 "EMAC1_TXOCTCNT_G,EMAC1 Tx Octet Count (Good) Register" group.long 0x168++0x3 line.long 0x00 "EMAC1_TXFRMCNT_G,EMAC1 Tx Frame Count (Good) Register" group.long 0x16C++0x3 line.long 0x00 "EMAC1_TXEXCESSDEF,EMAC1 Tx Excess Deferral Register" group.long 0x170++0x3 line.long 0x00 "EMAC1_TXPAUSEFRM,EMAC1 Tx Pause Frame Register" group.long 0x174++0x3 line.long 0x00 "EMAC1_TXVLANFRM_G,EMAC1 Tx VLAN Frames (Good) Register" group.long 0x178++0x3 line.long 0x00 "EMAC1_TXOVRSIZE_G,EMAC1 Number of Tx Frames (Good) greater than maxsize" group.long 0x180++0x3 line.long 0x00 "EMAC1_RXFRMCNT_GB,EMAC1 Rx Frame Count (Good/Bad) Register" group.long 0x184++0x3 line.long 0x00 "EMAC1_RXOCTCNT_GB,EMAC1 Rx Octet Count (Good/Bad) Register" group.long 0x188++0x3 line.long 0x00 "EMAC1_RXOCTCNT_G,EMAC1 Rx Octet Count (Good) Register" group.long 0x18C++0x3 line.long 0x00 "EMAC1_RXBCASTFRM_G,EMAC1 Rx Broadcast Frames (Good) Register" group.long 0x190++0x3 line.long 0x00 "EMAC1_RXMCASTFRM_G,EMAC1 Rx Multicast Frames (Good) Register" group.long 0x194++0x3 line.long 0x00 "EMAC1_RXCRC_ERR,EMAC1 Rx CRC Error Register" group.long 0x198++0x3 line.long 0x00 "EMAC1_RXALIGN_ERR,EMAC1 Rx alignment Error Register" group.long 0x19C++0x3 line.long 0x00 "EMAC1_RXRUNT_ERR,EMAC1 Rx Runt Error Register" group.long 0x1A0++0x3 line.long 0x00 "EMAC1_RXJAB_ERR,EMAC1 Rx Jab Error Register" group.long 0x1A4++0x3 line.long 0x00 "EMAC1_RXUSIZE_G,EMAC1 Rx Undersize (Good) Register" group.long 0x1A8++0x3 line.long 0x00 "EMAC1_RXOSIZE_G,EMAC1 Rx Oversize (Good) Register" group.long 0x1AC++0x3 line.long 0x00 "EMAC1_RX64_GB,EMAC1 Rx 64-Byte Frames (Good/Bad) Register" group.long 0x1B0++0x3 line.long 0x00 "EMAC1_RX65TO127_GB,EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register" group.long 0x1B4++0x3 line.long 0x00 "EMAC1_RX128TO255_GB,EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register" group.long 0x1B8++0x3 line.long 0x00 "EMAC1_RX256TO511_GB,EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register" group.long 0x1BC++0x3 line.long 0x00 "EMAC1_RX512TO1023_GB,EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register" group.long 0x1C0++0x3 line.long 0x00 "EMAC1_RX1024TOMAX_GB,EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register" group.long 0x1C4++0x3 line.long 0x00 "EMAC1_RXUCASTFRM_G,EMAC1 Rx Unicast Frames (Good) Register" group.long 0x1C8++0x3 line.long 0x00 "EMAC1_RXLEN_ERR,EMAC1 Rx Length Error Register" group.long 0x1CC++0x3 line.long 0x00 "EMAC1_RXOORTYPE,EMAC1 Rx Out Of Range Type Register" group.long 0x1D0++0x3 line.long 0x00 "EMAC1_RXPAUSEFRM,EMAC1 Rx Pause Frames Register" group.long 0x1D4++0x3 line.long 0x00 "EMAC1_RXFIFO_OVF,EMAC1 Rx FIFO Overflow Register" group.long 0x1D8++0x3 line.long 0x00 "EMAC1_RXVLANFRM_GB,EMAC1 Rx VLAN Frames (Good/Bad) Register" group.long 0x1DC++0x3 line.long 0x00 "EMAC1_RXWDOG_ERR,EMAC1 Rx Watch Dog Error Register" group.long 0x1E0++0x3 line.long 0x00 "EMAC1_RXRCV_ERR,EMAC1 Rx Error Frames Received Register" group.long 0x1E4++0x3 line.long 0x00 "EMAC1_RXCTLFRM_G,EMAC1 Rx Good Control Frames Register" group.long 0x200++0x3 line.long 0x00 "EMAC1_IPC_RXIMSK,EMAC1 MMC IPC Rx Interrupt Mask Register" bitfld.long 0x00 29. " ICMPERROCT ,Rx ICMP Error Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 28. " ICMPGOCT ,Rx ICMP (Good) Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 27. " TCPERROCT ,Rx TCP Error Octets Count Half/Full Mask" "0,1" newline bitfld.long 0x00 26. " TCPGOCT ,Rx TCP (Good) Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 25. " UDPERROCT ,Rx UDP Error Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 24. " UDPGOCT ,Rx UDP (Good) Octets Count Half/Full Mask" "0,1" newline bitfld.long 0x00 23. " V6NOPAYOCT ,Rx IPv6 No Payload Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 22. " V6HDERROCT ,Rx IPv6 Header Error Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 21. " V6GOCT ,Rx IPv6 (Good) Octets Count Half/Full Mask" "0,1" newline bitfld.long 0x00 20. " V4UDSBLOCT ,Rx IPv4 UDS Disable Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 19. " V4FRAGOCT ,Rx IPv4 Fragmented Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 18. " V4NOPAYOCT ,Rx IPv4 No Payload Octets Count Half/Full Mask" "0,1" newline bitfld.long 0x00 17. " V4HDERROCT ,Rx IPv4 Header Error Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 16. " V4GOCT ,Rx IPv4 (Good) Octets Count Half/Full Mask" "0,1" bitfld.long 0x00 13. " ICMPERRFRM ,Rx ICMP Error Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 12. " ICMPGFRM ,Rx ICMP (Good) Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 11. " TCPERRFRM ,Rx TCP Error Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 10. " TCPGFRM ,Rx TCP (Good) Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 9. " UDPERRFRM ,Rx UDP Error Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 8. " UDPGFRM ,Rx UDP (Good) Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 7. " V6NOPAYFRM ,Rx IPv6 No Payload Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 6. " V6HDERRFRM ,Rx IPv6 Header Error Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 5. " V6GFRM ,Rx IPv6 (Good) Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 4. " V4UDSBLFRM ,Rx IPv4 UDS Disable Frames Count Half/Full Mask" "0,1" newline bitfld.long 0x00 3. " V4FRAGFRM ,Rx IPv4 Fragmented Frames Count Half/Full Mask" "0,1" bitfld.long 0x00 2. " V4NOPAYFRM ,Rx IPv4 No Payload Frame Count Half/Full Mask" "0,1" bitfld.long 0x00 1. " V4HDERRFRM ,Rx IPv4 Header Error Frame Count Half/Full Mask" "0,1" newline bitfld.long 0x00 0. " V4GFRM ,Rx IPv4 (Good) Frames Count Half/Full Mask" "0,1" group.long 0x208++0x3 line.long 0x00 "EMAC1_IPC_RXINT,EMAC1 MMC IPC Rx Interrupt Register" bitfld.long 0x00 29. " ICMPERROCT ,Rx ICMP Error Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 28. " ICMPGOCT ,Rx ICMP (Good) Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 27. " TCPERROCT ,Rx TCP Error Octets Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 26. " TCPGOCT ,Rx TCP (Good) Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 25. " UDPERROCT ,Rx UDP Error Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 24. " UDPGOCT ,Rx UDP (Good) Octets Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 23. " V6NOPAYOCT ,Rx IPv6 No Payload Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 22. " V6HDERROCT ,Rx IPv6 Header Error Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 21. " V6GOCT ,Rx IPv6 (Good) Octets Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 20. " V4UDSBLOCT ,Rx IPv4 UDS Disable Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 19. " V4FRAGOCT ,Rx IPv4 Fragmented Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 18. " V4NOPAYOCT ,Rx IPv4 No Payload Octets Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 17. " V4HDERROCT ,Rx IPv4 Header Error Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 16. " V4GOCT ,Rx IPv4 (Good) Octets Count Half/Full Interrupt" "0,1" bitfld.long 0x00 13. " ICMPERRFRM ,Rx ICMP Error Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 12. " ICMPGFRM ,Rx ICMP (Good) Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 11. " TCPERRFRM ,Rx TCP Error Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 10. " TCPGFRM ,Rx TCP (Good) Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 9. " UDPERRFRM ,Rx IDP Error Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 8. " UDPGFRM ,Rx UDP (Good) Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 7. " V6NOPAYFRM ,Rx IPv6 No Payload Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 6. " V6HDERRFRM ,Rx IPv6 Header Error Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 5. " V6GFRM ,Rx IPv6 (Good) Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 4. " V4UDSBLFRM ,Rx IPv4 UDS Disable Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 3. " V4FRAGFRM ,Rx IPv4 Fragmented Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 2. " V4NOPAYFRM ,Rx IPv4 No Payload Frames Count Half/Full Interrupt" "0,1" bitfld.long 0x00 1. " V4HDERRFRM ,Rx IPv4 Header Error Frames Count Half/Full Interrupt" "0,1" newline bitfld.long 0x00 0. " V4GFRM ,Rx IPv4 (Good) Frames Count Half/Full Interrupt" "0,1" group.long 0x210++0x3 line.long 0x00 "EMAC1_RXIPV4_GD_FRM,EMAC1 Rx IPv4 Datagrams (Good) Register" group.long 0x214++0x3 line.long 0x00 "EMAC1_RXIPV4_HDR_ERR_FRM,EMAC1 Rx IPv4 Datagrams Header Errors Register" group.long 0x218++0x3 line.long 0x00 "EMAC1_RXIPV4_NOPAY_FRM,EMAC1 Rx IPv4 Datagrams No Payload Frame Register" group.long 0x21C++0x3 line.long 0x00 "EMAC1_RXIPV4_FRAG_FRM,EMAC1 Rx IPv4 Datagrams Fragmented Frames Register" group.long 0x220++0x3 line.long 0x00 "EMAC1_RXIPV4_UDSBL_FRM,EMAC1 Rx IPv4 UDP Disabled Frames Register" group.long 0x224++0x3 line.long 0x00 "EMAC1_RXIPV6_GD_FRM,EMAC1 Rx IPv6 Datagrams Good Frames Register" group.long 0x228++0x3 line.long 0x00 "EMAC1_RXIPV6_HDR_ERR_FRM,EMAC1 Rx IPv6 Datagrams Header Error Frames Register" group.long 0x22C++0x3 line.long 0x00 "EMAC1_RXIPV6_NOPAY_FRM,EMAC1 Rx IPv6 Datagrams No Payload Frames Register" group.long 0x230++0x3 line.long 0x00 "EMAC1_RXUDP_GD_FRM,EMAC1 Rx UDP Good Frames Register" group.long 0x234++0x3 line.long 0x00 "EMAC1_RXUDP_ERR_FRM,EMAC1 Rx UDP Error Frames Register" group.long 0x238++0x3 line.long 0x00 "EMAC1_RXTCP_GD_FRM,EMAC1 Rx TCP Good Frames Register" group.long 0x23C++0x3 line.long 0x00 "EMAC1_RXTCP_ERR_FRM,EMAC1 Rx TCP Error Frames Register" group.long 0x240++0x3 line.long 0x00 "EMAC1_RXICMP_GD_FRM,EMAC1 Rx ICMP Good Frames Register" group.long 0x244++0x3 line.long 0x00 "EMAC1_RXICMP_ERR_FRM,EMAC1 Rx ICMP Error Frames Register" group.long 0x250++0x3 line.long 0x00 "EMAC1_RXIPV4_GD_OCT,EMAC1 Rx IPv4 Datagrams Good Octets Register" group.long 0x254++0x3 line.long 0x00 "EMAC1_RXIPV4_HDR_ERR_OCT,EMAC1 Rx IPv4 Datagrams Header Errors Register" group.long 0x258++0x3 line.long 0x00 "EMAC1_RXIPV4_NOPAY_OCT,EMAC1 Rx IPv4 Datagrams No Payload Octets Register" group.long 0x25C++0x3 line.long 0x00 "EMAC1_RXIPV4_FRAG_OCT,EMAC1 Rx IPv4 Datagrams Fragmented Octets Register" group.long 0x260++0x3 line.long 0x00 "EMAC1_RXIPV4_UDSBL_OCT,EMAC1 Rx IPv4 UDP Disabled Octets Register" group.long 0x264++0x3 line.long 0x00 "EMAC1_RXIPV6_GD_OCT,EMAC1 Rx IPv6 Good Octets Register" group.long 0x268++0x3 line.long 0x00 "EMAC1_RXIPV6_HDR_ERR_OCT,EMAC1 Rx IPv6 Header Errors Register" group.long 0x26C++0x3 line.long 0x00 "EMAC1_RXIPV6_NOPAY_OCT,EMAC1 Rx IPv6 No Payload Octets Register" group.long 0x270++0x3 line.long 0x00 "EMAC1_RXUDP_GD_OCT,EMAC1 Rx UDP Good Octets Register" group.long 0x274++0x3 line.long 0x00 "EMAC1_RXUDP_ERR_OCT,EMAC1 Rx UDP Error Octets Register" group.long 0x278++0x3 line.long 0x00 "EMAC1_RXTCP_GD_OCT,EMAC1 Rx TCP Good Octets Register" group.long 0x27C++0x3 line.long 0x00 "EMAC1_RXTCP_ERR_OCT,EMAC1 Rx TCP Error Octets Register" group.long 0x280++0x3 line.long 0x00 "EMAC1_RXICMP_GD_OCT,EMAC1 Rx ICMP Good Octets Register" group.long 0x284++0x3 line.long 0x00 "EMAC1_RXICMP_ERR_OCT,EMAC1 Rx ICMP Error Octets Register" group.long 0x400++0x3 line.long 0x00 "EMAC1_L3L4_CTL,EMAC1 Layer3 and Layer4 Control Register" bitfld.long 0x00 21. " L4DPIM ,Layer 4 Destination Port Inverse Matching" "0,1" bitfld.long 0x00 20. " L4DPM ,Layer 4 Destination Port Matching" "0,1" bitfld.long 0x00 19. " L4SPIM ,Layer 4 Source Port Inverse Matching" "0,1" newline bitfld.long 0x00 18. " L4SPM ,Layer 4 Source Port Matching" "0,1" bitfld.long 0x00 16. " L4PEN ,Layer 4 Filtering Enable" "0,1" bitfld.long 0x00 11.--15. " L3HDBM ,Layer 3 Destination Address Bits Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6.--10. " L3HSBM ,Layer 3 Source Address Bits Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " L3DAIM ,Layer 3 Destination Address Inverse Matching" "0,1" bitfld.long 0x00 4. " L3DAM ,Layer 3 Destination Address Matching" "0,1" newline bitfld.long 0x00 3. " L3SAIM ,Layer 3 Source Address Inverse Matching" "0,1" bitfld.long 0x00 2. " L3SAM ,Layer 3 Source Address Matching" "0,1" bitfld.long 0x00 0. " L3PEN ,Layer 3 Enabled" "0,1" group.long 0x404++0x3 line.long 0x00 "EMAC1_L4_ADDR,EMAC1 Layer 4 Address Register" hexmask.long.word 0x00 16.--31. 1. " L4DP ,Layer 4 Destination Port" hexmask.long.word 0x00 0.--15. 1. " L4SP ,Layer 4 Source Port" group.long 0x410++0x3 line.long 0x00 "EMAC1_L3_ADDR0,EMAC1 Layer 3 Address0 Register" group.long 0x414++0x3 line.long 0x00 "EMAC1_L3_ADDR1,EMAC1 Layer 3 Address1 Register" group.long 0x418++0x3 line.long 0x00 "EMAC1_L3_ADDR2,EMAC1 Layer 3 Address2 Register" group.long 0x41C++0x3 line.long 0x00 "EMAC1_L3_ADDR3,EMAC1 Layer 3 Address3 Register" group.long 0x584++0x3 line.long 0x00 "EMAC1_VLAN_INCL,EMAC1 VLAN Tag Inclusion or Replacement Register" bitfld.long 0x00 19. " CSVL ,C-VLAN or S-VLAN" "0,1" bitfld.long 0x00 18. " VLP ,VLAN Priority Control" "0,1" bitfld.long 0x00 16.--17. " VLC ,VLAN Tag Control in Transmit Frames" "0,1,2,3" newline hexmask.long.word 0x00 0.--15. 1. " VLT ,VLAN Tag for Transmit Frames" group.long 0x588++0x3 line.long 0x00 "EMAC1_VLAN_HSHTBL,EMAC1 VLAN Hash Table Register" hexmask.long.word 0x00 0.--15. 1. " VLHT ,VLAN Hash Table" group.long 0x760++0x3 line.long 0x00 "EMAC1_TM_PPS0INTVL,EMAC1 Time Stamp PPS Interval Register" group.long 0x764++0x3 line.long 0x00 "EMAC1_TM_PPS0WIDTH,EMAC1 PPS Width Register" group.long 0x1000++0x3 line.long 0x00 "EMAC1_DMA0_BUSMODE,EMAC1 DMA Bus Mode Register" bitfld.long 0x00 25. " AAL ,Address Aligned Bursts" "0,1" bitfld.long 0x00 24. " PBL8 ,PBL * 8" "0,1" bitfld.long 0x00 23. " USP ,Use Separate PBL" "0,1" newline bitfld.long 0x00 17.--22. " RPBL ,Receive Programmable Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16. " FB ,Fixed Burst" "0,1" bitfld.long 0x00 8.--13. " PBL ,Programmable Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 7. " ATDS ,Alternate Descriptor Size" "0,1" bitfld.long 0x00 2.--6. " DSL ,Descriptor Skip Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " SWR ,Software Reset" "0,1" group.long 0x1004++0x3 line.long 0x00 "EMAC1_DMA0_TXPOLL,EMAC1 DMA Tx Poll Demand Register" group.long 0x1008++0x3 line.long 0x00 "EMAC1_DMA0_RXPOLL,EMAC1 DMA Rx Poll Demand register" group.long 0x100C++0x3 line.long 0x00 "EMAC1_DMA0_RXDSC_ADDR,EMAC1 DMA Rx Descriptor List Address Register" group.long 0x1010++0x3 line.long 0x00 "EMAC1_DMA0_TXDSC_ADDR,EMAC1 DMA Tx Descriptor List Address Register" group.long 0x1014++0x3 line.long 0x00 "EMAC1_DMA0_STAT,EMAC1 DMA Status Register" bitfld.long 0x00 29. " TTI ,Time Stamp Trigger Interrupt" "0,1" bitfld.long 0x00 27. " MCI ,MAC MMC Interrupt" "0,1" bitfld.long 0x00 23.--25. " EB ,Error Bits" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20.--22. " TS ,Tx Process State" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " RS ,Rx Process State" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16. " NIS ,Normal Interrupt Summary" "0,1" newline bitfld.long 0x00 15. " AIS ,Abnormal Interrupt Summary" "0,1" bitfld.long 0x00 14. " ERI ,Early Receive Interrupt" "0,1" bitfld.long 0x00 13. " FBI ,Fatal Bus Error Interrupt" "0,1" newline bitfld.long 0x00 10. " ETI ,Early Transmit Interrupt" "0,1" bitfld.long 0x00 9. " RWT ,Receive WatchDog Timeout" "0,1" bitfld.long 0x00 8. " RPS ,Receive Process Stopped" "0,1" newline bitfld.long 0x00 7. " RU ,Receive Buffer Unavailable" "0,1" bitfld.long 0x00 6. " RI ,Receive Interrupt" "0,1" bitfld.long 0x00 5. " UNF ,Transmit Buffer Underflow" "0,1" newline bitfld.long 0x00 4. " OVF ,Receive Buffer Overflow" "0,1" bitfld.long 0x00 3. " TJT ,Transmit Jabber Timeout" "0,1" bitfld.long 0x00 2. " TU ,Transmit Buffer Unavailable" "0,1" newline bitfld.long 0x00 1. " TPS ,Transmit Process Stopped" "0,1" bitfld.long 0x00 0. " TI ,Transmit Interrupt" "0,1" group.long 0x1018++0x3 line.long 0x00 "EMAC1_DMA0_OPMODE,EMAC1 DMA Operation Mode Register" bitfld.long 0x00 26. " DT ,Disable Dropping TCP/IP Errors" "0,1" bitfld.long 0x00 25. " RSF ,Receive Store and Forward" "0,1" bitfld.long 0x00 24. " DFF ,Disable Flushing of received Frames" "0,1" newline bitfld.long 0x00 21. " TSF ,Transmit Store and Forward" "0,1" bitfld.long 0x00 20. " FTF ,Flush Transmit FIFO" "0,1" bitfld.long 0x00 14.--16. " TTC ,Transmit Threshold Control" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 13. " ST ,Start/Stop Transmission" "0,1" bitfld.long 0x00 7. " FEF ,Forward Error Frames" "0,1" bitfld.long 0x00 6. " FUF ,Forward Undersized good Frames" "0,1" newline bitfld.long 0x00 5. " DGF ,Drop Gaint Frames" "0,1" bitfld.long 0x00 3.--4. " RTC ,Receive Threshold Control" "0,1,2,3" bitfld.long 0x00 2. " OSF ,Operate on Second Frame" "0,1" newline bitfld.long 0x00 1. " SR ,Start/Stop Receive" "0,1" group.long 0x101C++0x3 line.long 0x00 "EMAC1_DMA0_IEN,EMAC1 DMA Interrupt Enable Register" bitfld.long 0x00 16. " NIE ,Normal Interrupt Summary Enable" "0,1" bitfld.long 0x00 15. " AIE ,Abnormal Interrupt Summary Enable" "0,1" bitfld.long 0x00 14. " ERE ,Early Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 13. " FBE ,Fatal Bus Error Enable" "0,1" bitfld.long 0x00 10. " ETE ,Early Transmit Interrupt Enable" "0,1" bitfld.long 0x00 9. " RWE ,Receive WatchdogTimeout Enable" "0,1" newline bitfld.long 0x00 8. " RSE ,Receive Stopped Enable" "0,1" bitfld.long 0x00 7. " RUE ,Receive Buffer Unavailable Enable" "0,1" bitfld.long 0x00 6. " RIE ,Receive Interrupt Enable" "0,1" newline bitfld.long 0x00 5. " UNE ,Underflow Interrupt Enable" "0,1" bitfld.long 0x00 4. " OVE ,Overflow Interrupt Enable" "0,1" bitfld.long 0x00 3. " TJE ,Transmit Jabber Timeout Enable" "0,1" newline bitfld.long 0x00 2. " TUE ,Transmit Buffer Unavailable Enable" "0,1" bitfld.long 0x00 1. " TSE ,Transmit Stopped Enable" "0,1" bitfld.long 0x00 0. " TIE ,Transmit Interrupt Enable" "0,1" group.long 0x1020++0x3 line.long 0x00 "EMAC1_DMA0_MISS_FRM,EMAC1 DMA Missed Frame Register" bitfld.long 0x00 28. " OVFFIFO ,Overflow bit for FIFO Overflow Counter" "0,1" hexmask.long.word 0x00 17.--27. 1. " MISSFROV ,Missed Frames Buffer Overflow" bitfld.long 0x00 16. " OVFMISS ,Overflow bit for Missed Frame Counter" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " MISSFRUN ,Missed Frames Unavailable Buffer" group.long 0x1024++0x3 line.long 0x00 "EMAC1_DMA0_RXIWDOG,EMAC1 DMA Rx Interrupt Watch Dog Register" hexmask.long.byte 0x00 0.--7. 1. " RIWT ,RI WatchDog Timer Count" group.long 0x1028++0x3 line.long 0x00 "EMAC1_DMA0_BMMODE,EMAC1 DMA SCB Bus Mode Register" bitfld.long 0x00 20.--22. " WROSRLMT ,SCB Maximum Write Outstanding Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " RDOSRLMT ,SCB Maximum Read Outstanding Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " ONEKBBE ,1K Boundary Crossing Enable" "0,1" newline bitfld.long 0x00 12. " AAL ,Address Aligned Beats" "0,1" bitfld.long 0x00 3. " BLEN16 ,SCB Burst Length 16" "0,1" bitfld.long 0x00 2. " BLEN8 ,SCB Burst Length 8" "0,1" newline bitfld.long 0x00 1. " BLEN4 ,SCB Burst Length 4" "0,1" bitfld.long 0x00 0. " UNDEF ,SCB Undefined Burst Length" "0,1" group.long 0x102C++0x3 line.long 0x00 "EMAC1_DMA0_BMSTAT,EMAC1 DMA SCB Status Register" bitfld.long 0x00 1. " BUSRD ,Bus (SCB master) Read Active" "0,1" bitfld.long 0x00 0. " BUSWR ,Bus (SCB master) Write Active" "0,1" group.long 0x1048++0x3 line.long 0x00 "EMAC1_DMA0_TXDSC_CUR,EMAC1 DMA Tx Descriptor Current Register" group.long 0x104C++0x3 line.long 0x00 "EMAC1_DMA0_RXDSC_CUR,EMAC1 DMA Rx Descriptor Current Register" group.long 0x1050++0x3 line.long 0x00 "EMAC1_DMA0_TXBUF_CUR,EMAC1 DMA Tx Buffer Current Register" group.long 0x1054++0x3 line.long 0x00 "EMAC1_DMA0_RXBUF_CUR,EMAC1 DMA Rx Buffer Current Register" tree.end tree.end tree "EMDMA (Extended Memory DMA)" tree "EMDMA0" base ad:0x310E002C width 15. group.long 0x0++0x3 line.long 0x00 "EMDMA0_CTL,EMDMA0 External Memory DMA Control Register" bitfld.long 0x00 25. " DIRS ,DMA Transfer Direction Status" "0,1" bitfld.long 0x00 24. " DMAS1 ,DMA External Interface Status" "0,1" bitfld.long 0x00 23. " WBS ,Write Back Status" "0,1" newline bitfld.long 0x00 22. " TLS ,TAP List Loading Status" "0,1" bitfld.long 0x00 21. " CHS ,DMA Chaining Status" "0,1" bitfld.long 0x00 20. " DMAS0 ,DMA Transfer Status" "0,1" newline bitfld.long 0x00 16.--17. " DFS ,DMA FIFO Status" "0,1,2,3" bitfld.long 0x00 12. " INTDONE0 ,Internal DMA Completion Interrupt (Control)" "0,1" bitfld.long 0x00 9. " TLEN ,Tap List DMA Enable" "0,1" newline bitfld.long 0x00 8. " OFCEN ,On the Fly Control Loading Enable" "0,1" bitfld.long 0x00 7. " WRBEN ,Write Back Enable" "0,1" bitfld.long 0x00 5. " DFLSH ,Flush DMA FIFO" "0,1" newline bitfld.long 0x00 4. " CBEN ,Circular Buffering Enable" "0,1" bitfld.long 0x00 3. " DLEN ,Enable Delay Line DMA" "0,1" bitfld.long 0x00 2. " CHEN ,Enable Chaining" "0,1" newline bitfld.long 0x00 1. " TRAN ,DMA Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "EMDMA0_INDX1,EMDMA0 External Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,DMA External Address Index" group.long 0x58++0x3 line.long 0x00 "EMDMA0_MOD1,EMDMA0 External Modifier Register" hexmask.long 0x00 0.--26. 1. " VALUE ,DMA External Address Modifier" group.long 0x5C++0x3 line.long 0x00 "EMDMA0_CNT1,EMDMA0 External Count Register" group.long 0x60++0x3 line.long 0x00 "EMDMA0_INDX0,EMDMA0 Internal Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,DMA buffer Start Address" group.long 0x64++0x3 line.long 0x00 "EMDMA0_MOD0,EMDMA0 Internal Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,DMA Address Modifier" group.long 0x68++0x3 line.long 0x00 "EMDMA0_CNT0,EMDMA0 Internal Count Register" group.long 0x6C++0x3 line.long 0x00 "EMDMA0_CHNPTR,EMDMA0 Chain Pointer Register" bitfld.long 0x00 31. " CPDR ,CPDR DMA Direction for the next TCB" "0,1" bitfld.long 0x00 30. " PCI ,Program Controlled Interrupt" "0,1" hexmask.long 0x00 0.--29. 1. " ADDR ,Next Descriptor (Chain) Pointer Address" group.long 0x70++0x3 line.long 0x00 "EMDMA0_BASE,EMDMA0 External Base Address Register" hexmask.long 0x00 0.--29. 1. " ADDR ,External Delay Line Base Address" group.long 0x74++0x3 line.long 0x00 "EMDMA0_TPTR,EMDMA0 Tap List Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Delay Line Tap List Pointer" group.long 0x78++0x3 line.long 0x00 "EMDMA0_BUFLEN,EMDMA0 Circular Buffer Length Register" hexmask.long 0x00 0.--25. 1. " CLEN ,Delay Line Circular Buffer Length" group.long 0x80++0x3 line.long 0x00 "EMDMA0_TCNT,EMDMA0 Delay Line Tap Count Register" tree.end tree "EMDMA1" base ad:0x310E0030 width 15. group.long 0x0++0x3 line.long 0x00 "EMDMA1_CTL,EMDMA1 External Memory DMA Control Register" bitfld.long 0x00 25. " DIRS ,DMA Transfer Direction Status" "0,1" bitfld.long 0x00 24. " DMAS1 ,DMA External Interface Status" "0,1" bitfld.long 0x00 23. " WBS ,Write Back Status" "0,1" newline bitfld.long 0x00 22. " TLS ,TAP List Loading Status" "0,1" bitfld.long 0x00 21. " CHS ,DMA Chaining Status" "0,1" bitfld.long 0x00 20. " DMAS0 ,DMA Transfer Status" "0,1" newline bitfld.long 0x00 16.--17. " DFS ,DMA FIFO Status" "0,1,2,3" bitfld.long 0x00 12. " INTDONE0 ,Internal DMA Completion Interrupt (Control)" "0,1" bitfld.long 0x00 9. " TLEN ,Tap List DMA Enable" "0,1" newline bitfld.long 0x00 8. " OFCEN ,On the Fly Control Loading Enable" "0,1" bitfld.long 0x00 7. " WRBEN ,Write Back Enable" "0,1" bitfld.long 0x00 5. " DFLSH ,Flush DMA FIFO" "0,1" newline bitfld.long 0x00 4. " CBEN ,Circular Buffering Enable" "0,1" bitfld.long 0x00 3. " DLEN ,Enable Delay Line DMA" "0,1" bitfld.long 0x00 2. " CHEN ,Enable Chaining" "0,1" newline bitfld.long 0x00 1. " TRAN ,DMA Direction" "0,1" bitfld.long 0x00 0. " EN ,DMA Enable" "0,1" group.long 0x90++0x3 line.long 0x00 "EMDMA1_INDX1,EMDMA1 External Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,DMA External Address Index" group.long 0x94++0x3 line.long 0x00 "EMDMA1_MOD1,EMDMA1 External Modifier Register" hexmask.long 0x00 0.--26. 1. " VALUE ,DMA External Address Modifier" group.long 0x98++0x3 line.long 0x00 "EMDMA1_CNT1,EMDMA1 External Count Register" group.long 0x9C++0x3 line.long 0x00 "EMDMA1_INDX0,EMDMA1 Internal Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,DMA buffer Start Address" group.long 0xA0++0x3 line.long 0x00 "EMDMA1_MOD0,EMDMA1 Internal Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,DMA Address Modifier" group.long 0xA4++0x3 line.long 0x00 "EMDMA1_CNT0,EMDMA1 Internal Count Register" group.long 0xA8++0x3 line.long 0x00 "EMDMA1_CHNPTR,EMDMA1 Chain Pointer Register" bitfld.long 0x00 31. " CPDR ,CPDR DMA Direction for the next TCB" "0,1" bitfld.long 0x00 30. " PCI ,Program Controlled Interrupt" "0,1" hexmask.long 0x00 0.--29. 1. " ADDR ,Next Descriptor (Chain) Pointer Address" group.long 0xAC++0x3 line.long 0x00 "EMDMA1_BASE,EMDMA1 External Base Address Register" hexmask.long 0x00 0.--29. 1. " ADDR ,External Delay Line Base Address" group.long 0xB0++0x3 line.long 0x00 "EMDMA1_TPTR,EMDMA1 Tap List Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Delay Line Tap List Pointer" group.long 0xB4++0x3 line.long 0x00 "EMDMA1_BUFLEN,EMDMA1 Circular Buffer Length Register" hexmask.long 0x00 0.--25. 1. " CLEN ,Delay Line Circular Buffer Length" group.long 0xBC++0x3 line.long 0x00 "EMDMA1_TCNT,EMDMA1 Delay Line Tap Count Register" tree.end tree.end tree "EPPI0" base ad:0x31029000 width 17. group.long 0x0++0x3 line.long 0x00 "EPPI0_STAT,EPPI0 Status Register" bitfld.long 0x00 15. " FLD ,Current Field Received by EPPI" "0,1" bitfld.long 0x00 14. " ERRDET ,Preamble Error Detected" "0,1" bitfld.long 0x00 7. " PXPERR ,PxP Ready Error" "0,1" newline bitfld.long 0x00 6. " ERRNCOR ,Preamble Error Not Corrected" "0,1" bitfld.long 0x00 5. " FTERRUNDR ,Frame Track Underflow" "0,1" bitfld.long 0x00 4. " FTERROVR ,Frame Track Overflow" "0,1" newline bitfld.long 0x00 3. " LTERRUNDR ,Line Track Underflow" "0,1" bitfld.long 0x00 2. " LTERROVR ,Line Track Overflow" "0,1" bitfld.long 0x00 1. " YFIFOERR ,Luma FIFO Error" "0,1" newline bitfld.long 0x00 0. " CFIFOERR ,Chroma FIFO Error" "0,1" group.long 0x4++0x3 line.long 0x00 "EPPI0_HCNT,EPPI0 Horizontal Transfer Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Horizontal Transfer Count" group.long 0x8++0x3 line.long 0x00 "EPPI0_HDLY,EPPI0 Horizontal Delay Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Horizontal Delay Count" group.long 0xC++0x3 line.long 0x00 "EPPI0_VCNT,EPPI0 Vertical Transfer Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Vertical Transfer Count" group.long 0x10++0x3 line.long 0x00 "EPPI0_VDLY,EPPI0 Vertical Delay Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Vertical Delay Count" group.long 0x14++0x3 line.long 0x00 "EPPI0_FRAME,EPPI0 Lines Per Frame Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Lines Per Frame" group.long 0x18++0x3 line.long 0x00 "EPPI0_LINE,EPPI0 Samples Per Line Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Samples Per Line" group.long 0x1C++0x3 line.long 0x00 "EPPI0_CLKDIV,EPPI0 Clock Divide Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Internal Clock Divider" group.long 0x20++0x3 line.long 0x00 "EPPI0_CTL,EPPI0 Control Register" bitfld.long 0x00 31. " CLKGATEN ,Clock Gating Enable" "0,1" bitfld.long 0x00 30. " MUXSEL ,MUX Select" "0,1" bitfld.long 0x00 29. " DMAFINEN ,DMA Finish Enable" "0,1" newline bitfld.long 0x00 28. " DMACFG ,One or Two DMA Channels Mode" "0,1" bitfld.long 0x00 27. " RGBFMTEN ,RGB Formatting Enable" "0,1" bitfld.long 0x00 26. " SPLTWRD ,Split Word" "0,1" newline bitfld.long 0x00 25. " SUBSPLTODD ,Sub-Split Odd Samples" "0,1" bitfld.long 0x00 24. " SPLTEO ,Split Even and Odd Data Samples" "0,1" bitfld.long 0x00 23. " SWAPEN ,Swap Enable" "0,1" newline bitfld.long 0x00 22. " PACKEN ,Pack/Unpack Enable" "0,1" bitfld.long 0x00 21. " SKIPEO ,Skip Even or Odd" "0,1" bitfld.long 0x00 20. " SKIPEN ,Skip Enable" "0,1" newline bitfld.long 0x00 19. " DMIRR ,Data Mirroring" "0,1" bitfld.long 0x00 16.--18. " DLEN ,Data Length" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--15. " POLS ,Frame Sync Polarity" "0,1,2,3" newline bitfld.long 0x00 12.--13. " POLC ,Clock Polarity" "0,1,2,3" bitfld.long 0x00 11. " SIGNEXT ,Sign Extension" "0,1" bitfld.long 0x00 10. " IFSGEN ,Internal Frame Sync Generation" "0,1" newline bitfld.long 0x00 9. " ICLKGEN ,Internal Clock Generation" "0,1" bitfld.long 0x00 8. " BLANKGEN ,Blanking Generation (ITU Output Mode)" "0,1" bitfld.long 0x00 7. " ITUTYPE ,ITU Interlace or Progressive" "0,1" newline bitfld.long 0x00 6. " FLDSEL ,Field Select/Trigger" "0,1" bitfld.long 0x00 4.--5. " FSCFG ,Frame Sync Configuration" "0,1,2,3" bitfld.long 0x00 2.--3. " XFRTYPE ,Transfer Type ( Operating Mode)" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,PPI Direction" "0,1" bitfld.long 0x00 0. " EN ,PPI Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "EPPI0_FS1_WLHB,EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register" group.long 0x28++0x3 line.long 0x00 "EPPI0_FS1_PASPL,EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register" group.long 0x2C++0x3 line.long 0x00 "EPPI0_FS2_WLVB,EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register" hexmask.long.byte 0x00 24.--31. 1. " F2VBAD ,Field 2 Vertical Blanking After Data" hexmask.long.byte 0x00 16.--23. 1. " F2VBBD ,Field 2 Vertical Blanking Before Data" hexmask.long.byte 0x00 8.--15. 1. " F1VBAD ,Field 1 Vertical Blanking After Data" newline hexmask.long.byte 0x00 0.--7. 1. " F1VBBD ,Field 1 Vertical Blanking Before Data" group.long 0x30++0x3 line.long 0x00 "EPPI0_FS2_PALPF,EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register" hexmask.long.word 0x00 16.--31. 1. " F2ACT ,Field 2 Active" hexmask.long.word 0x00 0.--15. 1. " F1ACT ,Field 1 Active" group.long 0x34++0x3 line.long 0x00 "EPPI0_IMSK,EPPI0 Interrupt Mask Register" bitfld.long 0x00 7. " PXPERR ,PxP Ready Error Interrupt Mask" "0,1" bitfld.long 0x00 6. " ERRNCOR ,ITU Preamble Error Not Corrected Interrupt Mask" "0,1" bitfld.long 0x00 5. " FTERRUNDR ,Frame Track Underflow Error Interrupt Mask" "0,1" newline bitfld.long 0x00 4. " FTERROVR ,Frame Track Overflow Error Interrupt Mask" "0,1" bitfld.long 0x00 3. " LTERRUNDR ,Line Track Underflow Error Interrupt Mask" "0,1" bitfld.long 0x00 2. " LTERROVR ,Line Track Overflow Error Interrupt Mask" "0,1" newline bitfld.long 0x00 1. " YFIFOERR ,YFIFO Underflow or Overflow Error Interrupt Mask" "0,1" bitfld.long 0x00 0. " CFIFOERR ,CFIFO Underflow or Overflow Error Interrupt Mask" "0,1" group.long 0x3C++0x3 line.long 0x00 "EPPI0_ODDCLIP,EPPI0 Clipping Register for ODD (Chroma) Data Register" hexmask.long.word 0x00 16.--31. 1. " HIGHODD ,High Odd Clipping Threshold (Chroma Data)" hexmask.long.word 0x00 0.--15. 1. " LOWODD ,Low Odd Clipping Threshold (Chroma Data)" group.long 0x40++0x3 line.long 0x00 "EPPI0_EVENCLIP,EPPI0 Clipping Register for EVEN (Luma) Data Register" hexmask.long.word 0x00 16.--31. 1. " HIGHEVEN ,High Even Clipping Threshold (Luma Data)" hexmask.long.word 0x00 0.--15. 1. " LOWEVEN ,Low Even Clipping Threshold (Luma Data)" group.long 0x44++0x3 line.long 0x00 "EPPI0_FS1_DLY,EPPI0 Frame Sync 1 Delay Value Register" group.long 0x48++0x3 line.long 0x00 "EPPI0_FS2_DLY,EPPI0 Frame Sync 2 Delay Value Register" group.long 0x4C++0x3 line.long 0x00 "EPPI0_CTL2,EPPI0 Control Register 2 Register" bitfld.long 0x00 1. " FS1FINEN ,HSYNC Finish Enable" "0,1" tree.end tree "FIR (FIR Accelerator)" tree "FIR0" base ad:0x310C3000 width 16. group.long 0x0++0x3 line.long 0x00 "FIR0_CTL1,FIR0 FIR Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,HALT (pause accelerator)" "0,1" bitfld.long 0x00 29. " BURST16_DIS ,Disable 16 Burst" "0,1" newline bitfld.long 0x00 28. " DCP_DIS ,Disable Data Coefficient Load in Parallel" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" newline bitfld.long 0x00 13. " TC ,Two's-Complement" "0,1" bitfld.long 0x00 12. " FXD ,Fixed-Point Accelerator Select" "0,1" bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" newline bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 6. " BURSTEN ,Burst Mode Select" "0,1" newline bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,FIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "FIR0_DMASTAT,FIR0 FIR DMA Status Register" bitfld.long 0x00 14. " HALT_STAT ,Accelerator HALT status." "0,1" bitfld.long 0x00 12.--13. " CURITER ,Current MAC Iteration" "0,1,2,3" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" bitfld.long 0x00 5. " WDONE ,Channel Done" "0,1" bitfld.long 0x00 4. " WRBK ,Writing Back" "0,1" newline bitfld.long 0x00 3. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 2. " DLD ,Data Preload" "0,1" bitfld.long 0x00 1. " CLD ,Coefficient Loading" "0,1" newline bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "FIR0_MACSTAT,FIR0 FIR MAC Status Register" bitfld.long 0x00 23. " AINV3 ,Addition Invalid" "0,1" bitfld.long 0x00 22. " ARI3 ,Adder Result Overflow" "0,1" bitfld.long 0x00 21. " ARZ3 ,Adder Result Underflow" "0,1" newline bitfld.long 0x00 20. " MINV3 ,Multiply Invalid" "0,1" bitfld.long 0x00 19. " MRI3 ,Multiplier Result Overflow" "0,1" bitfld.long 0x00 18. " MRZ3 ,Multiplier Result Underflow" "0,1" newline bitfld.long 0x00 17. " AINV2 ,Addition Invalid" "0,1" bitfld.long 0x00 16. " ARI2 ,Adder Result Overflow" "0,1" bitfld.long 0x00 15. " ARZ2 ,Adder Result Underflow" "0,1" newline bitfld.long 0x00 14. " MINV2 ,Multiply Invalid" "0,1" bitfld.long 0x00 13. " MRI2 ,Multiplier Result Overflow" "0,1" bitfld.long 0x00 12. " MRZ2 ,Multiplier Result Underflow" "0,1" newline bitfld.long 0x00 11. " AINV1 ,Addition Invalid" "0,1" bitfld.long 0x00 10. " ARI1 ,Adder Result Overflow" "0,1" bitfld.long 0x00 9. " ARZ1 ,Adder Result Underflow" "0,1" newline bitfld.long 0x00 8. " MINV1 ,Multiply Invalid" "0,1" bitfld.long 0x00 7. " MRI1 ,Multiplier Result Overflow" "0,1" bitfld.long 0x00 6. " MRZ1 ,Multiplier Result Underflow" "0,1" newline bitfld.long 0x00 5. " AINV0 ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI0 ,Adder Result Overflow" "0,1" bitfld.long 0x00 3. " ARZ0 ,Adder Result Underflow" "0,1" newline bitfld.long 0x00 2. " MINV0 ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI0 ,Multiplier Result Overflow" "0,1" bitfld.long 0x00 0. " MRZ0 ,Multiplier Result Underflow" "0,1" group.long 0x10++0x3 line.long 0x00 "FIR0_DBG_CTL,FIR0 FIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x14++0x3 line.long 0x00 "FIR0_DBG_ADDR,FIR0 Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x18++0x3 line.long 0x00 "FIR0_DBG_WRDAT,FIR0 FIR Debug Data Write Register" group.long 0x1C++0x3 line.long 0x00 "FIR0_DBG_RDDAT,FIR0 FIR Debug Data Read Register" group.long 0x40++0x3 line.long 0x00 "FIR0_CTL2,FIR0 FIR Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger Mask" "0,1" bitfld.long 0x00 30. " UPSAMP ,Up Sampling Enable" "0,1" bitfld.long 0x00 29. " SRCEN ,Sample Rate Conversion Enable" "0,1" newline bitfld.long 0x00 28. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 25.--27. " RATIO ,Up/Down Sampling Ratio" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size" bitfld.long 0x00 12.--13. " PRIO ,Priority level" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TAPLEN ,Tap Length" group.long 0x44++0x3 line.long 0x00 "FIR0_INIDX,FIR0 FIR Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Address with Lower 2 Bits Removed" group.long 0x48++0x3 line.long 0x00 "FIR0_INMOD,FIR0 FIR Input Data Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Modifier" group.long 0x4C++0x3 line.long 0x00 "FIR0_INCNT,FIR0 FIR Input Data Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Count" group.long 0x50++0x3 line.long 0x00 "FIR0_INBASE,FIR0 FIR Input Data Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Address with Lower 2 Bits Removed" group.long 0x54++0x3 line.long 0x00 "FIR0_OUTIDX,FIR0 FIR Output Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Address with Lower 2 Bits Removed" group.long 0x58++0x3 line.long 0x00 "FIR0_OUTMOD,FIR0 FIR Output Data Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Modifier" group.long 0x5C++0x3 line.long 0x00 "FIR0_OUTCNT,FIR0 FIR Output Data Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Buffer Count" group.long 0x60++0x3 line.long 0x00 "FIR0_OUTBASE,FIR0 FIR Output Data Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Address with Lower 2 Bits Removed" group.long 0x64++0x3 line.long 0x00 "FIR0_COEFIDX,FIR0 FIR Coefficient Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Addresses with Lower 2 Bits Removed" group.long 0x68++0x3 line.long 0x00 "FIR0_COEFMOD,FIR0 FIR Coefficient Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Coefficient Index Modifier" group.long 0x6C++0x3 line.long 0x00 "FIR0_COEFCNT,FIR0 FIR Coefficient Count Register" hexmask.long.word 0x00 0.--15. 1. " CCNT ,16-bit Coefficient Buffer Count" group.long 0x70++0x3 line.long 0x00 "FIR0_CHNPTR,FIR0 FIR Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "FIR0_SCTL1,FIR0 software control register 1" group.long 0x78++0x3 line.long 0x00 "FIR0_SCTL2,FIR0 software control register 2" group.long 0x7C++0x3 line.long 0x00 "FIR0_SGCTL,FIR0 Secondary global control register" bitfld.long 0x00 14. " RND ,Rounding Mode Select For Floating-Point Mode." "0,1" bitfld.long 0x00 13. " TC ,Two's-Complement Format Input Select For Fixed-Point Mode." "0,1" bitfld.long 0x00 12. " FXD ,Fixed-Point Accelerator Select." "0,1" tree.end tree "FIR1" base ad:0x310BD000 width 16. group.long 0x0++0x3 line.long 0x00 "FIR1_CTL1,FIR1 FIR Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,HALT (pause accelerator)" "0,1" bitfld.long 0x00 29. " BURST16_DIS ,Disable 16 Burst" "0,1" newline bitfld.long 0x00 28. " DCP_DIS ,Disable Data Coefficient Load in Parallel" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" newline bitfld.long 0x00 13. " TC ,Two's-Complement" "0,1" bitfld.long 0x00 12. " FXD ,Fixed-Point Accelerator Select" "0,1" bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" newline bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 6. " BURSTEN ,Burst Mode Select" "0,1" newline bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,FIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "FIR1_DMASTAT,FIR1 FIR DMA Status Register" bitfld.long 0x00 14. " HALT_STAT ,Accelerator HALT status." "0,1" bitfld.long 0x00 12.--13. " CURITER ,Current MAC Iteration" "0,1,2,3" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" bitfld.long 0x00 5. " WDONE ,Channel Done" "0,1" bitfld.long 0x00 4. " WRBK ,Writing Back" "0,1" newline bitfld.long 0x00 3. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 2. " DLD ,Data Preload" "0,1" bitfld.long 0x00 1. " CLD ,Coefficient Loading" "0,1" newline bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "FIR1_MACSTAT,FIR1 FIR MAC Status Register" bitfld.long 0x00 23. " AINV3 ,Addition Invalid" "0,1" bitfld.long 0x00 22. " ARI3 ,Adder Result Overflow" "0,1" bitfld.long 0x00 21. " ARZ3 ,Adder Result Underflow" "0,1" newline bitfld.long 0x00 20. " MINV3 ,Multiply Invalid" "0,1" bitfld.long 0x00 19. " MRI3 ,Multiplier Result Overflow" "0,1" bitfld.long 0x00 18. " MRZ3 ,Multiplier Result Underflow" "0,1" newline bitfld.long 0x00 17. " AINV2 ,Addition Invalid" "0,1" bitfld.long 0x00 16. " ARI2 ,Adder Result Overflow" "0,1" bitfld.long 0x00 15. " ARZ2 ,Adder Result Underflow" "0,1" newline bitfld.long 0x00 14. " MINV2 ,Multiply Invalid" "0,1" bitfld.long 0x00 13. " MRI2 ,Multiplier Result Overflow" "0,1" bitfld.long 0x00 12. " MRZ2 ,Multiplier Result Underflow" "0,1" newline bitfld.long 0x00 11. " AINV1 ,Addition Invalid" "0,1" bitfld.long 0x00 10. " ARI1 ,Adder Result Overflow" "0,1" bitfld.long 0x00 9. " ARZ1 ,Adder Result Underflow" "0,1" newline bitfld.long 0x00 8. " MINV1 ,Multiply Invalid" "0,1" bitfld.long 0x00 7. " MRI1 ,Multiplier Result Overflow" "0,1" bitfld.long 0x00 6. " MRZ1 ,Multiplier Result Underflow" "0,1" newline bitfld.long 0x00 5. " AINV0 ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI0 ,Adder Result Overflow" "0,1" bitfld.long 0x00 3. " ARZ0 ,Adder Result Underflow" "0,1" newline bitfld.long 0x00 2. " MINV0 ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI0 ,Multiplier Result Overflow" "0,1" bitfld.long 0x00 0. " MRZ0 ,Multiplier Result Underflow" "0,1" group.long 0x10++0x3 line.long 0x00 "FIR1_DBG_CTL,FIR1 FIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x14++0x3 line.long 0x00 "FIR1_DBG_ADDR,FIR1 Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x18++0x3 line.long 0x00 "FIR1_DBG_WRDAT,FIR1 FIR Debug Data Write Register" group.long 0x1C++0x3 line.long 0x00 "FIR1_DBG_RDDAT,FIR1 FIR Debug Data Read Register" group.long 0x40++0x3 line.long 0x00 "FIR1_CTL2,FIR1 FIR Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger Mask" "0,1" bitfld.long 0x00 30. " UPSAMP ,Up Sampling Enable" "0,1" bitfld.long 0x00 29. " SRCEN ,Sample Rate Conversion Enable" "0,1" newline bitfld.long 0x00 28. " TWAIT ,Wait for Trigger" "0,1" bitfld.long 0x00 25.--27. " RATIO ,Up/Down Sampling Ratio" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size" bitfld.long 0x00 12.--13. " PRIO ,Priority level" "0,1,2,3" hexmask.long.word 0x00 0.--11. 1. " TAPLEN ,Tap Length" group.long 0x44++0x3 line.long 0x00 "FIR1_INIDX,FIR1 FIR Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Address with Lower 2 Bits Removed" group.long 0x48++0x3 line.long 0x00 "FIR1_INMOD,FIR1 FIR Input Data Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Modifier" group.long 0x4C++0x3 line.long 0x00 "FIR1_INCNT,FIR1 FIR Input Data Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Count" group.long 0x50++0x3 line.long 0x00 "FIR1_INBASE,FIR1 FIR Input Data Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Address with Lower 2 Bits Removed" group.long 0x54++0x3 line.long 0x00 "FIR1_OUTIDX,FIR1 FIR Output Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Address with Lower 2 Bits Removed" group.long 0x58++0x3 line.long 0x00 "FIR1_OUTMOD,FIR1 FIR Output Data Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Modifier" group.long 0x5C++0x3 line.long 0x00 "FIR1_OUTCNT,FIR1 FIR Output Data Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Buffer Count" group.long 0x60++0x3 line.long 0x00 "FIR1_OUTBASE,FIR1 FIR Output Data Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Address with Lower 2 Bits Removed" group.long 0x64++0x3 line.long 0x00 "FIR1_COEFIDX,FIR1 FIR Coefficient Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Word Addresses with Lower 2 Bits Removed" group.long 0x68++0x3 line.long 0x00 "FIR1_COEFMOD,FIR1 FIR Coefficient Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Coefficient Index Modifier" group.long 0x6C++0x3 line.long 0x00 "FIR1_COEFCNT,FIR1 FIR Coefficient Count Register" hexmask.long.word 0x00 0.--15. 1. " CCNT ,16-bit Coefficient Buffer Count" group.long 0x70++0x3 line.long 0x00 "FIR1_CHNPTR,FIR1 FIR Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "FIR1_SCTL1,FIR1 software control register 1" group.long 0x78++0x3 line.long 0x00 "FIR1_SCTL2,FIR1 software control register 2" group.long 0x7C++0x3 line.long 0x00 "FIR1_SGCTL,FIR1 Secondary global control register" bitfld.long 0x00 14. " RND ,Rounding Mode Select For Floating-Point Mode." "0,1" bitfld.long 0x00 13. " TC ,Two's-Complement Format Input Select For Fixed-Point Mode." "0,1" bitfld.long 0x00 12. " FXD ,Fixed-Point Accelerator Select." "0,1" tree.end tree.end tree "GICCPU0" base ad:0x310B4000 width 22. group.long 0x0++0x3 line.long 0x00 "GICCPU0_CTL,GICCPU0 CPU Interface Control Register (ICCICR)" group.long 0x4++0x3 line.long 0x00 "GICCPU0_PRIO_MSK,GICCPU0 Priority Mask Register (ICCIPMR)" group.long 0x8++0x3 line.long 0x00 "GICCPU0_BIN_PT,GICCPU0 Binary Point Register (ICCBPR)" group.long 0xC++0x3 line.long 0x00 "GICCPU0_INT_ACK,GICCPU0 Interrupt Acknowledge Register (ICCIAR)" group.long 0x10++0x3 line.long 0x00 "GICCPU0_EOI,GICCPU0 End of Interrupt Register (ICCEOIR)" group.long 0x14++0x3 line.long 0x00 "GICCPU0_RUN_PRIO,GICCPU0 Running Priority Register (ICCRPR)" group.long 0x18++0x3 line.long 0x00 "GICCPU0_PND_HI,GICCPU0 Highest Pending Interrupt Register (ICCHPIR)" group.long 0x1C++0x3 line.long 0x00 "GICCPU0_BIN_PT_ALIAS,GICCPU0 Aliased Binary Point Register (ICCABPR)" tree.end tree "GICDST0" base ad:0x310B2000 width 24. group.long 0x0++0x3 line.long 0x00 "GICDST0_EN,GICDST0 GIC Port 0 Enable" bitfld.long 0x00 0. " VALUE ,Global Interrupt Monitor Enable" "0,1" group.word 0x80++0x1 line.word 0x00 "GICDST0_SGI_SECURITY,GICDST0 Software Generated Interrupt Security Register" group.long 0x84++0x3 line.long 0x00 "GICDST0_SPI_SECURITY0,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0x88++0x3 line.long 0x00 "GICDST0_SPI_SECURITY1,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0x8C++0x3 line.long 0x00 "GICDST0_SPI_SECURITY2,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0x90++0x3 line.long 0x00 "GICDST0_SPI_SECURITY3,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0x94++0x3 line.long 0x00 "GICDST0_SPI_SECURITY4,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0x98++0x3 line.long 0x00 "GICDST0_SPI_SECURITY5,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0x9C++0x3 line.long 0x00 "GICDST0_SPI_SECURITY6,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0xA0++0x3 line.long 0x00 "GICDST0_SPI_SECURITY7,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0xA4++0x3 line.long 0x00 "GICDST0_SPI_SECURITY8,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0xA8++0x3 line.long 0x00 "GICDST0_SPI_SECURITY9,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0xAC++0x3 line.long 0x00 "GICDST0_SPI_SECURITY10,GICDST0 Shared Peripheral Interrupt Security Register" group.long 0x104++0x3 line.long 0x00 "GICDST0_SPI_EN_SET0,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x108++0x3 line.long 0x00 "GICDST0_SPI_EN_SET1,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x10C++0x3 line.long 0x00 "GICDST0_SPI_EN_SET2,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x110++0x3 line.long 0x00 "GICDST0_SPI_EN_SET3,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x114++0x3 line.long 0x00 "GICDST0_SPI_EN_SET4,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x118++0x3 line.long 0x00 "GICDST0_SPI_EN_SET5,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x11C++0x3 line.long 0x00 "GICDST0_SPI_EN_SET6,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x120++0x3 line.long 0x00 "GICDST0_SPI_EN_SET7,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x124++0x3 line.long 0x00 "GICDST0_SPI_EN_SET8,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x128++0x3 line.long 0x00 "GICDST0_SPI_EN_SET9,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x12C++0x3 line.long 0x00 "GICDST0_SPI_EN_SET10,GICDST0 Shared Peripheral Interrupt Enable Set Register" group.long 0x184++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR0,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x188++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR1,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x18C++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR2,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x190++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR3,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x194++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR4,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x198++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR5,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x19C++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR6,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x1A0++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR7,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x1A4++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR8,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x1A8++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR9,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.long 0x1AC++0x3 line.long 0x00 "GICDST0_SPI_EN_CLR10,GICDST0 Shared Peripheral Interrupt Enable Clear Register" group.word 0x200++0x1 line.word 0x00 "GICDST0_SGI_PND_SET,GICDST0 Software Generated Interrupt Pending Set Register" group.long 0x204++0x3 line.long 0x00 "GICDST0_SPI_PND_SET0,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x208++0x3 line.long 0x00 "GICDST0_SPI_PND_SET1,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x20C++0x3 line.long 0x00 "GICDST0_SPI_PND_SET2,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x210++0x3 line.long 0x00 "GICDST0_SPI_PND_SET3,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x214++0x3 line.long 0x00 "GICDST0_SPI_PND_SET4,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x218++0x3 line.long 0x00 "GICDST0_SPI_PND_SET5,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x21C++0x3 line.long 0x00 "GICDST0_SPI_PND_SET6,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x220++0x3 line.long 0x00 "GICDST0_SPI_PND_SET7,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x224++0x3 line.long 0x00 "GICDST0_SPI_PND_SET8,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x228++0x3 line.long 0x00 "GICDST0_SPI_PND_SET9,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.long 0x22C++0x3 line.long 0x00 "GICDST0_SPI_PND_SET10,GICDST0 Shared Peripheral Interrupt Pending Set Register" group.word 0x280++0x1 line.word 0x00 "GICDST0_SGI_PND_CLR,GICDST0 Software Generated Interrupt Clear-Pending Register" group.long 0x284++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR0,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x288++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR1,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x28C++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR2,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x290++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR3,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x294++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR4,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x298++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR5,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x29C++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR6,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x2A0++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR7,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x2A4++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR8,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x2A8++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR9,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.long 0x2AC++0x3 line.long 0x00 "GICDST0_SPI_PND_CLR10,GICDST0 Shared Peripheral Interrupt Pending Clear Register" group.word 0x300++0x1 line.word 0x00 "GICDST0_SGI_ACTIVE,GICDST0 Software Generated Interrupt Active Register" group.long 0x304++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE0,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x308++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE1,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x30C++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE2,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x310++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE3,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x314++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE4,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x318++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE5,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x31C++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE6,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x320++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE7,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x324++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE8,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x328++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE9,GICDST0 Shared Peripheral Interrupt Active Register" group.long 0x32C++0x3 line.long 0x00 "GICDST0_SPI_ACTIVE10,GICDST0 Shared Peripheral Interrupt Active Register" group.byte 0x400++0x0 line.byte 0x00 "GICDST0_SGI_PRIO0,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x401++0x0 line.byte 0x00 "GICDST0_SGI_PRIO1,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x402++0x0 line.byte 0x00 "GICDST0_SGI_PRIO2,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x403++0x0 line.byte 0x00 "GICDST0_SGI_PRIO3,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x404++0x0 line.byte 0x00 "GICDST0_SGI_PRIO4,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x405++0x0 line.byte 0x00 "GICDST0_SGI_PRIO5,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x406++0x0 line.byte 0x00 "GICDST0_SGI_PRIO6,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x407++0x0 line.byte 0x00 "GICDST0_SGI_PRIO7,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x408++0x0 line.byte 0x00 "GICDST0_SGI_PRIO8,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x409++0x0 line.byte 0x00 "GICDST0_SGI_PRIO9,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x40A++0x0 line.byte 0x00 "GICDST0_SGI_PRIO10,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x40B++0x0 line.byte 0x00 "GICDST0_SGI_PRIO11,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x40C++0x0 line.byte 0x00 "GICDST0_SGI_PRIO12,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x40D++0x0 line.byte 0x00 "GICDST0_SGI_PRIO13,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x40E++0x0 line.byte 0x00 "GICDST0_SGI_PRIO14,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x40F++0x0 line.byte 0x00 "GICDST0_SGI_PRIO15,GICDST0 Software Generated Interrupt Priority Register" group.byte 0x420++0x0 line.byte 0x00 "GICDST0_SPI_PRIO0,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x421++0x0 line.byte 0x00 "GICDST0_SPI_PRIO1,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x422++0x0 line.byte 0x00 "GICDST0_SPI_PRIO2,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x423++0x0 line.byte 0x00 "GICDST0_SPI_PRIO3,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x424++0x0 line.byte 0x00 "GICDST0_SPI_PRIO4,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x425++0x0 line.byte 0x00 "GICDST0_SPI_PRIO5,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x426++0x0 line.byte 0x00 "GICDST0_SPI_PRIO6,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x427++0x0 line.byte 0x00 "GICDST0_SPI_PRIO7,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x428++0x0 line.byte 0x00 "GICDST0_SPI_PRIO8,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x429++0x0 line.byte 0x00 "GICDST0_SPI_PRIO9,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x42A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO10,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x42B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO11,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x42C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO12,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x42D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO13,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x42E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO14,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x42F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO15,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x430++0x0 line.byte 0x00 "GICDST0_SPI_PRIO16,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x431++0x0 line.byte 0x00 "GICDST0_SPI_PRIO17,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x432++0x0 line.byte 0x00 "GICDST0_SPI_PRIO18,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x433++0x0 line.byte 0x00 "GICDST0_SPI_PRIO19,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x434++0x0 line.byte 0x00 "GICDST0_SPI_PRIO20,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x435++0x0 line.byte 0x00 "GICDST0_SPI_PRIO21,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x436++0x0 line.byte 0x00 "GICDST0_SPI_PRIO22,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x437++0x0 line.byte 0x00 "GICDST0_SPI_PRIO23,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x438++0x0 line.byte 0x00 "GICDST0_SPI_PRIO24,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x439++0x0 line.byte 0x00 "GICDST0_SPI_PRIO25,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x43A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO26,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x43B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO27,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x43C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO28,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x43D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO29,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x43E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO30,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x43F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO31,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x440++0x0 line.byte 0x00 "GICDST0_SPI_PRIO32,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x441++0x0 line.byte 0x00 "GICDST0_SPI_PRIO33,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x442++0x0 line.byte 0x00 "GICDST0_SPI_PRIO34,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x443++0x0 line.byte 0x00 "GICDST0_SPI_PRIO35,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x444++0x0 line.byte 0x00 "GICDST0_SPI_PRIO36,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x445++0x0 line.byte 0x00 "GICDST0_SPI_PRIO37,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x446++0x0 line.byte 0x00 "GICDST0_SPI_PRIO38,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x447++0x0 line.byte 0x00 "GICDST0_SPI_PRIO39,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x448++0x0 line.byte 0x00 "GICDST0_SPI_PRIO40,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x449++0x0 line.byte 0x00 "GICDST0_SPI_PRIO41,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x44A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO42,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x44B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO43,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x44C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO44,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x44D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO45,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x44E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO46,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x44F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO47,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x450++0x0 line.byte 0x00 "GICDST0_SPI_PRIO48,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x451++0x0 line.byte 0x00 "GICDST0_SPI_PRIO49,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x452++0x0 line.byte 0x00 "GICDST0_SPI_PRIO50,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x453++0x0 line.byte 0x00 "GICDST0_SPI_PRIO51,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x454++0x0 line.byte 0x00 "GICDST0_SPI_PRIO52,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x455++0x0 line.byte 0x00 "GICDST0_SPI_PRIO53,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x456++0x0 line.byte 0x00 "GICDST0_SPI_PRIO54,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x457++0x0 line.byte 0x00 "GICDST0_SPI_PRIO55,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x458++0x0 line.byte 0x00 "GICDST0_SPI_PRIO56,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x459++0x0 line.byte 0x00 "GICDST0_SPI_PRIO57,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x45A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO58,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x45B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO59,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x45C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO60,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x45D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO61,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x45E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO62,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x45F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO63,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x460++0x0 line.byte 0x00 "GICDST0_SPI_PRIO64,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x461++0x0 line.byte 0x00 "GICDST0_SPI_PRIO65,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x462++0x0 line.byte 0x00 "GICDST0_SPI_PRIO66,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x463++0x0 line.byte 0x00 "GICDST0_SPI_PRIO67,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x464++0x0 line.byte 0x00 "GICDST0_SPI_PRIO68,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x465++0x0 line.byte 0x00 "GICDST0_SPI_PRIO69,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x466++0x0 line.byte 0x00 "GICDST0_SPI_PRIO70,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x467++0x0 line.byte 0x00 "GICDST0_SPI_PRIO71,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x468++0x0 line.byte 0x00 "GICDST0_SPI_PRIO72,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x469++0x0 line.byte 0x00 "GICDST0_SPI_PRIO73,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x46A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO74,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x46B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO75,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x46C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO76,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x46D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO77,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x46E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO78,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x46F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO79,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x470++0x0 line.byte 0x00 "GICDST0_SPI_PRIO80,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x471++0x0 line.byte 0x00 "GICDST0_SPI_PRIO81,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x472++0x0 line.byte 0x00 "GICDST0_SPI_PRIO82,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x473++0x0 line.byte 0x00 "GICDST0_SPI_PRIO83,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x474++0x0 line.byte 0x00 "GICDST0_SPI_PRIO84,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x475++0x0 line.byte 0x00 "GICDST0_SPI_PRIO85,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x476++0x0 line.byte 0x00 "GICDST0_SPI_PRIO86,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x477++0x0 line.byte 0x00 "GICDST0_SPI_PRIO87,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x478++0x0 line.byte 0x00 "GICDST0_SPI_PRIO88,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x479++0x0 line.byte 0x00 "GICDST0_SPI_PRIO89,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x47A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO90,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x47B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO91,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x47C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO92,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x47D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO93,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x47E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO94,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x47F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO95,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x480++0x0 line.byte 0x00 "GICDST0_SPI_PRIO96,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x481++0x0 line.byte 0x00 "GICDST0_SPI_PRIO97,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x482++0x0 line.byte 0x00 "GICDST0_SPI_PRIO98,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x483++0x0 line.byte 0x00 "GICDST0_SPI_PRIO99,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x484++0x0 line.byte 0x00 "GICDST0_SPI_PRIO100,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x485++0x0 line.byte 0x00 "GICDST0_SPI_PRIO101,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x486++0x0 line.byte 0x00 "GICDST0_SPI_PRIO102,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x487++0x0 line.byte 0x00 "GICDST0_SPI_PRIO103,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x488++0x0 line.byte 0x00 "GICDST0_SPI_PRIO104,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x489++0x0 line.byte 0x00 "GICDST0_SPI_PRIO105,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x48A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO106,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x48B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO107,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x48C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO108,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x48D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO109,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x48E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO110,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x48F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO111,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x490++0x0 line.byte 0x00 "GICDST0_SPI_PRIO112,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x491++0x0 line.byte 0x00 "GICDST0_SPI_PRIO113,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x492++0x0 line.byte 0x00 "GICDST0_SPI_PRIO114,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x493++0x0 line.byte 0x00 "GICDST0_SPI_PRIO115,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x494++0x0 line.byte 0x00 "GICDST0_SPI_PRIO116,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x495++0x0 line.byte 0x00 "GICDST0_SPI_PRIO117,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x496++0x0 line.byte 0x00 "GICDST0_SPI_PRIO118,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x497++0x0 line.byte 0x00 "GICDST0_SPI_PRIO119,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x498++0x0 line.byte 0x00 "GICDST0_SPI_PRIO120,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x499++0x0 line.byte 0x00 "GICDST0_SPI_PRIO121,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x49A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO122,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x49B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO123,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x49C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO124,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x49D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO125,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x49E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO126,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x49F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO127,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A0++0x0 line.byte 0x00 "GICDST0_SPI_PRIO128,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A1++0x0 line.byte 0x00 "GICDST0_SPI_PRIO129,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A2++0x0 line.byte 0x00 "GICDST0_SPI_PRIO130,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A3++0x0 line.byte 0x00 "GICDST0_SPI_PRIO131,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A4++0x0 line.byte 0x00 "GICDST0_SPI_PRIO132,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A5++0x0 line.byte 0x00 "GICDST0_SPI_PRIO133,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A6++0x0 line.byte 0x00 "GICDST0_SPI_PRIO134,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A7++0x0 line.byte 0x00 "GICDST0_SPI_PRIO135,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A8++0x0 line.byte 0x00 "GICDST0_SPI_PRIO136,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4A9++0x0 line.byte 0x00 "GICDST0_SPI_PRIO137,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4AA++0x0 line.byte 0x00 "GICDST0_SPI_PRIO138,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4AB++0x0 line.byte 0x00 "GICDST0_SPI_PRIO139,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4AC++0x0 line.byte 0x00 "GICDST0_SPI_PRIO140,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4AD++0x0 line.byte 0x00 "GICDST0_SPI_PRIO141,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4AE++0x0 line.byte 0x00 "GICDST0_SPI_PRIO142,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4AF++0x0 line.byte 0x00 "GICDST0_SPI_PRIO143,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B0++0x0 line.byte 0x00 "GICDST0_SPI_PRIO144,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B1++0x0 line.byte 0x00 "GICDST0_SPI_PRIO145,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B2++0x0 line.byte 0x00 "GICDST0_SPI_PRIO146,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B3++0x0 line.byte 0x00 "GICDST0_SPI_PRIO147,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B4++0x0 line.byte 0x00 "GICDST0_SPI_PRIO148,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B5++0x0 line.byte 0x00 "GICDST0_SPI_PRIO149,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B6++0x0 line.byte 0x00 "GICDST0_SPI_PRIO150,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B7++0x0 line.byte 0x00 "GICDST0_SPI_PRIO151,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B8++0x0 line.byte 0x00 "GICDST0_SPI_PRIO152,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4B9++0x0 line.byte 0x00 "GICDST0_SPI_PRIO153,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4BA++0x0 line.byte 0x00 "GICDST0_SPI_PRIO154,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4BB++0x0 line.byte 0x00 "GICDST0_SPI_PRIO155,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4BC++0x0 line.byte 0x00 "GICDST0_SPI_PRIO156,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4BD++0x0 line.byte 0x00 "GICDST0_SPI_PRIO157,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4BE++0x0 line.byte 0x00 "GICDST0_SPI_PRIO158,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4BF++0x0 line.byte 0x00 "GICDST0_SPI_PRIO159,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C0++0x0 line.byte 0x00 "GICDST0_SPI_PRIO160,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C1++0x0 line.byte 0x00 "GICDST0_SPI_PRIO161,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C2++0x0 line.byte 0x00 "GICDST0_SPI_PRIO162,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C3++0x0 line.byte 0x00 "GICDST0_SPI_PRIO163,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C4++0x0 line.byte 0x00 "GICDST0_SPI_PRIO164,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C5++0x0 line.byte 0x00 "GICDST0_SPI_PRIO165,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C6++0x0 line.byte 0x00 "GICDST0_SPI_PRIO166,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C7++0x0 line.byte 0x00 "GICDST0_SPI_PRIO167,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C8++0x0 line.byte 0x00 "GICDST0_SPI_PRIO168,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4C9++0x0 line.byte 0x00 "GICDST0_SPI_PRIO169,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4CA++0x0 line.byte 0x00 "GICDST0_SPI_PRIO170,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4CB++0x0 line.byte 0x00 "GICDST0_SPI_PRIO171,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4CC++0x0 line.byte 0x00 "GICDST0_SPI_PRIO172,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4CD++0x0 line.byte 0x00 "GICDST0_SPI_PRIO173,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4CE++0x0 line.byte 0x00 "GICDST0_SPI_PRIO174,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4CF++0x0 line.byte 0x00 "GICDST0_SPI_PRIO175,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D0++0x0 line.byte 0x00 "GICDST0_SPI_PRIO176,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D1++0x0 line.byte 0x00 "GICDST0_SPI_PRIO177,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D2++0x0 line.byte 0x00 "GICDST0_SPI_PRIO178,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D3++0x0 line.byte 0x00 "GICDST0_SPI_PRIO179,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D4++0x0 line.byte 0x00 "GICDST0_SPI_PRIO180,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D5++0x0 line.byte 0x00 "GICDST0_SPI_PRIO181,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D6++0x0 line.byte 0x00 "GICDST0_SPI_PRIO182,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D7++0x0 line.byte 0x00 "GICDST0_SPI_PRIO183,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D8++0x0 line.byte 0x00 "GICDST0_SPI_PRIO184,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4D9++0x0 line.byte 0x00 "GICDST0_SPI_PRIO185,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4DA++0x0 line.byte 0x00 "GICDST0_SPI_PRIO186,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4DB++0x0 line.byte 0x00 "GICDST0_SPI_PRIO187,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4DC++0x0 line.byte 0x00 "GICDST0_SPI_PRIO188,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4DD++0x0 line.byte 0x00 "GICDST0_SPI_PRIO189,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4DE++0x0 line.byte 0x00 "GICDST0_SPI_PRIO190,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4DF++0x0 line.byte 0x00 "GICDST0_SPI_PRIO191,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E0++0x0 line.byte 0x00 "GICDST0_SPI_PRIO192,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E1++0x0 line.byte 0x00 "GICDST0_SPI_PRIO193,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E2++0x0 line.byte 0x00 "GICDST0_SPI_PRIO194,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E3++0x0 line.byte 0x00 "GICDST0_SPI_PRIO195,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E4++0x0 line.byte 0x00 "GICDST0_SPI_PRIO196,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E5++0x0 line.byte 0x00 "GICDST0_SPI_PRIO197,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E6++0x0 line.byte 0x00 "GICDST0_SPI_PRIO198,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E7++0x0 line.byte 0x00 "GICDST0_SPI_PRIO199,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E8++0x0 line.byte 0x00 "GICDST0_SPI_PRIO200,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4E9++0x0 line.byte 0x00 "GICDST0_SPI_PRIO201,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4EA++0x0 line.byte 0x00 "GICDST0_SPI_PRIO202,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4EB++0x0 line.byte 0x00 "GICDST0_SPI_PRIO203,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4EC++0x0 line.byte 0x00 "GICDST0_SPI_PRIO204,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4ED++0x0 line.byte 0x00 "GICDST0_SPI_PRIO205,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4EE++0x0 line.byte 0x00 "GICDST0_SPI_PRIO206,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4EF++0x0 line.byte 0x00 "GICDST0_SPI_PRIO207,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F0++0x0 line.byte 0x00 "GICDST0_SPI_PRIO208,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F1++0x0 line.byte 0x00 "GICDST0_SPI_PRIO209,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F2++0x0 line.byte 0x00 "GICDST0_SPI_PRIO210,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F3++0x0 line.byte 0x00 "GICDST0_SPI_PRIO211,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F4++0x0 line.byte 0x00 "GICDST0_SPI_PRIO212,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F5++0x0 line.byte 0x00 "GICDST0_SPI_PRIO213,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F6++0x0 line.byte 0x00 "GICDST0_SPI_PRIO214,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F7++0x0 line.byte 0x00 "GICDST0_SPI_PRIO215,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F8++0x0 line.byte 0x00 "GICDST0_SPI_PRIO216,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4F9++0x0 line.byte 0x00 "GICDST0_SPI_PRIO217,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4FA++0x0 line.byte 0x00 "GICDST0_SPI_PRIO218,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4FB++0x0 line.byte 0x00 "GICDST0_SPI_PRIO219,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4FC++0x0 line.byte 0x00 "GICDST0_SPI_PRIO220,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4FD++0x0 line.byte 0x00 "GICDST0_SPI_PRIO221,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4FE++0x0 line.byte 0x00 "GICDST0_SPI_PRIO222,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x4FF++0x0 line.byte 0x00 "GICDST0_SPI_PRIO223,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x500++0x0 line.byte 0x00 "GICDST0_SPI_PRIO224,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x501++0x0 line.byte 0x00 "GICDST0_SPI_PRIO225,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x502++0x0 line.byte 0x00 "GICDST0_SPI_PRIO226,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x503++0x0 line.byte 0x00 "GICDST0_SPI_PRIO227,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x504++0x0 line.byte 0x00 "GICDST0_SPI_PRIO228,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x505++0x0 line.byte 0x00 "GICDST0_SPI_PRIO229,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x506++0x0 line.byte 0x00 "GICDST0_SPI_PRIO230,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x507++0x0 line.byte 0x00 "GICDST0_SPI_PRIO231,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x508++0x0 line.byte 0x00 "GICDST0_SPI_PRIO232,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x509++0x0 line.byte 0x00 "GICDST0_SPI_PRIO233,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x50A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO234,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x50B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO235,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x50C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO236,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x50D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO237,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x50E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO238,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x50F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO239,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x510++0x0 line.byte 0x00 "GICDST0_SPI_PRIO240,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x511++0x0 line.byte 0x00 "GICDST0_SPI_PRIO241,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x512++0x0 line.byte 0x00 "GICDST0_SPI_PRIO242,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x513++0x0 line.byte 0x00 "GICDST0_SPI_PRIO243,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x514++0x0 line.byte 0x00 "GICDST0_SPI_PRIO244,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x515++0x0 line.byte 0x00 "GICDST0_SPI_PRIO245,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x516++0x0 line.byte 0x00 "GICDST0_SPI_PRIO246,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x517++0x0 line.byte 0x00 "GICDST0_SPI_PRIO247,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x518++0x0 line.byte 0x00 "GICDST0_SPI_PRIO248,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x519++0x0 line.byte 0x00 "GICDST0_SPI_PRIO249,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x51A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO250,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x51B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO251,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x51C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO252,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x51D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO253,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x51E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO254,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x51F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO255,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x520++0x0 line.byte 0x00 "GICDST0_SPI_PRIO256,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x521++0x0 line.byte 0x00 "GICDST0_SPI_PRIO257,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x522++0x0 line.byte 0x00 "GICDST0_SPI_PRIO258,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x523++0x0 line.byte 0x00 "GICDST0_SPI_PRIO259,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x524++0x0 line.byte 0x00 "GICDST0_SPI_PRIO260,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x525++0x0 line.byte 0x00 "GICDST0_SPI_PRIO261,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x526++0x0 line.byte 0x00 "GICDST0_SPI_PRIO262,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x527++0x0 line.byte 0x00 "GICDST0_SPI_PRIO263,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x528++0x0 line.byte 0x00 "GICDST0_SPI_PRIO264,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x529++0x0 line.byte 0x00 "GICDST0_SPI_PRIO265,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x52A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO266,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x52B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO267,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x52C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO268,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x52D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO269,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x52E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO270,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x52F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO271,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x530++0x0 line.byte 0x00 "GICDST0_SPI_PRIO272,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x531++0x0 line.byte 0x00 "GICDST0_SPI_PRIO273,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x532++0x0 line.byte 0x00 "GICDST0_SPI_PRIO274,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x533++0x0 line.byte 0x00 "GICDST0_SPI_PRIO275,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x534++0x0 line.byte 0x00 "GICDST0_SPI_PRIO276,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x535++0x0 line.byte 0x00 "GICDST0_SPI_PRIO277,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x536++0x0 line.byte 0x00 "GICDST0_SPI_PRIO278,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x537++0x0 line.byte 0x00 "GICDST0_SPI_PRIO279,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x538++0x0 line.byte 0x00 "GICDST0_SPI_PRIO280,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x539++0x0 line.byte 0x00 "GICDST0_SPI_PRIO281,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x53A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO282,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x53B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO283,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x53C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO284,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x53D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO285,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x53E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO286,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x53F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO287,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x540++0x0 line.byte 0x00 "GICDST0_SPI_PRIO288,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x541++0x0 line.byte 0x00 "GICDST0_SPI_PRIO289,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x542++0x0 line.byte 0x00 "GICDST0_SPI_PRIO290,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x543++0x0 line.byte 0x00 "GICDST0_SPI_PRIO291,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x544++0x0 line.byte 0x00 "GICDST0_SPI_PRIO292,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x545++0x0 line.byte 0x00 "GICDST0_SPI_PRIO293,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x546++0x0 line.byte 0x00 "GICDST0_SPI_PRIO294,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x547++0x0 line.byte 0x00 "GICDST0_SPI_PRIO295,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x548++0x0 line.byte 0x00 "GICDST0_SPI_PRIO296,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x549++0x0 line.byte 0x00 "GICDST0_SPI_PRIO297,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x54A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO298,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x54B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO299,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x54C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO300,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x54D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO301,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x54E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO302,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x54F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO303,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x550++0x0 line.byte 0x00 "GICDST0_SPI_PRIO304,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x551++0x0 line.byte 0x00 "GICDST0_SPI_PRIO305,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x552++0x0 line.byte 0x00 "GICDST0_SPI_PRIO306,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x553++0x0 line.byte 0x00 "GICDST0_SPI_PRIO307,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x554++0x0 line.byte 0x00 "GICDST0_SPI_PRIO308,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x555++0x0 line.byte 0x00 "GICDST0_SPI_PRIO309,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x556++0x0 line.byte 0x00 "GICDST0_SPI_PRIO310,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x557++0x0 line.byte 0x00 "GICDST0_SPI_PRIO311,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x558++0x0 line.byte 0x00 "GICDST0_SPI_PRIO312,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x559++0x0 line.byte 0x00 "GICDST0_SPI_PRIO313,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x55A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO314,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x55B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO315,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x55C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO316,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x55D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO317,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x55E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO318,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x55F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO319,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x560++0x0 line.byte 0x00 "GICDST0_SPI_PRIO320,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x561++0x0 line.byte 0x00 "GICDST0_SPI_PRIO321,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x562++0x0 line.byte 0x00 "GICDST0_SPI_PRIO322,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x563++0x0 line.byte 0x00 "GICDST0_SPI_PRIO323,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x564++0x0 line.byte 0x00 "GICDST0_SPI_PRIO324,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x565++0x0 line.byte 0x00 "GICDST0_SPI_PRIO325,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x566++0x0 line.byte 0x00 "GICDST0_SPI_PRIO326,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x567++0x0 line.byte 0x00 "GICDST0_SPI_PRIO327,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x568++0x0 line.byte 0x00 "GICDST0_SPI_PRIO328,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x569++0x0 line.byte 0x00 "GICDST0_SPI_PRIO329,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x56A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO330,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x56B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO331,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x56C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO332,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x56D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO333,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x56E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO334,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x56F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO335,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x570++0x0 line.byte 0x00 "GICDST0_SPI_PRIO336,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x571++0x0 line.byte 0x00 "GICDST0_SPI_PRIO337,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x572++0x0 line.byte 0x00 "GICDST0_SPI_PRIO338,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x573++0x0 line.byte 0x00 "GICDST0_SPI_PRIO339,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x574++0x0 line.byte 0x00 "GICDST0_SPI_PRIO340,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x575++0x0 line.byte 0x00 "GICDST0_SPI_PRIO341,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x576++0x0 line.byte 0x00 "GICDST0_SPI_PRIO342,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x577++0x0 line.byte 0x00 "GICDST0_SPI_PRIO343,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x578++0x0 line.byte 0x00 "GICDST0_SPI_PRIO344,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x579++0x0 line.byte 0x00 "GICDST0_SPI_PRIO345,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x57A++0x0 line.byte 0x00 "GICDST0_SPI_PRIO346,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x57B++0x0 line.byte 0x00 "GICDST0_SPI_PRIO347,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x57C++0x0 line.byte 0x00 "GICDST0_SPI_PRIO348,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x57D++0x0 line.byte 0x00 "GICDST0_SPI_PRIO349,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x57E++0x0 line.byte 0x00 "GICDST0_SPI_PRIO350,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x57F++0x0 line.byte 0x00 "GICDST0_SPI_PRIO351,GICDST0 Shared Peripheral Interrupt Priority Register" bitfld.byte 0x00 0. " VALUE ,Priority" "0,1" group.byte 0x820++0x0 line.byte 0x00 "GICDST0_SPI_TRGT0,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x821++0x0 line.byte 0x00 "GICDST0_SPI_TRGT1,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x822++0x0 line.byte 0x00 "GICDST0_SPI_TRGT2,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x823++0x0 line.byte 0x00 "GICDST0_SPI_TRGT3,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x824++0x0 line.byte 0x00 "GICDST0_SPI_TRGT4,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x825++0x0 line.byte 0x00 "GICDST0_SPI_TRGT5,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x826++0x0 line.byte 0x00 "GICDST0_SPI_TRGT6,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x827++0x0 line.byte 0x00 "GICDST0_SPI_TRGT7,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x828++0x0 line.byte 0x00 "GICDST0_SPI_TRGT8,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x829++0x0 line.byte 0x00 "GICDST0_SPI_TRGT9,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x82A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT10,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x82B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT11,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x82C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT12,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x82D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT13,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x82E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT14,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x82F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT15,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x830++0x0 line.byte 0x00 "GICDST0_SPI_TRGT16,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x831++0x0 line.byte 0x00 "GICDST0_SPI_TRGT17,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x832++0x0 line.byte 0x00 "GICDST0_SPI_TRGT18,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x833++0x0 line.byte 0x00 "GICDST0_SPI_TRGT19,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x834++0x0 line.byte 0x00 "GICDST0_SPI_TRGT20,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x835++0x0 line.byte 0x00 "GICDST0_SPI_TRGT21,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x836++0x0 line.byte 0x00 "GICDST0_SPI_TRGT22,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x837++0x0 line.byte 0x00 "GICDST0_SPI_TRGT23,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x838++0x0 line.byte 0x00 "GICDST0_SPI_TRGT24,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x839++0x0 line.byte 0x00 "GICDST0_SPI_TRGT25,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x83A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT26,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x83B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT27,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x83C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT28,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x83D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT29,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x83E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT30,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x83F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT31,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x840++0x0 line.byte 0x00 "GICDST0_SPI_TRGT32,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x841++0x0 line.byte 0x00 "GICDST0_SPI_TRGT33,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x842++0x0 line.byte 0x00 "GICDST0_SPI_TRGT34,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x843++0x0 line.byte 0x00 "GICDST0_SPI_TRGT35,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x844++0x0 line.byte 0x00 "GICDST0_SPI_TRGT36,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x845++0x0 line.byte 0x00 "GICDST0_SPI_TRGT37,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x846++0x0 line.byte 0x00 "GICDST0_SPI_TRGT38,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x847++0x0 line.byte 0x00 "GICDST0_SPI_TRGT39,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x848++0x0 line.byte 0x00 "GICDST0_SPI_TRGT40,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x849++0x0 line.byte 0x00 "GICDST0_SPI_TRGT41,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x84A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT42,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x84B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT43,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x84C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT44,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x84D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT45,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x84E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT46,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x84F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT47,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x850++0x0 line.byte 0x00 "GICDST0_SPI_TRGT48,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x851++0x0 line.byte 0x00 "GICDST0_SPI_TRGT49,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x852++0x0 line.byte 0x00 "GICDST0_SPI_TRGT50,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x853++0x0 line.byte 0x00 "GICDST0_SPI_TRGT51,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x854++0x0 line.byte 0x00 "GICDST0_SPI_TRGT52,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x855++0x0 line.byte 0x00 "GICDST0_SPI_TRGT53,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x856++0x0 line.byte 0x00 "GICDST0_SPI_TRGT54,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x857++0x0 line.byte 0x00 "GICDST0_SPI_TRGT55,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x858++0x0 line.byte 0x00 "GICDST0_SPI_TRGT56,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x859++0x0 line.byte 0x00 "GICDST0_SPI_TRGT57,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x85A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT58,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x85B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT59,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x85C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT60,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x85D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT61,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x85E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT62,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x85F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT63,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x860++0x0 line.byte 0x00 "GICDST0_SPI_TRGT64,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x861++0x0 line.byte 0x00 "GICDST0_SPI_TRGT65,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x862++0x0 line.byte 0x00 "GICDST0_SPI_TRGT66,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x863++0x0 line.byte 0x00 "GICDST0_SPI_TRGT67,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x864++0x0 line.byte 0x00 "GICDST0_SPI_TRGT68,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x865++0x0 line.byte 0x00 "GICDST0_SPI_TRGT69,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x866++0x0 line.byte 0x00 "GICDST0_SPI_TRGT70,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x867++0x0 line.byte 0x00 "GICDST0_SPI_TRGT71,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x868++0x0 line.byte 0x00 "GICDST0_SPI_TRGT72,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x869++0x0 line.byte 0x00 "GICDST0_SPI_TRGT73,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x86A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT74,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x86B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT75,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x86C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT76,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x86D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT77,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x86E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT78,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x86F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT79,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x870++0x0 line.byte 0x00 "GICDST0_SPI_TRGT80,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x871++0x0 line.byte 0x00 "GICDST0_SPI_TRGT81,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x872++0x0 line.byte 0x00 "GICDST0_SPI_TRGT82,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x873++0x0 line.byte 0x00 "GICDST0_SPI_TRGT83,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x874++0x0 line.byte 0x00 "GICDST0_SPI_TRGT84,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x875++0x0 line.byte 0x00 "GICDST0_SPI_TRGT85,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x876++0x0 line.byte 0x00 "GICDST0_SPI_TRGT86,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x877++0x0 line.byte 0x00 "GICDST0_SPI_TRGT87,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x878++0x0 line.byte 0x00 "GICDST0_SPI_TRGT88,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x879++0x0 line.byte 0x00 "GICDST0_SPI_TRGT89,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x87A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT90,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x87B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT91,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x87C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT92,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x87D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT93,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x87E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT94,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x87F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT95,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x880++0x0 line.byte 0x00 "GICDST0_SPI_TRGT96,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x881++0x0 line.byte 0x00 "GICDST0_SPI_TRGT97,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x882++0x0 line.byte 0x00 "GICDST0_SPI_TRGT98,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x883++0x0 line.byte 0x00 "GICDST0_SPI_TRGT99,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x884++0x0 line.byte 0x00 "GICDST0_SPI_TRGT100,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x885++0x0 line.byte 0x00 "GICDST0_SPI_TRGT101,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x886++0x0 line.byte 0x00 "GICDST0_SPI_TRGT102,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x887++0x0 line.byte 0x00 "GICDST0_SPI_TRGT103,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x888++0x0 line.byte 0x00 "GICDST0_SPI_TRGT104,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x889++0x0 line.byte 0x00 "GICDST0_SPI_TRGT105,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x88A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT106,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x88B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT107,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x88C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT108,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x88D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT109,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x88E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT110,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x88F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT111,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x890++0x0 line.byte 0x00 "GICDST0_SPI_TRGT112,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x891++0x0 line.byte 0x00 "GICDST0_SPI_TRGT113,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x892++0x0 line.byte 0x00 "GICDST0_SPI_TRGT114,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x893++0x0 line.byte 0x00 "GICDST0_SPI_TRGT115,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x894++0x0 line.byte 0x00 "GICDST0_SPI_TRGT116,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x895++0x0 line.byte 0x00 "GICDST0_SPI_TRGT117,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x896++0x0 line.byte 0x00 "GICDST0_SPI_TRGT118,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x897++0x0 line.byte 0x00 "GICDST0_SPI_TRGT119,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x898++0x0 line.byte 0x00 "GICDST0_SPI_TRGT120,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x899++0x0 line.byte 0x00 "GICDST0_SPI_TRGT121,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x89A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT122,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x89B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT123,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x89C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT124,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x89D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT125,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x89E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT126,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x89F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT127,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A0++0x0 line.byte 0x00 "GICDST0_SPI_TRGT128,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A1++0x0 line.byte 0x00 "GICDST0_SPI_TRGT129,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A2++0x0 line.byte 0x00 "GICDST0_SPI_TRGT130,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A3++0x0 line.byte 0x00 "GICDST0_SPI_TRGT131,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A4++0x0 line.byte 0x00 "GICDST0_SPI_TRGT132,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A5++0x0 line.byte 0x00 "GICDST0_SPI_TRGT133,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A6++0x0 line.byte 0x00 "GICDST0_SPI_TRGT134,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A7++0x0 line.byte 0x00 "GICDST0_SPI_TRGT135,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A8++0x0 line.byte 0x00 "GICDST0_SPI_TRGT136,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8A9++0x0 line.byte 0x00 "GICDST0_SPI_TRGT137,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8AA++0x0 line.byte 0x00 "GICDST0_SPI_TRGT138,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8AB++0x0 line.byte 0x00 "GICDST0_SPI_TRGT139,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8AC++0x0 line.byte 0x00 "GICDST0_SPI_TRGT140,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8AD++0x0 line.byte 0x00 "GICDST0_SPI_TRGT141,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8AE++0x0 line.byte 0x00 "GICDST0_SPI_TRGT142,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8AF++0x0 line.byte 0x00 "GICDST0_SPI_TRGT143,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B0++0x0 line.byte 0x00 "GICDST0_SPI_TRGT144,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B1++0x0 line.byte 0x00 "GICDST0_SPI_TRGT145,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B2++0x0 line.byte 0x00 "GICDST0_SPI_TRGT146,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B3++0x0 line.byte 0x00 "GICDST0_SPI_TRGT147,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B4++0x0 line.byte 0x00 "GICDST0_SPI_TRGT148,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B5++0x0 line.byte 0x00 "GICDST0_SPI_TRGT149,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B6++0x0 line.byte 0x00 "GICDST0_SPI_TRGT150,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B7++0x0 line.byte 0x00 "GICDST0_SPI_TRGT151,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B8++0x0 line.byte 0x00 "GICDST0_SPI_TRGT152,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8B9++0x0 line.byte 0x00 "GICDST0_SPI_TRGT153,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8BA++0x0 line.byte 0x00 "GICDST0_SPI_TRGT154,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8BB++0x0 line.byte 0x00 "GICDST0_SPI_TRGT155,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8BC++0x0 line.byte 0x00 "GICDST0_SPI_TRGT156,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8BD++0x0 line.byte 0x00 "GICDST0_SPI_TRGT157,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8BE++0x0 line.byte 0x00 "GICDST0_SPI_TRGT158,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8BF++0x0 line.byte 0x00 "GICDST0_SPI_TRGT159,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C0++0x0 line.byte 0x00 "GICDST0_SPI_TRGT160,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C1++0x0 line.byte 0x00 "GICDST0_SPI_TRGT161,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C2++0x0 line.byte 0x00 "GICDST0_SPI_TRGT162,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C3++0x0 line.byte 0x00 "GICDST0_SPI_TRGT163,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C4++0x0 line.byte 0x00 "GICDST0_SPI_TRGT164,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C5++0x0 line.byte 0x00 "GICDST0_SPI_TRGT165,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C6++0x0 line.byte 0x00 "GICDST0_SPI_TRGT166,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C7++0x0 line.byte 0x00 "GICDST0_SPI_TRGT167,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C8++0x0 line.byte 0x00 "GICDST0_SPI_TRGT168,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8C9++0x0 line.byte 0x00 "GICDST0_SPI_TRGT169,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8CA++0x0 line.byte 0x00 "GICDST0_SPI_TRGT170,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8CB++0x0 line.byte 0x00 "GICDST0_SPI_TRGT171,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8CC++0x0 line.byte 0x00 "GICDST0_SPI_TRGT172,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8CD++0x0 line.byte 0x00 "GICDST0_SPI_TRGT173,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8CE++0x0 line.byte 0x00 "GICDST0_SPI_TRGT174,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8CF++0x0 line.byte 0x00 "GICDST0_SPI_TRGT175,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D0++0x0 line.byte 0x00 "GICDST0_SPI_TRGT176,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D1++0x0 line.byte 0x00 "GICDST0_SPI_TRGT177,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D2++0x0 line.byte 0x00 "GICDST0_SPI_TRGT178,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D3++0x0 line.byte 0x00 "GICDST0_SPI_TRGT179,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D4++0x0 line.byte 0x00 "GICDST0_SPI_TRGT180,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D5++0x0 line.byte 0x00 "GICDST0_SPI_TRGT181,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D6++0x0 line.byte 0x00 "GICDST0_SPI_TRGT182,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D7++0x0 line.byte 0x00 "GICDST0_SPI_TRGT183,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D8++0x0 line.byte 0x00 "GICDST0_SPI_TRGT184,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8D9++0x0 line.byte 0x00 "GICDST0_SPI_TRGT185,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8DA++0x0 line.byte 0x00 "GICDST0_SPI_TRGT186,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8DB++0x0 line.byte 0x00 "GICDST0_SPI_TRGT187,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8DC++0x0 line.byte 0x00 "GICDST0_SPI_TRGT188,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8DD++0x0 line.byte 0x00 "GICDST0_SPI_TRGT189,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8DE++0x0 line.byte 0x00 "GICDST0_SPI_TRGT190,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8DF++0x0 line.byte 0x00 "GICDST0_SPI_TRGT191,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E0++0x0 line.byte 0x00 "GICDST0_SPI_TRGT192,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E1++0x0 line.byte 0x00 "GICDST0_SPI_TRGT193,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E2++0x0 line.byte 0x00 "GICDST0_SPI_TRGT194,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E3++0x0 line.byte 0x00 "GICDST0_SPI_TRGT195,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E4++0x0 line.byte 0x00 "GICDST0_SPI_TRGT196,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E5++0x0 line.byte 0x00 "GICDST0_SPI_TRGT197,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E6++0x0 line.byte 0x00 "GICDST0_SPI_TRGT198,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E7++0x0 line.byte 0x00 "GICDST0_SPI_TRGT199,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E8++0x0 line.byte 0x00 "GICDST0_SPI_TRGT200,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8E9++0x0 line.byte 0x00 "GICDST0_SPI_TRGT201,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8EA++0x0 line.byte 0x00 "GICDST0_SPI_TRGT202,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8EB++0x0 line.byte 0x00 "GICDST0_SPI_TRGT203,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8EC++0x0 line.byte 0x00 "GICDST0_SPI_TRGT204,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8ED++0x0 line.byte 0x00 "GICDST0_SPI_TRGT205,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8EE++0x0 line.byte 0x00 "GICDST0_SPI_TRGT206,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8EF++0x0 line.byte 0x00 "GICDST0_SPI_TRGT207,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F0++0x0 line.byte 0x00 "GICDST0_SPI_TRGT208,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F1++0x0 line.byte 0x00 "GICDST0_SPI_TRGT209,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F2++0x0 line.byte 0x00 "GICDST0_SPI_TRGT210,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F3++0x0 line.byte 0x00 "GICDST0_SPI_TRGT211,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F4++0x0 line.byte 0x00 "GICDST0_SPI_TRGT212,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F5++0x0 line.byte 0x00 "GICDST0_SPI_TRGT213,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F6++0x0 line.byte 0x00 "GICDST0_SPI_TRGT214,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F7++0x0 line.byte 0x00 "GICDST0_SPI_TRGT215,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F8++0x0 line.byte 0x00 "GICDST0_SPI_TRGT216,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8F9++0x0 line.byte 0x00 "GICDST0_SPI_TRGT217,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8FA++0x0 line.byte 0x00 "GICDST0_SPI_TRGT218,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8FB++0x0 line.byte 0x00 "GICDST0_SPI_TRGT219,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8FC++0x0 line.byte 0x00 "GICDST0_SPI_TRGT220,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8FD++0x0 line.byte 0x00 "GICDST0_SPI_TRGT221,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8FE++0x0 line.byte 0x00 "GICDST0_SPI_TRGT222,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x8FF++0x0 line.byte 0x00 "GICDST0_SPI_TRGT223,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x900++0x0 line.byte 0x00 "GICDST0_SPI_TRGT224,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x901++0x0 line.byte 0x00 "GICDST0_SPI_TRGT225,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x902++0x0 line.byte 0x00 "GICDST0_SPI_TRGT226,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x903++0x0 line.byte 0x00 "GICDST0_SPI_TRGT227,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x904++0x0 line.byte 0x00 "GICDST0_SPI_TRGT228,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x905++0x0 line.byte 0x00 "GICDST0_SPI_TRGT229,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x906++0x0 line.byte 0x00 "GICDST0_SPI_TRGT230,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x907++0x0 line.byte 0x00 "GICDST0_SPI_TRGT231,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x908++0x0 line.byte 0x00 "GICDST0_SPI_TRGT232,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x909++0x0 line.byte 0x00 "GICDST0_SPI_TRGT233,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x90A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT234,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x90B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT235,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x90C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT236,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x90D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT237,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x90E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT238,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x90F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT239,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x910++0x0 line.byte 0x00 "GICDST0_SPI_TRGT240,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x911++0x0 line.byte 0x00 "GICDST0_SPI_TRGT241,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x912++0x0 line.byte 0x00 "GICDST0_SPI_TRGT242,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x913++0x0 line.byte 0x00 "GICDST0_SPI_TRGT243,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x914++0x0 line.byte 0x00 "GICDST0_SPI_TRGT244,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x915++0x0 line.byte 0x00 "GICDST0_SPI_TRGT245,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x916++0x0 line.byte 0x00 "GICDST0_SPI_TRGT246,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x917++0x0 line.byte 0x00 "GICDST0_SPI_TRGT247,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x918++0x0 line.byte 0x00 "GICDST0_SPI_TRGT248,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x919++0x0 line.byte 0x00 "GICDST0_SPI_TRGT249,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x91A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT250,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x91B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT251,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x91C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT252,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x91D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT253,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x91E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT254,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x91F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT255,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x920++0x0 line.byte 0x00 "GICDST0_SPI_TRGT256,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x921++0x0 line.byte 0x00 "GICDST0_SPI_TRGT257,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x922++0x0 line.byte 0x00 "GICDST0_SPI_TRGT258,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x923++0x0 line.byte 0x00 "GICDST0_SPI_TRGT259,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x924++0x0 line.byte 0x00 "GICDST0_SPI_TRGT260,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x925++0x0 line.byte 0x00 "GICDST0_SPI_TRGT261,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x926++0x0 line.byte 0x00 "GICDST0_SPI_TRGT262,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x927++0x0 line.byte 0x00 "GICDST0_SPI_TRGT263,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x928++0x0 line.byte 0x00 "GICDST0_SPI_TRGT264,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x929++0x0 line.byte 0x00 "GICDST0_SPI_TRGT265,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x92A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT266,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x92B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT267,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x92C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT268,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x92D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT269,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x92E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT270,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x92F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT271,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x930++0x0 line.byte 0x00 "GICDST0_SPI_TRGT272,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x931++0x0 line.byte 0x00 "GICDST0_SPI_TRGT273,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x932++0x0 line.byte 0x00 "GICDST0_SPI_TRGT274,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x933++0x0 line.byte 0x00 "GICDST0_SPI_TRGT275,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x934++0x0 line.byte 0x00 "GICDST0_SPI_TRGT276,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x935++0x0 line.byte 0x00 "GICDST0_SPI_TRGT277,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x936++0x0 line.byte 0x00 "GICDST0_SPI_TRGT278,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x937++0x0 line.byte 0x00 "GICDST0_SPI_TRGT279,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x938++0x0 line.byte 0x00 "GICDST0_SPI_TRGT280,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x939++0x0 line.byte 0x00 "GICDST0_SPI_TRGT281,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x93A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT282,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x93B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT283,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x93C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT284,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x93D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT285,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x93E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT286,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x93F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT287,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x940++0x0 line.byte 0x00 "GICDST0_SPI_TRGT288,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x941++0x0 line.byte 0x00 "GICDST0_SPI_TRGT289,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x942++0x0 line.byte 0x00 "GICDST0_SPI_TRGT290,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x943++0x0 line.byte 0x00 "GICDST0_SPI_TRGT291,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x944++0x0 line.byte 0x00 "GICDST0_SPI_TRGT292,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x945++0x0 line.byte 0x00 "GICDST0_SPI_TRGT293,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x946++0x0 line.byte 0x00 "GICDST0_SPI_TRGT294,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x947++0x0 line.byte 0x00 "GICDST0_SPI_TRGT295,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x948++0x0 line.byte 0x00 "GICDST0_SPI_TRGT296,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x949++0x0 line.byte 0x00 "GICDST0_SPI_TRGT297,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x94A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT298,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x94B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT299,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x94C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT300,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x94D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT301,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x94E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT302,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x94F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT303,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x950++0x0 line.byte 0x00 "GICDST0_SPI_TRGT304,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x951++0x0 line.byte 0x00 "GICDST0_SPI_TRGT305,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x952++0x0 line.byte 0x00 "GICDST0_SPI_TRGT306,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x953++0x0 line.byte 0x00 "GICDST0_SPI_TRGT307,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x954++0x0 line.byte 0x00 "GICDST0_SPI_TRGT308,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x955++0x0 line.byte 0x00 "GICDST0_SPI_TRGT309,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x956++0x0 line.byte 0x00 "GICDST0_SPI_TRGT310,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x957++0x0 line.byte 0x00 "GICDST0_SPI_TRGT311,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x958++0x0 line.byte 0x00 "GICDST0_SPI_TRGT312,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x959++0x0 line.byte 0x00 "GICDST0_SPI_TRGT313,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x95A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT314,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x95B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT315,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x95C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT316,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x95D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT317,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x95E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT318,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x95F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT319,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x960++0x0 line.byte 0x00 "GICDST0_SPI_TRGT320,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x961++0x0 line.byte 0x00 "GICDST0_SPI_TRGT321,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x962++0x0 line.byte 0x00 "GICDST0_SPI_TRGT322,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x963++0x0 line.byte 0x00 "GICDST0_SPI_TRGT323,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x964++0x0 line.byte 0x00 "GICDST0_SPI_TRGT324,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x965++0x0 line.byte 0x00 "GICDST0_SPI_TRGT325,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x966++0x0 line.byte 0x00 "GICDST0_SPI_TRGT326,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x967++0x0 line.byte 0x00 "GICDST0_SPI_TRGT327,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x968++0x0 line.byte 0x00 "GICDST0_SPI_TRGT328,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x969++0x0 line.byte 0x00 "GICDST0_SPI_TRGT329,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x96A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT330,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x96B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT331,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x96C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT332,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x96D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT333,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x96E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT334,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x96F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT335,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x970++0x0 line.byte 0x00 "GICDST0_SPI_TRGT336,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x971++0x0 line.byte 0x00 "GICDST0_SPI_TRGT337,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x972++0x0 line.byte 0x00 "GICDST0_SPI_TRGT338,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x973++0x0 line.byte 0x00 "GICDST0_SPI_TRGT339,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x974++0x0 line.byte 0x00 "GICDST0_SPI_TRGT340,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x975++0x0 line.byte 0x00 "GICDST0_SPI_TRGT341,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x976++0x0 line.byte 0x00 "GICDST0_SPI_TRGT342,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x977++0x0 line.byte 0x00 "GICDST0_SPI_TRGT343,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x978++0x0 line.byte 0x00 "GICDST0_SPI_TRGT344,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x979++0x0 line.byte 0x00 "GICDST0_SPI_TRGT345,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x97A++0x0 line.byte 0x00 "GICDST0_SPI_TRGT346,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x97B++0x0 line.byte 0x00 "GICDST0_SPI_TRGT347,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x97C++0x0 line.byte 0x00 "GICDST0_SPI_TRGT348,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x97D++0x0 line.byte 0x00 "GICDST0_SPI_TRGT349,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x97E++0x0 line.byte 0x00 "GICDST0_SPI_TRGT350,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.byte 0x97F++0x0 line.byte 0x00 "GICDST0_SPI_TRGT351,GICDST0 Shared Peripheral Interrupt Processor Targets Register" group.long 0xC08++0x3 line.long 0x00 "GICDST0_SPI_CFG0,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC0C++0x3 line.long 0x00 "GICDST0_SPI_CFG1,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC10++0x3 line.long 0x00 "GICDST0_SPI_CFG2,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC14++0x3 line.long 0x00 "GICDST0_SPI_CFG3,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC18++0x3 line.long 0x00 "GICDST0_SPI_CFG4,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC1C++0x3 line.long 0x00 "GICDST0_SPI_CFG5,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC20++0x3 line.long 0x00 "GICDST0_SPI_CFG6,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC24++0x3 line.long 0x00 "GICDST0_SPI_CFG7,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC28++0x3 line.long 0x00 "GICDST0_SPI_CFG8,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC2C++0x3 line.long 0x00 "GICDST0_SPI_CFG9,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC30++0x3 line.long 0x00 "GICDST0_SPI_CFG10,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC34++0x3 line.long 0x00 "GICDST0_SPI_CFG11,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC38++0x3 line.long 0x00 "GICDST0_SPI_CFG12,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC3C++0x3 line.long 0x00 "GICDST0_SPI_CFG13,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC40++0x3 line.long 0x00 "GICDST0_SPI_CFG14,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xC44++0x3 line.long 0x00 "GICDST0_SPI_CFG15,GICDST0 Shared Peripheral Interrupt Configuration Register" group.long 0xD04++0x3 line.long 0x00 "GICDST0_SPI0,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD08++0x3 line.long 0x00 "GICDST0_SPI1,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD0C++0x3 line.long 0x00 "GICDST0_SPI2,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD10++0x3 line.long 0x00 "GICDST0_SPI3,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD14++0x3 line.long 0x00 "GICDST0_SPI4,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD18++0x3 line.long 0x00 "GICDST0_SPI5,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD1C++0x3 line.long 0x00 "GICDST0_SPI6,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD20++0x3 line.long 0x00 "GICDST0_SPI7,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD24++0x3 line.long 0x00 "GICDST0_SPI8,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD28++0x3 line.long 0x00 "GICDST0_SPI9,GICDST0 Shared Peripheral Interrupt Register" group.long 0xD2C++0x3 line.long 0x00 "GICDST0_SPI10,GICDST0 Shared Peripheral Interrupt Register" group.long 0xF00++0x3 line.long 0x00 "GICDST0_SGI_CTL,GICDST0 Software Generated Interrupt Control Register" bitfld.long 0x00 24.--25. " TRGLSTFILT ,Target List Filter" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CPUTRGTLST ,CPU Target list" bitfld.long 0x00 15. " SATT ,Security Value of the SGI" "0,1" newline bitfld.long 0x00 0.--3. " SGIINTID ,The Interrupt ID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "HADC (Housekeeping ADC)" base ad:0x31016000 width 16. group.long 0x0++0x3 line.long 0x00 "HADC0_CTL,HADC0 Control Register" bitfld.long 0x00 13. " ENLS ,Enable Level Shifters" "0,1" bitfld.long 0x00 12. " DOUTOREOCB ,Serial data on DOUT." "0,1" bitfld.long 0x00 8.--11. " FIXEDCNV ,Fixed Conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 7. " CONT ,Continuous Conversion" "0,1" bitfld.long 0x00 3.--6. " FDIV ,Frequency Divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 2. " STARTCNV ,Start conversion." "0,1" newline bitfld.long 0x00 1. " PD ,Power down." "0,1" bitfld.long 0x00 0. " NRST ,Reset." "0,1" group.long 0x4++0x3 line.long 0x00 "HADC0_CHAN_MSK,HADC0 Channel Mask Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Mask for Each Channel" group.long 0x8++0x3 line.long 0x00 "HADC0_IMSK,HADC0 Interrupt Mask Register" bitfld.long 0x00 17. " RDY ,Mask interrupt when ADC ready to convert" "0,1" bitfld.long 0x00 16. " SEQ ,Mask interrupt at end of sequence completion" "0,1" hexmask.long.word 0x00 0.--15. 1. " CHAN ,Channel Mask" group.long 0xC++0x3 line.long 0x00 "HADC0_STAT,HADC0 Status Register" bitfld.long 0x00 20. " TMUHADC_BUSY ,Temperature Conversion Status" "0,1" hexmask.long.word 0x00 4.--19. 1. " INTRW1C ,Conversion Complete Interrupt" bitfld.long 0x00 3. " SEQOVRW1C ,End of Sequence Conversion" "0,1" newline bitfld.long 0x00 2. " RDYW1C ,Ready to Convert" "0,1" bitfld.long 0x00 0. " RDY ,ADC Ready" "0,1" group.long 0x10++0x3 line.long 0x00 "HADC0_DATA00,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x14++0x3 line.long 0x00 "HADC0_DATA01,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x18++0x3 line.long 0x00 "HADC0_DATA02,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x1C++0x3 line.long 0x00 "HADC0_DATA03,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x20++0x3 line.long 0x00 "HADC0_DATA04,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x24++0x3 line.long 0x00 "HADC0_DATA05,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x28++0x3 line.long 0x00 "HADC0_DATA06,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x2C++0x3 line.long 0x00 "HADC0_DATA07,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x30++0x3 line.long 0x00 "HADC0_DATA08,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x34++0x3 line.long 0x00 "HADC0_DATA09,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x38++0x3 line.long 0x00 "HADC0_DATA10,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x3C++0x3 line.long 0x00 "HADC0_DATA11,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x40++0x3 line.long 0x00 "HADC0_DATA12,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x44++0x3 line.long 0x00 "HADC0_DATA13,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x48++0x3 line.long 0x00 "HADC0_DATA14,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" group.long 0x4C++0x3 line.long 0x00 "HADC0_DATA15,HADC0 Channel Data Registers" hexmask.long.word 0x00 0.--11. 1. " VALUE ,Converted Data" tree.end tree "IIR (IIR Accelerator)" tree "IIR0" base ad:0x310C4000 width 19. group.long 0x0++0x3 line.long 0x00 "IIR0_CTL1,IIR0 Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,Pause accelerator" "0,1" bitfld.long 0x00 29. " SSESEL ,Write Back Interrupt Select" "0,1" newline bitfld.long 0x00 28. " L_TWAIT_EN ,Enable TWAIT Feature in Legacy Mode" "0,1" bitfld.long 0x00 27. " L_TIMASK_EN ,Enable Trigger and Interrupt Masking in Legacy Mode" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" newline bitfld.long 0x00 17. " BURSTEN ,Burst Mode Enable" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Boundary Select" "0,1" newline bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" newline bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,IIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "IIR0_DMASTAT,IIR0 DMA Status Register" bitfld.long 0x00 12. " HALT_STAT ,Accelerator HALT status" "0,1" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" newline bitfld.long 0x00 5. " WDONE ,Current Channel Done" "0,1" bitfld.long 0x00 4. " SVDK ,Save Updated Dk State" "0,1" bitfld.long 0x00 3. " WRBK ,Write Back" "0,1" newline bitfld.long 0x00 2. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 1. " CDKLD ,Coefficient and Dk Loading" "0,1" bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "IIR0_MACSTAT,IIR0 MAC Status Register" bitfld.long 0x00 5. " AINV ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI ,Adder Result Infinity" "0,1" bitfld.long 0x00 3. " ARZ ,Adder Result Zero" "0,1" newline bitfld.long 0x00 2. " MINV ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI ,Multiplier Result Infinity" "0,1" bitfld.long 0x00 0. " MRZ ,Multiplier Result Zero" "0,1" group.long 0xC++0x3 line.long 0x00 "IIR0_DBG_CTL,IIR0 IIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release the MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold or Single Step" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "IIR0_DBG_ADDR,IIR0 IIR Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x14++0x3 line.long 0x00 "IIR0_DBG_WRDAT_LO,IIR0 IIR Debug Write Data Low Register" group.long 0x18++0x3 line.long 0x00 "IIR0_DBG_WRDAT_HI,IIR0 IIR Debug Write Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Write Data Highest 8 Bits" group.long 0x1C++0x3 line.long 0x00 "IIR0_DBG_RDDAT_LO,IIR0 IIR Debug Read Data Low Register" group.long 0x20++0x3 line.long 0x00 "IIR0_DBG_RDDAT_HI,IIR0 IIR Debug Read Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Read Data Highest 8 Bits" group.long 0x40++0x3 line.long 0x00 "IIR0_CTL2,IIR0 Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger mask bit" "0,1" bitfld.long 0x00 28. " TWAIT ,Wait for trigger" "0,1" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size Parameter" bitfld.long 0x00 12.--13. " PRIO ,Priority Level" "0,1,2,3" bitfld.long 0x00 0.--5. " BIQUADS ,Number of Biquads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "IIR0_INIDX,IIR0 Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Index" group.long 0x48++0x3 line.long 0x00 "IIR0_INMOD,IIR0 Input Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x4C++0x3 line.long 0x00 "IIR0_INLEN,IIR0 Input Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Input Data Buffer Length" group.long 0x50++0x3 line.long 0x00 "IIR0_INBASE,IIR0 Input Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Base" group.long 0x54++0x3 line.long 0x00 "IIR0_OUTIDX,IIR0 Output Data Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Data Buffer Index" group.long 0x58++0x3 line.long 0x00 "IIR0_OUTMOD,IIR0 IIR Output Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x5C++0x3 line.long 0x00 "IIR0_OUTLEN,IIR0 IIR Output Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Buffer Length" group.long 0x60++0x3 line.long 0x00 "IIR0_OUTBASE,IIR0 Output Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Buffer Base" group.long 0x64++0x3 line.long 0x00 "IIR0_COEFIDX,IIR0 Coefficient Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Coefficient Buffer Index" group.long 0x68++0x3 line.long 0x00 "IIR0_COEFMOD,IIR0 Coefficient Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Modifier" group.long 0x6C++0x3 line.long 0x00 "IIR0_COEFLEN,IIR0 Coefficient Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Length" group.long 0x70++0x3 line.long 0x00 "IIR0_CHNPTR,IIR0 Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,IIR Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "IIR0_SCTL1,IIR0 Software Control Register1" group.long 0x78++0x3 line.long 0x00 "IIR0_SCTL2,IIR0 Software Control Register2" group.long 0x7C++0x3 line.long 0x00 "IIR0_SGCTL,IIR0 Secondary Global Control Register" bitfld.long 0x00 29. " SSESEL ,Select Between Write Back or Save State Completion Interrupt" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode Select" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Format Select" "0,1" newline bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" tree.end tree "IIR1" base ad:0x310C0000 width 19. group.long 0x0++0x3 line.long 0x00 "IIR1_CTL1,IIR1 Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,Pause accelerator" "0,1" bitfld.long 0x00 29. " SSESEL ,Write Back Interrupt Select" "0,1" newline bitfld.long 0x00 28. " L_TWAIT_EN ,Enable TWAIT Feature in Legacy Mode" "0,1" bitfld.long 0x00 27. " L_TIMASK_EN ,Enable Trigger and Interrupt Masking in Legacy Mode" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" newline bitfld.long 0x00 17. " BURSTEN ,Burst Mode Enable" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Boundary Select" "0,1" newline bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" newline bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,IIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "IIR1_DMASTAT,IIR1 DMA Status Register" bitfld.long 0x00 12. " HALT_STAT ,Accelerator HALT status" "0,1" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" newline bitfld.long 0x00 5. " WDONE ,Current Channel Done" "0,1" bitfld.long 0x00 4. " SVDK ,Save Updated Dk State" "0,1" bitfld.long 0x00 3. " WRBK ,Write Back" "0,1" newline bitfld.long 0x00 2. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 1. " CDKLD ,Coefficient and Dk Loading" "0,1" bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "IIR1_MACSTAT,IIR1 MAC Status Register" bitfld.long 0x00 5. " AINV ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI ,Adder Result Infinity" "0,1" bitfld.long 0x00 3. " ARZ ,Adder Result Zero" "0,1" newline bitfld.long 0x00 2. " MINV ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI ,Multiplier Result Infinity" "0,1" bitfld.long 0x00 0. " MRZ ,Multiplier Result Zero" "0,1" group.long 0xC++0x3 line.long 0x00 "IIR1_DBG_CTL,IIR1 IIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release the MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold or Single Step" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "IIR1_DBG_ADDR,IIR1 IIR Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x14++0x3 line.long 0x00 "IIR1_DBG_WRDAT_LO,IIR1 IIR Debug Write Data Low Register" group.long 0x18++0x3 line.long 0x00 "IIR1_DBG_WRDAT_HI,IIR1 IIR Debug Write Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Write Data Highest 8 Bits" group.long 0x1C++0x3 line.long 0x00 "IIR1_DBG_RDDAT_LO,IIR1 IIR Debug Read Data Low Register" group.long 0x20++0x3 line.long 0x00 "IIR1_DBG_RDDAT_HI,IIR1 IIR Debug Read Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Read Data Highest 8 Bits" group.long 0x40++0x3 line.long 0x00 "IIR1_CTL2,IIR1 Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger mask bit" "0,1" bitfld.long 0x00 28. " TWAIT ,Wait for trigger" "0,1" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size Parameter" bitfld.long 0x00 12.--13. " PRIO ,Priority Level" "0,1,2,3" bitfld.long 0x00 0.--5. " BIQUADS ,Number of Biquads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "IIR1_INIDX,IIR1 Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Index" group.long 0x48++0x3 line.long 0x00 "IIR1_INMOD,IIR1 Input Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x4C++0x3 line.long 0x00 "IIR1_INLEN,IIR1 Input Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Input Data Buffer Length" group.long 0x50++0x3 line.long 0x00 "IIR1_INBASE,IIR1 Input Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Base" group.long 0x54++0x3 line.long 0x00 "IIR1_OUTIDX,IIR1 Output Data Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Data Buffer Index" group.long 0x58++0x3 line.long 0x00 "IIR1_OUTMOD,IIR1 IIR Output Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x5C++0x3 line.long 0x00 "IIR1_OUTLEN,IIR1 IIR Output Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Buffer Length" group.long 0x60++0x3 line.long 0x00 "IIR1_OUTBASE,IIR1 Output Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Buffer Base" group.long 0x64++0x3 line.long 0x00 "IIR1_COEFIDX,IIR1 Coefficient Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Coefficient Buffer Index" group.long 0x68++0x3 line.long 0x00 "IIR1_COEFMOD,IIR1 Coefficient Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Modifier" group.long 0x6C++0x3 line.long 0x00 "IIR1_COEFLEN,IIR1 Coefficient Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Length" group.long 0x70++0x3 line.long 0x00 "IIR1_CHNPTR,IIR1 Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,IIR Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "IIR1_SCTL1,IIR1 Software Control Register1" group.long 0x78++0x3 line.long 0x00 "IIR1_SCTL2,IIR1 Software Control Register2" group.long 0x7C++0x3 line.long 0x00 "IIR1_SGCTL,IIR1 Secondary Global Control Register" bitfld.long 0x00 29. " SSESEL ,Select Between Write Back or Save State Completion Interrupt" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode Select" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Format Select" "0,1" newline bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" tree.end tree "IIR2" base ad:0x310C1000 width 19. group.long 0x0++0x3 line.long 0x00 "IIR2_CTL1,IIR2 Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,Pause accelerator" "0,1" bitfld.long 0x00 29. " SSESEL ,Write Back Interrupt Select" "0,1" newline bitfld.long 0x00 28. " L_TWAIT_EN ,Enable TWAIT Feature in Legacy Mode" "0,1" bitfld.long 0x00 27. " L_TIMASK_EN ,Enable Trigger and Interrupt Masking in Legacy Mode" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" newline bitfld.long 0x00 17. " BURSTEN ,Burst Mode Enable" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Boundary Select" "0,1" newline bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" newline bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,IIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "IIR2_DMASTAT,IIR2 DMA Status Register" bitfld.long 0x00 12. " HALT_STAT ,Accelerator HALT status" "0,1" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" newline bitfld.long 0x00 5. " WDONE ,Current Channel Done" "0,1" bitfld.long 0x00 4. " SVDK ,Save Updated Dk State" "0,1" bitfld.long 0x00 3. " WRBK ,Write Back" "0,1" newline bitfld.long 0x00 2. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 1. " CDKLD ,Coefficient and Dk Loading" "0,1" bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "IIR2_MACSTAT,IIR2 MAC Status Register" bitfld.long 0x00 5. " AINV ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI ,Adder Result Infinity" "0,1" bitfld.long 0x00 3. " ARZ ,Adder Result Zero" "0,1" newline bitfld.long 0x00 2. " MINV ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI ,Multiplier Result Infinity" "0,1" bitfld.long 0x00 0. " MRZ ,Multiplier Result Zero" "0,1" group.long 0xC++0x3 line.long 0x00 "IIR2_DBG_CTL,IIR2 IIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release the MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold or Single Step" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "IIR2_DBG_ADDR,IIR2 IIR Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x14++0x3 line.long 0x00 "IIR2_DBG_WRDAT_LO,IIR2 IIR Debug Write Data Low Register" group.long 0x18++0x3 line.long 0x00 "IIR2_DBG_WRDAT_HI,IIR2 IIR Debug Write Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Write Data Highest 8 Bits" group.long 0x1C++0x3 line.long 0x00 "IIR2_DBG_RDDAT_LO,IIR2 IIR Debug Read Data Low Register" group.long 0x20++0x3 line.long 0x00 "IIR2_DBG_RDDAT_HI,IIR2 IIR Debug Read Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Read Data Highest 8 Bits" group.long 0x40++0x3 line.long 0x00 "IIR2_CTL2,IIR2 Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger mask bit" "0,1" bitfld.long 0x00 28. " TWAIT ,Wait for trigger" "0,1" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size Parameter" bitfld.long 0x00 12.--13. " PRIO ,Priority Level" "0,1,2,3" bitfld.long 0x00 0.--5. " BIQUADS ,Number of Biquads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "IIR2_INIDX,IIR2 Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Index" group.long 0x48++0x3 line.long 0x00 "IIR2_INMOD,IIR2 Input Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x4C++0x3 line.long 0x00 "IIR2_INLEN,IIR2 Input Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Input Data Buffer Length" group.long 0x50++0x3 line.long 0x00 "IIR2_INBASE,IIR2 Input Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Base" group.long 0x54++0x3 line.long 0x00 "IIR2_OUTIDX,IIR2 Output Data Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Data Buffer Index" group.long 0x58++0x3 line.long 0x00 "IIR2_OUTMOD,IIR2 IIR Output Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x5C++0x3 line.long 0x00 "IIR2_OUTLEN,IIR2 IIR Output Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Buffer Length" group.long 0x60++0x3 line.long 0x00 "IIR2_OUTBASE,IIR2 Output Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Buffer Base" group.long 0x64++0x3 line.long 0x00 "IIR2_COEFIDX,IIR2 Coefficient Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Coefficient Buffer Index" group.long 0x68++0x3 line.long 0x00 "IIR2_COEFMOD,IIR2 Coefficient Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Modifier" group.long 0x6C++0x3 line.long 0x00 "IIR2_COEFLEN,IIR2 Coefficient Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Length" group.long 0x70++0x3 line.long 0x00 "IIR2_CHNPTR,IIR2 Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,IIR Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "IIR2_SCTL1,IIR2 Software Control Register1" group.long 0x78++0x3 line.long 0x00 "IIR2_SCTL2,IIR2 Software Control Register2" group.long 0x7C++0x3 line.long 0x00 "IIR2_SGCTL,IIR2 Secondary Global Control Register" bitfld.long 0x00 29. " SSESEL ,Select Between Write Back or Save State Completion Interrupt" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode Select" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Format Select" "0,1" newline bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" tree.end tree "IIR3" base ad:0x310C2000 width 19. group.long 0x0++0x3 line.long 0x00 "IIR3_CTL1,IIR3 Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,Pause accelerator" "0,1" bitfld.long 0x00 29. " SSESEL ,Write Back Interrupt Select" "0,1" newline bitfld.long 0x00 28. " L_TWAIT_EN ,Enable TWAIT Feature in Legacy Mode" "0,1" bitfld.long 0x00 27. " L_TIMASK_EN ,Enable Trigger and Interrupt Masking in Legacy Mode" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" newline bitfld.long 0x00 17. " BURSTEN ,Burst Mode Enable" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Boundary Select" "0,1" newline bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" newline bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,IIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "IIR3_DMASTAT,IIR3 DMA Status Register" bitfld.long 0x00 12. " HALT_STAT ,Accelerator HALT status" "0,1" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" newline bitfld.long 0x00 5. " WDONE ,Current Channel Done" "0,1" bitfld.long 0x00 4. " SVDK ,Save Updated Dk State" "0,1" bitfld.long 0x00 3. " WRBK ,Write Back" "0,1" newline bitfld.long 0x00 2. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 1. " CDKLD ,Coefficient and Dk Loading" "0,1" bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "IIR3_MACSTAT,IIR3 MAC Status Register" bitfld.long 0x00 5. " AINV ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI ,Adder Result Infinity" "0,1" bitfld.long 0x00 3. " ARZ ,Adder Result Zero" "0,1" newline bitfld.long 0x00 2. " MINV ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI ,Multiplier Result Infinity" "0,1" bitfld.long 0x00 0. " MRZ ,Multiplier Result Zero" "0,1" group.long 0xC++0x3 line.long 0x00 "IIR3_DBG_CTL,IIR3 IIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release the MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold or Single Step" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "IIR3_DBG_ADDR,IIR3 IIR Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x14++0x3 line.long 0x00 "IIR3_DBG_WRDAT_LO,IIR3 IIR Debug Write Data Low Register" group.long 0x18++0x3 line.long 0x00 "IIR3_DBG_WRDAT_HI,IIR3 IIR Debug Write Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Write Data Highest 8 Bits" group.long 0x1C++0x3 line.long 0x00 "IIR3_DBG_RDDAT_LO,IIR3 IIR Debug Read Data Low Register" group.long 0x20++0x3 line.long 0x00 "IIR3_DBG_RDDAT_HI,IIR3 IIR Debug Read Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Read Data Highest 8 Bits" group.long 0x40++0x3 line.long 0x00 "IIR3_CTL2,IIR3 Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger mask bit" "0,1" bitfld.long 0x00 28. " TWAIT ,Wait for trigger" "0,1" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size Parameter" bitfld.long 0x00 12.--13. " PRIO ,Priority Level" "0,1,2,3" bitfld.long 0x00 0.--5. " BIQUADS ,Number of Biquads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "IIR3_INIDX,IIR3 Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Index" group.long 0x48++0x3 line.long 0x00 "IIR3_INMOD,IIR3 Input Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x4C++0x3 line.long 0x00 "IIR3_INLEN,IIR3 Input Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Input Data Buffer Length" group.long 0x50++0x3 line.long 0x00 "IIR3_INBASE,IIR3 Input Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Base" group.long 0x54++0x3 line.long 0x00 "IIR3_OUTIDX,IIR3 Output Data Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Data Buffer Index" group.long 0x58++0x3 line.long 0x00 "IIR3_OUTMOD,IIR3 IIR Output Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x5C++0x3 line.long 0x00 "IIR3_OUTLEN,IIR3 IIR Output Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Buffer Length" group.long 0x60++0x3 line.long 0x00 "IIR3_OUTBASE,IIR3 Output Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Buffer Base" group.long 0x64++0x3 line.long 0x00 "IIR3_COEFIDX,IIR3 Coefficient Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Coefficient Buffer Index" group.long 0x68++0x3 line.long 0x00 "IIR3_COEFMOD,IIR3 Coefficient Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Modifier" group.long 0x6C++0x3 line.long 0x00 "IIR3_COEFLEN,IIR3 Coefficient Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Length" group.long 0x70++0x3 line.long 0x00 "IIR3_CHNPTR,IIR3 Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,IIR Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "IIR3_SCTL1,IIR3 Software Control Register1" group.long 0x78++0x3 line.long 0x00 "IIR3_SCTL2,IIR3 Software Control Register2" group.long 0x7C++0x3 line.long 0x00 "IIR3_SGCTL,IIR3 Secondary Global Control Register" bitfld.long 0x00 29. " SSESEL ,Select Between Write Back or Save State Completion Interrupt" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode Select" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Format Select" "0,1" newline bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" tree.end tree "IIR4" base ad:0x310BE000 width 19. group.long 0x0++0x3 line.long 0x00 "IIR4_CTL1,IIR4 Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,Pause accelerator" "0,1" bitfld.long 0x00 29. " SSESEL ,Write Back Interrupt Select" "0,1" newline bitfld.long 0x00 28. " L_TWAIT_EN ,Enable TWAIT Feature in Legacy Mode" "0,1" bitfld.long 0x00 27. " L_TIMASK_EN ,Enable Trigger and Interrupt Masking in Legacy Mode" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" newline bitfld.long 0x00 17. " BURSTEN ,Burst Mode Enable" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Boundary Select" "0,1" newline bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" newline bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,IIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "IIR4_DMASTAT,IIR4 DMA Status Register" bitfld.long 0x00 12. " HALT_STAT ,Accelerator HALT status" "0,1" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" newline bitfld.long 0x00 5. " WDONE ,Current Channel Done" "0,1" bitfld.long 0x00 4. " SVDK ,Save Updated Dk State" "0,1" bitfld.long 0x00 3. " WRBK ,Write Back" "0,1" newline bitfld.long 0x00 2. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 1. " CDKLD ,Coefficient and Dk Loading" "0,1" bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "IIR4_MACSTAT,IIR4 MAC Status Register" bitfld.long 0x00 5. " AINV ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI ,Adder Result Infinity" "0,1" bitfld.long 0x00 3. " ARZ ,Adder Result Zero" "0,1" newline bitfld.long 0x00 2. " MINV ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI ,Multiplier Result Infinity" "0,1" bitfld.long 0x00 0. " MRZ ,Multiplier Result Zero" "0,1" group.long 0xC++0x3 line.long 0x00 "IIR4_DBG_CTL,IIR4 IIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release the MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold or Single Step" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "IIR4_DBG_ADDR,IIR4 IIR Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x14++0x3 line.long 0x00 "IIR4_DBG_WRDAT_LO,IIR4 IIR Debug Write Data Low Register" group.long 0x18++0x3 line.long 0x00 "IIR4_DBG_WRDAT_HI,IIR4 IIR Debug Write Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Write Data Highest 8 Bits" group.long 0x1C++0x3 line.long 0x00 "IIR4_DBG_RDDAT_LO,IIR4 IIR Debug Read Data Low Register" group.long 0x20++0x3 line.long 0x00 "IIR4_DBG_RDDAT_HI,IIR4 IIR Debug Read Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Read Data Highest 8 Bits" group.long 0x40++0x3 line.long 0x00 "IIR4_CTL2,IIR4 Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger mask bit" "0,1" bitfld.long 0x00 28. " TWAIT ,Wait for trigger" "0,1" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size Parameter" bitfld.long 0x00 12.--13. " PRIO ,Priority Level" "0,1,2,3" bitfld.long 0x00 0.--5. " BIQUADS ,Number of Biquads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "IIR4_INIDX,IIR4 Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Index" group.long 0x48++0x3 line.long 0x00 "IIR4_INMOD,IIR4 Input Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x4C++0x3 line.long 0x00 "IIR4_INLEN,IIR4 Input Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Input Data Buffer Length" group.long 0x50++0x3 line.long 0x00 "IIR4_INBASE,IIR4 Input Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Base" group.long 0x54++0x3 line.long 0x00 "IIR4_OUTIDX,IIR4 Output Data Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Data Buffer Index" group.long 0x58++0x3 line.long 0x00 "IIR4_OUTMOD,IIR4 IIR Output Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x5C++0x3 line.long 0x00 "IIR4_OUTLEN,IIR4 IIR Output Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Buffer Length" group.long 0x60++0x3 line.long 0x00 "IIR4_OUTBASE,IIR4 Output Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Buffer Base" group.long 0x64++0x3 line.long 0x00 "IIR4_COEFIDX,IIR4 Coefficient Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Coefficient Buffer Index" group.long 0x68++0x3 line.long 0x00 "IIR4_COEFMOD,IIR4 Coefficient Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Modifier" group.long 0x6C++0x3 line.long 0x00 "IIR4_COEFLEN,IIR4 Coefficient Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Length" group.long 0x70++0x3 line.long 0x00 "IIR4_CHNPTR,IIR4 Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,IIR Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "IIR4_SCTL1,IIR4 Software Control Register1" group.long 0x78++0x3 line.long 0x00 "IIR4_SCTL2,IIR4 Software Control Register2" group.long 0x7C++0x3 line.long 0x00 "IIR4_SGCTL,IIR4 Secondary Global Control Register" bitfld.long 0x00 29. " SSESEL ,Select Between Write Back or Save State Completion Interrupt" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode Select" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Format Select" "0,1" newline bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" tree.end tree "IIR5" base ad:0x310BA000 width 19. group.long 0x0++0x3 line.long 0x00 "IIR5_CTL1,IIR5 Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,Pause accelerator" "0,1" bitfld.long 0x00 29. " SSESEL ,Write Back Interrupt Select" "0,1" newline bitfld.long 0x00 28. " L_TWAIT_EN ,Enable TWAIT Feature in Legacy Mode" "0,1" bitfld.long 0x00 27. " L_TIMASK_EN ,Enable Trigger and Interrupt Masking in Legacy Mode" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" newline bitfld.long 0x00 17. " BURSTEN ,Burst Mode Enable" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Boundary Select" "0,1" newline bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" newline bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,IIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "IIR5_DMASTAT,IIR5 DMA Status Register" bitfld.long 0x00 12. " HALT_STAT ,Accelerator HALT status" "0,1" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" newline bitfld.long 0x00 5. " WDONE ,Current Channel Done" "0,1" bitfld.long 0x00 4. " SVDK ,Save Updated Dk State" "0,1" bitfld.long 0x00 3. " WRBK ,Write Back" "0,1" newline bitfld.long 0x00 2. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 1. " CDKLD ,Coefficient and Dk Loading" "0,1" bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "IIR5_MACSTAT,IIR5 MAC Status Register" bitfld.long 0x00 5. " AINV ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI ,Adder Result Infinity" "0,1" bitfld.long 0x00 3. " ARZ ,Adder Result Zero" "0,1" newline bitfld.long 0x00 2. " MINV ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI ,Multiplier Result Infinity" "0,1" bitfld.long 0x00 0. " MRZ ,Multiplier Result Zero" "0,1" group.long 0xC++0x3 line.long 0x00 "IIR5_DBG_CTL,IIR5 IIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release the MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold or Single Step" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "IIR5_DBG_ADDR,IIR5 IIR Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x14++0x3 line.long 0x00 "IIR5_DBG_WRDAT_LO,IIR5 IIR Debug Write Data Low Register" group.long 0x18++0x3 line.long 0x00 "IIR5_DBG_WRDAT_HI,IIR5 IIR Debug Write Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Write Data Highest 8 Bits" group.long 0x1C++0x3 line.long 0x00 "IIR5_DBG_RDDAT_LO,IIR5 IIR Debug Read Data Low Register" group.long 0x20++0x3 line.long 0x00 "IIR5_DBG_RDDAT_HI,IIR5 IIR Debug Read Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Read Data Highest 8 Bits" group.long 0x40++0x3 line.long 0x00 "IIR5_CTL2,IIR5 Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger mask bit" "0,1" bitfld.long 0x00 28. " TWAIT ,Wait for trigger" "0,1" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size Parameter" bitfld.long 0x00 12.--13. " PRIO ,Priority Level" "0,1,2,3" bitfld.long 0x00 0.--5. " BIQUADS ,Number of Biquads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "IIR5_INIDX,IIR5 Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Index" group.long 0x48++0x3 line.long 0x00 "IIR5_INMOD,IIR5 Input Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x4C++0x3 line.long 0x00 "IIR5_INLEN,IIR5 Input Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Input Data Buffer Length" group.long 0x50++0x3 line.long 0x00 "IIR5_INBASE,IIR5 Input Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Base" group.long 0x54++0x3 line.long 0x00 "IIR5_OUTIDX,IIR5 Output Data Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Data Buffer Index" group.long 0x58++0x3 line.long 0x00 "IIR5_OUTMOD,IIR5 IIR Output Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x5C++0x3 line.long 0x00 "IIR5_OUTLEN,IIR5 IIR Output Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Buffer Length" group.long 0x60++0x3 line.long 0x00 "IIR5_OUTBASE,IIR5 Output Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Buffer Base" group.long 0x64++0x3 line.long 0x00 "IIR5_COEFIDX,IIR5 Coefficient Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Coefficient Buffer Index" group.long 0x68++0x3 line.long 0x00 "IIR5_COEFMOD,IIR5 Coefficient Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Modifier" group.long 0x6C++0x3 line.long 0x00 "IIR5_COEFLEN,IIR5 Coefficient Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Length" group.long 0x70++0x3 line.long 0x00 "IIR5_CHNPTR,IIR5 Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,IIR Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "IIR5_SCTL1,IIR5 Software Control Register1" group.long 0x78++0x3 line.long 0x00 "IIR5_SCTL2,IIR5 Software Control Register2" group.long 0x7C++0x3 line.long 0x00 "IIR5_SGCTL,IIR5 Secondary Global Control Register" bitfld.long 0x00 29. " SSESEL ,Select Between Write Back or Save State Completion Interrupt" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode Select" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Format Select" "0,1" newline bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" tree.end tree "IIR6" base ad:0x310BB000 width 19. group.long 0x0++0x3 line.long 0x00 "IIR6_CTL1,IIR6 Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,Pause accelerator" "0,1" bitfld.long 0x00 29. " SSESEL ,Write Back Interrupt Select" "0,1" newline bitfld.long 0x00 28. " L_TWAIT_EN ,Enable TWAIT Feature in Legacy Mode" "0,1" bitfld.long 0x00 27. " L_TIMASK_EN ,Enable Trigger and Interrupt Masking in Legacy Mode" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" newline bitfld.long 0x00 17. " BURSTEN ,Burst Mode Enable" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Boundary Select" "0,1" newline bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" newline bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,IIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "IIR6_DMASTAT,IIR6 DMA Status Register" bitfld.long 0x00 12. " HALT_STAT ,Accelerator HALT status" "0,1" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" newline bitfld.long 0x00 5. " WDONE ,Current Channel Done" "0,1" bitfld.long 0x00 4. " SVDK ,Save Updated Dk State" "0,1" bitfld.long 0x00 3. " WRBK ,Write Back" "0,1" newline bitfld.long 0x00 2. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 1. " CDKLD ,Coefficient and Dk Loading" "0,1" bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "IIR6_MACSTAT,IIR6 MAC Status Register" bitfld.long 0x00 5. " AINV ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI ,Adder Result Infinity" "0,1" bitfld.long 0x00 3. " ARZ ,Adder Result Zero" "0,1" newline bitfld.long 0x00 2. " MINV ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI ,Multiplier Result Infinity" "0,1" bitfld.long 0x00 0. " MRZ ,Multiplier Result Zero" "0,1" group.long 0xC++0x3 line.long 0x00 "IIR6_DBG_CTL,IIR6 IIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release the MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold or Single Step" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "IIR6_DBG_ADDR,IIR6 IIR Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x14++0x3 line.long 0x00 "IIR6_DBG_WRDAT_LO,IIR6 IIR Debug Write Data Low Register" group.long 0x18++0x3 line.long 0x00 "IIR6_DBG_WRDAT_HI,IIR6 IIR Debug Write Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Write Data Highest 8 Bits" group.long 0x1C++0x3 line.long 0x00 "IIR6_DBG_RDDAT_LO,IIR6 IIR Debug Read Data Low Register" group.long 0x20++0x3 line.long 0x00 "IIR6_DBG_RDDAT_HI,IIR6 IIR Debug Read Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Read Data Highest 8 Bits" group.long 0x40++0x3 line.long 0x00 "IIR6_CTL2,IIR6 Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger mask bit" "0,1" bitfld.long 0x00 28. " TWAIT ,Wait for trigger" "0,1" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size Parameter" bitfld.long 0x00 12.--13. " PRIO ,Priority Level" "0,1,2,3" bitfld.long 0x00 0.--5. " BIQUADS ,Number of Biquads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "IIR6_INIDX,IIR6 Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Index" group.long 0x48++0x3 line.long 0x00 "IIR6_INMOD,IIR6 Input Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x4C++0x3 line.long 0x00 "IIR6_INLEN,IIR6 Input Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Input Data Buffer Length" group.long 0x50++0x3 line.long 0x00 "IIR6_INBASE,IIR6 Input Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Base" group.long 0x54++0x3 line.long 0x00 "IIR6_OUTIDX,IIR6 Output Data Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Data Buffer Index" group.long 0x58++0x3 line.long 0x00 "IIR6_OUTMOD,IIR6 IIR Output Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x5C++0x3 line.long 0x00 "IIR6_OUTLEN,IIR6 IIR Output Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Buffer Length" group.long 0x60++0x3 line.long 0x00 "IIR6_OUTBASE,IIR6 Output Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Buffer Base" group.long 0x64++0x3 line.long 0x00 "IIR6_COEFIDX,IIR6 Coefficient Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Coefficient Buffer Index" group.long 0x68++0x3 line.long 0x00 "IIR6_COEFMOD,IIR6 Coefficient Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Modifier" group.long 0x6C++0x3 line.long 0x00 "IIR6_COEFLEN,IIR6 Coefficient Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Length" group.long 0x70++0x3 line.long 0x00 "IIR6_CHNPTR,IIR6 Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,IIR Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "IIR6_SCTL1,IIR6 Software Control Register1" group.long 0x78++0x3 line.long 0x00 "IIR6_SCTL2,IIR6 Software Control Register2" group.long 0x7C++0x3 line.long 0x00 "IIR6_SGCTL,IIR6 Secondary Global Control Register" bitfld.long 0x00 29. " SSESEL ,Select Between Write Back or Save State Completion Interrupt" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode Select" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Format Select" "0,1" newline bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" tree.end tree "IIR7" base ad:0x310BC000 width 19. group.long 0x0++0x3 line.long 0x00 "IIR7_CTL1,IIR7 Global Control Register" bitfld.long 0x00 31. " ACM ,Auto Configuration Mode" "0,1" bitfld.long 0x00 30. " HALT ,Pause accelerator" "0,1" bitfld.long 0x00 29. " SSESEL ,Write Back Interrupt Select" "0,1" newline bitfld.long 0x00 28. " L_TWAIT_EN ,Enable TWAIT Feature in Legacy Mode" "0,1" bitfld.long 0x00 27. " L_TIMASK_EN ,Enable Trigger and Interrupt Masking in Legacy Mode" "0,1" bitfld.long 0x00 26. " SMQ_LIUPS_EN ,Legacy I/P and O/P Index Update Scheme in SMART_Q Mode" "0,1" newline bitfld.long 0x00 17. " BURSTEN ,Burst Mode Enable" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Boundary Select" "0,1" newline bitfld.long 0x00 11. " CCINTR ,Channel Complete Interrupt" "0,1" bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" bitfld.long 0x00 9. " CAI ,Channel Auto Iterate" "0,1" newline bitfld.long 0x00 8. " DMAEN ,DMA Enable" "0,1" bitfld.long 0x00 1.--5. " CH ,Number of Channels" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,IIR Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "IIR7_DMASTAT,IIR7 DMA Status Register" bitfld.long 0x00 12. " HALT_STAT ,Accelerator HALT status" "0,1" bitfld.long 0x00 7.--11. " CURCHNL ,Current Channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " ACDONE ,All Channels Done" "0,1" newline bitfld.long 0x00 5. " WDONE ,Current Channel Done" "0,1" bitfld.long 0x00 4. " SVDK ,Save Updated Dk State" "0,1" bitfld.long 0x00 3. " WRBK ,Write Back" "0,1" newline bitfld.long 0x00 2. " PPGS ,MAC Processing in Progress" "0,1" bitfld.long 0x00 1. " CDKLD ,Coefficient and Dk Loading" "0,1" bitfld.long 0x00 0. " CPLD ,Chain Pointer Loading Status" "0,1" group.long 0x8++0x3 line.long 0x00 "IIR7_MACSTAT,IIR7 MAC Status Register" bitfld.long 0x00 5. " AINV ,Addition Invalid" "0,1" bitfld.long 0x00 4. " ARI ,Adder Result Infinity" "0,1" bitfld.long 0x00 3. " ARZ ,Adder Result Zero" "0,1" newline bitfld.long 0x00 2. " MINV ,Multiply Invalid" "0,1" bitfld.long 0x00 1. " MRI ,Multiplier Result Infinity" "0,1" bitfld.long 0x00 0. " MRZ ,Multiplier Result Zero" "0,1" group.long 0xC++0x3 line.long 0x00 "IIR7_DBG_CTL,IIR7 IIR Debug Control Register" bitfld.long 0x00 5. " ADRINC ,Address Auto Increment" "0,1" bitfld.long 0x00 4. " MEM ,Local Memory Access" "0,1" bitfld.long 0x00 2. " RUN ,Release the MAC" "0,1" newline bitfld.long 0x00 1. " HLD ,Hold or Single Step" "0,1" bitfld.long 0x00 0. " EN ,Debug Mode Enable" "0,1" group.long 0x10++0x3 line.long 0x00 "IIR7_DBG_ADDR,IIR7 IIR Debug Address Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Debug Address, Coefficient Memory Select" group.long 0x14++0x3 line.long 0x00 "IIR7_DBG_WRDAT_LO,IIR7 IIR Debug Write Data Low Register" group.long 0x18++0x3 line.long 0x00 "IIR7_DBG_WRDAT_HI,IIR7 IIR Debug Write Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Write Data Highest 8 Bits" group.long 0x1C++0x3 line.long 0x00 "IIR7_DBG_RDDAT_LO,IIR7 IIR Debug Read Data Low Register" group.long 0x20++0x3 line.long 0x00 "IIR7_DBG_RDDAT_HI,IIR7 IIR Debug Read Data High Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Debug Read Data Highest 8 Bits" group.long 0x40++0x3 line.long 0x00 "IIR7_CTL2,IIR7 Channel Control Register" bitfld.long 0x00 31. " TMASK ,Trigger mask bit" "0,1" bitfld.long 0x00 28. " TWAIT ,Wait for trigger" "0,1" bitfld.long 0x00 24. " IMASK ,Interrupt Mask" "0,1" newline hexmask.long.word 0x00 14.--23. 1. " WINDOW ,Window Size Parameter" bitfld.long 0x00 12.--13. " PRIO ,Priority Level" "0,1,2,3" bitfld.long 0x00 0.--5. " BIQUADS ,Number of Biquads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x44++0x3 line.long 0x00 "IIR7_INIDX,IIR7 Input Data Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Index" group.long 0x48++0x3 line.long 0x00 "IIR7_INMOD,IIR7 Input Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x4C++0x3 line.long 0x00 "IIR7_INLEN,IIR7 Input Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Input Data Buffer Length" group.long 0x50++0x3 line.long 0x00 "IIR7_INBASE,IIR7 Input Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Input Data Buffer Base" group.long 0x54++0x3 line.long 0x00 "IIR7_OUTIDX,IIR7 Output Data Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Data Buffer Index" group.long 0x58++0x3 line.long 0x00 "IIR7_OUTMOD,IIR7 IIR Output Data Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Input Data Buffer Index Modifier" group.long 0x5C++0x3 line.long 0x00 "IIR7_OUTLEN,IIR7 IIR Output Data Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Output Data Buffer Length" group.long 0x60++0x3 line.long 0x00 "IIR7_OUTBASE,IIR7 Output Buffer Base Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Output Buffer Base" group.long 0x64++0x3 line.long 0x00 "IIR7_COEFIDX,IIR7 Coefficient Buffer Index Register" hexmask.long 0x00 0.--29. 1. " VALUE ,Coefficient Buffer Index" group.long 0x68++0x3 line.long 0x00 "IIR7_COEFMOD,IIR7 Coefficient Index Modifier Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Modifier" group.long 0x6C++0x3 line.long 0x00 "IIR7_COEFLEN,IIR7 Coefficient Buffer Length Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Coefficient Length" group.long 0x70++0x3 line.long 0x00 "IIR7_CHNPTR,IIR7 Chain Pointer Register" hexmask.long 0x00 0.--29. 1. " VALUE ,IIR Chain Pointer Address" group.long 0x74++0x3 line.long 0x00 "IIR7_SCTL1,IIR7 Software Control Register1" group.long 0x78++0x3 line.long 0x00 "IIR7_SCTL2,IIR7 Software Control Register2" group.long 0x7C++0x3 line.long 0x00 "IIR7_SGCTL,IIR7 Secondary Global Control Register" bitfld.long 0x00 29. " SSESEL ,Select Between Write Back or Save State Completion Interrupt" "0,1" bitfld.long 0x00 14. " RND ,Rounding Mode Select" "0,1" bitfld.long 0x00 12. " FORTYBIT ,40-Bit Floating-Point Format Select" "0,1" newline bitfld.long 0x00 10. " SS ,Save Biquad State" "0,1" tree.end tree.end tree "L2CTL0" base ad:0x31080000 width 17. group.long 0x0++0x3 line.long 0x00 "L2CTL0_CTL,L2CTL0 Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 28. " DISURP ,Disable Urgent Request Priority" "0,1" bitfld.long 0x00 8. " BK8EDIS ,Bank 8 (ROM) ECC Disable" "0,1" newline bitfld.long 0x00 7. " BK7EDIS ,Bank 7 ECC Disable" "0,1" bitfld.long 0x00 6. " BK6EDIS ,Bank 6 ECC Disable" "0,1" bitfld.long 0x00 5. " BK5EDIS ,Bank 5 ECC Disable" "0,1" newline bitfld.long 0x00 4. " BK4EDIS ,Bank 4 ECC Disable" "0,1" bitfld.long 0x00 3. " BK3EDIS ,Bank 3 ECC Disable" "0,1" bitfld.long 0x00 2. " BK2EDIS ,Bank 2 ECC Disable" "0,1" newline bitfld.long 0x00 1. " BK1EDIS ,Bank 1 ECC Disable" "0,1" bitfld.long 0x00 0. " BK0EDIS ,Bank 0 ECC Disable" "0,1" group.long 0x10++0x3 line.long 0x00 "L2CTL0_STAT,L2CTL0 Status Register" bitfld.long 0x00 16. " ECCERR8 ,ECC Error Bank 8 (ROM)" "0,1" bitfld.long 0x00 15. " ECCERR7 ,ECC Error Bank 7" "0,1" bitfld.long 0x00 14. " ECCERR6 ,ECC Error Bank 6" "0,1" newline bitfld.long 0x00 13. " ECCERR5 ,ECC Error Bank 5" "0,1" bitfld.long 0x00 12. " ECCERR4 ,ECC Error Bank 4" "0,1" bitfld.long 0x00 11. " ECCERR3 ,ECC Error Bank 3" "0,1" newline bitfld.long 0x00 10. " ECCERR2 ,ECC Error Bank 2" "0,1" bitfld.long 0x00 9. " ECCERR1 ,ECC Error Bank 1" "0,1" bitfld.long 0x00 8. " ECCERR0 ,ECC Error Bank 0" "0,1" newline bitfld.long 0x00 5. " INITDN ,Initialization Status" "0,1" bitfld.long 0x00 4. " SCRBDN ,Scrub Status" "0,1" bitfld.long 0x00 1. " ERR1 ,Error Port 1" "0,1" newline bitfld.long 0x00 0. " ERR0 ,Error Port 0" "0,1" group.long 0x14++0x3 line.long 0x00 "L2CTL0_RPCR0,L2CTL0 Read Priority Count Register" hexmask.long.byte 0x00 24.--31. 1. " RPC3 ,Read Priority Count 3" hexmask.long.byte 0x00 16.--23. 1. " RPC2 ,Read Priority Count 2" hexmask.long.byte 0x00 8.--15. 1. " RPC1 ,Read Priority Count 1" newline hexmask.long.byte 0x00 0.--7. 1. " RPC0 ,Read Priority Count 0" group.long 0x18++0x3 line.long 0x00 "L2CTL0_WPCR0,L2CTL0 Write Priority Count Register" hexmask.long.byte 0x00 24.--31. 1. " WPC3 ,Write Priority Count 3" hexmask.long.byte 0x00 16.--23. 1. " WPC2 ,Write Priority Count 2" hexmask.long.byte 0x00 8.--15. 1. " WPC1 ,Write Priority Count 1" newline hexmask.long.byte 0x00 0.--7. 1. " WPC0 ,Write Priority Count 0" group.long 0x24++0x3 line.long 0x00 "L2CTL0_INIT,L2CTL0 Initialization Register" bitfld.long 0x00 7. " BK7 ,Initialize Bank 7" "0,1" bitfld.long 0x00 6. " BK6 ,Initialize Bank 6" "0,1" bitfld.long 0x00 5. " BK5 ,Initialize Bank 5" "0,1" newline bitfld.long 0x00 4. " BK4 ,Initialize Bank 4" "0,1" bitfld.long 0x00 3. " BK3 ,Initialize Bank 3" "0,1" bitfld.long 0x00 2. " BK2 ,Initialize Bank 2" "0,1" newline bitfld.long 0x00 1. " BK1 ,Initialize Bank 1" "0,1" bitfld.long 0x00 0. " BK0 ,Initialize Bank 0" "0,1" group.long 0x38++0x3 line.long 0x00 "L2CTL0_ISTAT,L2CTL0 Initialization Status Register" bitfld.long 0x00 7. " BK7 ,Bank 7 Initialization Status" "0,1" bitfld.long 0x00 6. " BK6 ,Bank 6 Initialization Status" "0,1" bitfld.long 0x00 5. " BK5 ,Bank 5 Initialization Status" "0,1" newline bitfld.long 0x00 4. " BK4 ,Bank 4 Initialization Status" "0,1" bitfld.long 0x00 3. " BK3 ,Bank 3 Initialization Status" "0,1" bitfld.long 0x00 2. " BK2 ,Bank 2 Initialization Status" "0,1" newline bitfld.long 0x00 1. " BK1 ,Bank 1 Initialization Status" "0,1" bitfld.long 0x00 0. " BK0 ,Bank 0 Initialization Status" "0,1" group.long 0x3C++0x3 line.long 0x00 "L2CTL0_PCTL,L2CTL0 Power Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 23. " BK7SD ,Bank 7 Shut Down Enable" "0,1" bitfld.long 0x00 22. " BK6SD ,Bank 6 Shut Down Enable" "0,1" newline bitfld.long 0x00 21. " BK5SD ,Bank 5 Shut Down Enable" "0,1" bitfld.long 0x00 20. " BK4SD ,Bank 4 Shut Down Enable" "0,1" bitfld.long 0x00 19. " BK3SD ,Bank 3 Shut Down Enable" "0,1" newline bitfld.long 0x00 18. " BK2SD ,Bank 2 Shut Down Enable" "0,1" bitfld.long 0x00 17. " BK1SD ,Bank 1 Shut Down Enable" "0,1" bitfld.long 0x00 16. " BK0SD ,Bank 0 Shut Down Enable" "0,1" newline bitfld.long 0x00 7. " BK7DS ,Bank 7 Deep Sleep Enable" "0,1" bitfld.long 0x00 6. " BK6DS ,Bank 6 Deep Sleep Enable" "0,1" bitfld.long 0x00 5. " BK5DS ,Bank 5 Deep Sleep Enable" "0,1" newline bitfld.long 0x00 4. " BK4DS ,Bank 4 Deep Sleep Enable" "0,1" bitfld.long 0x00 3. " BK3DS ,Bank 3 Deep Sleep Enable" "0,1" bitfld.long 0x00 2. " BK2DS ,Bank 2 Deep Sleep Enable" "0,1" newline bitfld.long 0x00 1. " BK1DS ,Bank 1 Deep Sleep Enable" "0,1" bitfld.long 0x00 0. " BK0DS ,Bank 0 Deep Sleep Enable" "0,1" group.long 0x40++0x3 line.long 0x00 "L2CTL0_ERRADDR0,L2CTL0 ECC Error Address 0 Register" group.long 0x44++0x3 line.long 0x00 "L2CTL0_ERRADDR1,L2CTL0 ECC Error Address 1 Register" group.long 0x48++0x3 line.long 0x00 "L2CTL0_ERRADDR2,L2CTL0 ECC Error Address 2 Register" group.long 0x4C++0x3 line.long 0x00 "L2CTL0_ERRADDR3,L2CTL0 ECC Error Address 3 Register" group.long 0x50++0x3 line.long 0x00 "L2CTL0_ERRADDR4,L2CTL0 ECC Error Address 4 Register" group.long 0x54++0x3 line.long 0x00 "L2CTL0_ERRADDR5,L2CTL0 ECC Error Address 5 Register" group.long 0x58++0x3 line.long 0x00 "L2CTL0_ERRADDR6,L2CTL0 ECC Error Address 6 Register" group.long 0x5C++0x3 line.long 0x00 "L2CTL0_ERRADDR7,L2CTL0 ECC Error Address 7 Register" group.long 0x60++0x3 line.long 0x00 "L2CTL0_ERRADDR8,L2CTL0 ECC Error Address 8 Register" group.long 0x80++0x3 line.long 0x00 "L2CTL0_ET0,L2CTL0 Error Type 0 Register" hexmask.long.word 0x00 8.--20. 1. " ID ,Error ID" bitfld.long 0x00 4. " RDWR ,Read/Write Error" "0,1" bitfld.long 0x00 3. " ECCERR ,ECC Error" "0,1" newline bitfld.long 0x00 2. " ACCERR ,Access Error" "0,1" bitfld.long 0x00 0. " ROMERR ,ROM Error" "0,1" group.long 0x84++0x3 line.long 0x00 "L2CTL0_EADDR0,L2CTL0 Error Type 0 Address Register" group.long 0x88++0x3 line.long 0x00 "L2CTL0_ET1,L2CTL0 Error Type 1 Register" hexmask.long.word 0x00 8.--20. 1. " ID ,Error ID" bitfld.long 0x00 4. " RDWR ,Read/Write Error" "0,1" bitfld.long 0x00 3. " ECCERR ,ECC Error" "0,1" newline bitfld.long 0x00 2. " ACCERR ,Access Error" "0,1" bitfld.long 0x00 0. " ROMERR ,ROM Error" "0,1" group.long 0x8C++0x3 line.long 0x00 "L2CTL0_EADDR1,L2CTL0 Error Type 1 Address Register" group.long 0xEC++0x3 line.long 0x00 "L2CTL0_SCTL,L2CTL0 Scrub Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 30. " SEN ,Scrub Enable" "0,1" hexmask.long.word 0x00 0.--15. 1. " SRT ,Scrub Rate" group.long 0xF0++0x3 line.long 0x00 "L2CTL0_SADR,L2CTL0 Scrub Start Address Register" group.long 0xF4++0x3 line.long 0x00 "L2CTL0_SCNT,L2CTL0 Scrub Count Register" hexmask.long.tbyte 0x00 0.--17. 1. " VALUE ,Scrub Count" group.long 0xFC++0x3 line.long 0x00 "L2CTL0_REVID,L2CTL0 Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Revision ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x3 line.long 0x00 "L2CTL0_STAT_1,L2CTL0 L2 Port Error Status Register" bitfld.long 0x00 4. " ERR4 ,Error Port4" "0,1" bitfld.long 0x00 3. " ERR3 ,Error Port3" "0,1" bitfld.long 0x00 2. " ERR2 ,Error Port2" "0,1" group.long 0x104++0x3 line.long 0x00 "L2CTL0_ET2,L2CTL0 Error Type 2 Register" hexmask.long.word 0x00 8.--20. 1. " ID ,Error ID" bitfld.long 0x00 4. " RDWR ,Read/Write Error" "0,1" bitfld.long 0x00 3. " ECCERR ,ECC Error" "0,1" newline bitfld.long 0x00 2. " ACCERR ,Access Error" "0,1" bitfld.long 0x00 0. " ROMERR ,ROM Error" "0,1" group.long 0x108++0x3 line.long 0x00 "L2CTL0_EADDR2,L2CTL0 Error Type 2 Address Register" group.long 0x10C++0x3 line.long 0x00 "L2CTL0_ET3,L2CTL0 Error Type 3 Register" hexmask.long.word 0x00 8.--20. 1. " ID ,Error ID" bitfld.long 0x00 4. " RDWR ,Read/Write Error" "0,1" bitfld.long 0x00 3. " ECCERR ,ECC Error" "0,1" newline bitfld.long 0x00 2. " ACCERR ,Access Error" "0,1" bitfld.long 0x00 0. " ROMERR ,ROM Error" "0,1" group.long 0x110++0x3 line.long 0x00 "L2CTL0_EADDR3,L2CTL0 Error Type 3 Address Register" group.long 0x114++0x3 line.long 0x00 "L2CTL0_ET4,L2CTL0 Error Type 4 Register" hexmask.long.word 0x00 8.--20. 1. " ID ,Error ID" bitfld.long 0x00 4. " RDWR ,Read/Write Error" "0,1" bitfld.long 0x00 3. " ECCERR ,ECC Error" "0,1" newline bitfld.long 0x00 2. " ACCERR ,Access Error" "0,1" bitfld.long 0x00 0. " ROMERR ,ROM Error" "0,1" group.long 0x118++0x3 line.long 0x00 "L2CTL0_EADDR4,L2CTL0 Error Type 4 Address Register" group.long 0x130++0x3 line.long 0x00 "L2CTL0_RPCR1,L2CTL0 Read Priority Count Register" hexmask.long.byte 0x00 0.--7. 1. " RPC4 ,Read Priority Count 4" group.long 0x134++0x3 line.long 0x00 "L2CTL0_WPCR1,L2CTL0 Write Priority Count Register" hexmask.long.byte 0x00 0.--7. 1. " WPC4 ,Write Priority Count 4" tree.end tree "LP (Link Port)" tree "LP0" base ad:0x30FFE000 width 16. group.long 0x0++0x3 line.long 0x00 "LP0_CTL,LP0 Control Register" bitfld.long 0x00 12.--14. " MODE ,Select Mode of operation" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " ROVFMSK ,Receive FIFO Overflow Interrupt Mask" "0,1" bitfld.long 0x00 9. " RRQMSK ,Receive Request Interrupt Mask" "0,1" newline bitfld.long 0x00 8. " TRQMSK ,Transmit Request Interrupt Mask" "0,1" bitfld.long 0x00 3. " TRAN ,Transfer Direction" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "LP0_STAT,LP0 Status Register" bitfld.long 0x00 8. " LPBS ,Bus Status" "0,1" bitfld.long 0x00 7. " LPACK ,Buffer Pack Status" "0,1" bitfld.long 0x00 4.--6. " FFST ,FIFO Status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. " ROVF ,Receive FIFO Overflow Interrupt" "0,1" bitfld.long 0x00 1. " LRRQ ,Receive Request" "0,1" bitfld.long 0x00 0. " LTRQ ,Transmit Request" "0,1" group.long 0x8++0x3 line.long 0x00 "LP0_DIV,LP0 Clock Divider Value Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Divisor Value" group.long 0x10++0x3 line.long 0x00 "LP0_TX,LP0 Transmit Buffer Register" group.long 0x14++0x3 line.long 0x00 "LP0_RX,LP0 Receive Buffer Register" group.long 0x18++0x3 line.long 0x00 "LP0_TXIN_SHDW,LP0 Shadow Input Transmit Buffer Register" group.long 0x1C++0x3 line.long 0x00 "LP0_TXOUT_SHDW,LP0 Shadow Output Transmit Buffer Register" tree.end tree "LP1" base ad:0x30FFE100 width 16. group.long 0x0++0x3 line.long 0x00 "LP1_CTL,LP1 Control Register" bitfld.long 0x00 12.--14. " MODE ,Select Mode of operation" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " ROVFMSK ,Receive FIFO Overflow Interrupt Mask" "0,1" bitfld.long 0x00 9. " RRQMSK ,Receive Request Interrupt Mask" "0,1" newline bitfld.long 0x00 8. " TRQMSK ,Transmit Request Interrupt Mask" "0,1" bitfld.long 0x00 3. " TRAN ,Transfer Direction" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "LP1_STAT,LP1 Status Register" bitfld.long 0x00 8. " LPBS ,Bus Status" "0,1" bitfld.long 0x00 7. " LPACK ,Buffer Pack Status" "0,1" bitfld.long 0x00 4.--6. " FFST ,FIFO Status" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. " ROVF ,Receive FIFO Overflow Interrupt" "0,1" bitfld.long 0x00 1. " LRRQ ,Receive Request" "0,1" bitfld.long 0x00 0. " LTRQ ,Transmit Request" "0,1" group.long 0x8++0x3 line.long 0x00 "LP1_DIV,LP1 Clock Divider Value Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Divisor Value" group.long 0x10++0x3 line.long 0x00 "LP1_TX,LP1 Transmit Buffer Register" group.long 0x14++0x3 line.long 0x00 "LP1_RX,LP1 Receive Buffer Register" group.long 0x18++0x3 line.long 0x00 "LP1_TXIN_SHDW,LP1 Shadow Input Transmit Buffer Register" group.long 0x1C++0x3 line.long 0x00 "LP1_TXOUT_SHDW,LP1 Shadow Output Transmit Buffer Register" tree.end tree.end tree "MEPU (Memory Error Protection Unit)" tree "MEC0" base ad:0x310A2000 width 20. group.long 0x0++0x3 line.long 0x00 "MEC0_PEIRQ_GCTL0,MEC0 Parity Error Interrupt Request Global Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Global Control Register Lock bit" "0,1" bitfld.long 0x00 0.--3. " VALUE ,Parity Error Global Control bit. '1' indicates enable and '0' indicates disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "MEC0_PEIRQ_GSTAT0,MEC0 Parity Error Interrupt Request Global Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Global Control Register Lock Write Error" "0,1" bitfld.long 0x00 0.--3. " VALUE ,Parity Error Global Status bit. '1' indicates assertion of interrupt/trigger and '0' indicates no interrupt/trigger." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x3 line.long 0x00 "MEC0_PERR_CTL0,MEC0 Parity Error Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Control Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Control bit. 1 indicates enable and 0 indicates disable" group.long 0x44++0x3 line.long 0x00 "MEC0_PERR_CTL1,MEC0 Parity Error Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Control Register Lock bit" "0,1" hexmask.long.word 0x00 0.--15. 1. " VALUE1 ,Parity Error Control bit. 1 indicates enable and 0 indicates disable" group.long 0x80++0x3 line.long 0x00 "MEC0_PERR_STAT0,MEC0 Parity Error Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Control or Interrupt Mask Register Lock Write Error" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." group.long 0x84++0x3 line.long 0x00 "MEC0_PERR_STAT1,MEC0 Parity Error Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Control or Interrupt Mask Register Lock Write Error" "0,1" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Parity Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." group.long 0xC0++0x3 line.long 0x00 "MEC0_PERR_IMASK0,MEC0 Parity Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,Core Memory Error Interrupt Mask Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates interrupt unmasked." group.long 0xC4++0x3 line.long 0x00 "MEC0_PERR_IMASK1,MEC0 Parity Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,Parity Error Interrupt Mask Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates interrupt unmasked." group.long 0x100++0x3 line.long 0x00 "MEC0_EEIRQ_GCTL0,MEC0 ECC Error Interrupt Request Global Control Register" bitfld.long 0x00 31. " LOCK ,ECC Error Global Control Register Lock bit" "0,1" bitfld.long 0x00 0. " VALUE ,ECC Error Global Control bit. '1' indicates enable and '0' indicates disable." "0,1" group.long 0x110++0x3 line.long 0x00 "MEC0_EEIRQ_GSTAT0,MEC0 ECC Error Interrupt Request Global Status Register" bitfld.long 0x00 31. " LWERR ,ECC Error Global Control Register Lock Write Error" "0,1" bitfld.long 0x00 0. " VALUE ,ECC Error Global Status bit. '1' indicates assertion of interrupt/trigger and '0' indicates no interrupt/trigger." "0,1" group.long 0x140++0x3 line.long 0x00 "MEC0_ECCERR_CTL0,MEC0 ECC Error Control Register" bitfld.long 0x00 31. " LOCK ,ECC Error Control Register Lock bit" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Control bit. '1' indicates enable and '0' indicates disable." "0,1,2,3,4,5,6,7" group.long 0x180++0x3 line.long 0x00 "MEC0_ECCERR_STAT0,MEC0 ECC Error Status Register" bitfld.long 0x00 31. " LWERR ,ECC Error Control or Interrupt Mask Register Lock Write Error" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." "0,1,2,3,4,5,6,7" group.long 0x1C0++0x3 line.long 0x00 "MEC0_ECCERR_IMASK0,MEC0 ECC Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,ECC Error Interrupt Mask Register Lock bit" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates unmasked" "0,1,2,3,4,5,6,7" group.long 0xF00++0x3 line.long 0x00 "MEC0_CLR,MEC0 Clear Register" bitfld.long 0x00 0. " CLRSTAT ,Clear Status bit. Write of '1' to this bit clears all status registers of MEC" "0,1" group.long 0xFD0++0x3 line.long 0x00 "MEC0_PID4,MEC0 Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,Number of 4k blocks. Size of component 4k chunks minus 1 (i.e. 0=4k)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " JEP106CC ,JEDEC JEP106 continuation code (number of leading 0x7Fs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFD4++0x3 line.long 0x00 "MEC0_PID5,MEC0 Peripheral ID5 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFD8++0x3 line.long 0x00 "MEC0_PID6,MEC0 Peripheral ID6 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFDC++0x3 line.long 0x00 "MEC0_PID7,MEC0 Peripheral ID7 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFE0++0x3 line.long 0x00 "MEC0_PID0,MEC0 Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PARTNUM ,Part Number for component identification" group.long 0xFE4++0x3 line.long 0x00 "MEC0_PID1,MEC0 Peripheral ID1 Register" bitfld.long 0x00 4.--7. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PARTNUM ,Part Number for component identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE8++0x3 line.long 0x00 "MEC0_PID2,MEC0 Peripheral ID2 Register" bitfld.long 0x00 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " JEDECASGN ,A JEDEC Assigned Value is Used. Indicates that a JEDEC assigned value is used." "0,1" bitfld.long 0x00 0.--2. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7" group.long 0xFEC++0x3 line.long 0x00 "MEC0_PID3,MEC0 Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CUSTMOD ,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF0++0x3 line.long 0x00 "MEC0_CID0,MEC0 Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" group.long 0xFF4++0x3 line.long 0x00 "MEC0_CID1,MEC0 Component ID1 Register" bitfld.long 0x00 4.--7. " COMPCLASS ,Component Class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF8++0x3 line.long 0x00 "MEC0_CID2,MEC0 Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" group.long 0xFFC++0x3 line.long 0x00 "MEC0_CID3,MEC0 Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" tree.end tree "MEC1" base ad:0x310A3000 width 20. group.long 0x0++0x3 line.long 0x00 "MEC1_PEIRQ_GCTL0,MEC1 Parity Error Interrupt Request Global Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Global Control Register Lock bit" "0,1" bitfld.long 0x00 0.--3. " VALUE ,Parity Error Global Control bit. '1' indicates enable and '0' indicates disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "MEC1_PEIRQ_GSTAT0,MEC1 Parity Error Interrupt Request Global Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Global Control Register Lock Write Error" "0,1" bitfld.long 0x00 0.--3. " VALUE ,Parity Error Global Status bit. '1' indicates assertion of interrupt/trigger and '0' indicates no interrupt/trigger." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x3 line.long 0x00 "MEC1_PERR_CTL0,MEC1 Parity Error Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Control Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Control bit. 1 indicates enable and 0 indicates disable" group.long 0x44++0x3 line.long 0x00 "MEC1_PERR_CTL1,MEC1 Parity Error Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Control Register Lock bit" "0,1" hexmask.long.word 0x00 0.--15. 1. " VALUE1 ,Parity Error Control bit. 1 indicates enable and 0 indicates disable" group.long 0x80++0x3 line.long 0x00 "MEC1_PERR_STAT0,MEC1 Parity Error Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Control or Interrupt Mask Register Lock Write Error" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." group.long 0x84++0x3 line.long 0x00 "MEC1_PERR_STAT1,MEC1 Parity Error Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Control or Interrupt Mask Register Lock Write Error" "0,1" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Parity Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." group.long 0xC0++0x3 line.long 0x00 "MEC1_PERR_IMASK0,MEC1 Parity Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,Core Memory Error Interrupt Mask Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates interrupt unmasked." group.long 0xC4++0x3 line.long 0x00 "MEC1_PERR_IMASK1,MEC1 Parity Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,Parity Error Interrupt Mask Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates interrupt unmasked." group.long 0x100++0x3 line.long 0x00 "MEC1_EEIRQ_GCTL0,MEC1 ECC Error Interrupt Request Global Control Register" bitfld.long 0x00 31. " LOCK ,ECC Error Global Control Register Lock bit" "0,1" bitfld.long 0x00 0. " VALUE ,ECC Error Global Control bit. '1' indicates enable and '0' indicates disable." "0,1" group.long 0x110++0x3 line.long 0x00 "MEC1_EEIRQ_GSTAT0,MEC1 ECC Error Interrupt Request Global Status Register" bitfld.long 0x00 31. " LWERR ,ECC Error Global Control Register Lock Write Error" "0,1" bitfld.long 0x00 0. " VALUE ,ECC Error Global Status bit. '1' indicates assertion of interrupt/trigger and '0' indicates no interrupt/trigger." "0,1" group.long 0x140++0x3 line.long 0x00 "MEC1_ECCERR_CTL0,MEC1 ECC Error Control Register" bitfld.long 0x00 31. " LOCK ,ECC Error Control Register Lock bit" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Control bit. '1' indicates enable and '0' indicates disable." "0,1,2,3,4,5,6,7" group.long 0x180++0x3 line.long 0x00 "MEC1_ECCERR_STAT0,MEC1 ECC Error Status Register" bitfld.long 0x00 31. " LWERR ,ECC Error Control or Interrupt Mask Register Lock Write Error" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." "0,1,2,3,4,5,6,7" group.long 0x1C0++0x3 line.long 0x00 "MEC1_ECCERR_IMASK0,MEC1 ECC Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,ECC Error Interrupt Mask Register Lock bit" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates unmasked" "0,1,2,3,4,5,6,7" group.long 0xF00++0x3 line.long 0x00 "MEC1_CLR,MEC1 Clear Register" bitfld.long 0x00 0. " CLRSTAT ,Clear Status bit. Write of '1' to this bit clears all status registers of MEC" "0,1" group.long 0xFD0++0x3 line.long 0x00 "MEC1_PID4,MEC1 Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,Number of 4k blocks. Size of component 4k chunks minus 1 (i.e. 0=4k)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " JEP106CC ,JEDEC JEP106 continuation code (number of leading 0x7Fs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFD4++0x3 line.long 0x00 "MEC1_PID5,MEC1 Peripheral ID5 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFD8++0x3 line.long 0x00 "MEC1_PID6,MEC1 Peripheral ID6 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFDC++0x3 line.long 0x00 "MEC1_PID7,MEC1 Peripheral ID7 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFE0++0x3 line.long 0x00 "MEC1_PID0,MEC1 Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PARTNUM ,Part Number for component identification" group.long 0xFE4++0x3 line.long 0x00 "MEC1_PID1,MEC1 Peripheral ID1 Register" bitfld.long 0x00 4.--7. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PARTNUM ,Part Number for component identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE8++0x3 line.long 0x00 "MEC1_PID2,MEC1 Peripheral ID2 Register" bitfld.long 0x00 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " JEDECASGN ,A JEDEC Assigned Value is Used. Indicates that a JEDEC assigned value is used." "0,1" bitfld.long 0x00 0.--2. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7" group.long 0xFEC++0x3 line.long 0x00 "MEC1_PID3,MEC1 Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CUSTMOD ,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF0++0x3 line.long 0x00 "MEC1_CID0,MEC1 Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" group.long 0xFF4++0x3 line.long 0x00 "MEC1_CID1,MEC1 Component ID1 Register" bitfld.long 0x00 4.--7. " COMPCLASS ,Component Class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF8++0x3 line.long 0x00 "MEC1_CID2,MEC1 Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" group.long 0xFFC++0x3 line.long 0x00 "MEC1_CID3,MEC1 Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" tree.end tree "MEC2" base ad:0x310A4000 width 20. group.long 0x0++0x3 line.long 0x00 "MEC2_PEIRQ_GCTL0,MEC2 Parity Error Interrupt Request Global Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Global Control Register Lock bit" "0,1" bitfld.long 0x00 0.--3. " VALUE ,Parity Error Global Control bit. '1' indicates enable and '0' indicates disable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x3 line.long 0x00 "MEC2_PEIRQ_GSTAT0,MEC2 Parity Error Interrupt Request Global Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Global Control Register Lock Write Error" "0,1" bitfld.long 0x00 0.--3. " VALUE ,Parity Error Global Status bit. '1' indicates assertion of interrupt/trigger and '0' indicates no interrupt/trigger." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40++0x3 line.long 0x00 "MEC2_PERR_CTL0,MEC2 Parity Error Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Control Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Control bit. 1 indicates enable and 0 indicates disable" group.long 0x44++0x3 line.long 0x00 "MEC2_PERR_CTL1,MEC2 Parity Error Control Register" bitfld.long 0x00 31. " LOCK ,Parity Error Control Register Lock bit" "0,1" hexmask.long.word 0x00 0.--15. 1. " VALUE1 ,Parity Error Control bit. 1 indicates enable and 0 indicates disable" group.long 0x80++0x3 line.long 0x00 "MEC2_PERR_STAT0,MEC2 Parity Error Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Control or Interrupt Mask Register Lock Write Error" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." group.long 0x84++0x3 line.long 0x00 "MEC2_PERR_STAT1,MEC2 Parity Error Status Register" bitfld.long 0x00 31. " LWERR ,Parity Error Control or Interrupt Mask Register Lock Write Error" "0,1" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Parity Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." group.long 0xC0++0x3 line.long 0x00 "MEC2_PERR_IMASK0,MEC2 Parity Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,Core Memory Error Interrupt Mask Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates interrupt unmasked." group.long 0xC4++0x3 line.long 0x00 "MEC2_PERR_IMASK1,MEC2 Parity Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,Parity Error Interrupt Mask Register Lock bit" "0,1" hexmask.long 0x00 0.--30. 1. " VALUE ,Parity Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates interrupt unmasked." group.long 0x100++0x3 line.long 0x00 "MEC2_EEIRQ_GCTL0,MEC2 ECC Error Interrupt Request Global Control Register" bitfld.long 0x00 31. " LOCK ,ECC Error Global Control Register Lock bit" "0,1" bitfld.long 0x00 0. " VALUE ,ECC Error Global Control bit. '1' indicates enable and '0' indicates disable." "0,1" group.long 0x110++0x3 line.long 0x00 "MEC2_EEIRQ_GSTAT0,MEC2 ECC Error Interrupt Request Global Status Register" bitfld.long 0x00 31. " LWERR ,ECC Error Global Control Register Lock Write Error" "0,1" bitfld.long 0x00 0. " VALUE ,ECC Error Global Status bit. '1' indicates assertion of interrupt/trigger and '0' indicates no interrupt/trigger." "0,1" group.long 0x140++0x3 line.long 0x00 "MEC2_ECCERR_CTL0,MEC2 ECC Error Control Register" bitfld.long 0x00 31. " LOCK ,ECC Error Control Register Lock bit" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Control bit. '1' indicates enable and '0' indicates disable." "0,1,2,3,4,5,6,7" group.long 0x180++0x3 line.long 0x00 "MEC2_ECCERR_STAT0,MEC2 ECC Error Status Register" bitfld.long 0x00 31. " LWERR ,ECC Error Control or Interrupt Mask Register Lock Write Error" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Status bit. '1' indicates error and '0' indicates no error. Sticky bit, write '1' to clear." "0,1,2,3,4,5,6,7" group.long 0x1C0++0x3 line.long 0x00 "MEC2_ECCERR_IMASK0,MEC2 ECC Error Interrupt Mask Register" bitfld.long 0x00 31. " LOCK ,ECC Error Interrupt Mask Register Lock bit" "0,1" bitfld.long 0x00 0.--2. " VALUE ,ECC Error Interrupt Mask bit. '1' indicates interrupt masked and '0' indicates unmasked" "0,1,2,3,4,5,6,7" group.long 0xF00++0x3 line.long 0x00 "MEC2_CLR,MEC2 Clear Register" bitfld.long 0x00 0. " CLRSTAT ,Clear Status bit. Write of '1' to this bit clears all status registers of MEC" "0,1" group.long 0xFD0++0x3 line.long 0x00 "MEC2_PID4,MEC2 Peripheral ID4 Register" bitfld.long 0x00 4.--7. " SIZE ,Number of 4k blocks. Size of component 4k chunks minus 1 (i.e. 0=4k)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " JEP106CC ,JEDEC JEP106 continuation code (number of leading 0x7Fs)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFD4++0x3 line.long 0x00 "MEC2_PID5,MEC2 Peripheral ID5 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFD8++0x3 line.long 0x00 "MEC2_PID6,MEC2 Peripheral ID6 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFDC++0x3 line.long 0x00 "MEC2_PID7,MEC2 Peripheral ID7 Register" hexmask.long.byte 0x00 0.--7. 1. " FUTUREUSE ,For future use" group.long 0xFE0++0x3 line.long 0x00 "MEC2_PID0,MEC2 Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PARTNUM ,Part Number for component identification" group.long 0xFE4++0x3 line.long 0x00 "MEC2_PID1,MEC2 Peripheral ID1 Register" bitfld.long 0x00 4.--7. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PARTNUM ,Part Number for component identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFE8++0x3 line.long 0x00 "MEC2_PID2,MEC2 Peripheral ID2 Register" bitfld.long 0x00 4.--7. " REV ,Peripheral Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " JEDECASGN ,A JEDEC Assigned Value is Used. Indicates that a JEDEC assigned value is used." "0,1" bitfld.long 0x00 0.--2. " JEP106IC ,JEDEC JEP106 identity (Manufacturer ID) code" "0,1,2,3,4,5,6,7" group.long 0xFEC++0x3 line.long 0x00 "MEC2_PID3,MEC2 Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVAND ,Metal fix revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CUSTMOD ,Customer Modified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF0++0x3 line.long 0x00 "MEC2_CID0,MEC2 Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" group.long 0xFF4++0x3 line.long 0x00 "MEC2_CID1,MEC2 Component ID1 Register" bitfld.long 0x00 4.--7. " COMPCLASS ,Component Class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF8++0x3 line.long 0x00 "MEC2_CID2,MEC2 Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" group.long 0xFFC++0x3 line.long 0x00 "MEC2_CID3,MEC2 Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Component ID Preamble. Identifies this as a Component ID Register" tree.end tree.end tree "MISCREG" base ad:0x310A9000 width 30. group.long 0x0++0x3 line.long 0x00 "MISCREG_SH0_PFB_RANGE_SELECT,MISCREG Prefetch Range Selection Register" hexmask.long.word 0x00 16.--31. 1. " IPORT_RANGE_SELECT ,IPORT Prefetch Range Select" hexmask.long.word 0x00 0.--15. 1. " DPORT_RANGE_SELECT ,DPORT Prefetch Range Select" group.long 0x10++0x3 line.long 0x00 "MISCREG_CAN_SYSCTL,MISCREG $rname" bitfld.long 0x00 6. " CAN1_IPG_DEBUG ,Debug mode request to can_node_1 ; 1: set can1_ipg_debug , 0: clear can1_ipg_debug" "0,1" bitfld.long 0x00 5. " CAN1_IPG_STOP ,Stop mode request to can_node_1 ; 1: set can1_ipg_stop , 0: clear can1_ipg_stop" "0,1" bitfld.long 0x00 4. " CAN1_IPG_DOZE ,Doze mode request to can_node_1 ; 1: set can1_ipg_doze , 0: clear can1_ipg_doze" "0,1" newline bitfld.long 0x00 3. " CAN0_IPG_SRST ,Soft reset to can_node_0 ; 1: set can0_ipg_soft_reset , 0: clear can0_ipg_soft_reset" "0,1" bitfld.long 0x00 2. " CAN0_IPG_DEBUG ,Debug mode request to can_node_0 ; 1: set can0_ipg_debug , 0: clear can0_ipg_debug" "0,1" bitfld.long 0x00 1. " CAN0_IPG_STOP ,Stop mode request to can_node_0 ; 1: set can0_ipg_stop , 0: clear can0_ipg_stop" "0,1" newline bitfld.long 0x00 0. " CAN0_IPG_DOZE ,Doze mode request to can_node_0 ; 1: set can0_ipg_doze , 0: clear can0_ipg_doze" "0,1" group.long 0x14++0x3 line.long 0x00 "MISCREG_SHARC_BRIDGE_REMAP,MISCREG $rname" bitfld.long 0x00 17. " SH1_DRT_INTR_EN ,SPORT Direct Interrupt Enable for SH1, Reset value 1'b0, Should not be set if IIR1 of the SH1 is in use" "0,1" bitfld.long 0x00 16. " SH0_DRT_INTR_EN ,SPORT Direct Interrupt Enable for SH0, Reset value 1'b0, Should not be set if IIR1 of the SH0 is in use" "0,1" group.long 0x1C++0x3 line.long 0x00 "MISCREG_PFB_L2CC_EXCL_CTL,MISCREG $rname" bitfld.long 0x00 2. " SH1_L2CC_EN ,1'b1 - DPORT Access within the range defined by Range Registers, reaches L2CC ; 1'b0 - All DPORT Access reaches actual destination" "0,1" bitfld.long 0x00 1. " SH0_L2CC_EN ,1'b1 - DPORT Access within the range defined by Range Registers, reaches L2CC ; 1'b0 - All DPORT Access reaches actual destination" "0,1" bitfld.long 0x00 0. " L2CC_EN_OVW ,1'b0 - exclusive control between PFB and L2CC when using sharc range registers; 1'b1 - shared control between PFB and L2CC when using sharc range registers" "0,1" group.long 0x44++0x3 line.long 0x00 "MISCREG_SH1_PFB_RANGE_SELECT,MISCREG Prefetch Range Selection Register" hexmask.long.word 0x00 16.--31. 1. " SH1_IPORT_RANGE_SELECT ,SH1 IPORT Prefetch Range Select" hexmask.long.word 0x00 0.--15. 1. " SH1_DPORT_RANGE_SELECT ,SH1 DPORT Prefetch Range Select" tree.end sif cpuis("ADSP-SC594W") tree "MLB0" base ad:0x3109D000 width 12. group.long 0x0++0x3 line.long 0x00 "MLB0_CTL0,MLB0 MediaLB Control 0 Register" bitfld.long 0x00 15.--17. " FCNT ,Frames Per Sub-buffer" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14. " CTLRETRY ,Control Tx Packet Retry" "0,1" bitfld.long 0x00 12. " ASYRETRY ,Asynchronous Tx Packet Retry" "0,1" newline bitfld.long 0x00 7. " LKSTAT ,Lock Status" "0,1" bitfld.long 0x00 5. " PEN ,6-pin Enable" "0,1" bitfld.long 0x00 2.--4. " CLK ,Clock Speed Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x8++0x3 line.long 0x00 "MLB0_PCTL0,MLB0 MediaLB 6-pin Control 0 Register" bitfld.long 0x00 1. " CMRES ,MediaLB 6-pin common mode resistor enable" "0,1" group.long 0xC++0x3 line.long 0x00 "MLB0_MS0,MLB0 Channel Status 0 Register" group.long 0x14++0x3 line.long 0x00 "MLB0_MS1,MLB0 Channel Status 1 Register" group.long 0x20++0x3 line.long 0x00 "MLB0_MSS,MLB0 System Status Register" bitfld.long 0x00 5. " SERVREQ ,Service Request Enable" "0,1" bitfld.long 0x00 4. " SWSYSCMD ,Software System Command Detected" "0,1" bitfld.long 0x00 3. " CSSYSCMD ,Channel Scan System Command Detected" "0,1" newline bitfld.long 0x00 2. " ULKSYSCMD ,Network Unlock System Command Detected" "0,1" bitfld.long 0x00 1. " LKSYSCMD ,Network Lock System Command Detected" "0,1" bitfld.long 0x00 0. " RSTSYSCMD ,Reset System Command Detected" "0,1" group.long 0x24++0x3 line.long 0x00 "MLB0_MSD,MLB0 System Data Register" hexmask.long.byte 0x00 24.--31. 1. " SD3 ,System Data Byte 3 (MSB)" hexmask.long.byte 0x00 16.--23. 1. " SD2 ,System Data Byte 2" hexmask.long.byte 0x00 8.--15. 1. " SD1 ,System Data Byte 1" newline hexmask.long.byte 0x00 0.--7. 1. " SD0 ,System Data Byte 0 (LSB)" group.long 0x2C++0x3 line.long 0x00 "MLB0_MIEN,MLB0 Interrupt Enable Register" bitfld.long 0x00 29. " CTXBREAK ,Control Transmit Break Enable" "0,1" bitfld.long 0x00 28. " CTXPE ,Control Transmit Protocol Error Enable" "0,1" bitfld.long 0x00 27. " CTXDONE ,Control Transmit Packet Done Enable" "0,1" newline bitfld.long 0x00 26. " CRXBREAK ,Control Receive Break Enable" "0,1" bitfld.long 0x00 25. " CRXPE ,Control Receive Protocol Error Enable" "0,1" bitfld.long 0x00 24. " CRXDONE ,Control Receive Packet Done Enable" "0,1" newline bitfld.long 0x00 22. " ATXBREAK ,Asynchronous Transmit Break Enable" "0,1" bitfld.long 0x00 21. " ATXPE ,Asynchronous Transmit Protocol Error Enable" "0,1" bitfld.long 0x00 20. " ATXDONE ,Asynchronous Transmit Done Enable" "0,1" newline bitfld.long 0x00 19. " ARXBREAK ,Asynchronous Receive Break Enable" "0,1" bitfld.long 0x00 18. " ARXPE ,Asynchronous Receive Protocol Error Enable" "0,1" bitfld.long 0x00 17. " ARXDONE ,Asynchronous Receive Packet Done Enable" "0,1" newline bitfld.long 0x00 16. " SYNCPE ,Synchronous Protocol Error Enable" "0,1" bitfld.long 0x00 1. " ISOCBUFO ,Isochronous Receive Buffer Overflow Enable" "0,1" bitfld.long 0x00 0. " ISOCPE ,Isochronous Receive Protocol Error Enable" "0,1" group.long 0x34++0x3 line.long 0x00 "MLB0_GCTL,MLB0 MLB Global Control Register" bitfld.long 0x00 2. " CLKOUTSEL ,CLKOUT Select" "0,1" bitfld.long 0x00 1. " CLKOUTEN ,CLKOUT Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "MLB0_CTL1,MLB0 Control 1 Register" hexmask.long.byte 0x00 8.--15. 1. " NDA ,Node Device Address" bitfld.long 0x00 7. " CLKM ,Lock Missing Status" "0,1" bitfld.long 0x00 6. " LOCK ,Lock Error Status" "0,1" group.long 0x80++0x3 line.long 0x00 "MLB0_HCTL,MLB0 HBI Control Register" bitfld.long 0x00 15. " EN ,HBI Enable" "0,1" bitfld.long 0x00 1. " RST1 ,AGU1 Software Reset" "0,1" bitfld.long 0x00 0. " RST0 ,AGU0 Software Reset" "0,1" group.long 0x88++0x3 line.long 0x00 "MLB0_HCMR0,MLB0 HBI Channel Mask 0 Register" group.long 0x8C++0x3 line.long 0x00 "MLB0_HCMR1,MLB0 HBI Channel Mask 1 Register" group.long 0x90++0x3 line.long 0x00 "MLB0_HCER0,MLB0 HBI Channel Error 0 Register" group.long 0x94++0x3 line.long 0x00 "MLB0_HCER1,MLB0 HBI Channel Error 1 Register" group.long 0x98++0x3 line.long 0x00 "MLB0_HCBR0,MLB0 HBI Channel Busy 0 Register" group.long 0x9C++0x3 line.long 0x00 "MLB0_HCBR1,MLB0 HBI Channel Busy 1 Register" group.long 0xC0++0x3 line.long 0x00 "MLB0_MDAT0,MLB0 Memory Interface Control Data 0 Register" group.long 0xC4++0x3 line.long 0x00 "MLB0_MDAT1,MLB0 Memory Interface Control Data 1 Register" group.long 0xC8++0x3 line.long 0x00 "MLB0_MDAT2,MLB0 Memory Interface Control Data 2 Register" group.long 0xCC++0x3 line.long 0x00 "MLB0_MDAT3,MLB0 Memory Interface Control Data 3 Register" group.long 0xD0++0x3 line.long 0x00 "MLB0_MDWE0,MLB0 Memory Interface Control Data Write Enable 0 Register" group.long 0xD4++0x3 line.long 0x00 "MLB0_MDWE1,MLB0 Memory Interface Control Data Write Enable 1 Register" group.long 0xD8++0x3 line.long 0x00 "MLB0_MDWE2,MLB0 Memory Interface Control Data Write Enable 2 Register" group.long 0xDC++0x3 line.long 0x00 "MLB0_MDWE3,MLB0 Memory Interface Control Data Write Enable 3 Register" group.long 0xE0++0x3 line.long 0x00 "MLB0_MCTL,MLB0 Memory Interface Control Register" bitfld.long 0x00 0. " XCMP ,Transfer Complete (Write 0 to clear)" "0,1" group.long 0xE4++0x3 line.long 0x00 "MLB0_MADR,MLB0 Memory Interface Address Register" bitfld.long 0x00 31. " WNR ,Write-Not-Read" "0,1" bitfld.long 0x00 30. " TB ,Target Bit" "0,1" hexmask.long.byte 0x00 8.--15. 1. " ADDRH ,Address Higher Bits" newline hexmask.long.byte 0x00 0.--7. 1. " ADDRL ,Address Lower Bits" group.long 0x3C0++0x3 line.long 0x00 "MLB0_ACTL,MLB0 Bus Control Register" bitfld.long 0x00 4. " MPB ,Packet Buffering Mode" "0,1" bitfld.long 0x00 2. " DMAMODE ,DMA Mode" "0,1" bitfld.long 0x00 1. " SMX ,Interrupt Multiplex Enable" "0,1" newline bitfld.long 0x00 0. " SCE ,Software Clear Enable" "0,1" group.long 0x3D0++0x3 line.long 0x00 "MLB0_ACSR0,MLB0 Peripheral Channel Status 0 Register" group.long 0x3D4++0x3 line.long 0x00 "MLB0_ACSR1,MLB0 Peripheral Channel Status 1 Register" group.long 0x3D8++0x3 line.long 0x00 "MLB0_ACMR0,MLB0 Peripheral Channel Mask 0 Register" group.long 0x3DC++0x3 line.long 0x00 "MLB0_ACMR1,MLB0 Peripheral Channel Mask 1 Register" tree.end endif tree "OSPI0" base ad:0x31027000 width 18. group.long 0x0++0x3 line.long 0x00 "OSPI0_CTL,OSPI0 Octal SPI Control Register" bitfld.long 0x00 31. " IDLE ,Idle" "0,1" bitfld.long 0x00 30. " OPCODEEN ,Dual Byte Opcode Enable" "0,1" bitfld.long 0x00 25. " PIPEPHYEN ,Pipeline PHY Mode Enable" "0,1" newline bitfld.long 0x00 24. " DTREN ,Enable DTR Protocol" "0,1" bitfld.long 0x00 19.--22. " BAUD ,Master Mode Baud Rate Divisor (2 to 32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18. " XIPIMM ,Enter XIP Mode Immediately" "0,1" newline bitfld.long 0x00 17. " XIPRD ,Enter XIP Mode on Next Read" "0,1" bitfld.long 0x00 16. " AHBADDREN ,Enable AHB Address Remapping" "0,1" bitfld.long 0x00 14. " WRPROT ,Write Protect Flash" "0,1" newline bitfld.long 0x00 10.--13. " SSEL ,Peripheral Chip Select Lines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. " SSELDCODE ,Peripheral Select Decode" "0,1" bitfld.long 0x00 7. " DACEN ,Direct Access Controller Enable" "0,1" newline bitfld.long 0x00 6. " RSTCFG ,Reset Configuration" "0,1" bitfld.long 0x00 5. " RST ,Reset Pin" "0,1" bitfld.long 0x00 4. " HLD ,Hold Pin" "0,1" newline bitfld.long 0x00 3. " PHYEN ,PHY Mode Enable" "0,1" bitfld.long 0x00 2. " CPHA ,Clock Phase" "0,1" bitfld.long 0x00 1. " CPOL ,Clock Polarity" "0,1" newline bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "OSPI0_DRICTL,OSPI0 Device Read Instruction Control Register" bitfld.long 0x00 24.--28. " DMYRD ,Dummy Read Clock Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " MODEEN ,Mode Enable" "0,1" bitfld.long 0x00 16.--17. " DATATRNSFR ,Data Transfer Type" "0,1,2,3" newline bitfld.long 0x00 12.--13. " ADDRTRNSFR ,Address Transfer Type" "0,1,2,3" bitfld.long 0x00 10. " DDREN ,DDR Enable" "0,1" bitfld.long 0x00 8.--9. " INSTRTYP ,Instruction Type" "0,1,2,3" newline hexmask.long.byte 0x00 0.--7. 1. " OPCODERD ,Read Opcode in Non-XIP Mode" group.long 0x8++0x3 line.long 0x00 "OSPI0_DWICTL,OSPI0 Device Write Instruction Control Register" bitfld.long 0x00 24.--28. " DMYWR ,Dummy Write Clock Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " DATATRNSFR ,Data Transfer Type" "0,1,2,3" bitfld.long 0x00 12.--13. " ADDRTRNSFR ,Address Transfer Type" "0,1,2,3" newline bitfld.long 0x00 8. " WELDIS ,WEL Disable" "0,1" hexmask.long.byte 0x00 0.--7. 1. " OPCODEWR ,Write Opcode" group.long 0xC++0x3 line.long 0x00 "OSPI0_DLY,OSPI0 Device Delay Register" hexmask.long.byte 0x00 24.--31. 1. " DSRT ,Clock Delay for Chip Select Deassert" hexmask.long.byte 0x00 16.--23. 1. " DACT ,Clock Delay for Chip Select Deactivation" hexmask.long.byte 0x00 8.--15. 1. " LSTTRAN ,Clock Delay for Last Transaction" newline hexmask.long.byte 0x00 0.--7. 1. " INIT ,Clock Delay" group.long 0x10++0x3 line.long 0x00 "OSPI0_RDC,OSPI0 Read Data Capture Register" bitfld.long 0x00 16.--19. " DDRDLYRD ,DDR Read Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " DQSEN ,DQS Enable" "0,1" bitfld.long 0x00 5. " SMPLEDG ,Sample Edge Selection" "0,1" newline bitfld.long 0x00 1.--4. " DLYRD ,Read Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14++0x3 line.long 0x00 "OSPI0_DSCTL,OSPI0 Device Size Control Register" bitfld.long 0x00 16.--20. " BLKSZ ,Number of Bytes per Block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 4.--15. 1. " PGSZ ,Number of Bytes per Device Page" bitfld.long 0x00 0.--3. " ADDRSZ ,Number of Address Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "OSPI0_REMAPADDR,OSPI0 Remap Address Register" group.long 0x28++0x3 line.long 0x00 "OSPI0_MBCTL,OSPI0 Mode Bit Control Register" hexmask.long.byte 0x00 0.--7. 1. " MODE ,Mode" group.long 0x38++0x3 line.long 0x00 "OSPI0_WCCTL,OSPI0 Write Completion Control Register" hexmask.long.byte 0x00 24.--31. 1. " REPDLY ,Polling Repetition Delay" hexmask.long.byte 0x00 16.--23. 1. " CNT ,Poll Count" bitfld.long 0x00 15. " EXPEN ,Enable Polling Expiration" "0,1" newline bitfld.long 0x00 14. " DIS ,Disable Polling" "0,1" bitfld.long 0x00 13. " POLRTY ,Polling Polarity" "0,1" bitfld.long 0x00 8.--10. " INDEX ,Polling Index" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Opcode" group.long 0x3C++0x3 line.long 0x00 "OSPI0_POLLEXP,OSPI0 Polling Expiration Register" group.long 0x40++0x3 line.long 0x00 "OSPI0_ISTAT,OSPI0 Interrupt Status Register" bitfld.long 0x00 14. " STIGREQ ,STIG Request Completion Interrupt" "0,1" bitfld.long 0x00 13. " POLEXP ,Poll Expiration Cycles" "0,1" bitfld.long 0x00 5. " ILLACCES ,Illegal AHB Access Detected" "0,1" newline bitfld.long 0x00 4. " WRPROT ,Write to Protected Area is Attempted and Rejected" "0,1" bitfld.long 0x00 1. " UNDRFLW ,Underflow Detection" "0,1" group.long 0x44++0x3 line.long 0x00 "OSPI0_IMSK,OSPI0 Interrupt Mask Register" bitfld.long 0x00 14. " STIGREQ_MSK ,STIG Request Completion Mask" "0,1" bitfld.long 0x00 13. " POLEXP_MSK ,Polling Expiration Detected Mask" "0,1" bitfld.long 0x00 5. " ILLACCES_MSK ,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x00 4. " WRPROT_MSK ,Protected Area Write Attempt Mask" "0,1" bitfld.long 0x00 1. " UNDRFLW_MSK ,Underflow Detected Mask" "0,1" bitfld.long 0x00 0. " MODEFAIL_MSK ,Mode M Failure Mask" "0,1" group.long 0x50++0x3 line.long 0x00 "OSPI0_WRPROT_LWR,OSPI0 Lower Write Protection Register" group.long 0x54++0x3 line.long 0x00 "OSPI0_WRPROT_UP,OSPI0 Upper Write Protection Register" group.long 0x58++0x3 line.long 0x00 "OSPI0_WRPROT_CTL,OSPI0 Write Protection Control Register" bitfld.long 0x00 1. " EN ,Write Protection Enable Bit" "0,1" bitfld.long 0x00 0. " INV ,Write Protection Inversion Bit" "0,1" group.long 0x8C++0x3 line.long 0x00 "OSPI0_FCMCTL,OSPI0 Flash Command Control Memory Register" hexmask.long.word 0x00 20.--28. 1. " BNKADDR ,Memory Bank Address" bitfld.long 0x00 16.--18. " RDSZ ,Number of STIG Bytes" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 8.--15. 1. " BNKDATA ,Last Requested Data from STIG Memory Bank" newline bitfld.long 0x00 1. " BNKREQ ,Memory Bank Data Request in Progress" "0,1" bitfld.long 0x00 0. " TRIGREQ ,Trigger Memory Bank Data Request" "0,1" group.long 0x90++0x3 line.long 0x00 "OSPI0_FCCTL,OSPI0 Flash Command Control Register" hexmask.long.byte 0x00 24.--31. 1. " OPCODE ,Command Opcode" bitfld.long 0x00 23. " RDEN ,Read Data Enable" "0,1" bitfld.long 0x00 20.--22. " RDSZ ,Number of Read Data Bytes" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 19. " ADDREN ,Command Address Enable" "0,1" bitfld.long 0x00 18. " MODEEN ,Mode Bit Enable" "0,1" bitfld.long 0x00 16.--17. " ADDRSZ ,Number of Address Bytes" "0,1,2,3" newline bitfld.long 0x00 15. " WREN ,Write Data Enable" "0,1" bitfld.long 0x00 12.--14. " WRSZ ,Number of Write Data Bytes" "0,1,2,3,4,5,6,7" bitfld.long 0x00 7.--11. " DMY ,Number of Dummy Cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 2. " STIGBNKEN ,STIG Memory Bank Enable" "0,1" bitfld.long 0x00 1. " STAT ,Command Execution in Progress" "0,1" bitfld.long 0x00 0. " EXE ,Execute the STIG Command" "0,1" group.long 0x94++0x3 line.long 0x00 "OSPI0_FCA,OSPI0 Flash Command Address Register" group.long 0xA0++0x3 line.long 0x00 "OSPI0_FCRD_LWR,OSPI0 Flash Command Read Data Register (Lower)" group.long 0xA4++0x3 line.long 0x00 "OSPI0_FCRD_UP,OSPI0 Flash Command Read Data Register (Upper)" group.long 0xA8++0x3 line.long 0x00 "OSPI0_FCWD_LWR,OSPI0 Flash Command Write Data Register (Lower)" group.long 0xAC++0x3 line.long 0x00 "OSPI0_FCWD_UP,OSPI0 Flash Command Write Data Register (Upper)" group.long 0xB0++0x3 line.long 0x00 "OSPI0_POLSTAT,OSPI0 Polling Flash Status Register" bitfld.long 0x00 16.--19. " DMY ,Number of Dummy Cycles for Auto Polling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " STAT ,Device Status Valid" "0,1" hexmask.long.byte 0x00 0.--7. 1. " DEVSTAT ,Defines Actual Status Register of Device" group.long 0xB4++0x3 line.long 0x00 "OSPI0_PHYCTL,OSPI0 PHY Control Register" bitfld.long 0x00 31. " RESYNC ,Re-synchronization Delay" "0,1" bitfld.long 0x00 30. " RST ,DLL Reset" "0,1" bitfld.long 0x00 29. " RXBYP ,Receive DLL Bypass" "0,1" newline bitfld.long 0x00 23.--28. " RSVRD2 ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 16.--22. 1. " TXDLY ,Transmit DLL Delay" hexmask.long.word 0x00 7.--15. 1. " RSVRD1 ,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. " RXDLY ,Receive DLL Delay" group.long 0xB8++0x3 line.long 0x00 "OSPI0_PHYMCTL,OSPI0 PHY DLL Master Control Register" hexmask.long.byte 0x00 25.--31. 1. " RSVRD3 ,Reserved" bitfld.long 0x00 24. " LCK ,PHY Master Lock Mode" "0,1" bitfld.long 0x00 23. " BYPCTL ,Bypass Mode Control" "0,1" newline bitfld.long 0x00 20.--22. " PDSEL ,PHY Master Phase Detect Selector" "0,1,2,3,4,5,6,7" bitfld.long 0x00 19. " RSVRD2 ,Reserved" "0,1" bitfld.long 0x00 16.--18. " IND ,Increment/Decrement Indication" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x00 7.--15. 1. " RSVRD1 ,Reserved" hexmask.long.byte 0x00 0.--6. 1. " INITDLY ,Initial Delay" group.long 0xBC++0x3 line.long 0x00 "OSPI0_DLLOB_LWR,OSPI0 DLL Observable Register (Lower)" hexmask.long.byte 0x00 24.--31. 1. " INCSTAT ,State of Cumulative DLL Lock Inc Register" hexmask.long.byte 0x00 16.--23. 1. " DECSTAT ,State of Cumulative DLL Lock Dec Register" bitfld.long 0x00 15. " LOCK_LB ,Loop Back Lock" "0,1" newline hexmask.long.byte 0x00 8.--14. 1. " LWRLOCK ,DLL Observable Lower Lock Value" bitfld.long 0x00 3.--7. " UNLOCK ,DLL Observable Lower Unlock Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1.--2. " LOCK ,Mode in Which DLL is Locked" "0,1,2,3" newline bitfld.long 0x00 0. " STAT ,Indicates DLL Status" "0,1" group.long 0xC0++0x3 line.long 0x00 "OSPI0_DLLOB_UP,OSPI0 DLL Observable Register (Upper)" hexmask.long.word 0x00 23.--31. 1. " RSVRD2 ,Reserved" hexmask.long.byte 0x00 16.--22. 1. " TXOP ,DLL Observable Upper Transmit Decoder Output" hexmask.long.word 0x00 7.--15. 1. " RSVRD1 ,Reserved" newline hexmask.long.byte 0x00 0.--6. 1. " RXOP ,DLL Observable Upper Receive Decoder Output" group.long 0xE0++0x3 line.long 0x00 "OSPI0_OE_LWR,OSPI0 Opcode Extension Register (Lower)" hexmask.long.byte 0x00 24.--31. 1. " XRDBYT ,Supplement Byte of Any Read Opcode" hexmask.long.byte 0x00 16.--23. 1. " XWRBYT ,Supplement Byte of Any Write Opcode" hexmask.long.byte 0x00 8.--15. 1. " XPOLBYT ,Supplement Byte of Any Polling Opcode" newline hexmask.long.byte 0x00 0.--7. 1. " XSTIGBYT ,Supplement Byte of Any STIG Opcode" group.long 0xE4++0x3 line.long 0x00 "OSPI0_OE_UP,OSPI0 Opcode Extension Register (Upper)" hexmask.long.byte 0x00 24.--31. 1. " FSTBYTWEL ,First Byte of Any WEL Opcode" hexmask.long.byte 0x00 16.--23. 1. " XBYTWEL ,Supplement Byte of Any WEL Opcode" group.long 0xFC++0x3 line.long 0x00 "OSPI0_MODID,OSPI0 Module ID Register" hexmask.long.byte 0x00 24.--31. 1. " PATCH ,Fix/Patch Number" hexmask.long.word 0x00 8.--23. 1. " REVID ,Module/Revision ID Number" bitfld.long 0x00 0.--1. " CFGID ,Configuration ID" "0,1,2,3" tree.end tree "OTPC0" base ad:0x31011004 width 18. group.long 0x0++0x3 line.long 0x00 "OTPC0_STAT,OTPC0 OTP Status Register" bitfld.long 0x00 13.--14. " ADDRERR ,OTP Address Error" "0,1,2,3" group.long 0x28++0x3 line.long 0x00 "OTPC0_SECU_STATE,OTPC0 OTP Security State Register" bitfld.long 0x00 0.--1. " PARTLOCK ,Part Locked" "0,1,2,3" tree.end tree "PADS0" base ad:0x31004604 width 19. group.long 0x0++0x3 line.long 0x00 "PADS0_PCFG0,PADS0 Peripheral PAD Configuration0 Register" bitfld.long 0x00 18. " FAULT_DIS ,FAULT does not exist" "0,1" bitfld.long 0x00 17. " EMACAUXIE ,Input enable control for PTP_AUXIN pins" "0,1" bitfld.long 0x00 16. " PUTMS ,Pull-Up Enable for TMS/SWDIO (debug port)" "0,1" newline bitfld.long 0x00 7. " CNT0DGSEL ,CNT0 Down Input Select" "0,1" bitfld.long 0x00 6. " CNT0UDSEL ,CNT0 Up Input Select" "0,1" bitfld.long 0x00 3.--4. " EMACPHYISEL ,Select PHY Interface RGMII/RMII/MII" "0,1,2,3" newline bitfld.long 0x00 2. " EMACRESET ,Reset Enable for RGMII" "0,1" bitfld.long 0x00 0.--1. " EMAC0 ,PTP Clock Source 0" "0,1,2,3" group.long 0x4++0x3 line.long 0x00 "PADS0_PCFG1,PADS0 Peripheral Configuration1 Register" hexmask.long.word 0x00 16.--25. 1. " TIMER_SEC_INP ,Selects secondary inputs to timers." group.long 0x8++0x3 line.long 0x00 "PADS0_PORTA0_DS,PADS0 PORTA 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PA7 ,DS control for PA7 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PA6 ,DS control for PA6 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PA5 ,DS control for PA5 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PA4 ,DS control for PA4 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PA3 ,DS control for PA3 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PA2 ,DS control for PA2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PA1 ,DS control for PA1 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PA0 ,DS control for PA0 IO." "0,1,2,3,4,5,6,7" group.long 0xC++0x3 line.long 0x00 "PADS0_PORTA1_DS,PADS0 PORTA 8 - 15 pins DS control" bitfld.long 0x00 21.--23. " PA15 ,DS control for PA15 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PA14 ,DS control for PA14 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PA13 ,DS control for PA13 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PA12 ,DS control for PA12 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PA11 ,DS control for PA11 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PA10 ,DS control for PA10 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PA9 ,DS control for PA9 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PA8 ,DS control for PA8 IO." "0,1,2,3,4,5,6,7" group.long 0x10++0x3 line.long 0x00 "PADS0_PORTB0_DS,PADS0 PORTB 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PB7 ,DS control for PB7 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PB6 ,DS control for PB6 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PB5 ,DS control for PB5 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PB4 ,DS control for PB4 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PB3 ,DS control for PB3 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PB2 ,DS control for PB2 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PB1 ,DS control for PB1 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PB0 ,DS control for PB0 IO." "0,1,2,3,4,5,6,7" group.long 0x14++0x3 line.long 0x00 "PADS0_PORTB1_DS,PADS0 PORTB 8 - 15 pins DS control" bitfld.long 0x00 21.--23. " PB15 ,DS control for PB15 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PB14 ,DS control for PB14 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PB13 ,DS control for PB13 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PB12 ,DS control for PB12 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PB11 ,DS control for PB11 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PB10 ,DS control for PB10 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PB9 ,DS control for PB9 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PB8 ,DS control for PB8 IO." "0,1,2,3,4,5,6,7" group.long 0x18++0x3 line.long 0x00 "PADS0_PORTC0_DS,PADS0 PORTC 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PC7 ,DS control for PC7 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PC6 ,DS control for PC6 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PC5 ,DS control for PC5 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PC4 ,DS control for PC4 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PC3 ,DS control for PC3 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PC2 ,DS control for PC2 IO." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PC1 ,DS control for PC1 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PC0 ,DS control for PC0 IO." "0,1,2,3,4,5,6,7" group.long 0x1C++0x3 line.long 0x00 "PADS0_PORTC1_DS,PADS0 PORTC 8 - 15 pins DS control" bitfld.long 0x00 21.--23. " PC15 ,DS control for PC15 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PC14 ,DS control for PC14 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PC13 ,DS control for PC13 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PC12 ,DS control for PC12 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PC11 ,DS control for PC11 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PC10 ,DS control for PC10 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PC9 ,DS control for PC9 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PC8 ,DS control for PC8 IO" "0,1,2,3,4,5,6,7" group.long 0x20++0x3 line.long 0x00 "PADS0_PORTD0_DS,PADS0 PORTD 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PD7 ,DS control for PD7 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PD6 ,DS control for PD6 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PD5 ,DS control for PD5 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PD4 ,DS control for PD4 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PD3 ,DS control for PD3 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PD2 ,DS control for PD2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PD1 ,DS control for PD1 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PD0 ,DS control for PD0 IO" "0,1,2,3,4,5,6,7" group.long 0x24++0x3 line.long 0x00 "PADS0_PORTD1_DS,PADS0 PORTD 8 to 15 pins DS control" bitfld.long 0x00 21.--23. " PD15 ,DS control for PD15 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PD14 ,DS control for PD14 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PD13 ,DS control for PD13 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PD12 ,DS control for PD12 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PD11 ,DS control for PD11 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PD10 ,DS control for PD10 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PD9 ,DS control for PD9 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PD8 ,DS control for PD8 IO" "0,1,2,3,4,5,6,7" group.long 0x28++0x3 line.long 0x00 "PADS0_PORTE0_DS,PADS0 PORTE 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PE7 ,DS control for PE7 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PE6 ,DS control for PE6 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PE5 ,DS control for PE5 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PE4 ,DS control for PE4 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PE3 ,DS control for PE3 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PE2 ,DS control for PE2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PE1 ,DS control for PE1 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PE0 ,DS control for PE0 IO" "0,1,2,3,4,5,6,7" group.long 0x2C++0x3 line.long 0x00 "PADS0_PORTE1_DS,PADS0 PORTE 8 to 15 pins DS control" bitfld.long 0x00 21.--23. " PE15 ,DS control for PE15 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PE14 ,DS control for PE14 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PE13 ,DS control for PE13 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PE12 ,DS control for PE12 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PE11 ,DS control for PE11 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PE10 ,DS control for PE10 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PE9 ,DS control for PE9 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PE8 ,DS control for PE8 IO" "0,1,2,3,4,5,6,7" group.long 0x30++0x3 line.long 0x00 "PADS0_PORTF0_DS,PADS0 PORTF 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PF7 ,DS control for PF7 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PF6 ,DS control for PF6 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PF5 ,DS control for PF5 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PF4 ,DS control for PF4 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PF3 ,DS control for PF3 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PF2 ,DS control for PF2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PF1 ,DS control for PF1 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PF0 ,DS control for PF0 IO" "0,1,2,3,4,5,6,7" group.long 0x34++0x3 line.long 0x00 "PADS0_PORTF1_DS,PADS0 PORTF 8 to 15 pins DS control" bitfld.long 0x00 21.--23. " PF15 ,DS control for PF15 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PF14 ,DS control for PF14 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PF13 ,DS control for PF13 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PF12 ,DS control for PF12 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PF11 ,DS control for PF11 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PF10 ,DS control for PF10 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PF9 ,DS control for PF9 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PF8 ,DS control for PF8 IO" "0,1,2,3,4,5,6,7" group.long 0x38++0x3 line.long 0x00 "PADS0_PORTG0_DS,PADS0 PORTG 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PG7 ,DS control for PG7 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PG6 ,DS control for PG6 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PG5 ,DS control for PG5 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PG4 ,DS control for PG4 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PG3 ,DS control for PG3 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PG2 ,DS control for PG2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PG1 ,DS control for PG1 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PG0 ,DS control for PG0 IO" "0,1,2,3,4,5,6,7" group.long 0x3C++0x3 line.long 0x00 "PADS0_PORTG1_DS,PADS0 PORTG 8 to 15 pins DS control" bitfld.long 0x00 21.--23. " PG15 ,DS control for PG15 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PG14 ,DS control for PG14 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PG13 ,DS control for PG13 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PG12 ,DS control for PG12 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PG11 ,DS control for PG11 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PG10 ,DS control for PG10 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PG9 ,DS control for PG9 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PG8 ,DS control for PG8 IO" "0,1,2,3,4,5,6,7" group.long 0x40++0x3 line.long 0x00 "PADS0_PORTH0_DS,PADS0 PORTH 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PH7 ,DS control for PH7 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PH6 ,DS control for PH6 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PH5 ,DS control for PH5 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PH4 ,DS control for PH4 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PH3 ,DS control for PH3 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PH2 ,DS control for PH2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PH1 ,DS control for PH1 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PH0 ,DS control for PH0 IO" "0,1,2,3,4,5,6,7" group.long 0x44++0x3 line.long 0x00 "PADS0_PORTH1_DS,PADS0 PORTH 8 to 15 pins DS control" bitfld.long 0x00 21.--23. " PH15 ,DS control for PH15 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PH14 ,DS control for PH14 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PH13 ,DS control for PH13 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PH12 ,DS control for PH12 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PH11 ,DS control for PH11 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PH10 ,DS control for PH10 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PH9 ,DS control for PH9 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PH8 ,DS control for PH8 IO" "0,1,2,3,4,5,6,7" group.long 0x48++0x3 line.long 0x00 "PADS0_PORTI0_DS,PADS0 PORTI 0 to 7 pins DS control" bitfld.long 0x00 21.--23. " PI7 ,DS control for PI7 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " PI6 ,DS control for PI6 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " PI5 ,DS control for PI5 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. " PI4 ,DS control for PI4 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 9.--11. " PI3 ,DS control for PI3 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " PI2 ,DS control for PI2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3.--5. " PI1 ,DS control for PI1 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " PI0 ,DS control for PI0 IO" "0,1,2,3,4,5,6,7" group.long 0x4C++0x3 line.long 0x00 "PADS0_NONPORTS_DS,PADS0 Non-GPIO Drive Strength Register" bitfld.long 0x00 18.--20. " FAULT ,FAULT DS control." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " OSPI ,OSPI pins DS control." "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " LP0CK ,LP0 Clock Drive Strength Control." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. " LP1CK ,LP1 Clock Drive Strength Control." "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " FAULTB ,FAULTB DS control." "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " RESOUTB ,RESOUTB DS control." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " CKOUT ,CLKOUT DS control." "0,1,2,3,4,5,6,7" group.long 0x74++0x3 line.long 0x00 "PADS0_DAI0_0_DS,PADS0 DAI0 1 to 10 pins DS control" bitfld.long 0x00 27.--29. " DAI10 ,DS control for DAI10 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " DAI9 ,DS control for DAI9 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. " DAI8 ,DS control for DAI8 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " DAI7 ,DS control for DAI7 IO." "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " DAI6 ,DS control for DAI6 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " DAI5 ,DS control for DAI5 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. " DAI4 ,DS control for DAI4 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " DAI3 ,DS control for DAI3 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " DAI2 ,DS control for DAI2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " DAI1 ,DS control for DAI1 IO" "0,1,2,3,4,5,6,7" group.long 0x78++0x3 line.long 0x00 "PADS0_DAI0_1_DS,PADS0 DAI0 11 to 20 pins DS control" bitfld.long 0x00 27.--29. " DAI20 ,DS control for DAI20 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " DAI19 ,DS control for DAI19 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. " DAI18 ,DS control for DAI18 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " DAI17 ,DS control for DAI17 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " DAI16 ,DS control for DAI16 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " DAI15 ,DS control for DAI15 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. " DAI14 ,DS control for DAI14 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " DAI13 ,DS control for DAI13 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " DAI12 ,DS control for DAI12 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " DAI11 ,DS control for DAI11 IO" "0,1,2,3,4,5,6,7" group.long 0x7C++0x3 line.long 0x00 "PADS0_DAI1_0_DS,PADS0 DAI1 1 to 10 pins DS control" bitfld.long 0x00 27.--29. " DAI10 ,DS control for DAI10 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " DAI9 ,DS control for DAI9 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. " DAI8 ,DS control for DAI8 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " DAI7 ,DS control for DAI7 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " DAI6 ,DS control for DAI6 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " DAI5 ,DS control for DAI5 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. " DAI4 ,DS control for DAI4 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " DAI3 ,DS control for DAI3 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " DAI2 ,DS control for DAI2 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " DAI1 ,DS control for DAI1 IO" "0,1,2,3,4,5,6,7" group.long 0x80++0x3 line.long 0x00 "PADS0_DAI1_1_DS,PADS0 DAI1 11 to 20 pins DS control" bitfld.long 0x00 27.--29. " DAI20 ,DS control for DAI20 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " DAI19 ,DS control for DAI19 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 21.--23. " DAI18 ,DS control for DAI18 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 18.--20. " DAI17 ,DS control for DAI17 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 15.--17. " DAI16 ,DS control for DAI16 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " DAI15 ,DS control for DAI15 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. " DAI14 ,DS control for DAI14 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " DAI13 ,DS control for DAI13 IO" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3.--5. " DAI12 ,DS control for DAI12 IO" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. " DAI11 ,DS control for DAI11 IO" "0,1,2,3,4,5,6,7" group.long 0x8C++0x3 line.long 0x00 "PADS0_DAI0_IE,PADS0 DAI0 Port Input Enable Control Register" hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,DAI0 Input Enable Control" group.long 0x90++0x3 line.long 0x00 "PADS0_DAI1_IE,PADS0 DAI1 Port Input Enable Control Register" hexmask.long.tbyte 0x00 0.--19. 1. " VALUE ,DAI1 Input Enable Control" group.long 0x94++0x3 line.long 0x00 "PADS0_PORTA_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0x98++0x3 line.long 0x00 "PADS0_PORTB_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0x9C++0x3 line.long 0x00 "PADS0_PORTC_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0xA0++0x3 line.long 0x00 "PADS0_PORTD_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0xA4++0x3 line.long 0x00 "PADS0_PORTE_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0xA8++0x3 line.long 0x00 "PADS0_PORTF_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0xAC++0x3 line.long 0x00 "PADS0_PORTG_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0xB0++0x3 line.long 0x00 "PADS0_PORTH_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0xB4++0x3 line.long 0x00 "PADS0_PORTI_PUE,PADS0 PORTx Pull-Up Enable" hexmask.long.word 0x00 0.--15. 1. " PUE ,Pull-Up Enable" group.long 0xB8++0x3 line.long 0x00 "PADS0_DAI0_PUE,PADS0 DAIx Pull-Up Enable" hexmask.long.tbyte 0x00 0.--19. 1. " PUE ,Pull-Up Enable" group.long 0xBC++0x3 line.long 0x00 "PADS0_DAI1_PUE,PADS0 DAIx Pull-Up Enable" hexmask.long.tbyte 0x00 0.--19. 1. " PUE ,Pull-Up Enable" group.long 0xC0++0x3 line.long 0x00 "PADS0_PORTA_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xC4++0x3 line.long 0x00 "PADS0_PORTB_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xC8++0x3 line.long 0x00 "PADS0_PORTC_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xCC++0x3 line.long 0x00 "PADS0_PORTD_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xD0++0x3 line.long 0x00 "PADS0_PORTE_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xD4++0x3 line.long 0x00 "PADS0_PORTF_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xD8++0x3 line.long 0x00 "PADS0_PORTG_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xDC++0x3 line.long 0x00 "PADS0_PORTH_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xE0++0x3 line.long 0x00 "PADS0_PORTI_PDE,PADS0 PORTx Pull-Down Enable" hexmask.long.word 0x00 0.--15. 1. " PUD ,Pull-Up Disable" group.long 0xF8++0x3 line.long 0x00 "PADS0_DAI0_PDE,PADS0 DAIx Pull-Down Enable" hexmask.long.tbyte 0x00 0.--19. 1. " PUD ,Pull-Up Disable" group.long 0xFC++0x3 line.long 0x00 "PADS0_DAI1_PDE,PADS0 DAIx Pull-Down Enable" hexmask.long.tbyte 0x00 0.--19. 1. " PUD ,Pull-Up Disable" tree.end tree "PCG (Precision Clock Generators)" base ad:0x310C9300 width 12. group.long 0x0++0x3 line.long 0x00 "PCG0_CTLA0,PCG0 Precision Clock A Control 0 Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "0,1" bitfld.long 0x00 30. " FSEN ,Frame Sync Enable" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for Frame Sync High" newline hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame Sync Divider" group.long 0x4++0x3 line.long 0x00 "PCG0_CTLA1,PCG0 Precision Clock A Control 1 Register" bitfld.long 0x00 31. " CLKSRC ,Clock Source" "0,1" bitfld.long 0x00 30. " FSSRC ,Frame Sync Source" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASELO ,Phase for Frame Sync Low" newline hexmask.long.tbyte 0x00 0.--19. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "PCG0_CTLB0,PCG0 Precision Clock B Control 0 Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "0,1" bitfld.long 0x00 30. " FSEN ,Frame Sync Enable" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for Frame Sync High" newline hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame Sync Divider" group.long 0xC++0x3 line.long 0x00 "PCG0_CTLB1,PCG0 Precision Clock B Control 1 Register" bitfld.long 0x00 31. " CLKSRC ,Clock Source" "0,1" bitfld.long 0x00 30. " FSSRC ,Frame Sync Source" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASELO ,Phase for Frame Sync Low" newline hexmask.long.tbyte 0x00 0.--19. 1. " CLKDIV ,Clock Divisor" group.long 0x10++0x3 line.long 0x00 "PCG0_PW1,PCG0 Precision Clock Pulse Width Control 1 Register" hexmask.long.word 0x00 16.--31. 1. " FSB ,Pulse Width for Frame Sync PCG B" bitfld.long 0x00 17. " INVFSB ,Active Low Frame Sync Select for Frame in Bypass PCG B" "0,1" bitfld.long 0x00 16. " STROBEB ,One Shot Frame Sync Bypass Mode PCG B" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " FSA ,Pulse Width for Frame Sync PCG A" bitfld.long 0x00 1. " INVFSA ,Active Low Frame Sync Select for Frame Sync in Bypass Mode" "0,1" bitfld.long 0x00 0. " STROBEA ,One Shot Frame Sync PCG A" "0,1" group.long 0x14++0x3 line.long 0x00 "PCG0_SYNC1,PCG0 Precision Clock Frame Sync Synchronization 1 Register" bitfld.long 0x00 22. " HWB_TRIGEN ,Hardware trigger Sync B Enable" "0,1" bitfld.long 0x00 21. " FSB_CLKINSEL ,CLKIN source for FSB" "0,1" bitfld.long 0x00 20. " CLKB_CLKINSEL ,CLKIN source for CLKB" "0,1" newline bitfld.long 0x00 19. " FSBSRC ,Frame Sync B Source" "0,1" bitfld.long 0x00 18. " CLKBSRC ,Clock B Source" "0,1" bitfld.long 0x00 17. " CLKB ,Clock B Enable" "0,1" newline bitfld.long 0x00 16. " FSB ,Frame Sync B Enable" "0,1" bitfld.long 0x00 6. " HWA_TRIGEN ,Hardware trigger Sync A Enable" "0,1" bitfld.long 0x00 5. " FSA_CLKINSEL ,CLKIN source for FSA" "0,1" newline bitfld.long 0x00 4. " CLKA_CLKINSEL ,CLKIN source for CLKA" "0,1" bitfld.long 0x00 3. " FSASRC ,Frame Sync Source" "0,1" bitfld.long 0x00 2. " CLKASRC ,Clock A Source" "0,1" newline bitfld.long 0x00 1. " CLKA ,Clock A Enable" "0,1" bitfld.long 0x00 0. " FSA ,Frame Sync A Enable" "0,1" group.long 0x18++0x3 line.long 0x00 "PCG0_CTLE0,PCG0 Precision Clock E Control 0 Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "0,1" bitfld.long 0x00 30. " FSEN ,Frame Sync Enable" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for Frame Sync High" newline hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame Sync Divider" group.long 0x1C++0x3 line.long 0x00 "PCG0_CTLE1,PCG0 Precision Clock E Control 1 Register" bitfld.long 0x00 31. " CLKSRC ,Clock Source" "0,1" bitfld.long 0x00 30. " FSSRC ,Frame Sync Source" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASELO ,Phase for Frame Sync Low" newline hexmask.long.tbyte 0x00 0.--19. 1. " CLKDIV ,Clock Divisor" group.long 0x20++0x3 line.long 0x00 "PCG0_CTLF0,PCG0 Precision Clock F Control 0 Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "0,1" bitfld.long 0x00 30. " FSEN ,Frame Sync Enable" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for Frame Sync High" newline hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame Sync Divider" group.long 0x24++0x3 line.long 0x00 "PCG0_CTLF1,PCG0 Precision Clock F Control 1 Register" bitfld.long 0x00 31. " CLKSRC ,Clock Source" "0,1" bitfld.long 0x00 30. " FSSRC ,Frame Sync Source" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASELO ,Phase for Frame Sync Low" newline hexmask.long.tbyte 0x00 0.--19. 1. " CLKDIV ,Clock Divisor" group.long 0x28++0x3 line.long 0x00 "PCG0_PW3,PCG0 Precision Clock Pulse Width Control 3 Register" hexmask.long.word 0x00 16.--31. 1. " FSF ,Pulse Width for Frame Sync PCG F" bitfld.long 0x00 17. " INVFSF ,Active Low Frame Sync Select for Frame Sync in Bypass Mode" "0,1" bitfld.long 0x00 16. " STROBEF ,One Shot Frame Sync PCG D" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " FSE ,Pulse Width for Frame Sync PCG E" bitfld.long 0x00 1. " INVFSE ,Active Low Frame Sync Select for Frame Sync in Bypass Mode" "0,1" bitfld.long 0x00 0. " STROBEE ,One Shot Frame Sync PCG E" "0,1" group.long 0x2C++0x3 line.long 0x00 "PCG0_SYNC3,PCG0 Precision Clock Frame Sync Synchronization 3 Register" bitfld.long 0x00 22. " HWF_TRIGEN ,Hardware Trigger Sync F Enable" "0,1" bitfld.long 0x00 21. " FSF_CLKINSEL ,CLKIN source for FSF" "0,1" bitfld.long 0x00 20. " CLKF_CLKINSEL ,CLKIN source for CLKF" "0,1" newline bitfld.long 0x00 19. " FSFSRC ,Frame Sync F Source" "0,1" bitfld.long 0x00 18. " CLKFSRC ,Clock F Source" "0,1" bitfld.long 0x00 17. " CLKF ,Clock F Enable" "0,1" newline bitfld.long 0x00 16. " FSF ,Frame Sync F Enable" "0,1" bitfld.long 0x00 6. " HWE_TRIGEN ,Hardware Trigger Sync E Enable" "0,1" bitfld.long 0x00 5. " FSE_CLKINSEL ,CLKIN source for FSE" "0,1" newline bitfld.long 0x00 4. " CLKE_CLKINSEL ,CLKIN source for CLKE" "0,1" bitfld.long 0x00 3. " FSESRC ,Frame Sync Source" "0,1" bitfld.long 0x00 2. " CLKESRC ,Clock E Source" "0,1" newline bitfld.long 0x00 1. " CLKE ,Clock E Enable" "0,1" bitfld.long 0x00 0. " FSE ,Frame Sync E Enable" "0,1" group.long 0x1000++0x3 line.long 0x00 "PCG0_CTLC0,PCG0 Precision Clock C Control 0 Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "0,1" bitfld.long 0x00 30. " FSEN ,Frame Sync Enable" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for Frame Sync High" newline hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame Sync Divider" group.long 0x1004++0x3 line.long 0x00 "PCG0_CTLC1,PCG0 Precision Clock C Control 1 Register" bitfld.long 0x00 31. " CLKSRC ,Clock Source" "0,1" bitfld.long 0x00 30. " FSSRC ,Frame Sync Source" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASELO ,Phase for Frame Sync Low" newline hexmask.long.tbyte 0x00 0.--19. 1. " CLKDIV ,Clock Divisor" group.long 0x1008++0x3 line.long 0x00 "PCG0_CTLD0,PCG0 Precision Clock D Control 0 Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "0,1" bitfld.long 0x00 30. " FSEN ,Frame Sync Enable" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for Frame Sync High" newline hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame Sync Divider" group.long 0x100C++0x3 line.long 0x00 "PCG0_CTLD1,PCG0 Precision Clock D Control 1 Register" bitfld.long 0x00 31. " CLKSRC ,Clock Source" "0,1" bitfld.long 0x00 30. " FSSRC ,Frame Sync Source" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASELO ,Phase for Frame Sync Low" newline hexmask.long.tbyte 0x00 0.--19. 1. " CLKDIV ,Clock Divisor" group.long 0x1010++0x3 line.long 0x00 "PCG0_PW2,PCG0 Precision Clock Pulse Width Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " FSD ,Pulse Width for Frame Sync PCG D" bitfld.long 0x00 17. " INVFSD ,Active Low Frame Sync Select for Frame Sync in Bypass Mode" "0,1" bitfld.long 0x00 16. " STROBED ,One Shot Frame Sync PCG D" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " FSC ,Pulse Width for Frame Sync PCG C" bitfld.long 0x00 1. " INVFSC ,Active Low Frame Sync Select for Frame Sync in Bypass Mode" "0,1" bitfld.long 0x00 0. " STROBEC ,One Shot Frame Sync PCG C" "0,1" group.long 0x1014++0x3 line.long 0x00 "PCG0_SYNC2,PCG0 Precision Clock Frame Sync Synchronization 2 Register" bitfld.long 0x00 22. " HWD_TRIGEN ,Hardware trigger Sync D Enable" "0,1" bitfld.long 0x00 21. " FSD_CLKINSEL ,CLKIN source for FSD" "0,1" bitfld.long 0x00 20. " CLKD_CLKINSEL ,CLKIN source for CLKD" "0,1" newline bitfld.long 0x00 19. " FSDSRC ,Frame Sync D Source" "0,1" bitfld.long 0x00 18. " CLKDSRC ,Clock D Source" "0,1" bitfld.long 0x00 17. " CLKD ,Clock D Enable" "0,1" newline bitfld.long 0x00 16. " FSD ,Frame Sync D Enable" "0,1" bitfld.long 0x00 6. " HWC_TRIGEN ,Hardware trigger Sync C Enable" "0,1" bitfld.long 0x00 5. " FSC_CLKINSEL ,CLKIN source for FSC" "0,1" newline bitfld.long 0x00 4. " CLKC_CLKINSEL ,CLKIN source for CLKC" "0,1" bitfld.long 0x00 3. " FSCSRC ,Frame Sync Source" "0,1" bitfld.long 0x00 2. " CLKCSRC ,Clock C Source" "0,1" newline bitfld.long 0x00 1. " CLKC ,Clock C Enable" "0,1" bitfld.long 0x00 0. " FSC ,Frame Sync C Enable" "0,1" group.long 0x1018++0x3 line.long 0x00 "PCG0_CTLG0,PCG0 Precision Clock G Control 0 Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "0,1" bitfld.long 0x00 30. " FSEN ,Frame Sync Enable" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for Frame Sync High" newline hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame Sync Divider" group.long 0x101C++0x3 line.long 0x00 "PCG0_CTLG1,PCG0 Precision Clock G Control 1 Register" bitfld.long 0x00 31. " CLKSRC ,Clock Source" "0,1" bitfld.long 0x00 30. " FSSRC ,Frame Sync Source" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASELO ,Phase for Frame Sync Low" newline hexmask.long.tbyte 0x00 0.--19. 1. " CLKDIV ,Clock Divisor" group.long 0x1020++0x3 line.long 0x00 "PCG0_CTLH0,PCG0 Precision Clock H Control 0 Register" bitfld.long 0x00 31. " CLKEN ,Clock Enable" "0,1" bitfld.long 0x00 30. " FSEN ,Frame Sync Enable" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASEHI ,Phase for Frame Sync High" newline hexmask.long.tbyte 0x00 0.--19. 1. " FSDIV ,Frame Sync Divider" group.long 0x1024++0x3 line.long 0x00 "PCG0_CTLH1,PCG0 Precision Clock H Control 1 Register" bitfld.long 0x00 31. " CLKSRC ,Clock Source" "0,1" bitfld.long 0x00 30. " FSSRC ,Frame Sync Source" "0,1" hexmask.long.word 0x00 20.--29. 1. " FSPHASELO ,Phase for Frame Sync Low" newline hexmask.long.tbyte 0x00 0.--19. 1. " CLKDIV ,Clock Divisor" group.long 0x1028++0x3 line.long 0x00 "PCG0_PW4,PCG0 Precision Clock Pulse Width Control 4 Register" hexmask.long.word 0x00 16.--31. 1. " FSH ,Pulse Width for Frame Sync PCG H" bitfld.long 0x00 17. " INVFSH ,Active Low Frame Sync Select for Frame Sync in Bypass Mode" "0,1" bitfld.long 0x00 16. " STROBEH ,One Shot Frame Sync PCG H" "0,1" newline hexmask.long.word 0x00 0.--15. 1. " FSG ,Pulse Width for Frame Sync PCG G" bitfld.long 0x00 1. " INVFSG ,Active Low Frame Sync Select for Frame Sync in Bypass Mode" "0,1" bitfld.long 0x00 0. " STROBEG ,One Shot Frame Sync PCG G" "0,1" group.long 0x102C++0x3 line.long 0x00 "PCG0_SYNC4,PCG0 Precision Clock Frame Sync Synchronization 4 Register" bitfld.long 0x00 22. " HWH_TRIGEN ,Hardware Trigger Sync H Enable" "0,1" bitfld.long 0x00 21. " FSH_CLKINSEL ,CLKIN source for FSH" "0,1" bitfld.long 0x00 20. " CLKH_CLKINSEL ,CLKIN source for CLKH" "0,1" newline bitfld.long 0x00 19. " FSHSRC ,Frame Sync H Source" "0,1" bitfld.long 0x00 18. " CLKHSRC ,Clock H Source" "0,1" bitfld.long 0x00 17. " CLKH ,Clock H Enable" "0,1" newline bitfld.long 0x00 16. " FSH ,Frame Sync H Enable" "0,1" bitfld.long 0x00 6. " HWG_TRIGEN ,Hardware Trigger Sync G Enable" "0,1" bitfld.long 0x00 5. " FSG_CLKINSEL ,CLKIN source for FSG" "0,1" newline bitfld.long 0x00 4. " CLKG_CLKINSEL ,CLKIN source for CLKG" "0,1" bitfld.long 0x00 3. " FSGSRC ,Frame Sync Source" "0,1" bitfld.long 0x00 2. " CLKGSRC ,Clock G Source" "0,1" newline bitfld.long 0x00 1. " CLKG ,Clock G Enable" "0,1" bitfld.long 0x00 0. " FSG ,Frame Sync G Enable" "0,1" tree.end tree "PDM0" base ad:0x310C90A4 width 14. group.long 0x0++0x3 line.long 0x00 "PDM0_CTL0,PDM0 PDM Control Register" bitfld.long 0x00 8.--9. " DEC_RATIO ,Decimation Ratio" "0,1,2,3" bitfld.long 0x00 4. " CLK0_EN ,PDM Clock0 Enable" "0,1" bitfld.long 0x00 1. " CH23_EN ,Channels 2/3 (PDM_DAT1) Enable" "0,1" newline bitfld.long 0x00 0. " CH01_EN ,Channels 0/1 (PDM_DAT0) Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "PDM0_HPF_CTL,PDM0 High Pass Filter Control Register" bitfld.long 0x00 4.--7. " FC ,High-pass filter cutoff frequency relative to output sample rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " EN ,High-pass filter enable" "0,1" group.long 0x8++0x3 line.long 0x00 "PDM0_SP_CTL0,PDM0 Serial Port Control0 Register" bitfld.long 0x00 9. " BCLK_POL ,Serial port - selects bclk polarity" "0,1" bitfld.long 0x00 8. " LRCLK_POL ,Serial port - selects lrclk polarity" "0,1" bitfld.long 0x00 6. " TRI_STATE ,Serial port output - tri-state enable" "0,1" newline bitfld.long 0x00 4.--5. " CH0_SLOT_WIDTH ,Serial port - selects slot width" "0,1,2,3" bitfld.long 0x00 1.--3. " DATA_FORMAT ,Serial port - selects data format" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " SAI_MODE ,Serial port - selects SAI mode" "0,1" group.long 0xC++0x3 line.long 0x00 "PDM0_SP_CTL1,PDM0 Serial Port Control1 Register" bitfld.long 0x00 28.--31. " CH3_SLOT ,Serial Port Channel 3 Slot Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24. " CH3_DRV ,Serial Port Channel 3 drive select" "0,1" bitfld.long 0x00 20.--23. " CH2_SLOT ,Serial Port Channel 2 Slot Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16. " CH2_DRV ,Serial Port Channel 2 drive select" "0,1" bitfld.long 0x00 12.--15. " CH1_SLOT ,Serial Port Channel 1 Slot Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " CH1_DRV ,Serial Port Channel 1 drive select" "0,1" newline bitfld.long 0x00 4.--7. " CH0_SLOT ,Serial Port Channel 0 Slot Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CH0_DRV ,Serial Port Channel 0 drive select" "0,1" group.long 0x10++0x3 line.long 0x00 "PDM0_RESET,PDM0 Software Reset Register" bitfld.long 0x00 0. " SOFT ,Software reset not including register settings" "0,1" tree.end tree "PDM1" base ad:0x310CA0A4 width 14. group.long 0x0++0x3 line.long 0x00 "PDM1_CTL0,PDM1 PDM Control Register" bitfld.long 0x00 8.--9. " DEC_RATIO ,Decimation Ratio" "0,1,2,3" bitfld.long 0x00 4. " CLK0_EN ,PDM Clock0 Enable" "0,1" bitfld.long 0x00 1. " CH23_EN ,Channels 2/3 (PDM_DAT1) Enable" "0,1" newline bitfld.long 0x00 0. " CH01_EN ,Channels 0/1 (PDM_DAT0) Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "PDM1_HPF_CTL,PDM1 High Pass Filter Control Register" bitfld.long 0x00 4.--7. " FC ,High-pass filter cutoff frequency relative to output sample rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " EN ,High-pass filter enable" "0,1" group.long 0x8++0x3 line.long 0x00 "PDM1_SP_CTL0,PDM1 Serial Port Control0 Register" bitfld.long 0x00 9. " BCLK_POL ,Serial port - selects bclk polarity" "0,1" bitfld.long 0x00 8. " LRCLK_POL ,Serial port - selects lrclk polarity" "0,1" bitfld.long 0x00 6. " TRI_STATE ,Serial port output - tri-state enable" "0,1" newline bitfld.long 0x00 4.--5. " CH0_SLOT_WIDTH ,Serial port - selects slot width" "0,1,2,3" bitfld.long 0x00 1.--3. " DATA_FORMAT ,Serial port - selects data format" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " SAI_MODE ,Serial port - selects SAI mode" "0,1" group.long 0xC++0x3 line.long 0x00 "PDM1_SP_CTL1,PDM1 Serial Port Control1 Register" bitfld.long 0x00 28.--31. " CH3_SLOT ,Serial Port Channel 3 Slot Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24. " CH3_DRV ,Serial Port Channel 3 drive select" "0,1" bitfld.long 0x00 20.--23. " CH2_SLOT ,Serial Port Channel 2 Slot Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16. " CH2_DRV ,Serial Port Channel 2 drive select" "0,1" bitfld.long 0x00 12.--15. " CH1_SLOT ,Serial Port Channel 1 Slot Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " CH1_DRV ,Serial Port Channel 1 drive select" "0,1" newline bitfld.long 0x00 4.--7. " CH0_SLOT ,Serial Port Channel 0 Slot Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CH0_DRV ,Serial Port Channel 0 drive select" "0,1" group.long 0x10++0x3 line.long 0x00 "PDM1_RESET,PDM1 Software Reset Register" bitfld.long 0x00 0. " SOFT ,Software reset not including register settings" "0,1" tree.end tree "PKA (Public Key Accelerator)" base ad:0x310D4000 width 16. group.long 0x0++0x3 line.long 0x00 "PKA0_APTR,PKA0 PKA Vector_A Address" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Pointer to Vector A" group.long 0x4++0x3 line.long 0x00 "PKA0_BPTR,PKA0 PKA Vector_B Address" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Pointer to Vector B" group.long 0x8++0x3 line.long 0x00 "PKA0_CPTR,PKA0 PKA Vector_C Address" hexmask.long.word 0x00 0.--10. 1. " CPTR ,Pointer to Vector C" group.long 0xC++0x3 line.long 0x00 "PKA0_DPTR,PKA0 PKA Vector_D Address" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Pointer to Vector D" group.long 0x10++0x3 line.long 0x00 "PKA0_ALEN,PKA0 PKA Vector_A Length" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Length of Vector A" group.long 0x14++0x3 line.long 0x00 "PKA0_BLEN,PKA0 PKA Vector_B Length" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Length of Vector B" group.long 0x18++0x3 line.long 0x00 "PKA0_SHIFT,PKA0 PKA Bit Shift Value" bitfld.long 0x00 0.--4. " VALUE ,Bits to Shift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x1C++0x3 line.long 0x00 "PKA0_FUNC,PKA0 PKA Function" bitfld.long 0x00 24. " STALLRSLT ,Stall Result" "0,1" bitfld.long 0x00 15. " RUN ,Run" "0,1" bitfld.long 0x00 12.--14. " SEQOPS ,Sequencer Operation Select" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 11. " CPY ,Copy" "0,1" bitfld.long 0x00 10. " CMP ,Perform Compare Operation" "0,1" bitfld.long 0x00 9. " MODULO ,Perform Modulo Operation" "0,1" newline bitfld.long 0x00 8. " DIV ,Perform Divide Operation" "0,1" bitfld.long 0x00 7. " LSHFT ,Perform Left Shift Operation" "0,1" bitfld.long 0x00 6. " RSHFT ,Perform Right Shift Operation" "0,1" newline bitfld.long 0x00 5. " SUB ,Perform Subtract Operation" "0,1" bitfld.long 0x00 4. " ADD ,Perform Add Operation" "0,1" bitfld.long 0x00 3. " MSONE ,Most Significant One" "0,1" newline bitfld.long 0x00 1. " ADDSUB ,Perform Combined Add/Subtract Operation" "0,1" bitfld.long 0x00 0. " MULT ,Perform Multiply Operation" "0,1" group.long 0x20++0x3 line.long 0x00 "PKA0_COMPARE,PKA0 PKA Compare Result" bitfld.long 0x00 2. " AGTB ,Vector A is Greater Than Vector B" "0,1" bitfld.long 0x00 1. " ALTB ,Vector A is Less Than Vector B" "0,1" bitfld.long 0x00 0. " AEQB ,Vector A is equal to Vector B" "0,1" group.long 0x24++0x3 line.long 0x00 "PKA0_RESULTMSW,PKA0 PKA Most-Significant-Word of Result Vector" bitfld.long 0x00 15. " ZERO ,Result Is Zero" "0,1" hexmask.long.word 0x00 0.--10. 1. " ADDR ,Address of Most-significant Nonzero Word" group.long 0x28++0x3 line.long 0x00 "PKA0_DIVMSW,PKA0 PKA Most-Significant-Word of Divide Remainder" bitfld.long 0x00 15. " ZERO ,Remainder Result Vector is Zeros" "0,1" hexmask.long.word 0x00 0.--10. 1. " ADDR ,Address of Most-significant Nonzero Word" group.long 0x2000++0x3 line.long 0x00 "PKA0_RAM,PKA0 Start of PKA RAM space" tree.end tree "PKIC (Public Key Interrupt Controller)" base ad:0x310D8000 width 16. group.long 0x0++0x3 line.long 0x00 "PKIC0_POL_CTL,PKIC0 Polarity Control Register" bitfld.long 0x00 5. " SLERRINT ,Slave Error IRQ" "0,1" bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "0,1" bitfld.long 0x00 1. " PKAINT1 ,PKA Completion IRQ" "0,1" group.long 0x4++0x3 line.long 0x00 "PKIC0_TYPE_CTL,PKIC0 Type Control Register" bitfld.long 0x00 5. " SLERRINT ,Slave Error IRQ" "0,1" bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "0,1" bitfld.long 0x00 1. " PKAINT1 ,PKA Completion IRQ" "0,1" group.long 0x8++0x3 line.long 0x00 "PKIC0_EN_CTL,PKIC0 Enable Control Register" bitfld.long 0x00 5. " SLERRINT ,Slave Error IRQ" "0,1" bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "0,1" bitfld.long 0x00 1. " PKAINT1 ,PKA Completion IRQ" "0,1" group.long 0xC++0x3 line.long 0x00 "PKIC0_RAW_STAT,PKIC0 Raw Status Register" bitfld.long 0x00 5. " SLERRINT ,Slave Error IRQ" "0,1" bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "0,1" bitfld.long 0x00 1. " PKAINT1 ,PKA Completion IRQ" "0,1" group.long 0xC++0x3 line.long 0x00 "PKIC0_EN_SET,PKIC0 Enable Set Register" bitfld.long 0x00 5. " SLERRINT ,Slave Error IRQ" "0,1" bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "0,1" bitfld.long 0x00 1. " PKAINT1 ,PKA Completion IRQ" "0,1" group.long 0x10++0x3 line.long 0x00 "PKIC0_ACK,PKIC0 Acknowledge Register" bitfld.long 0x00 5. " SLERRINT ,Slave Error IRQ" "0,1" bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "0,1" bitfld.long 0x00 1. " PKAINT1 ,PKA Completion IRQ" "0,1" group.long 0x10++0x3 line.long 0x00 "PKIC0_EN_STAT,PKIC0 Enabled Status Register" bitfld.long 0x00 5. " SLERRINT ,Slave Error IRQ" "0,1" bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "0,1" bitfld.long 0x00 1. " PKAINT1 ,PKA Completion IRQ" "0,1" group.long 0x14++0x3 line.long 0x00 "PKIC0_EN_CLR,PKIC0 Enable Clear Register" bitfld.long 0x00 5. " SLERRINT ,Slave Error IRQ" "0,1" bitfld.long 0x00 3. " TRNGINT ,TRNG IRQ" "0,1" bitfld.long 0x00 1. " PKAINT1 ,PKA Completion IRQ" "0,1" tree.end tree "PKTE (Security Packet Engine)" base ad:0x310CD000 width 23. group.long 0x0++0x3 line.long 0x00 "PKTE0_CTL_STAT,PKTE0 Packet Engine Control Register" hexmask.long.byte 0x00 24.--31. 1. " PADCTLSTAT ,Pad Control/Pad Status" bitfld.long 0x00 20.--23. " EXTERRCD ,Extended Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " EXTERR ,Extended Error" "0,1" newline bitfld.long 0x00 18. " SQNMERR ,Sequence Number Error" "0,1" bitfld.long 0x00 17. " PADERR ,Pad Error" "0,1" bitfld.long 0x00 16. " AUTHERR ,Authentication Error" "0,1" newline hexmask.long.byte 0x00 8.--15. 1. " PADVAL ,Pad Value" bitfld.long 0x00 6.--7. " PRNGMD ,PRNG Mode" "0,1,2,3" bitfld.long 0x00 4. " HASHFINAL ,Hash Final" "0,1" newline bitfld.long 0x00 3. " INITARC4 ,Init ARC4" "0,1" bitfld.long 0x00 1. " PERDY ,Packet Engine Ready" "0,1" bitfld.long 0x00 0. " HOSTRDY ,Host Ready" "0,1" group.long 0x4++0x3 line.long 0x00 "PKTE0_SRC_ADDR,PKTE0 Packet Engine Source Address" group.long 0x8++0x3 line.long 0x00 "PKTE0_DEST_ADDR,PKTE0 Packet Engine Destination Address" group.long 0xC++0x3 line.long 0x00 "PKTE0_SA_ADDR,PKTE0 Packet Engine SA Address" group.long 0x10++0x3 line.long 0x00 "PKTE0_STATE_ADDR,PKTE0 Packet Engine State Record Address" group.long 0x14++0x3 line.long 0x00 "PKTE0_ARC4STATE_ADDR,PKTE0 Packet Engine ARC4 State Record Address" group.long 0x18++0x3 line.long 0x00 "PKTE0_USERID,PKTE0 Packet Engine User ID" group.long 0x1C++0x3 line.long 0x00 "PKTE0_LEN,PKTE0 Packet Engine Length Register" hexmask.long.byte 0x00 24.--31. 1. " BYPASS ,Bypass" bitfld.long 0x00 23. " PEDONE ,PE Done" "0,1" bitfld.long 0x00 22. " HSTRDY ,Host Ready" "0,1" newline hexmask.long.tbyte 0x00 0.--19. 1. " TOTLEN ,Total length" group.long 0x80++0x3 line.long 0x00 "PKTE0_CDRBASE_ADDR,PKTE0 Packet Engine Command Descriptor Ring Base Address" group.long 0x84++0x3 line.long 0x00 "PKTE0_RDRBASE_ADDR,PKTE0 Packet Engine Result Descriptor Ring Base Address" group.long 0x88++0x3 line.long 0x00 "PKTE0_RING_CFG,PKTE0 Packet Engine Ring Configuration" bitfld.long 0x00 31. " ENEXTTRIG ,Enable External Trigger" "0,1" hexmask.long.word 0x00 0.--9. 1. " RINGSZ ,Ring Size" group.long 0x8C++0x3 line.long 0x00 "PKTE0_RING_THRESH,PKTE0 Packet Engine Ring Threshold Registers" bitfld.long 0x00 31. " TOEN ,Timeout Enable" "0,1" bitfld.long 0x00 26.--29. " RDTO ,Read Descriptor Timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 16.--25. 1. " RDRTHRSH ,Result Descriptor Ring Threshold" newline hexmask.long.word 0x00 0.--9. 1. " CDRTHRSH ,Command Descriptor Ring Threshold" group.long 0x90++0x3 line.long 0x00 "PKTE0_CDSC_INCR,PKTE0 Packet Engine Command Descriptor Count Increment Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Command Descriptor Count Increment" group.long 0x90++0x3 line.long 0x00 "PKTE0_CDSC_CNT,PKTE0 Packet Engine Command Descriptor Count Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Command Descriptor Count" group.long 0x94++0x3 line.long 0x00 "PKTE0_RDSC_DECR,PKTE0 Packet Engine Result Descriptor Count Decrement Registers" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Read Count Decrement" group.long 0x94++0x3 line.long 0x00 "PKTE0_RDSC_CNT,PKTE0 Packet Engine Result Descriptor Count Registers" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Result Descriptor Count" group.long 0x98++0x3 line.long 0x00 "PKTE0_RING_PTR,PKTE0 Packet Engine Ring Pointer Status" hexmask.long.word 0x00 16.--25. 1. " RDRPTR ,Result Descriptor Ring Write Pointer" hexmask.long.word 0x00 0.--9. 1. " CDRPTR ,Command Descriptor Ring Read Pointer" group.long 0x9C++0x3 line.long 0x00 "PKTE0_RING_STAT,PKTE0 Packet Engine Ring Status" bitfld.long 0x00 1. " RDRUNFL ,Result Descriptor Ring Underflow" "0,1" bitfld.long 0x00 0. " CDROVFL ,Command Descriptor Ring Overflow" "0,1" group.long 0x100++0x3 line.long 0x00 "PKTE0_CFG,PKTE0 Packet Engine Configuration Register" bitfld.long 0x00 18. " SWPDAT ,Swap Data" "0,1" bitfld.long 0x00 17. " SWPSA ,Swap SA" "0,1" bitfld.long 0x00 16. " SWPCDRD ,Swap CD RD" "0,1" newline bitfld.long 0x00 10. " ENCDRUPDT ,Enable CDR Update" "0,1" bitfld.long 0x00 8.--9. " MODE ,Packet Engine Mode" "0,1,2,3" bitfld.long 0x00 1. " RSTRING ,Reset Ring" "0,1" newline bitfld.long 0x00 0. " RSTPE ,Reset Packet Engine" "0,1" group.long 0x104++0x3 line.long 0x00 "PKTE0_STAT,PKTE0 Packet Engine Status Register" hexmask.long.word 0x00 22.--31. 1. " OBUFFULLCNT ,Output Buffer Full Count" hexmask.long.word 0x00 12.--21. 1. " IBUFEMPTYCNT ,Input Buffer Empty Count" bitfld.long 0x00 11. " OBUFREQ ,Output Buffer Request Active" "0,1" newline bitfld.long 0x00 10. " IBUFREQ ,Input Buffer Request Active" "0,1" bitfld.long 0x00 9. " OPDN ,Operation Done" "0,1" bitfld.long 0x00 8. " EXTERR ,Extended Error" "0,1" newline bitfld.long 0x00 7. " SNUMERR ,Sequence Number Error" "0,1" bitfld.long 0x00 6. " PADERR ,Pad Error" "0,1" bitfld.long 0x00 5. " AUTHERR ,Authentication Error" "0,1" newline bitfld.long 0x00 4. " OUTHSHDN ,Outer Hash Done" "0,1" bitfld.long 0x00 3. " INHSHDN ,Inner Hash Done" "0,1" bitfld.long 0x00 2. " ENCRYPTDN ,Encrypt Done" "0,1" newline bitfld.long 0x00 1. " OUTPTDN ,PE Output Done" "0,1" bitfld.long 0x00 0. " INPTDN ,Packet Engine Input Done" "0,1" group.long 0x10C++0x3 line.long 0x00 "PKTE0_BUF_THRESH,PKTE0 Packet Engine Buffer Threshold Register" hexmask.long.byte 0x00 16.--23. 1. " OUTBUF ,Output Buffer Threshold" hexmask.long.byte 0x00 0.--7. 1. " INBUF ,Input Buffer Threshold" group.long 0x110++0x3 line.long 0x00 "PKTE0_INBUF_CNT,PKTE0 Packet Engine Input Buffer Count Register" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Input Buffer Count" group.long 0x110++0x3 line.long 0x00 "PKTE0_INBUF_INCR,PKTE0 Packet Engine Input Buffer Count Increment Register" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Input Buffer Increment" group.long 0x114++0x3 line.long 0x00 "PKTE0_OUTBUF_DECR,PKTE0 Packet Engine Output Buffer Count Decrement Register" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Output Buffer Count Decrement" group.long 0x114++0x3 line.long 0x00 "PKTE0_OUTBUF_CNT,PKTE0 Packet Engine Output Buffer Count Register" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Output Buffer Count" group.long 0x118++0x3 line.long 0x00 "PKTE0_BUF_PTR,PKTE0 Packet Engine Buffer Pointer Register" hexmask.long.byte 0x00 16.--23. 1. " OUTBUF ,Output Buffer Pointer" hexmask.long.byte 0x00 0.--7. 1. " INBUF ,Input Buffer Pointer" group.long 0x120++0x3 line.long 0x00 "PKTE0_DMA_CFG,PKTE0 Packet Engine DMA Configuration Register" bitfld.long 0x00 20. " IDLE ,Idle Enable" "0,1" bitfld.long 0x00 19. " INCR ,Increment Enable" "0,1" bitfld.long 0x00 16. " MSTRBIGEND ,Master Big Endian" "0,1" newline bitfld.long 0x00 0.--3. " MXBRSTSZ ,Max Burst Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1D0++0x3 line.long 0x00 "PKTE0_ENDIAN_CFG,PKTE0 Packet Engine Endian Configuration Register" hexmask.long.byte 0x00 16.--23. 1. " TGTBSWP ,Target Byte Swap" hexmask.long.byte 0x00 0.--7. 1. " MSTRBSWP ,Master Byte Swap" group.long 0x1E0++0x3 line.long 0x00 "PKTE0_HLT_STAT,PKTE0 Packet Engine Halt Status Register" bitfld.long 0x00 24.--26. " DATSTATE ,Data State" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--23. " RDSASTATE ,Read SA State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " MNSTATE ,Main State" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. " WRRD ,Halt On Write Result Descriptor" "0,1" bitfld.long 0x00 4. " WRSA ,Halt On Write SA" "0,1" bitfld.long 0x00 3. " WRDAT ,Halt On Write Data" "0,1" newline bitfld.long 0x00 2. " RDSA ,Halt On Read SA" "0,1" bitfld.long 0x00 1. " RDCD ,Halt On Read Command Descriptor" "0,1" bitfld.long 0x00 0. " EN ,Halt Mode Enabled Status" "0,1" group.long 0x1E0++0x3 line.long 0x00 "PKTE0_HLT_CTL,PKTE0 Packet Engine Halt Control Register" bitfld.long 0x00 5. " WRRD ,Halt On Write Result Descriptor" "0,1" bitfld.long 0x00 4. " WRSA ,Halt On Write SA" "0,1" bitfld.long 0x00 3. " HWRDAT ,Halt On Write Data" "0,1" newline bitfld.long 0x00 2. " RDSA ,Halt On Read SA" "0,1" bitfld.long 0x00 1. " RDCD ,Halt On Read Command Descriptor" "0,1" bitfld.long 0x00 0. " EN ,Enable Halt Mode" "0,1" group.long 0x1E4++0x3 line.long 0x00 "PKTE0_CONT,PKTE0 PKTE Continue Register" group.long 0x1E8++0x3 line.long 0x00 "PKTE0_CLK_CTL,PKTE0 PE Clock Control Register" bitfld.long 0x00 4. " ENHSHCLK ,Enable Hash Clock" "0,1" bitfld.long 0x00 3. " ENARC4CLK ,Enable ARC4 Clock" "0,1" bitfld.long 0x00 2. " ENAESCLK ,Enable AES Clock" "0,1" newline bitfld.long 0x00 1. " ENDESCLK ,Enable DES Clock" "0,1" bitfld.long 0x00 0. " ENPECLK ,Enable Packet Engine Clock" "0,1" group.long 0x200++0x3 line.long 0x00 "PKTE0_IUMSK_STAT,PKTE0 Interrupt Unmasked Status Register" bitfld.long 0x00 18. " IFERR ,Interface Error" "0,1" bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "0,1" bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "0,1" newline bitfld.long 0x00 15. " HLT ,Halt" "0,1" bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "0,1" bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "0,1" newline bitfld.long 0x00 9. " OPDN ,Operation Done" "0,1" bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "0,1" bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "0,1" group.long 0x204++0x3 line.long 0x00 "PKTE0_IMSK_STAT,PKTE0 Interrupt Masked Status Register" bitfld.long 0x00 18. " IFERR ,Interface Error" "0,1" bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "0,1" bitfld.long 0x00 16. " RINGERR ,PE Ring Error" "0,1" newline bitfld.long 0x00 15. " HLT ,Halt" "0,1" bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "0,1" bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "0,1" newline bitfld.long 0x00 9. " OPDN ,Operation Done" "0,1" bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "0,1" bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "0,1" group.long 0x204++0x3 line.long 0x00 "PKTE0_INT_CLR,PKTE0 Interrupt Clear Register" bitfld.long 0x00 18. " IFERR ,Interface Error" "0,1" bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "0,1" bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "0,1" newline bitfld.long 0x00 15. " HLT ,Halt" "0,1" bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "0,1" bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "0,1" newline bitfld.long 0x00 9. " OPDN ,Operation Done" "0,1" bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "0,1" bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "0,1" group.long 0x208++0x3 line.long 0x00 "PKTE0_INT_EN,PKTE0 Interrupt Enable Register" bitfld.long 0x00 18. " IFERR ,Interface Error" "0,1" bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "0,1" bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "0,1" newline bitfld.long 0x00 15. " HLT ,Halt" "0,1" bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "0,1" bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "0,1" newline bitfld.long 0x00 9. " OPDN ,Operation Done" "0,1" bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "0,1" bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "0,1" group.long 0x20C++0x3 line.long 0x00 "PKTE0_INT_CFG,PKTE0 Interrupt Configuration Register" bitfld.long 0x00 1. " PULSECLR ,Clear After Pulse Interrupt" "0,1" bitfld.long 0x00 0. " TYPE ,Interrupt Type" "0,1" group.long 0x210++0x3 line.long 0x00 "PKTE0_IMSK_EN,PKTE0 Interrupt Mask Enable Register" bitfld.long 0x00 18. " IFERR ,Interface Error" "0,1" bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "0,1" bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "0,1" newline bitfld.long 0x00 15. " HLT ,Halt" "0,1" bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "0,1" bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "0,1" newline bitfld.long 0x00 9. " OPDN ,Operation Done" "0,1" bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "0,1" bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "0,1" group.long 0x214++0x3 line.long 0x00 "PKTE0_IMSK_DIS,PKTE0 Interrupt Mask Disable Register" bitfld.long 0x00 18. " IFERR ,Interface Error" "0,1" bitfld.long 0x00 17. " PROCERR ,PKTE Processing Error" "0,1" bitfld.long 0x00 16. " RINGERR ,PKTE Ring Error" "0,1" newline bitfld.long 0x00 15. " HLT ,Halt" "0,1" bitfld.long 0x00 11. " OBUFTHRSH ,Output Buffer Threshold" "0,1" bitfld.long 0x00 10. " IBUFTHRSH ,Input Buffer Threshold" "0,1" newline bitfld.long 0x00 9. " OPDN ,Operation Done" "0,1" bitfld.long 0x00 1. " RDRTHRSH ,RDR Threshold" "0,1" bitfld.long 0x00 0. " CDRTHRSH ,CDR Threshold" "0,1" group.long 0x400++0x3 line.long 0x00 "PKTE0_SA_CMD0,PKTE0 SA Command 0" bitfld.long 0x00 29. " SVHASH ,Save Hash" "0,1" bitfld.long 0x00 28. " SVIV ,Save IV" "0,1" bitfld.long 0x00 26.--27. " HASHSRC ,Hash Source" "0,1,2,3" newline bitfld.long 0x00 24.--25. " IVSRC ,IV Source" "0,1,2,3" bitfld.long 0x00 20.--23. " DIGESTLEN ,Digest Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 19. " HDRPROC ,Header Processing" "0,1" newline bitfld.long 0x00 18. " EXTPAD ,Extended Pad" "0,1" bitfld.long 0x00 17. " SCPAD ,Stream Cipher Padding" "0,1" bitfld.long 0x00 12.--15. " HASH ,Hash Algorithm Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. " CIPHER ,Cipher Algorithm Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. " PADTYPE ,Pad Type" "0,1,2,3" bitfld.long 0x00 4.--5. " OPGRP ,Operation Group" "0,1,2,3" newline bitfld.long 0x00 3. " DIR ,Direction" "0,1" bitfld.long 0x00 0.--2. " OPCD ,Operation Code" "0,1,2,3,4,5,6,7" group.long 0x404++0x3 line.long 0x00 "PKTE0_SA_CMD1,PKTE0 SA Command 1" bitfld.long 0x00 29. " ENSQNCHK ,Sequence Number Check Enable" "0,1" bitfld.long 0x00 24.--28. " ARC4KEYLEN ,ARC4 Key Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 28. " AESDECKEY ,AES Dec Key" "0,1" newline bitfld.long 0x00 24.--26. " AESKEYLEN ,AES Key Length" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. " HSHCOFFST ,Hash Crypt Offset" bitfld.long 0x00 13. " BYTEOFFST ,Byte Offset" "0,1" newline bitfld.long 0x00 12. " HMAC ,Keyed-Hash SSL Message Authentication Code" "0,1" bitfld.long 0x00 11. " SSLMAC ,Ssl Mac" "0,1" bitfld.long 0x00 8.--9. " CIPHERMD ,Cipher Mode" "0,1,2,3" newline bitfld.long 0x00 3. " CPYPAD ,Copy Pad" "0,1" bitfld.long 0x00 2. " CPYPAYLD ,Copy Payload" "0,1" bitfld.long 0x00 1. " CPYHDR ,Copy Header" "0,1" newline bitfld.long 0x00 0. " CPYDGST ,Copy Digest" "0,1" group.long 0x408++0x3 line.long 0x00 "PKTE0_SA_KEY0,PKTE0 SA Key Registers" group.long 0x40C++0x3 line.long 0x00 "PKTE0_SA_KEY1,PKTE0 SA Key Registers" group.long 0x410++0x3 line.long 0x00 "PKTE0_SA_KEY2,PKTE0 SA Key Registers" group.long 0x414++0x3 line.long 0x00 "PKTE0_SA_KEY3,PKTE0 SA Key Registers" group.long 0x418++0x3 line.long 0x00 "PKTE0_SA_KEY4,PKTE0 SA Key Registers" group.long 0x41C++0x3 line.long 0x00 "PKTE0_SA_KEY5,PKTE0 SA Key Registers" group.long 0x420++0x3 line.long 0x00 "PKTE0_SA_KEY6,PKTE0 SA Key Registers" group.long 0x424++0x3 line.long 0x00 "PKTE0_SA_KEY7,PKTE0 SA Key Registers" group.long 0x428++0x3 line.long 0x00 "PKTE0_SA_IDIGEST0,PKTE0 SA Inner Hash Digest Registers" group.long 0x42C++0x3 line.long 0x00 "PKTE0_SA_IDIGEST1,PKTE0 SA Inner Hash Digest Registers" group.long 0x430++0x3 line.long 0x00 "PKTE0_SA_IDIGEST2,PKTE0 SA Inner Hash Digest Registers" group.long 0x434++0x3 line.long 0x00 "PKTE0_SA_IDIGEST3,PKTE0 SA Inner Hash Digest Registers" group.long 0x438++0x3 line.long 0x00 "PKTE0_SA_IDIGEST4,PKTE0 SA Inner Hash Digest Registers" group.long 0x43C++0x3 line.long 0x00 "PKTE0_SA_IDIGEST5,PKTE0 SA Inner Hash Digest Registers" group.long 0x440++0x3 line.long 0x00 "PKTE0_SA_IDIGEST6,PKTE0 SA Inner Hash Digest Registers" group.long 0x444++0x3 line.long 0x00 "PKTE0_SA_IDIGEST7,PKTE0 SA Inner Hash Digest Registers" group.long 0x448++0x3 line.long 0x00 "PKTE0_SA_ODIGEST0,PKTE0 SA Outer Hash Digest Registers" group.long 0x44C++0x3 line.long 0x00 "PKTE0_SA_ODIGEST1,PKTE0 SA Outer Hash Digest Registers" group.long 0x450++0x3 line.long 0x00 "PKTE0_SA_ODIGEST2,PKTE0 SA Outer Hash Digest Registers" group.long 0x454++0x3 line.long 0x00 "PKTE0_SA_ODIGEST3,PKTE0 SA Outer Hash Digest Registers" group.long 0x458++0x3 line.long 0x00 "PKTE0_SA_ODIGEST4,PKTE0 SA Outer Hash Digest Registers" group.long 0x45C++0x3 line.long 0x00 "PKTE0_SA_ODIGEST5,PKTE0 SA Outer Hash Digest Registers" group.long 0x460++0x3 line.long 0x00 "PKTE0_SA_ODIGEST6,PKTE0 SA Outer Hash Digest Registers" group.long 0x464++0x3 line.long 0x00 "PKTE0_SA_ODIGEST7,PKTE0 SA Outer Hash Digest Registers" group.long 0x468++0x3 line.long 0x00 "PKTE0_SA_SPI,PKTE0 SA SPI Register" group.long 0x46C++0x3 line.long 0x00 "PKTE0_SA_SEQNUM0,PKTE0 SA Sequence Number Register" group.long 0x470++0x3 line.long 0x00 "PKTE0_SA_SEQNUM1,PKTE0 SA Sequence Number Register" group.long 0x474++0x3 line.long 0x00 "PKTE0_SA_SEQNUM_MSK0,PKTE0 SA Sequence Number Mask Registers" group.long 0x478++0x3 line.long 0x00 "PKTE0_SA_SEQNUM_MSK1,PKTE0 SA Sequence Number Mask Registers" group.long 0x47C++0x3 line.long 0x00 "PKTE0_SA_RDY,PKTE0 SA Ready Indicator" group.long 0x47C++0x3 line.long 0x00 "PKTE0_SA_ARC4IJPTR,PKTE0 ARC4 i and j Pointer Register" hexmask.long.byte 0x00 8.--15. 1. " JPTR ,J Pointer" hexmask.long.byte 0x00 0.--7. 1. " IPTR ,I Pointer" group.long 0x47C++0x3 line.long 0x00 "PKTE0_SA_NONCE,PKTE0 SA Initialization Vector Register" group.long 0x500++0x3 line.long 0x00 "PKTE0_STATE_IV0,PKTE0 State Initialization Vector Registers" group.long 0x504++0x3 line.long 0x00 "PKTE0_STATE_IV1,PKTE0 State Initialization Vector Registers" group.long 0x508++0x3 line.long 0x00 "PKTE0_STATE_IV2,PKTE0 State Initialization Vector Registers" group.long 0x50C++0x3 line.long 0x00 "PKTE0_STATE_IV3,PKTE0 State Initialization Vector Registers" group.long 0x510++0x3 line.long 0x00 "PKTE0_STATE_BYTE_CNT0,PKTE0 State Hash Byte Count Registers" group.long 0x514++0x3 line.long 0x00 "PKTE0_STATE_BYTE_CNT1,PKTE0 State Hash Byte Count Registers" group.long 0x518++0x3 line.long 0x00 "PKTE0_STATE_IDIGEST0,PKTE0 State Inner Digest Registers" group.long 0x51C++0x3 line.long 0x00 "PKTE0_STATE_IDIGEST1,PKTE0 State Inner Digest Registers" group.long 0x520++0x3 line.long 0x00 "PKTE0_STATE_IDIGEST2,PKTE0 State Inner Digest Registers" group.long 0x524++0x3 line.long 0x00 "PKTE0_STATE_IDIGEST3,PKTE0 State Inner Digest Registers" group.long 0x528++0x3 line.long 0x00 "PKTE0_STATE_IDIGEST4,PKTE0 State Inner Digest Registers" group.long 0x52C++0x3 line.long 0x00 "PKTE0_STATE_IDIGEST5,PKTE0 State Inner Digest Registers" group.long 0x530++0x3 line.long 0x00 "PKTE0_STATE_IDIGEST6,PKTE0 State Inner Digest Registers" group.long 0x534++0x3 line.long 0x00 "PKTE0_STATE_IDIGEST7,PKTE0 State Inner Digest Registers" group.long 0x700++0x3 line.long 0x00 "PKTE0_ARC4STATE_BUF,PKTE0 Starting Entry of 256-byte ARC4 State Buffer" group.long 0x800++0x3 line.long 0x00 "PKTE0_DATAIO_BUF,PKTE0 Starting Entry of 256-byte Data Input/Output Buffer" tree.end tree "PORT (General-Purpose Ports)" tree "PINT0" base ad:0x31005000 width 16. group.long 0x0++0x3 line.long 0x00 "PINT0_MSK_SET,PINT0 PINT Mask Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Unmask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Unmask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Unmask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Unmask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Unmask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Unmask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Unmask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Unmask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Unmask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Unmask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Unmask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Unmask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Unmask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Unmask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Unmask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Unmask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Unmask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Unmask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Unmask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Unmask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Unmask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Unmask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Unmask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Unmask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Unmask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Unmask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Unmask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Unmask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Unmask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Unmask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Unmask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Unmask" "0,1" group.long 0x4++0x3 line.long 0x00 "PINT0_MSK_CLR,PINT0 PINT Mask Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Mask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Mask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Mask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Mask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Mask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Mask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Mask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Mask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Mask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Mask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Mask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Mask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Mask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Mask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Mask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Mask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Mask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Mask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Mask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Mask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Mask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Mask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Mask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Mask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Mask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Mask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Mask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Mask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Mask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Mask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Mask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Mask" "0,1" group.long 0x8++0x3 line.long 0x00 "PINT0_REQ,PINT0 PINT Request Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Request" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Request" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Request" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Request" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Request" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Request" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Request" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Request" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Request" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Request" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Request" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Request" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Request" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Request" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Request" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Request" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Request" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Request" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Request" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Request" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Request" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Request" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Request" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Request" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Request" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Request" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Request" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Request" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Request" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Request" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Request" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Request" "0,1" group.long 0xC++0x3 line.long 0x00 "PINT0_ASSIGN,PINT0 PINT Assign Register" hexmask.long.byte 0x00 25.--31. 1. " B3MSB0 ,Bits [7:1] of B3MAP" bitfld.long 0x00 24. " B3MAP ,Byte 3 Mapping" "0,1" hexmask.long.byte 0x00 17.--23. 1. " B2MSB0 ,Bits [7:1] of B2MAP" newline bitfld.long 0x00 16. " B2MAP ,Byte 2 Mapping" "0,1" hexmask.long.byte 0x00 9.--15. 1. " B1MSB0 ,Bits [7:1] of B1MAP" bitfld.long 0x00 8. " B1MAP ,Byte 1 Mapping" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. " B0MSB0 ,Bits [7:1] of B0MAP" bitfld.long 0x00 0. " B0MAP ,Byte 0 Mapping" "0,1" group.long 0x10++0x3 line.long 0x00 "PINT0_EDGE_SET,PINT0 PINT Edge Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Edge" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Edge" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Edge" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Edge" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Edge" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Edge" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Edge" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Edge" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Edge" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Edge" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Edge" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Edge" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Edge" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Edge" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Edge" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Edge" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Edge" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Edge" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Edge" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Edge" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Edge" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Edge" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Edge" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Edge" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Edge" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Edge" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Edge" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Edge" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Edge" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Edge" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Edge" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Edge" "0,1" group.long 0x14++0x3 line.long 0x00 "PINT0_EDGE_CLR,PINT0 PINT Edge Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Level" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Level" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Level" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Level" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Level" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Level" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Level" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Level" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Level" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Level" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Level" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Level" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Level" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Level" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Level" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Level" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Level" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Level" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Level" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Level" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Level" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Level" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Level" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Level" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Level" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Level" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Level" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Level" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Level" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Level" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Level" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Level" "0,1" group.long 0x18++0x3 line.long 0x00 "PINT0_INV_SET,PINT0 PINT Invert Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Invert" "0,1" group.long 0x1C++0x3 line.long 0x00 "PINT0_INV_CLR,PINT0 PINT Invert Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 No Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 No Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 No Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 No Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 No Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 No Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 No Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 No Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 No Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 No Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 No Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 No Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 No Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 No Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 No Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 No Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 No Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 No Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 No Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 No Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 No Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 No Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 No Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 No Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 No Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 No Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 No Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 No Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 No Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 No Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 No Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 No Invert" "0,1" group.long 0x20++0x3 line.long 0x00 "PINT0_PINSTATE,PINT0 PINT Pin State Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 State" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 State" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 State" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 State" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 State" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 State" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 State" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 State" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 State" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 State" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 State" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 State" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 State" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 State" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 State" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 State" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 State" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 State" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 State" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 State" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 State" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 State" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 State" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 State" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 State" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 State" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 State" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 State" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 State" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 State" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 State" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 State" "0,1" group.long 0x24++0x3 line.long 0x00 "PINT0_LATCH,PINT0 PINT Latch Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Latch" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Latch" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Latch" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Latch" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Latch" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Latch" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Latch" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Latch" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Latch" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Latch" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Latch" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Latch" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Latch" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Latch" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Latch" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Latch" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Latch" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Latch" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Latch" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Latch" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Latch" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Latch" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Latch" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Latch" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Latch" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Latch" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Latch" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Latch" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Latch" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Latch" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Latch" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Latch" "0,1" tree.end tree "PINT1" base ad:0x31005100 width 16. group.long 0x0++0x3 line.long 0x00 "PINT1_MSK_SET,PINT1 PINT Mask Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Unmask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Unmask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Unmask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Unmask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Unmask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Unmask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Unmask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Unmask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Unmask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Unmask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Unmask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Unmask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Unmask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Unmask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Unmask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Unmask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Unmask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Unmask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Unmask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Unmask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Unmask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Unmask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Unmask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Unmask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Unmask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Unmask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Unmask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Unmask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Unmask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Unmask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Unmask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Unmask" "0,1" group.long 0x4++0x3 line.long 0x00 "PINT1_MSK_CLR,PINT1 PINT Mask Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Mask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Mask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Mask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Mask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Mask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Mask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Mask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Mask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Mask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Mask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Mask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Mask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Mask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Mask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Mask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Mask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Mask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Mask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Mask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Mask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Mask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Mask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Mask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Mask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Mask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Mask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Mask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Mask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Mask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Mask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Mask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Mask" "0,1" group.long 0x8++0x3 line.long 0x00 "PINT1_REQ,PINT1 PINT Request Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Request" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Request" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Request" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Request" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Request" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Request" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Request" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Request" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Request" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Request" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Request" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Request" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Request" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Request" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Request" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Request" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Request" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Request" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Request" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Request" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Request" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Request" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Request" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Request" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Request" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Request" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Request" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Request" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Request" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Request" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Request" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Request" "0,1" group.long 0xC++0x3 line.long 0x00 "PINT1_ASSIGN,PINT1 PINT Assign Register" hexmask.long.byte 0x00 25.--31. 1. " B3MSB0 ,Bits [7:1] of B3MAP" bitfld.long 0x00 24. " B3MAP ,Byte 3 Mapping" "0,1" hexmask.long.byte 0x00 17.--23. 1. " B2MSB0 ,Bits [7:1] of B2MAP" newline bitfld.long 0x00 16. " B2MAP ,Byte 2 Mapping" "0,1" hexmask.long.byte 0x00 9.--15. 1. " B1MSB0 ,Bits [7:1] of B1MAP" bitfld.long 0x00 8. " B1MAP ,Byte 1 Mapping" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. " B0MSB0 ,Bits [7:1] of B0MAP" bitfld.long 0x00 0. " B0MAP ,Byte 0 Mapping" "0,1" group.long 0x10++0x3 line.long 0x00 "PINT1_EDGE_SET,PINT1 PINT Edge Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Edge" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Edge" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Edge" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Edge" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Edge" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Edge" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Edge" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Edge" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Edge" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Edge" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Edge" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Edge" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Edge" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Edge" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Edge" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Edge" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Edge" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Edge" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Edge" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Edge" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Edge" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Edge" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Edge" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Edge" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Edge" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Edge" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Edge" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Edge" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Edge" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Edge" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Edge" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Edge" "0,1" group.long 0x14++0x3 line.long 0x00 "PINT1_EDGE_CLR,PINT1 PINT Edge Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Level" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Level" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Level" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Level" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Level" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Level" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Level" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Level" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Level" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Level" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Level" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Level" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Level" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Level" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Level" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Level" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Level" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Level" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Level" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Level" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Level" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Level" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Level" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Level" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Level" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Level" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Level" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Level" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Level" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Level" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Level" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Level" "0,1" group.long 0x18++0x3 line.long 0x00 "PINT1_INV_SET,PINT1 PINT Invert Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Invert" "0,1" group.long 0x1C++0x3 line.long 0x00 "PINT1_INV_CLR,PINT1 PINT Invert Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 No Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 No Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 No Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 No Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 No Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 No Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 No Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 No Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 No Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 No Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 No Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 No Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 No Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 No Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 No Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 No Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 No Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 No Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 No Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 No Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 No Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 No Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 No Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 No Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 No Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 No Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 No Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 No Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 No Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 No Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 No Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 No Invert" "0,1" group.long 0x20++0x3 line.long 0x00 "PINT1_PINSTATE,PINT1 PINT Pin State Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 State" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 State" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 State" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 State" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 State" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 State" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 State" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 State" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 State" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 State" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 State" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 State" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 State" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 State" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 State" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 State" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 State" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 State" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 State" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 State" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 State" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 State" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 State" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 State" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 State" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 State" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 State" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 State" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 State" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 State" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 State" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 State" "0,1" group.long 0x24++0x3 line.long 0x00 "PINT1_LATCH,PINT1 PINT Latch Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Latch" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Latch" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Latch" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Latch" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Latch" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Latch" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Latch" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Latch" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Latch" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Latch" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Latch" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Latch" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Latch" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Latch" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Latch" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Latch" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Latch" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Latch" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Latch" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Latch" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Latch" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Latch" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Latch" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Latch" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Latch" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Latch" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Latch" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Latch" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Latch" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Latch" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Latch" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Latch" "0,1" tree.end tree "PINT2" base ad:0x31005200 width 16. group.long 0x0++0x3 line.long 0x00 "PINT2_MSK_SET,PINT2 PINT Mask Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Unmask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Unmask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Unmask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Unmask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Unmask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Unmask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Unmask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Unmask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Unmask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Unmask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Unmask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Unmask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Unmask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Unmask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Unmask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Unmask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Unmask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Unmask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Unmask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Unmask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Unmask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Unmask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Unmask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Unmask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Unmask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Unmask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Unmask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Unmask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Unmask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Unmask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Unmask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Unmask" "0,1" group.long 0x4++0x3 line.long 0x00 "PINT2_MSK_CLR,PINT2 PINT Mask Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Mask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Mask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Mask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Mask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Mask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Mask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Mask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Mask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Mask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Mask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Mask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Mask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Mask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Mask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Mask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Mask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Mask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Mask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Mask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Mask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Mask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Mask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Mask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Mask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Mask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Mask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Mask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Mask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Mask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Mask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Mask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Mask" "0,1" group.long 0x8++0x3 line.long 0x00 "PINT2_REQ,PINT2 PINT Request Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Request" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Request" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Request" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Request" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Request" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Request" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Request" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Request" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Request" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Request" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Request" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Request" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Request" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Request" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Request" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Request" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Request" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Request" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Request" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Request" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Request" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Request" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Request" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Request" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Request" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Request" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Request" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Request" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Request" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Request" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Request" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Request" "0,1" group.long 0xC++0x3 line.long 0x00 "PINT2_ASSIGN,PINT2 PINT Assign Register" hexmask.long.byte 0x00 25.--31. 1. " B3MSB0 ,Bits [7:1] of B3MAP" bitfld.long 0x00 24. " B3MAP ,Byte 3 Mapping" "0,1" hexmask.long.byte 0x00 17.--23. 1. " B2MSB0 ,Bits [7:1] of B2MAP" newline bitfld.long 0x00 16. " B2MAP ,Byte 2 Mapping" "0,1" hexmask.long.byte 0x00 9.--15. 1. " B1MSB0 ,Bits [7:1] of B1MAP" bitfld.long 0x00 8. " B1MAP ,Byte 1 Mapping" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. " B0MSB0 ,Bits [7:1] of B0MAP" bitfld.long 0x00 0. " B0MAP ,Byte 0 Mapping" "0,1" group.long 0x10++0x3 line.long 0x00 "PINT2_EDGE_SET,PINT2 PINT Edge Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Edge" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Edge" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Edge" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Edge" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Edge" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Edge" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Edge" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Edge" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Edge" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Edge" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Edge" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Edge" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Edge" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Edge" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Edge" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Edge" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Edge" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Edge" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Edge" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Edge" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Edge" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Edge" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Edge" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Edge" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Edge" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Edge" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Edge" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Edge" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Edge" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Edge" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Edge" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Edge" "0,1" group.long 0x14++0x3 line.long 0x00 "PINT2_EDGE_CLR,PINT2 PINT Edge Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Level" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Level" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Level" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Level" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Level" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Level" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Level" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Level" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Level" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Level" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Level" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Level" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Level" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Level" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Level" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Level" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Level" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Level" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Level" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Level" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Level" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Level" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Level" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Level" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Level" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Level" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Level" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Level" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Level" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Level" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Level" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Level" "0,1" group.long 0x18++0x3 line.long 0x00 "PINT2_INV_SET,PINT2 PINT Invert Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Invert" "0,1" group.long 0x1C++0x3 line.long 0x00 "PINT2_INV_CLR,PINT2 PINT Invert Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 No Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 No Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 No Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 No Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 No Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 No Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 No Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 No Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 No Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 No Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 No Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 No Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 No Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 No Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 No Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 No Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 No Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 No Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 No Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 No Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 No Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 No Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 No Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 No Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 No Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 No Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 No Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 No Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 No Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 No Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 No Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 No Invert" "0,1" group.long 0x20++0x3 line.long 0x00 "PINT2_PINSTATE,PINT2 PINT Pin State Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 State" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 State" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 State" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 State" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 State" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 State" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 State" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 State" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 State" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 State" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 State" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 State" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 State" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 State" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 State" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 State" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 State" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 State" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 State" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 State" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 State" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 State" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 State" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 State" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 State" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 State" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 State" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 State" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 State" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 State" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 State" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 State" "0,1" group.long 0x24++0x3 line.long 0x00 "PINT2_LATCH,PINT2 PINT Latch Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Latch" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Latch" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Latch" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Latch" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Latch" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Latch" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Latch" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Latch" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Latch" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Latch" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Latch" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Latch" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Latch" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Latch" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Latch" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Latch" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Latch" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Latch" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Latch" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Latch" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Latch" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Latch" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Latch" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Latch" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Latch" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Latch" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Latch" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Latch" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Latch" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Latch" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Latch" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Latch" "0,1" tree.end tree "PINT3" base ad:0x31005300 width 16. group.long 0x0++0x3 line.long 0x00 "PINT3_MSK_SET,PINT3 PINT Mask Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Unmask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Unmask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Unmask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Unmask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Unmask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Unmask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Unmask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Unmask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Unmask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Unmask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Unmask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Unmask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Unmask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Unmask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Unmask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Unmask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Unmask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Unmask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Unmask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Unmask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Unmask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Unmask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Unmask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Unmask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Unmask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Unmask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Unmask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Unmask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Unmask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Unmask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Unmask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Unmask" "0,1" group.long 0x4++0x3 line.long 0x00 "PINT3_MSK_CLR,PINT3 PINT Mask Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Mask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Mask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Mask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Mask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Mask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Mask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Mask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Mask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Mask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Mask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Mask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Mask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Mask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Mask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Mask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Mask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Mask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Mask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Mask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Mask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Mask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Mask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Mask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Mask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Mask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Mask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Mask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Mask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Mask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Mask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Mask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Mask" "0,1" group.long 0x8++0x3 line.long 0x00 "PINT3_REQ,PINT3 PINT Request Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Request" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Request" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Request" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Request" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Request" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Request" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Request" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Request" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Request" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Request" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Request" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Request" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Request" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Request" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Request" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Request" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Request" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Request" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Request" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Request" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Request" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Request" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Request" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Request" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Request" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Request" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Request" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Request" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Request" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Request" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Request" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Request" "0,1" group.long 0xC++0x3 line.long 0x00 "PINT3_ASSIGN,PINT3 PINT Assign Register" hexmask.long.byte 0x00 25.--31. 1. " B3MSB0 ,Bits [7:1] of B3MAP" bitfld.long 0x00 24. " B3MAP ,Byte 3 Mapping" "0,1" hexmask.long.byte 0x00 17.--23. 1. " B2MSB0 ,Bits [7:1] of B2MAP" newline bitfld.long 0x00 16. " B2MAP ,Byte 2 Mapping" "0,1" hexmask.long.byte 0x00 9.--15. 1. " B1MSB0 ,Bits [7:1] of B1MAP" bitfld.long 0x00 8. " B1MAP ,Byte 1 Mapping" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. " B0MSB0 ,Bits [7:1] of B0MAP" bitfld.long 0x00 0. " B0MAP ,Byte 0 Mapping" "0,1" group.long 0x10++0x3 line.long 0x00 "PINT3_EDGE_SET,PINT3 PINT Edge Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Edge" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Edge" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Edge" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Edge" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Edge" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Edge" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Edge" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Edge" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Edge" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Edge" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Edge" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Edge" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Edge" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Edge" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Edge" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Edge" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Edge" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Edge" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Edge" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Edge" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Edge" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Edge" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Edge" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Edge" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Edge" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Edge" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Edge" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Edge" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Edge" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Edge" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Edge" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Edge" "0,1" group.long 0x14++0x3 line.long 0x00 "PINT3_EDGE_CLR,PINT3 PINT Edge Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Level" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Level" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Level" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Level" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Level" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Level" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Level" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Level" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Level" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Level" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Level" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Level" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Level" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Level" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Level" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Level" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Level" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Level" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Level" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Level" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Level" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Level" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Level" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Level" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Level" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Level" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Level" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Level" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Level" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Level" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Level" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Level" "0,1" group.long 0x18++0x3 line.long 0x00 "PINT3_INV_SET,PINT3 PINT Invert Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Invert" "0,1" group.long 0x1C++0x3 line.long 0x00 "PINT3_INV_CLR,PINT3 PINT Invert Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 No Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 No Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 No Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 No Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 No Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 No Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 No Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 No Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 No Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 No Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 No Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 No Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 No Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 No Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 No Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 No Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 No Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 No Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 No Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 No Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 No Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 No Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 No Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 No Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 No Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 No Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 No Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 No Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 No Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 No Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 No Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 No Invert" "0,1" group.long 0x20++0x3 line.long 0x00 "PINT3_PINSTATE,PINT3 PINT Pin State Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 State" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 State" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 State" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 State" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 State" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 State" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 State" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 State" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 State" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 State" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 State" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 State" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 State" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 State" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 State" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 State" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 State" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 State" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 State" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 State" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 State" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 State" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 State" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 State" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 State" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 State" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 State" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 State" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 State" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 State" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 State" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 State" "0,1" group.long 0x24++0x3 line.long 0x00 "PINT3_LATCH,PINT3 PINT Latch Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Latch" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Latch" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Latch" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Latch" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Latch" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Latch" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Latch" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Latch" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Latch" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Latch" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Latch" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Latch" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Latch" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Latch" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Latch" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Latch" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Latch" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Latch" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Latch" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Latch" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Latch" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Latch" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Latch" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Latch" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Latch" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Latch" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Latch" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Latch" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Latch" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Latch" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Latch" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Latch" "0,1" tree.end tree "PINT4" base ad:0x31005400 width 16. group.long 0x0++0x3 line.long 0x00 "PINT4_MSK_SET,PINT4 PINT Mask Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Unmask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Unmask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Unmask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Unmask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Unmask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Unmask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Unmask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Unmask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Unmask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Unmask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Unmask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Unmask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Unmask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Unmask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Unmask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Unmask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Unmask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Unmask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Unmask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Unmask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Unmask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Unmask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Unmask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Unmask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Unmask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Unmask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Unmask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Unmask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Unmask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Unmask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Unmask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Unmask" "0,1" group.long 0x4++0x3 line.long 0x00 "PINT4_MSK_CLR,PINT4 PINT Mask Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Mask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Mask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Mask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Mask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Mask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Mask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Mask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Mask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Mask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Mask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Mask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Mask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Mask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Mask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Mask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Mask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Mask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Mask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Mask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Mask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Mask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Mask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Mask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Mask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Mask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Mask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Mask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Mask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Mask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Mask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Mask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Mask" "0,1" group.long 0x8++0x3 line.long 0x00 "PINT4_REQ,PINT4 PINT Request Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Request" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Request" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Request" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Request" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Request" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Request" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Request" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Request" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Request" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Request" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Request" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Request" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Request" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Request" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Request" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Request" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Request" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Request" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Request" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Request" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Request" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Request" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Request" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Request" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Request" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Request" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Request" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Request" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Request" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Request" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Request" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Request" "0,1" group.long 0xC++0x3 line.long 0x00 "PINT4_ASSIGN,PINT4 PINT Assign Register" hexmask.long.byte 0x00 25.--31. 1. " B3MSB0 ,Bits [7:1] of B3MAP" bitfld.long 0x00 24. " B3MAP ,Byte 3 Mapping" "0,1" hexmask.long.byte 0x00 17.--23. 1. " B2MSB0 ,Bits [7:1] of B2MAP" newline bitfld.long 0x00 16. " B2MAP ,Byte 2 Mapping" "0,1" hexmask.long.byte 0x00 9.--15. 1. " B1MSB0 ,Bits [7:1] of B1MAP" bitfld.long 0x00 8. " B1MAP ,Byte 1 Mapping" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. " B0MSB0 ,Bits [7:1] of B0MAP" bitfld.long 0x00 0. " B0MAP ,Byte 0 Mapping" "0,1" group.long 0x10++0x3 line.long 0x00 "PINT4_EDGE_SET,PINT4 PINT Edge Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Edge" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Edge" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Edge" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Edge" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Edge" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Edge" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Edge" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Edge" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Edge" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Edge" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Edge" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Edge" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Edge" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Edge" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Edge" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Edge" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Edge" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Edge" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Edge" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Edge" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Edge" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Edge" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Edge" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Edge" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Edge" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Edge" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Edge" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Edge" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Edge" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Edge" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Edge" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Edge" "0,1" group.long 0x14++0x3 line.long 0x00 "PINT4_EDGE_CLR,PINT4 PINT Edge Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Level" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Level" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Level" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Level" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Level" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Level" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Level" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Level" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Level" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Level" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Level" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Level" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Level" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Level" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Level" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Level" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Level" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Level" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Level" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Level" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Level" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Level" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Level" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Level" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Level" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Level" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Level" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Level" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Level" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Level" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Level" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Level" "0,1" group.long 0x18++0x3 line.long 0x00 "PINT4_INV_SET,PINT4 PINT Invert Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Invert" "0,1" group.long 0x1C++0x3 line.long 0x00 "PINT4_INV_CLR,PINT4 PINT Invert Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 No Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 No Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 No Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 No Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 No Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 No Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 No Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 No Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 No Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 No Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 No Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 No Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 No Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 No Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 No Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 No Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 No Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 No Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 No Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 No Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 No Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 No Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 No Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 No Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 No Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 No Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 No Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 No Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 No Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 No Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 No Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 No Invert" "0,1" group.long 0x20++0x3 line.long 0x00 "PINT4_PINSTATE,PINT4 PINT Pin State Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 State" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 State" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 State" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 State" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 State" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 State" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 State" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 State" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 State" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 State" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 State" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 State" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 State" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 State" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 State" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 State" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 State" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 State" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 State" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 State" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 State" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 State" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 State" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 State" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 State" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 State" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 State" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 State" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 State" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 State" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 State" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 State" "0,1" group.long 0x24++0x3 line.long 0x00 "PINT4_LATCH,PINT4 PINT Latch Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Latch" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Latch" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Latch" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Latch" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Latch" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Latch" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Latch" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Latch" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Latch" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Latch" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Latch" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Latch" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Latch" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Latch" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Latch" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Latch" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Latch" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Latch" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Latch" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Latch" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Latch" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Latch" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Latch" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Latch" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Latch" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Latch" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Latch" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Latch" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Latch" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Latch" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Latch" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Latch" "0,1" tree.end tree "PINT5" base ad:0x31005500 width 16. group.long 0x0++0x3 line.long 0x00 "PINT5_MSK_SET,PINT5 PINT Mask Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Unmask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Unmask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Unmask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Unmask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Unmask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Unmask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Unmask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Unmask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Unmask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Unmask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Unmask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Unmask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Unmask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Unmask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Unmask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Unmask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Unmask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Unmask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Unmask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Unmask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Unmask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Unmask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Unmask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Unmask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Unmask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Unmask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Unmask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Unmask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Unmask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Unmask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Unmask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Unmask" "0,1" group.long 0x4++0x3 line.long 0x00 "PINT5_MSK_CLR,PINT5 PINT Mask Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Mask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Mask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Mask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Mask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Mask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Mask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Mask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Mask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Mask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Mask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Mask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Mask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Mask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Mask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Mask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Mask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Mask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Mask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Mask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Mask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Mask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Mask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Mask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Mask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Mask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Mask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Mask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Mask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Mask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Mask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Mask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Mask" "0,1" group.long 0x8++0x3 line.long 0x00 "PINT5_REQ,PINT5 PINT Request Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Request" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Request" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Request" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Request" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Request" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Request" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Request" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Request" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Request" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Request" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Request" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Request" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Request" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Request" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Request" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Request" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Request" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Request" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Request" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Request" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Request" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Request" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Request" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Request" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Request" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Request" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Request" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Request" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Request" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Request" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Request" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Request" "0,1" group.long 0xC++0x3 line.long 0x00 "PINT5_ASSIGN,PINT5 PINT Assign Register" hexmask.long.byte 0x00 25.--31. 1. " B3MSB0 ,Bits [7:1] of B3MAP" bitfld.long 0x00 24. " B3MAP ,Byte 3 Mapping" "0,1" hexmask.long.byte 0x00 17.--23. 1. " B2MSB0 ,Bits [7:1] of B2MAP" newline bitfld.long 0x00 16. " B2MAP ,Byte 2 Mapping" "0,1" hexmask.long.byte 0x00 9.--15. 1. " B1MSB0 ,Bits [7:1] of B1MAP" bitfld.long 0x00 8. " B1MAP ,Byte 1 Mapping" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. " B0MSB0 ,Bits [7:1] of B0MAP" bitfld.long 0x00 0. " B0MAP ,Byte 0 Mapping" "0,1" group.long 0x10++0x3 line.long 0x00 "PINT5_EDGE_SET,PINT5 PINT Edge Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Edge" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Edge" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Edge" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Edge" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Edge" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Edge" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Edge" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Edge" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Edge" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Edge" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Edge" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Edge" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Edge" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Edge" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Edge" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Edge" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Edge" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Edge" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Edge" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Edge" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Edge" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Edge" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Edge" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Edge" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Edge" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Edge" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Edge" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Edge" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Edge" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Edge" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Edge" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Edge" "0,1" group.long 0x14++0x3 line.long 0x00 "PINT5_EDGE_CLR,PINT5 PINT Edge Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Level" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Level" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Level" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Level" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Level" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Level" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Level" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Level" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Level" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Level" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Level" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Level" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Level" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Level" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Level" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Level" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Level" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Level" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Level" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Level" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Level" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Level" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Level" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Level" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Level" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Level" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Level" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Level" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Level" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Level" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Level" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Level" "0,1" group.long 0x18++0x3 line.long 0x00 "PINT5_INV_SET,PINT5 PINT Invert Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Invert" "0,1" group.long 0x1C++0x3 line.long 0x00 "PINT5_INV_CLR,PINT5 PINT Invert Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 No Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 No Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 No Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 No Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 No Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 No Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 No Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 No Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 No Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 No Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 No Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 No Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 No Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 No Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 No Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 No Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 No Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 No Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 No Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 No Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 No Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 No Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 No Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 No Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 No Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 No Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 No Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 No Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 No Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 No Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 No Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 No Invert" "0,1" group.long 0x20++0x3 line.long 0x00 "PINT5_PINSTATE,PINT5 PINT Pin State Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 State" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 State" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 State" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 State" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 State" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 State" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 State" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 State" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 State" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 State" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 State" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 State" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 State" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 State" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 State" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 State" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 State" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 State" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 State" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 State" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 State" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 State" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 State" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 State" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 State" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 State" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 State" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 State" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 State" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 State" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 State" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 State" "0,1" group.long 0x24++0x3 line.long 0x00 "PINT5_LATCH,PINT5 PINT Latch Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Latch" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Latch" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Latch" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Latch" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Latch" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Latch" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Latch" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Latch" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Latch" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Latch" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Latch" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Latch" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Latch" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Latch" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Latch" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Latch" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Latch" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Latch" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Latch" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Latch" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Latch" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Latch" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Latch" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Latch" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Latch" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Latch" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Latch" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Latch" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Latch" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Latch" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Latch" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Latch" "0,1" tree.end tree "PINT6" base ad:0x31005600 width 16. group.long 0x0++0x3 line.long 0x00 "PINT6_MSK_SET,PINT6 PINT Mask Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Unmask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Unmask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Unmask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Unmask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Unmask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Unmask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Unmask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Unmask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Unmask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Unmask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Unmask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Unmask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Unmask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Unmask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Unmask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Unmask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Unmask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Unmask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Unmask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Unmask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Unmask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Unmask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Unmask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Unmask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Unmask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Unmask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Unmask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Unmask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Unmask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Unmask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Unmask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Unmask" "0,1" group.long 0x4++0x3 line.long 0x00 "PINT6_MSK_CLR,PINT6 PINT Mask Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Mask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Mask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Mask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Mask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Mask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Mask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Mask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Mask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Mask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Mask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Mask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Mask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Mask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Mask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Mask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Mask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Mask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Mask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Mask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Mask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Mask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Mask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Mask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Mask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Mask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Mask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Mask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Mask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Mask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Mask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Mask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Mask" "0,1" group.long 0x8++0x3 line.long 0x00 "PINT6_REQ,PINT6 PINT Request Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Request" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Request" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Request" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Request" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Request" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Request" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Request" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Request" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Request" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Request" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Request" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Request" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Request" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Request" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Request" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Request" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Request" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Request" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Request" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Request" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Request" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Request" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Request" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Request" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Request" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Request" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Request" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Request" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Request" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Request" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Request" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Request" "0,1" group.long 0xC++0x3 line.long 0x00 "PINT6_ASSIGN,PINT6 PINT Assign Register" hexmask.long.byte 0x00 25.--31. 1. " B3MSB0 ,Bits [7:1] of B3MAP" bitfld.long 0x00 24. " B3MAP ,Byte 3 Mapping" "0,1" hexmask.long.byte 0x00 17.--23. 1. " B2MSB0 ,Bits [7:1] of B2MAP" newline bitfld.long 0x00 16. " B2MAP ,Byte 2 Mapping" "0,1" hexmask.long.byte 0x00 9.--15. 1. " B1MSB0 ,Bits [7:1] of B1MAP" bitfld.long 0x00 8. " B1MAP ,Byte 1 Mapping" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. " B0MSB0 ,Bits [7:1] of B0MAP" bitfld.long 0x00 0. " B0MAP ,Byte 0 Mapping" "0,1" group.long 0x10++0x3 line.long 0x00 "PINT6_EDGE_SET,PINT6 PINT Edge Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Edge" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Edge" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Edge" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Edge" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Edge" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Edge" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Edge" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Edge" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Edge" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Edge" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Edge" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Edge" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Edge" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Edge" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Edge" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Edge" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Edge" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Edge" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Edge" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Edge" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Edge" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Edge" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Edge" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Edge" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Edge" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Edge" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Edge" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Edge" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Edge" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Edge" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Edge" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Edge" "0,1" group.long 0x14++0x3 line.long 0x00 "PINT6_EDGE_CLR,PINT6 PINT Edge Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Level" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Level" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Level" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Level" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Level" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Level" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Level" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Level" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Level" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Level" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Level" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Level" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Level" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Level" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Level" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Level" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Level" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Level" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Level" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Level" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Level" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Level" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Level" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Level" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Level" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Level" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Level" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Level" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Level" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Level" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Level" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Level" "0,1" group.long 0x18++0x3 line.long 0x00 "PINT6_INV_SET,PINT6 PINT Invert Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Invert" "0,1" group.long 0x1C++0x3 line.long 0x00 "PINT6_INV_CLR,PINT6 PINT Invert Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 No Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 No Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 No Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 No Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 No Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 No Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 No Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 No Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 No Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 No Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 No Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 No Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 No Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 No Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 No Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 No Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 No Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 No Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 No Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 No Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 No Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 No Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 No Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 No Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 No Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 No Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 No Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 No Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 No Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 No Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 No Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 No Invert" "0,1" group.long 0x20++0x3 line.long 0x00 "PINT6_PINSTATE,PINT6 PINT Pin State Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 State" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 State" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 State" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 State" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 State" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 State" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 State" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 State" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 State" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 State" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 State" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 State" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 State" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 State" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 State" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 State" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 State" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 State" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 State" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 State" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 State" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 State" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 State" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 State" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 State" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 State" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 State" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 State" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 State" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 State" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 State" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 State" "0,1" group.long 0x24++0x3 line.long 0x00 "PINT6_LATCH,PINT6 PINT Latch Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Latch" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Latch" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Latch" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Latch" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Latch" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Latch" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Latch" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Latch" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Latch" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Latch" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Latch" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Latch" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Latch" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Latch" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Latch" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Latch" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Latch" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Latch" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Latch" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Latch" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Latch" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Latch" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Latch" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Latch" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Latch" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Latch" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Latch" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Latch" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Latch" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Latch" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Latch" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Latch" "0,1" tree.end tree "PINT7" base ad:0x31005700 width 16. group.long 0x0++0x3 line.long 0x00 "PINT7_MSK_SET,PINT7 PINT Mask Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Unmask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Unmask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Unmask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Unmask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Unmask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Unmask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Unmask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Unmask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Unmask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Unmask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Unmask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Unmask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Unmask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Unmask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Unmask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Unmask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Unmask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Unmask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Unmask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Unmask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Unmask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Unmask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Unmask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Unmask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Unmask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Unmask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Unmask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Unmask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Unmask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Unmask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Unmask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Unmask" "0,1" group.long 0x4++0x3 line.long 0x00 "PINT7_MSK_CLR,PINT7 PINT Mask Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Mask" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Mask" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Mask" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Mask" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Mask" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Mask" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Mask" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Mask" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Mask" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Mask" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Mask" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Mask" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Mask" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Mask" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Mask" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Mask" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Mask" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Mask" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Mask" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Mask" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Mask" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Mask" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Mask" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Mask" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Mask" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Mask" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Mask" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Mask" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Mask" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Mask" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Mask" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Mask" "0,1" group.long 0x8++0x3 line.long 0x00 "PINT7_REQ,PINT7 PINT Request Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Request" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Request" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Request" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Request" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Request" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Request" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Request" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Request" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Request" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Request" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Request" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Request" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Request" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Request" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Request" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Request" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Request" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Request" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Request" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Request" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Request" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Request" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Request" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Request" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Request" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Request" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Request" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Request" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Request" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Request" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Request" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Request" "0,1" group.long 0xC++0x3 line.long 0x00 "PINT7_ASSIGN,PINT7 PINT Assign Register" hexmask.long.byte 0x00 25.--31. 1. " B3MSB0 ,Bits [7:1] of B3MAP" bitfld.long 0x00 24. " B3MAP ,Byte 3 Mapping" "0,1" hexmask.long.byte 0x00 17.--23. 1. " B2MSB0 ,Bits [7:1] of B2MAP" newline bitfld.long 0x00 16. " B2MAP ,Byte 2 Mapping" "0,1" hexmask.long.byte 0x00 9.--15. 1. " B1MSB0 ,Bits [7:1] of B1MAP" bitfld.long 0x00 8. " B1MAP ,Byte 1 Mapping" "0,1" newline hexmask.long.byte 0x00 1.--7. 1. " B0MSB0 ,Bits [7:1] of B0MAP" bitfld.long 0x00 0. " B0MAP ,Byte 0 Mapping" "0,1" group.long 0x10++0x3 line.long 0x00 "PINT7_EDGE_SET,PINT7 PINT Edge Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Edge" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Edge" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Edge" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Edge" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Edge" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Edge" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Edge" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Edge" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Edge" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Edge" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Edge" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Edge" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Edge" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Edge" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Edge" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Edge" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Edge" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Edge" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Edge" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Edge" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Edge" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Edge" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Edge" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Edge" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Edge" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Edge" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Edge" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Edge" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Edge" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Edge" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Edge" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Edge" "0,1" group.long 0x14++0x3 line.long 0x00 "PINT7_EDGE_CLR,PINT7 PINT Edge Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Level" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Level" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Level" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Level" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Level" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Level" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Level" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Level" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Level" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Level" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Level" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Level" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Level" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Level" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Level" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Level" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Level" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Level" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Level" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Level" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Level" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Level" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Level" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Level" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Level" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Level" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Level" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Level" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Level" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Level" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Level" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Level" "0,1" group.long 0x18++0x3 line.long 0x00 "PINT7_INV_SET,PINT7 PINT Invert Set Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Invert" "0,1" group.long 0x1C++0x3 line.long 0x00 "PINT7_INV_CLR,PINT7 PINT Invert Clear Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 No Invert" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 No Invert" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 No Invert" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 No Invert" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 No Invert" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 No Invert" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 No Invert" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 No Invert" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 No Invert" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 No Invert" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 No Invert" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 No Invert" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 No Invert" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 No Invert" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 No Invert" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 No Invert" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 No Invert" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 No Invert" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 No Invert" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 No Invert" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 No Invert" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 No Invert" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 No Invert" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 No Invert" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 No Invert" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 No Invert" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 No Invert" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 No Invert" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 No Invert" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 No Invert" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 No Invert" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 No Invert" "0,1" group.long 0x20++0x3 line.long 0x00 "PINT7_PINSTATE,PINT7 PINT Pin State Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 State" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 State" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 State" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 State" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 State" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 State" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 State" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 State" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 State" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 State" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 State" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 State" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 State" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 State" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 State" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 State" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 State" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 State" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 State" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 State" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 State" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 State" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 State" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 State" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 State" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 State" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 State" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 State" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 State" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 State" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 State" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 State" "0,1" group.long 0x24++0x3 line.long 0x00 "PINT7_LATCH,PINT7 PINT Latch Register" bitfld.long 0x00 31. " PIQ31 ,Pin Interrupt 31 Latch" "0,1" bitfld.long 0x00 30. " PIQ30 ,Pin Interrupt 30 Latch" "0,1" bitfld.long 0x00 29. " PIQ29 ,Pin Interrupt 29 Latch" "0,1" newline bitfld.long 0x00 28. " PIQ28 ,Pin Interrupt 28 Latch" "0,1" bitfld.long 0x00 27. " PIQ27 ,Pin Interrupt 27 Latch" "0,1" bitfld.long 0x00 26. " PIQ26 ,Pin Interrupt 26 Latch" "0,1" newline bitfld.long 0x00 25. " PIQ25 ,Pin Interrupt 25 Latch" "0,1" bitfld.long 0x00 24. " PIQ24 ,Pin Interrupt 24 Latch" "0,1" bitfld.long 0x00 23. " PIQ23 ,Pin Interrupt 23 Latch" "0,1" newline bitfld.long 0x00 22. " PIQ22 ,Pin Interrupt 22 Latch" "0,1" bitfld.long 0x00 21. " PIQ21 ,Pin Interrupt 21 Latch" "0,1" bitfld.long 0x00 20. " PIQ20 ,Pin Interrupt 20 Latch" "0,1" newline bitfld.long 0x00 19. " PIQ19 ,Pin Interrupt 19 Latch" "0,1" bitfld.long 0x00 18. " PIQ18 ,Pin Interrupt 18 Latch" "0,1" bitfld.long 0x00 17. " PIQ17 ,Pin Interrupt 17 Latch" "0,1" newline bitfld.long 0x00 16. " PIQ16 ,Pin Interrupt 16 Latch" "0,1" bitfld.long 0x00 15. " PIQ15 ,Pin Interrupt 15 Latch" "0,1" bitfld.long 0x00 14. " PIQ14 ,Pin Interrupt 14 Latch" "0,1" newline bitfld.long 0x00 13. " PIQ13 ,Pin Interrupt 13 Latch" "0,1" bitfld.long 0x00 12. " PIQ12 ,Pin Interrupt 12 Latch" "0,1" bitfld.long 0x00 11. " PIQ11 ,Pin Interrupt 11 Latch" "0,1" newline bitfld.long 0x00 10. " PIQ10 ,Pin Interrupt 10 Latch" "0,1" bitfld.long 0x00 9. " PIQ9 ,Pin Interrupt 9 Latch" "0,1" bitfld.long 0x00 8. " PIQ8 ,Pin Interrupt 8 Latch" "0,1" newline bitfld.long 0x00 7. " PIQ7 ,Pin Interrupt 7 Latch" "0,1" bitfld.long 0x00 6. " PIQ6 ,Pin Interrupt 6 Latch" "0,1" bitfld.long 0x00 5. " PIQ5 ,Pin Interrupt 5 Latch" "0,1" newline bitfld.long 0x00 4. " PIQ4 ,Pin Interrupt 4 Latch" "0,1" bitfld.long 0x00 3. " PIQ3 ,Pin Interrupt 3 Latch" "0,1" bitfld.long 0x00 2. " PIQ2 ,Pin Interrupt 2 Latch" "0,1" newline bitfld.long 0x00 1. " PIQ1 ,Pin Interrupt 1 Latch" "0,1" bitfld.long 0x00 0. " PIQ0 ,Pin Interrupt 0 Latch" "0,1" tree.end tree "PORTA" base ad:0x31004000 width 16. group.long 0x0++0x3 line.long 0x00 "PORTA_FER,PORTA Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTA_FER_SET,PORTA Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTA_FER_CLR,PORTA Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTA_DATA,PORTA Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTA_DATA_SET,PORTA Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTA_DATA_CLR,PORTA Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTA_DIR,PORTA Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTA_DIR_SET,PORTA Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTA_DIR_CLR,PORTA Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTA_INEN,PORTA Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTA_INEN_SET,PORTA Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTA_INEN_CLR,PORTA Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTA_MUX,PORTA Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTA_DATA_TGL,PORTA Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTA_POL,PORTA Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTA_POL_SET,PORTA Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTA_POL_CLR,PORTA Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTA_LOCK,PORTA Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTA_TRIG_TGL,PORTA Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree "PORTB" base ad:0x31004080 width 16. group.long 0x0++0x3 line.long 0x00 "PORTB_FER,PORTB Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTB_FER_SET,PORTB Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTB_FER_CLR,PORTB Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTB_DATA,PORTB Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTB_DATA_SET,PORTB Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTB_DATA_CLR,PORTB Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTB_DIR,PORTB Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTB_DIR_SET,PORTB Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTB_DIR_CLR,PORTB Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTB_INEN,PORTB Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTB_INEN_SET,PORTB Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTB_INEN_CLR,PORTB Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTB_MUX,PORTB Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTB_DATA_TGL,PORTB Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTB_POL,PORTB Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTB_POL_SET,PORTB Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTB_POL_CLR,PORTB Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTB_LOCK,PORTB Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTB_TRIG_TGL,PORTB Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree "PORTC" base ad:0x31004100 width 16. group.long 0x0++0x3 line.long 0x00 "PORTC_FER,PORTC Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTC_FER_SET,PORTC Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTC_FER_CLR,PORTC Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTC_DATA,PORTC Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTC_DATA_SET,PORTC Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTC_DATA_CLR,PORTC Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTC_DIR,PORTC Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTC_DIR_SET,PORTC Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTC_DIR_CLR,PORTC Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTC_INEN,PORTC Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTC_INEN_SET,PORTC Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTC_INEN_CLR,PORTC Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTC_MUX,PORTC Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTC_DATA_TGL,PORTC Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTC_POL,PORTC Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTC_POL_SET,PORTC Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTC_POL_CLR,PORTC Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTC_LOCK,PORTC Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTC_TRIG_TGL,PORTC Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree "PORTD" base ad:0x31004180 width 16. group.long 0x0++0x3 line.long 0x00 "PORTD_FER,PORTD Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTD_FER_SET,PORTD Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTD_FER_CLR,PORTD Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTD_DATA,PORTD Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTD_DATA_SET,PORTD Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTD_DATA_CLR,PORTD Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTD_DIR,PORTD Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTD_DIR_SET,PORTD Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTD_DIR_CLR,PORTD Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTD_INEN,PORTD Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTD_INEN_SET,PORTD Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTD_INEN_CLR,PORTD Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTD_MUX,PORTD Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTD_DATA_TGL,PORTD Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTD_POL,PORTD Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTD_POL_SET,PORTD Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTD_POL_CLR,PORTD Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTD_LOCK,PORTD Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTD_TRIG_TGL,PORTD Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree "PORTE" base ad:0x31004200 width 16. group.long 0x0++0x3 line.long 0x00 "PORTE_FER,PORTE Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTE_FER_SET,PORTE Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTE_FER_CLR,PORTE Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTE_DATA,PORTE Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTE_DATA_SET,PORTE Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTE_DATA_CLR,PORTE Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTE_DIR,PORTE Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTE_DIR_SET,PORTE Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTE_DIR_CLR,PORTE Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTE_INEN,PORTE Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTE_INEN_SET,PORTE Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTE_INEN_CLR,PORTE Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTE_MUX,PORTE Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTE_DATA_TGL,PORTE Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTE_POL,PORTE Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTE_POL_SET,PORTE Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTE_POL_CLR,PORTE Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTE_LOCK,PORTE Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTE_TRIG_TGL,PORTE Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree "PORTF" base ad:0x31004280 width 16. group.long 0x0++0x3 line.long 0x00 "PORTF_FER,PORTF Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTF_FER_SET,PORTF Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTF_FER_CLR,PORTF Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTF_DATA,PORTF Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTF_DATA_SET,PORTF Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTF_DATA_CLR,PORTF Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTF_DIR,PORTF Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTF_DIR_SET,PORTF Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTF_DIR_CLR,PORTF Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTF_INEN,PORTF Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTF_INEN_SET,PORTF Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTF_INEN_CLR,PORTF Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTF_MUX,PORTF Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTF_DATA_TGL,PORTF Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTF_POL,PORTF Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTF_POL_SET,PORTF Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTF_POL_CLR,PORTF Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTF_LOCK,PORTF Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTF_TRIG_TGL,PORTF Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree "PORTG" base ad:0x31004300 width 16. group.long 0x0++0x3 line.long 0x00 "PORTG_FER,PORTG Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTG_FER_SET,PORTG Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTG_FER_CLR,PORTG Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTG_DATA,PORTG Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTG_DATA_SET,PORTG Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTG_DATA_CLR,PORTG Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTG_DIR,PORTG Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTG_DIR_SET,PORTG Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTG_DIR_CLR,PORTG Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTG_INEN,PORTG Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTG_INEN_SET,PORTG Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTG_INEN_CLR,PORTG Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTG_MUX,PORTG Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTG_DATA_TGL,PORTG Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTG_POL,PORTG Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTG_POL_SET,PORTG Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTG_POL_CLR,PORTG Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTG_LOCK,PORTG Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTG_TRIG_TGL,PORTG Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree "PORTH" base ad:0x31004380 width 16. group.long 0x0++0x3 line.long 0x00 "PORTH_FER,PORTH Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTH_FER_SET,PORTH Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTH_FER_CLR,PORTH Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTH_DATA,PORTH Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTH_DATA_SET,PORTH Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTH_DATA_CLR,PORTH Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTH_DIR,PORTH Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTH_DIR_SET,PORTH Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTH_DIR_CLR,PORTH Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTH_INEN,PORTH Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTH_INEN_SET,PORTH Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTH_INEN_CLR,PORTH Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTH_MUX,PORTH Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTH_DATA_TGL,PORTH Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTH_POL,PORTH Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTH_POL_SET,PORTH Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTH_POL_CLR,PORTH Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTH_LOCK,PORTH Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTH_TRIG_TGL,PORTH Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree "PORTI" base ad:0x31004400 width 16. group.long 0x0++0x3 line.long 0x00 "PORTI_FER,PORTI Port x Function Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode" "0,1" group.long 0x4++0x3 line.long 0x00 "PORTI_FER_SET,PORTI Port x Function Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Set" "0,1" group.long 0x8++0x3 line.long 0x00 "PORTI_FER_CLR,PORTI Port x Function Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Mode Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Mode Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Mode Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Mode Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Mode Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Mode Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Mode Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Mode Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Mode Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Mode Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Mode Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Mode Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Mode Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Mode Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Mode Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Mode Clear" "0,1" group.long 0xC++0x3 line.long 0x00 "PORTI_DATA,PORTI Port x GPIO Data Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data" "0,1" group.long 0x10++0x3 line.long 0x00 "PORTI_DATA_SET,PORTI Port x GPIO Data Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Set" "0,1" group.long 0x14++0x3 line.long 0x00 "PORTI_DATA_CLR,PORTI Port x GPIO Data Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Data Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Data Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Data Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Data Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Data Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Data Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Data Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Data Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Data Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Data Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Data Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Data Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Data Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Data Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Data Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Data Clear" "0,1" group.long 0x18++0x3 line.long 0x00 "PORTI_DIR,PORTI Port x GPIO Direction Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction" "0,1" group.long 0x1C++0x3 line.long 0x00 "PORTI_DIR_SET,PORTI Port x GPIO Direction Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Set" "0,1" group.long 0x20++0x3 line.long 0x00 "PORTI_DIR_CLR,PORTI Port x GPIO Direction Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Direction Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Direction Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Direction Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Direction Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Direction Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Direction Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Direction Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Direction Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Direction Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Direction Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Direction Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Direction Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Direction Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Direction Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Direction Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Direction Clear" "0,1" group.long 0x24++0x3 line.long 0x00 "PORTI_INEN,PORTI Port x GPIO Input Enable Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "PORTI_INEN_SET,PORTI Port x GPIO Input Enable Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Set" "0,1" group.long 0x2C++0x3 line.long 0x00 "PORTI_INEN_CLR,PORTI Port x GPIO Input Enable Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Input Enable Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Input Enable Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Input Enable Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Input Enable Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Input Enable Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Input Enable Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Input Enable Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Input Enable Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Input Enable Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Input Enable Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Input Enable Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Input Enable Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Input Enable Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Input Enable Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Input Enable Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Input Enable Clear" "0,1" group.long 0x30++0x3 line.long 0x00 "PORTI_MUX,PORTI Port x Multiplexer Control Register" bitfld.long 0x00 30.--31. " MUX15 ,Mux for Port x Bit 15" "0,1,2,3" bitfld.long 0x00 28.--29. " MUX14 ,Mux for Port x Bit 14" "0,1,2,3" bitfld.long 0x00 26.--27. " MUX13 ,Mux for Port x Bit 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " MUX12 ,Mux for Port x Bit 12" "0,1,2,3" bitfld.long 0x00 22.--23. " MUX11 ,Mux for Port x Bit 11" "0,1,2,3" bitfld.long 0x00 20.--21. " MUX10 ,Mux for Port x Bit 10" "0,1,2,3" newline bitfld.long 0x00 18.--19. " MUX9 ,Mux for Port x Bit 9" "0,1,2,3" bitfld.long 0x00 16.--17. " MUX8 ,Mux for Port x Bit 8" "0,1,2,3" bitfld.long 0x00 14.--15. " MUX7 ,Mux for Port x Bit 7" "0,1,2,3" newline bitfld.long 0x00 12.--13. " MUX6 ,Mux for Port x Bit 6" "0,1,2,3" bitfld.long 0x00 10.--11. " MUX5 ,Mux for Port x Bit 5" "0,1,2,3" bitfld.long 0x00 8.--9. " MUX4 ,Mux for Port x Bit 4" "0,1,2,3" newline bitfld.long 0x00 6.--7. " MUX3 ,Mux for Port x Bit 3" "0,1,2,3" bitfld.long 0x00 4.--5. " MUX2 ,Mux for Port x Bit 2" "0,1,2,3" bitfld.long 0x00 2.--3. " MUX1 ,Mux for Port x Bit 1" "0,1,2,3" newline bitfld.long 0x00 0.--1. " MUX0 ,Mux for Port x Bit 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "PORTI_DATA_TGL,PORTI Port x GPIO Output Toggle Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Toggle" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Toggle" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Toggle" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Toggle" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Toggle" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Toggle" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Toggle" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Toggle" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Toggle" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Toggle" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Toggle" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Toggle" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Toggle" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Toggle" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Toggle" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Toggle" "0,1" group.long 0x38++0x3 line.long 0x00 "PORTI_POL,PORTI Port x GPIO Polarity Invert Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert" "0,1" group.long 0x3C++0x3 line.long 0x00 "PORTI_POL_SET,PORTI Port x GPIO Polarity Invert Set Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Set" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Set" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Set" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Set" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Set" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Set" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Set" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Set" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Set" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Set" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Set" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Set" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Set" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Set" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Set" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Set" "0,1" group.long 0x40++0x3 line.long 0x00 "PORTI_POL_CLR,PORTI Port x GPIO Polarity Invert Clear Register" bitfld.long 0x00 15. " PX15 ,Port x Bit 15 Polarity Invert Clear" "0,1" bitfld.long 0x00 14. " PX14 ,Port x Bit 14 Polarity Invert Clear" "0,1" bitfld.long 0x00 13. " PX13 ,Port x Bit 13 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 12. " PX12 ,Port x Bit 12 Polarity Invert Clear" "0,1" bitfld.long 0x00 11. " PX11 ,Port x Bit 11 Polarity Invert Clear" "0,1" bitfld.long 0x00 10. " PX10 ,Port x Bit 10 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 9. " PX9 ,Port x Bit 9 Polarity Invert Clear" "0,1" bitfld.long 0x00 8. " PX8 ,Port x Bit 8 Polarity Invert Clear" "0,1" bitfld.long 0x00 7. " PX7 ,Port x Bit 7 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 6. " PX6 ,Port x Bit 6 Polarity Invert Clear" "0,1" bitfld.long 0x00 5. " PX5 ,Port x Bit 5 Polarity Invert Clear" "0,1" bitfld.long 0x00 4. " PX4 ,Port x Bit 4 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 3. " PX3 ,Port x Bit 3 Polarity Invert Clear" "0,1" bitfld.long 0x00 2. " PX2 ,Port x Bit 2 Polarity Invert Clear" "0,1" bitfld.long 0x00 1. " PX1 ,Port x Bit 1 Polarity Invert Clear" "0,1" newline bitfld.long 0x00 0. " PX0 ,Port x Bit 0 Polarity Invert Clear" "0,1" group.long 0x44++0x3 line.long 0x00 "PORTI_LOCK,PORTI Port x GPIO Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 5. " POLAR ,Polarity Lock" "0,1" bitfld.long 0x00 4. " INEN ,Input Enable Lock" "0,1" newline bitfld.long 0x00 3. " DIR ,Direction Lock" "0,1" bitfld.long 0x00 2. " DATA ,Data, TGL Lock" "0,1" bitfld.long 0x00 1. " MUX ,Function Multiplexer Lock" "0,1" newline bitfld.long 0x00 0. " FER ,Function Enable Lock" "0,1" group.long 0x48++0x3 line.long 0x00 "PORTI_TRIG_TGL,PORTI Port x GPIO Trigger Toggle Register" bitfld.long 0x00 15. " PX15 ,PX15 Data Toggle on Trigger" "0,1" bitfld.long 0x00 14. " PX14 ,PX14 Data Toggle on Trigger" "0,1" bitfld.long 0x00 13. " PX13 ,PX13 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 12. " PX12 ,PX12 Data Toggle on Trigger" "0,1" bitfld.long 0x00 11. " PX11 ,PX11 Data Toggle on Trigger" "0,1" bitfld.long 0x00 10. " PX10 ,PX10 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 9. " PX9 ,PX9 Data Toggle on Trigger" "0,1" bitfld.long 0x00 8. " PX8 ,PX8 Data Toggle on Trigger" "0,1" bitfld.long 0x00 7. " PX7 ,PX7 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 6. " PX6 ,PX6 Data Toggle on Trigger" "0,1" bitfld.long 0x00 5. " PX5 ,PX5 Data Toggle on Trigger" "0,1" bitfld.long 0x00 4. " PX4 ,PX4 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 3. " PX3 ,PX3 Data Toggle on Trigger" "0,1" bitfld.long 0x00 2. " PX2 ,PX2 Data Toggle on Trigger" "0,1" bitfld.long 0x00 1. " PX1 ,PX1 Data Toggle on Trigger" "0,1" newline bitfld.long 0x00 0. " PX0 ,PX0 Data Toggle on Trigger" "0,1" tree.end tree.end tree "RCU (Reset Control Unit)" base ad:0x3108C000 width 16. group.long 0x0++0x3 line.long 0x00 "RCU0_CTL,RCU0 Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 10. " CRSTMSKSEL ,Core Reset System Reset Mask Select" "0,1" bitfld.long 0x00 9. " CRSTREQEN ,Core Reset Request Enabled" "0,1" newline bitfld.long 0x00 8. " SRSTREQEN ,System Reset Request Enabled" "0,1" bitfld.long 0x00 2. " RSTOUTDSRT ,Reset Out Deassert" "0,1" bitfld.long 0x00 1. " RSTOUTASRT ,Reset Out Assert" "0,1" newline bitfld.long 0x00 0. " SYSRST ,System Reset" "0,1" group.long 0x4++0x3 line.long 0x00 "RCU0_STAT,RCU0 Status Register" bitfld.long 0x00 18. " RSTOUTERR ,Reset Out Error" "0,1" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADDRERR ,Address Error" "0,1" newline bitfld.long 0x00 8.--11. " BMODE ,Boot Mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5. " RSTOUT ,Reset Out Status" "0,1" bitfld.long 0x00 3. " SWRST ,Software Reset" "0,1" newline bitfld.long 0x00 2. " SSRST ,System Source Reset" "0,1" bitfld.long 0x00 0. " HWRST ,Hardware Reset" "0,1" group.long 0x8++0x3 line.long 0x00 "RCU0_CRCTL,RCU0 Core Reset Outputs Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 3. " CR3 ,Core Reset Outputs" "0,1" bitfld.long 0x00 2. " CR2 ,Core Reset Outputs" "0,1" newline bitfld.long 0x00 1. " CR1 ,Core Reset Outputs" "0,1" bitfld.long 0x00 0. " CR0 ,Core Reset Outputs" "0,1" group.long 0xC++0x3 line.long 0x00 "RCU0_CRSTAT,RCU0 Core Reset Outputs Status Register" bitfld.long 0x00 3. " CR3 ,Core Reset Outputs" "0,1" bitfld.long 0x00 2. " CR2 ,Core Reset Outputs" "0,1" bitfld.long 0x00 1. " CR1 ,Core Reset Outputs" "0,1" newline bitfld.long 0x00 0. " CR0 ,Core Reset Outputs" "0,1" group.long 0x18++0x3 line.long 0x00 "RCU0_SRRQSTAT,RCU0 System Reset Request Status Register" hexmask.long.byte 0x00 0.--7. 1. " SRRQ ,System Reset Triggered by System Reset Request [n]" group.long 0x1C++0x3 line.long 0x00 "RCU0_SIDIS,RCU0 System Interface Disable Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 2. " SI2 ,System Interface Disable Request [2:0]" "0,1" bitfld.long 0x00 1. " SI1 ,System Interface Disable Request [2:0]" "0,1" newline bitfld.long 0x00 0. " SI0 ,System Interface Disable Request [2:0]" "0,1" group.long 0x20++0x3 line.long 0x00 "RCU0_SISTAT,RCU0 System Interface Status Register" bitfld.long 0x00 2. " SI2 ,System Interface Disable Acknowledge [2:0]" "0,1" bitfld.long 0x00 1. " SI1 ,System Interface Disable Acknowledge [2:0]" "0,1" bitfld.long 0x00 0. " SI0 ,System Interface Disable Acknowledge [2:0]" "0,1" group.long 0x24++0x3 line.long 0x00 "RCU0_SVECT_LCK,RCU0 SVECT Lock Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 2. " SVECT2 ,Lock SVECTn Registers" "0,1" bitfld.long 0x00 1. " SVECT1 ,Lock SVECTn Registers" "0,1" newline bitfld.long 0x00 0. " SVECT0 ,Lock SVECTn Registers" "0,1" group.long 0x28++0x3 line.long 0x00 "RCU0_BCODE,RCU0 Boot Code Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 13. " IDLEONENTRY ,Idle On Entry" "0,1" bitfld.long 0x00 12. " NOL2CONFIG ,No L2 Configuration" "0,1" newline bitfld.long 0x00 10. " NOHOOK ,No Hook" "0,1" bitfld.long 0x00 9. " NOPREBOOT ,No Preboot" "0,1" bitfld.long 0x00 6. " NOFAULTS ,No Faults" "0,1" newline bitfld.long 0x00 5. " NOCACHE ,No Cache" "0,1" bitfld.long 0x00 4. " NOMEMINIT ,No Memory Initialization" "0,1" bitfld.long 0x00 3. " HBTOVW ,Execute Wakeup" "0,1" newline bitfld.long 0x00 2. " HALT ,Halt" "0,1" bitfld.long 0x00 1. " NOVECTINIT ,No Vector Initialize" "0,1" bitfld.long 0x00 0. " NOKERNEL ,No Boot Kernel" "0,1" group.long 0x2C++0x3 line.long 0x00 "RCU0_SVECT0,RCU0 Software Vector Register 0" group.long 0x30++0x3 line.long 0x00 "RCU0_SVECT1,RCU0 Software Vector Register 1" group.long 0x34++0x3 line.long 0x00 "RCU0_SVECT2,RCU0 Software Vector Register 2" group.long 0x6C++0x3 line.long 0x00 "RCU0_MSG,RCU0 Message Register" bitfld.long 0x00 31. " CALLERR ,Call Error Flag" "0,1" bitfld.long 0x00 30. " CALLBACK ,Callback Call Flag" "0,1" bitfld.long 0x00 29. " CALLINIT ,Call Initcode Flag" "0,1" newline bitfld.long 0x00 28. " CALLAPP ,Call Application Flag" "0,1" bitfld.long 0x00 27. " HALTONERR ,Halt on Error Call" "0,1" bitfld.long 0x00 26. " HALTONCALL ,Halt on Callback Call" "0,1" newline bitfld.long 0x00 25. " HALTONINIT ,Halt on Initcode Call" "0,1" bitfld.long 0x00 24. " HALTONAPP ,Halt on Application Call" "0,1" bitfld.long 0x00 23. " L3INIT ,L3 Initialized" "0,1" newline bitfld.long 0x00 22. " L2INIT ,L2 Initialized" "0,1" bitfld.long 0x00 21. " SECINIT ,SEC Initialized" "0,1" bitfld.long 0x00 20. " C2ACTIVATE ,Core 2 Activated" "0,1" newline bitfld.long 0x00 19. " C1ACTIVATE ,Core 1 Activated" "0,1" bitfld.long 0x00 18. " C2L1INIT ,Core 2 L1 Initialized" "0,1" bitfld.long 0x00 17. " C1L1INIT ,Core 1 L1 Initialized" "0,1" newline bitfld.long 0x00 16. " C0L1INIT ,Core 0 L1 Initialized" "0,1" bitfld.long 0x00 10. " C2IDLE ,Core 2 Idle" "0,1" bitfld.long 0x00 9. " C1IDLE ,Core 1 Idle" "0,1" newline bitfld.long 0x00 8. " C0IDLE ,Core 0 Idle" "0,1" hexmask.long.byte 0x00 0.--7. 1. " ERRCODE ,ROM Error Code" group.long 0x70++0x3 line.long 0x00 "RCU0_MSG_SET,RCU0 Message Set Bits Register" bitfld.long 0x00 31. " SET31 ,Set Message Bits" "0,1" bitfld.long 0x00 30. " SET30 ,Set Message Bits" "0,1" bitfld.long 0x00 29. " SET29 ,Set Message Bits" "0,1" newline bitfld.long 0x00 28. " SET28 ,Set Message Bits" "0,1" bitfld.long 0x00 27. " SET27 ,Set Message Bits" "0,1" bitfld.long 0x00 26. " SET26 ,Set Message Bits" "0,1" newline bitfld.long 0x00 25. " SET25 ,Set Message Bits" "0,1" bitfld.long 0x00 24. " SET24 ,Set Message Bits" "0,1" bitfld.long 0x00 23. " SET23 ,Set Message Bits" "0,1" newline bitfld.long 0x00 22. " SET22 ,Set Message Bits" "0,1" bitfld.long 0x00 21. " SET21 ,Set Message Bits" "0,1" bitfld.long 0x00 20. " SET20 ,Set Message Bits" "0,1" newline bitfld.long 0x00 19. " SET19 ,Set Message Bits" "0,1" bitfld.long 0x00 18. " SET18 ,Set Message Bits" "0,1" bitfld.long 0x00 17. " SET17 ,Set Message Bits" "0,1" newline bitfld.long 0x00 16. " SET16 ,Set Message Bits" "0,1" bitfld.long 0x00 15. " SET15 ,Set Message Bits" "0,1" bitfld.long 0x00 14. " SET14 ,Set Message Bits" "0,1" newline bitfld.long 0x00 13. " SET13 ,Set Message Bits" "0,1" bitfld.long 0x00 12. " SET12 ,Set Message Bits" "0,1" bitfld.long 0x00 11. " SET11 ,Set Message Bits" "0,1" newline bitfld.long 0x00 10. " SET10 ,Set Message Bits" "0,1" bitfld.long 0x00 9. " SET9 ,Set Message Bits" "0,1" bitfld.long 0x00 8. " SET8 ,Set Message Bits" "0,1" newline bitfld.long 0x00 7. " SET7 ,Set Message Bits" "0,1" bitfld.long 0x00 6. " SET6 ,Set Message Bits" "0,1" bitfld.long 0x00 5. " SET5 ,Set Message Bits" "0,1" newline bitfld.long 0x00 4. " SET4 ,Set Message Bits" "0,1" bitfld.long 0x00 3. " SET3 ,Set Message Bits" "0,1" bitfld.long 0x00 2. " SET2 ,Set Message Bits" "0,1" newline bitfld.long 0x00 1. " SET1 ,Set Message Bits" "0,1" bitfld.long 0x00 0. " SET0 ,Set Message Bits" "0,1" group.long 0x74++0x3 line.long 0x00 "RCU0_MSG_CLR,RCU0 Message Clear Bits Register" bitfld.long 0x00 31. " CLR31 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 30. " CLR30 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 29. " CLR29 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 28. " CLR28 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 27. " CLR27 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 26. " CLR26 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 25. " CLR25 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 24. " CLR24 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 23. " CLR23 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 22. " CLR22 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 21. " CLR21 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 20. " CLR20 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 19. " CLR19 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 18. " CLR18 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 17. " CLR17 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 16. " CLR16 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 15. " CLR15 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 14. " CLR14 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 13. " CLR13 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 12. " CLR12 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 11. " CLR11 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 10. " CLR10 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 9. " CLR9 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 8. " CLR8 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 7. " CLR7 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 6. " CLR6 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 5. " CLR5 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 4. " CLR4 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 3. " CLR3 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 2. " CLR2 ,Clear MSG Register Bits" "0,1" newline bitfld.long 0x00 1. " CLR1 ,Clear MSG Register Bits" "0,1" bitfld.long 0x00 0. " CLR0 ,Clear MSG Register Bits" "0,1" tree.end tree "SCB (System Crossbars)" tree "SCB0" base ad:0x30042100 width 28. group.long 0x0++0x3 line.long 0x00 "SCB0_sp0a_read_qos,SCB0 SP0A Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4++0x3 line.long 0x00 "SCB0_sp0a_write_qos,SCB0 SP0A Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1000++0x3 line.long 0x00 "SCB0_sp0b_read_qos,SCB0 SP0B Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1004++0x3 line.long 0x00 "SCB0_sp0b_write_qos,SCB0 SP0B Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2000++0x3 line.long 0x00 "SCB0_sp1a_read_qos,SCB0 SP1A Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2004++0x3 line.long 0x00 "SCB0_sp1a_write_qos,SCB0 SP1A Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3000++0x3 line.long 0x00 "SCB0_sp1b_read_qos,SCB0 SP1B Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3004++0x3 line.long 0x00 "SCB0_sp1b_write_qos,SCB0 SP1B Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4000++0x3 line.long 0x00 "SCB0_sp2a_read_qos,SCB0 SP2A Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4004++0x3 line.long 0x00 "SCB0_sp2a_write_qos,SCB0 SP2A Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5000++0x3 line.long 0x00 "SCB0_sp2b_read_qos,SCB0 SP2B Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5004++0x3 line.long 0x00 "SCB0_sp2b_write_qos,SCB0 SP2B Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x6000++0x3 line.long 0x00 "SCB0_sp3a_read_qos,SCB0 SP3A Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x6004++0x3 line.long 0x00 "SCB0_sp3a_write_qos,SCB0 SP3A Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x7000++0x3 line.long 0x00 "SCB0_sp3b_read_qos,SCB0 SP3B Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x7004++0x3 line.long 0x00 "SCB0_sp3b_write_qos,SCB0 SP3B Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8000++0x3 line.long 0x00 "SCB0_crc0_ch0_read_qos,SCB0 CRC0 Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8004++0x3 line.long 0x00 "SCB0_crc0_ch0_write_qos,SCB0 CRC0 Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9000++0x3 line.long 0x00 "SCB0_crc0_ch1_read_qos,SCB0 CRC0 Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9004++0x3 line.long 0x00 "SCB0_crc0_ch1_write_qos,SCB0 CRC0 Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA000++0x3 line.long 0x00 "SCB0_crc1_ch0_read_qos,SCB0 CRC1 Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA004++0x3 line.long 0x00 "SCB0_crc1_ch0_write_qos,SCB0 CRC1 Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB000++0x3 line.long 0x00 "SCB0_crc1_ch1_read_qos,SCB0 CRC1 Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB004++0x3 line.long 0x00 "SCB0_crc1_ch1_write_qos,SCB0 CRC1 Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC000++0x3 line.long 0x00 "SCB0_uart2_rx_read_qos,SCB0 UART2 RX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC004++0x3 line.long 0x00 "SCB0_uart2_rx_write_qos,SCB0 UART2 RX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD000++0x3 line.long 0x00 "SCB0_sh0_dport_read_qos,SCB0 SH0 DPORT Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD004++0x3 line.long 0x00 "SCB0_sh0_dport_write_qos,SCB0 SH0 DPORT Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE000++0x3 line.long 0x00 "SCB0_sh0_iport_read_qos,SCB0 SH0 LPORT Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE004++0x3 line.long 0x00 "SCB0_sh0_iport_write_qos,SCB0 SH0 LPORT Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF000++0x3 line.long 0x00 "SCB0_sp4a_read_qos,SCB0 SP4A Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF004++0x3 line.long 0x00 "SCB0_sp4a_write_qos,SCB0 SP4A Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10000++0x3 line.long 0x00 "SCB0_sp4b_read_qos,SCB0 SP4B Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10004++0x3 line.long 0x00 "SCB0_sp4b_write_qos,SCB0 SP4B Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x11000++0x3 line.long 0x00 "SCB0_uart3_tx_read_qos,SCB0 UART3 TX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x11004++0x3 line.long 0x00 "SCB0_uart3_tx_write_qos,SCB0 UART3 TX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x12000++0x3 line.long 0x00 "SCB0_uart3_rx_read_qos,SCB0 UART3 RX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x12004++0x3 line.long 0x00 "SCB0_uart3_rx_write_qos,SCB0 UART3 RX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x13000++0x3 line.long 0x00 "SCB0_hsmdma_ch0_read_qos,SCB0 HSMDMA Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x13004++0x3 line.long 0x00 "SCB0_hsmdma_ch0_write_qos,SCB0 HSMDMA Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14000++0x3 line.long 0x00 "SCB0_sp5a_read_qos,SCB0 SP5A Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14004++0x3 line.long 0x00 "SCB0_sp5a_write_qos,SCB0 SP5A Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x15000++0x3 line.long 0x00 "SCB0_mlb_read_qos,SCB0 MLB Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x15004++0x3 line.long 0x00 "SCB0_mlb_write_qos,SCB0 MLB Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x16000++0x3 line.long 0x00 "SCB0_uart0_tx_read_qos,SCB0 UART0 TX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x16004++0x3 line.long 0x00 "SCB0_uart0_tx_write_qos,SCB0 UART0 TX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x17000++0x3 line.long 0x00 "SCB0_uart0_rx_read_qos,SCB0 UART0 RX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x17004++0x3 line.long 0x00 "SCB0_uart0_rx_write_qos,SCB0 UART0 RX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18000++0x3 line.long 0x00 "SCB0_sp5b_read_qos,SCB0 SP5B Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x18004++0x3 line.long 0x00 "SCB0_sp5b_write_qos,SCB0 SP5B Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x19000++0x3 line.long 0x00 "SCB0_hsmdma_ch1_read_qos,SCB0 HSMDMA Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x19004++0x3 line.long 0x00 "SCB0_hsmdma_ch1_write_qos,SCB0 HSMDMA Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1A000++0x3 line.long 0x00 "SCB0_uart2_tx_read_qos,SCB0 UART2 TX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1A004++0x3 line.long 0x00 "SCB0_uart2_tx_write_qos,SCB0 UART2 TX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1B000++0x3 line.long 0x00 "SCB0_spi0tx_read_qos,SCB0 SPI0 TX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1B004++0x3 line.long 0x00 "SCB0_spi0tx_write_qos,SCB0 SPI0 TX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C000++0x3 line.long 0x00 "SCB0_spi0rx_read_qos,SCB0 SPI0 RX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C004++0x3 line.long 0x00 "SCB0_spi0rx_write_qos,SCB0 SPI0 RX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1D000++0x3 line.long 0x00 "SCB0_spi1tx_read_qos,SCB0 SPI1 TX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1D004++0x3 line.long 0x00 "SCB0_spi1tx_write_qos,SCB0 SPI1 TX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1E000++0x3 line.long 0x00 "SCB0_spi1rx_read_qos,SCB0 SPI1 RX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1E004++0x3 line.long 0x00 "SCB0_spi1rx_write_qos,SCB0 SPI1 RX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F000++0x3 line.long 0x00 "SCB0_spi2tx_read_qos,SCB0 SPI2 TX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F004++0x3 line.long 0x00 "SCB0_spi2tx_write_qos,SCB0 SPI2 TX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20000++0x3 line.long 0x00 "SCB0_spi2rx_read_qos,SCB0 SPI2 RX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20004++0x3 line.long 0x00 "SCB0_spi2rx_write_qos,SCB0 SPI2 RX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x21000++0x3 line.long 0x00 "SCB0_sp6a_read_qos,SCB0 SP6A Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x21004++0x3 line.long 0x00 "SCB0_sp6a_write_qos,SCB0 SP6A Write Quality of Service Registers" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x22000++0x3 line.long 0x00 "SCB0_sp6b_read_qos,SCB0 SP6B Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x22004++0x3 line.long 0x00 "SCB0_sp6b_write_qos,SCB0 SP6B Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x23000++0x3 line.long 0x00 "SCB0_lp0_read_qos,SCB0 LP0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x23004++0x3 line.long 0x00 "SCB0_lp0_write_qos,SCB0 LP0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24000++0x3 line.long 0x00 "SCB0_sp7a_read_qos,SCB0 SP7A Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24004++0x3 line.long 0x00 "SCB0_sp7a_write_qos,SCB0 SP7A Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x25000++0x3 line.long 0x00 "SCB0_sp7b_read_qos,SCB0 SP7B Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x25004++0x3 line.long 0x00 "SCB0_sp7b_write_qos,SCB0 SP7B Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x26000++0x3 line.long 0x00 "SCB0_sh0_mmr_read_qos,SCB0 SH0 MMR Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x26004++0x3 line.long 0x00 "SCB0_sh0_mmr_write_qos,SCB0 SH0 MMR Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x27000++0x3 line.long 0x00 "SCB0_spi3rx_read_qos,SCB0 SPI3 RX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x27004++0x3 line.long 0x00 "SCB0_spi3rx_write_qos,SCB0 SPI3 RX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28000++0x3 line.long 0x00 "SCB0_uart1_tx_read_qos,SCB0 UART1 TX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x28004++0x3 line.long 0x00 "SCB0_uart1_tx_write_qos,SCB0 UART1 TX Write Quality of Service Registers" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x29000++0x3 line.long 0x00 "SCB0_uart1_rx_read_qos,SCB0 UART1 RX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x29004++0x3 line.long 0x00 "SCB0_uart1_rx_write_qos,SCB0 UART1 RX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2A000++0x3 line.long 0x00 "SCB0_spi3tx_read_qos,SCB0 SPI3 TX Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2A004++0x3 line.long 0x00 "SCB0_spi3tx_write_qos,SCB0 SPI3 TX Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B000++0x3 line.long 0x00 "SCB0_lp1_read_qos,SCB0 LP1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2B004++0x3 line.long 0x00 "SCB0_lp1_write_qos,SCB0 LP1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C000++0x3 line.long 0x00 "SCB0_crc2_ch1_read_qos,SCB0 CRC2 Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2C004++0x3 line.long 0x00 "SCB0_crc2_ch1_write_qos,SCB0 CRC2 Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2D000++0x3 line.long 0x00 "SCB0_crc2_ch0_read_qos,SCB0 CRC2 Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2D004++0x3 line.long 0x00 "SCB0_crc2_ch0_write_qos,SCB0 CRC2 Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2E000++0x3 line.long 0x00 "SCB0_crc3_ch1_read_qos,SCB0 CRC3 Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2E004++0x3 line.long 0x00 "SCB0_crc3_ch1_write_qos,SCB0 CRC3 Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F000++0x3 line.long 0x00 "SCB0_crypto_read_qos,SCB0 CRYPTO Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2F004++0x3 line.long 0x00 "SCB0_crypto_write_qos,SCB0 CRYPTO Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30000++0x3 line.long 0x00 "SCB0_crc3_ch0_read_qos,SCB0 CRC3 Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30004++0x3 line.long 0x00 "SCB0_crc3_ch0_write_qos,SCB0 CRC3 Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x31000++0x3 line.long 0x00 "SCB0_msmdma1_ch1_read_qos,SCB0 MSMDMA1 Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x31004++0x3 line.long 0x00 "SCB0_msmdma1_ch1_write_qos,SCB0 MSMDMA1 Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x32000++0x3 line.long 0x00 "SCB0_sh0_fir_ch0_read_qos,SCB0 SH0 FIR Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x32004++0x3 line.long 0x00 "SCB0_sh0_fir_ch0_write_qos,SCB0 SH0 FIR Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x33000++0x3 line.long 0x00 "SCB0_sh0_fir_ch1_read_qos,SCB0 SH0 FIR Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x33004++0x3 line.long 0x00 "SCB0_sh0_fir_ch1_write_qos,SCB0 SH0 FIR Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34000++0x3 line.long 0x00 "SCB0_msmdma1_ch0_read_qos,SCB0 MSMDMA1 Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34004++0x3 line.long 0x00 "SCB0_msmdma1_ch0_write_qos,SCB0 MSMDMA1 Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x35000++0x3 line.long 0x00 "SCB0_hsmdma1_ch1_read_qos,SCB0 HSMDMA1 Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x35004++0x3 line.long 0x00 "SCB0_hsmdma1_ch1_write_qos,SCB0 HSMDMA1 Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x36000++0x3 line.long 0x00 "SCB0_dldma0_ch0_read_qos,SCB0 DLDMA0 Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x36004++0x3 line.long 0x00 "SCB0_dldma0_ch0_write_qos,SCB0 DLDMA0 Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x37000++0x3 line.long 0x00 "SCB0_dldma0_ch1_read_qos,SCB0 DLDMA0 Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x37004++0x3 line.long 0x00 "SCB0_dldma0_ch1_write_qos,SCB0 DLDMA0 Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38000++0x3 line.long 0x00 "SCB0_dldma1_ch0_read_qos,SCB0 DLDMA1 Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x38004++0x3 line.long 0x00 "SCB0_dldma1_ch0_write_qos,SCB0 DLDMA1 Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x39000++0x3 line.long 0x00 "SCB0_dldma1_ch1_read_qos,SCB0 DLDMA1 Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x39004++0x3 line.long 0x00 "SCB0_dldma1_ch1_write_qos,SCB0 DLDMA1 Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3A000++0x3 line.long 0x00 "SCB0_msmdma_ch0_read_qos,SCB0 MSMDMA Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3A004++0x3 line.long 0x00 "SCB0_msmdma_ch0_write_qos,SCB0 MSMDMA Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3B000++0x3 line.long 0x00 "SCB0_msmdma_ch1_read_qos,SCB0 MSMDMA Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3B004++0x3 line.long 0x00 "SCB0_msmdma_ch1_write_qos,SCB0 MSMDMA Channel 1 Write Quality of Service Registers" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C000++0x3 line.long 0x00 "SCB0_hsmdma1_ch0_read_qos,SCB0 HSMDMA1 Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C004++0x3 line.long 0x00 "SCB0_hsmdma1_ch0_write_qos,SCB0 HSMDMA1 Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D000++0x3 line.long 0x00 "SCB0_ppi_f0_read_qos,SCB0 PPI F0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3D004++0x3 line.long 0x00 "SCB0_ppi_f0_write_qos,SCB0 PPI F0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3E000++0x3 line.long 0x00 "SCB0_ppi_f1_read_qos,SCB0 PPI F1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3E004++0x3 line.long 0x00 "SCB0_ppi_f1_write_qos,SCB0 PPI F1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3F000++0x3 line.long 0x00 "SCB0_usb0_read_qos,SCB0 USB0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3F004++0x3 line.long 0x00 "SCB0_usb0_write_qos,SCB0 USB0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40000++0x3 line.long 0x00 "SCB0_sh1_iport_read_qos,SCB0 SH1 IPORT Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x40004++0x3 line.long 0x00 "SCB0_sh1_iport_write_qos,SCB0 SH1 IPORT Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41000++0x3 line.long 0x00 "SCB0_sh1_dport_read_qos,SCB0 SH1 DPORT Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x41004++0x3 line.long 0x00 "SCB0_sh1_dport_write_qos,SCB0 SH1 DPORT Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x42000++0x3 line.long 0x00 "SCB0_sh1_mmr_read_qos,SCB0 SH1 MMR Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x42004++0x3 line.long 0x00 "SCB0_sh1_mmr_write_qos,SCB0 SH1 MMR Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x43000++0x3 line.long 0x00 "SCB0_pl310_m0_read_qos,SCB0 ARM_L2CC M0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x43004++0x3 line.long 0x00 "SCB0_pl310_m0_write_qos,SCB0 ARM_L2CC M0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x44000++0x3 line.long 0x00 "SCB0_pl310_m1_read_qos,SCB0 ARM_L2CC M1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x44004++0x3 line.long 0x00 "SCB0_pl310_m1_write_qos,SCB0 ARM_L2CC M1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x45000++0x3 line.long 0x00 "SCB0_gige_read_qos,SCB0 GIGE Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x45004++0x3 line.long 0x00 "SCB0_gige_write_qos,SCB0 GIGE Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x46000++0x3 line.long 0x00 "SCB0_dbg_read_qos,SCB0 DBG Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x46004++0x3 line.long 0x00 "SCB0_dbg_write_qos,SCB0 DBG Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x47000++0x3 line.long 0x00 "SCB0_etr_read_qos,SCB0 ETR Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x47004++0x3 line.long 0x00 "SCB0_etr_write_qos,SCB0 ETR Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48000++0x3 line.long 0x00 "SCB0_emac_read_qos,SCB0 EMAC Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x48004++0x3 line.long 0x00 "SCB0_emac_write_qos,SCB0 EMAC Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x49000++0x3 line.long 0x00 "SCB0_sh1_fir_ch1_read_qos,SCB0 SH1 FIR Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x49004++0x3 line.long 0x00 "SCB0_sh1_fir_ch1_write_qos,SCB0 SH1 FIR Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A000++0x3 line.long 0x00 "SCB0_sh1_fir_ch0_read_qos,SCB0 SH1 FIR Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4A004++0x3 line.long 0x00 "SCB0_sh1_fir_ch0_write_qos,SCB0 SH1 FIR Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4B000++0x3 line.long 0x00 "SCB0_sh0_iir_ch0_read_qos,SCB0 SH0 IIR Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4B004++0x3 line.long 0x00 "SCB0_sh0_iir_ch0_write_qos,SCB0 SH0 IIR Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C000++0x3 line.long 0x00 "SCB0_sh0_iir_ch1_read_qos,SCB0 SH0 IIR Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4C004++0x3 line.long 0x00 "SCB0_sh0_iir_ch1_write_qos,SCB0 SH0 IIR Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4D000++0x3 line.long 0x00 "SCB0_sh1_iir_ch0_read_qos,SCB0 SH1 IIR Channel 0 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4D004++0x3 line.long 0x00 "SCB0_sh1_iir_ch0_write_qos,SCB0 SH1 IIR Channel 0 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E000++0x3 line.long 0x00 "SCB0_sh1_iir_ch1_read_qos,SCB0 SH1 IIR Channel 1 Read Quality of Service Register" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4E004++0x3 line.long 0x00 "SCB0_sh1_iir_ch1_write_qos,SCB0 SH1 IIR Channel 1 Write Quality of Service Register" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x7FF20++0x3 line.long 0x00 "SCB0_lp_sync_mode,SCB0 LP Fabric (CLKO8) Synchronization Mode Register" bitfld.long 0x00 0.--2. " sync_mode ,Sync Mode. Default is ASYNC('h4) other valid option is M:N('h3)." "0,1,2,3,4,5,6,7" tree.end tree "SCB1" base ad:0x30200020 width 23. group.long 0x0++0x3 line.long 0x00 "SCB1_DMC_IB_sync_mode,SCB1 DMC Fabric (CLK03) Synchronization Mode Register" bitfld.long 0x00 0.--2. " sync_mode ,Sync Mode. Default is ASYNC('h4) other valid option is M:N('h3)." "0,1,2,3,4,5,6,7" tree.end tree "SCB3" base ad:0x30102020 width 27. group.long 0x0++0x3 line.long 0x00 "SCB3_lp_mmr_ib_sync_mode,SCB3 DMC MMRG Fabric (CLK08) Synchronization Mode Register" bitfld.long 0x00 0.--2. " sync_mode ,Sync Mode. Default is ASYNC('h4) other valid option is M:N('h3)." "0,1,2,3,4,5,6,7" group.long 0x3000++0x3 line.long 0x00 "SCB3_dmc_mmr_ib_sync_mode,SCB3 DMC MMRG Fabric (CLK03) Synchronization Mode Register" bitfld.long 0x00 0.--2. " sync_mode ,Sync Mode" "0,1,2,3,4,5,6,7" group.long 0x9000++0x3 line.long 0x00 "SCB3_can_mmr_ib_sync_mode,SCB3 DMC MMRG Fabric (CLK04) Synchronization Mode Register" bitfld.long 0x00 0.--2. " sync_mode ,Sync Mode" "0,1,2,3,4,5,6,7" tree.end tree "SCB4" base ad:0x30342100 width 34. group.long 0x0++0x3 line.long 0x00 "SCB4_iir2_ch0_ib_read_qos,SCB4 Iir2 Ch0 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4++0x3 line.long 0x00 "SCB4_iir2_ch0_ib_write_qos,SCB4 Iir2 Ch0 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1000++0x3 line.long 0x00 "SCB4_sharc_dport_read_qos,SCB4 Sharc Dport.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1004++0x3 line.long 0x00 "SCB4_sharc_dport_write_qos,SCB4 Sharc Dport.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2000++0x3 line.long 0x00 "SCB4_fabric_s2port_ib_read_qos,SCB4 Fabric S2port Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2004++0x3 line.long 0x00 "SCB4_fabric_s2port_ib_write_qos,SCB4 Fabric S2port Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3000++0x3 line.long 0x00 "SCB4_fir_ch0_ib_read_qos,SCB4 Fir Ch0 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3004++0x3 line.long 0x00 "SCB4_fir_ch0_ib_write_qos,SCB4 Fir Ch0 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4000++0x3 line.long 0x00 "SCB4_fir_ch1_ib_read_qos,SCB4 Fir Ch1 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x4004++0x3 line.long 0x00 "SCB4_fir_ch1_ib_write_qos,SCB4 Fir Ch1 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5000++0x3 line.long 0x00 "SCB4_iir0_ch0_ib_read_qos,SCB4 Iir0 Ch0 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5004++0x3 line.long 0x00 "SCB4_iir0_ch0_ib_write_qos,SCB4 Iir0 Ch0 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x6000++0x3 line.long 0x00 "SCB4_iir0_ch1_ib_read_qos,SCB4 Iir0 Ch1 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x6004++0x3 line.long 0x00 "SCB4_iir0_ch1_ib_write_qos,SCB4 Iir0 Ch1 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x7000++0x3 line.long 0x00 "SCB4_iir2_ch1_ib_read_qos,SCB4 Iir2 Ch1 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x7004++0x3 line.long 0x00 "SCB4_iir2_ch1_ib_write_qos,SCB4 Iir2 Ch1 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8000++0x3 line.long 0x00 "SCB4_fabric_s1port_ib_read_qos,SCB4 Fabric S1port Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x8004++0x3 line.long 0x00 "SCB4_fabric_s1port_ib_write_qos,SCB4 Fabric S1port Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9000++0x3 line.long 0x00 "SCB4_iir3_ch0_ib_read_qos,SCB4 Iir3 Ch0 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x9004++0x3 line.long 0x00 "SCB4_iir3_ch0_ib_write_qos,SCB4 Iir3 Ch0 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA000++0x3 line.long 0x00 "SCB4_iir3_ch1_ib_read_qos,SCB4 Iir3 Ch1 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA004++0x3 line.long 0x00 "SCB4_iir3_ch1_ib_write_qos,SCB4 Iir3 Ch1 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB000++0x3 line.long 0x00 "SCB4_fabric_acc_mmr_ib_read_qos,SCB4 Fabric Acc Mmr Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB004++0x3 line.long 0x00 "SCB4_fabric_acc_mmr_ib_write_qos,SCB4 Fabric Acc Mmr Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC000++0x3 line.long 0x00 "SCB4_iir1_ch0_ib_read_qos,SCB4 Iir1 Ch0 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC004++0x3 line.long 0x00 "SCB4_iir1_ch0_ib_write_qos,SCB4 Iir1 Ch0 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD000++0x3 line.long 0x00 "SCB4_iir1_ch1_ib_read_qos,SCB4 Iir1 Ch1 Ib.read Qos" bitfld.long 0x00 0.--3. " ar_qos ,Ar Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD004++0x3 line.long 0x00 "SCB4_iir1_ch1_ib_write_qos,SCB4 Iir1 Ch1 Ib.write Qos" bitfld.long 0x00 0.--3. " aw_qos ,Aw Qos" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "SCB5" base ad:0x30400000 width 22. group.long 0x0++0x3 line.long 0x00 "SCB5_spi2_ospi_remap,SCB5 SPI2/OSPI Memory Map Address Remap Register" bitfld.long 0x00 0.--1. " remap ," "0,1,2,3" tree.end tree.end tree "SEC (System Event Controller)" base ad:0x31089000 width 17. group.long 0x0++0x3 line.long 0x00 "SEC0_GCTL,SEC0 Global Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 1. " RESET ,Reset" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SEC0_GSTAT,SEC0 Global Status Register" bitfld.long 0x00 31. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 30. " ADRERR ,Address Error" "0,1" hexmask.long.byte 0x00 16.--23. 1. " SID ,Source ID for SSI Error" newline bitfld.long 0x00 8.--11. " SCI ,SCI ID for SCI Error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8++0x3 line.long 0x00 "SEC0_RAISE,SEC0 Global Raise Register" hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID" group.long 0xC++0x3 line.long 0x00 "SEC0_END,SEC0 Global End Register" hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID IRQ to End" group.long 0x10++0x3 line.long 0x00 "SEC0_FCTL,SEC0 Fault Control Register" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 13. " TES ,Trigger Event Select" "0,1" bitfld.long 0x00 12. " CMS ,COP Mode Select" "0,1" newline bitfld.long 0x00 7. " FIEN ,Fault Input Enable" "0,1" bitfld.long 0x00 6. " SREN ,System Reset Enable" "0,1" bitfld.long 0x00 5. " TOEN ,Trigger Output Enable" "0,1" newline bitfld.long 0x00 4. " FOEN ,Fault Output Enable" "0,1" bitfld.long 0x00 1. " RESET ,Reset" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x14++0x3 line.long 0x00 "SEC0_FSTAT,SEC0 Fault Status Register" bitfld.long 0x00 10. " NPND ,Next Pending Fault" "0,1" bitfld.long 0x00 9. " ACT ,Fault Active" "0,1" bitfld.long 0x00 8. " PND ,Pending Fault" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x18++0x3 line.long 0x00 "SEC0_FSID,SEC0 Fault Source ID Register" bitfld.long 0x00 16. " FEXT ,Fault External" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID" group.long 0x1C++0x3 line.long 0x00 "SEC0_FEND,SEC0 Fault End Register" bitfld.long 0x00 16. " FEXT ,Fault External" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID" group.long 0x20++0x3 line.long 0x00 "SEC0_FDLY,SEC0 Fault Delay Register" group.long 0x24++0x3 line.long 0x00 "SEC0_FDLY_CUR,SEC0 Fault Delay Current Register" group.long 0x28++0x3 line.long 0x00 "SEC0_FSRDLY,SEC0 Fault System Reset Delay Register" group.long 0x2C++0x3 line.long 0x00 "SEC0_FSRDLY_CUR,SEC0 Fault System Reset Delay Current Register" group.long 0x30++0x3 line.long 0x00 "SEC0_FCOPP,SEC0 Fault COP Period Register" group.long 0x34++0x3 line.long 0x00 "SEC0_FCOPP_CUR,SEC0 Fault COP Period Current Register" group.long 0x440++0x3 line.long 0x00 "SEC0_CCTL1,SEC0 SCI Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 16. " NMIEN ,NMI Enable" "0,1" bitfld.long 0x00 12. " WFI ,Wait For Idle" "0,1" newline bitfld.long 0x00 1. " RESET ,Reset" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x444++0x3 line.long 0x00 "SEC0_CSTAT1,SEC0 SCI Status Register n" bitfld.long 0x00 16. " NMI ,Non-Maskable Interrupt" "0,1" bitfld.long 0x00 12. " WFI ,Wait For Idle" "0,1" bitfld.long 0x00 10. " SIDV ,SID Valid" "0,1" newline bitfld.long 0x00 9. " ACTV ,ACT Valid" "0,1" bitfld.long 0x00 8. " PNDV ,PND Valid" "0,1" bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" newline bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x448++0x3 line.long 0x00 "SEC0_CPND1,SEC0 Core Pending Register n" hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest Pending IRQ Priority" hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest Pending IRQ Source ID" group.long 0x44C++0x3 line.long 0x00 "SEC0_CACT1,SEC0 SCI Active Register n" hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest Active IRQ Priority" hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest Active IRQ Source ID" group.long 0x450++0x3 line.long 0x00 "SEC0_CPMSK1,SEC0 SCI Priority Mask Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ Priority Mask" group.long 0x454++0x3 line.long 0x00 "SEC0_CGMSK1,SEC0 SCI Group Mask Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 8. " UGRP ,Ungrouped Mask" "0,1" bitfld.long 0x00 0.--3. " GRP ,Grouped Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x458++0x3 line.long 0x00 "SEC0_CPLVL1,SEC0 SCI Priority Level Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 0.--2. " PLVL ,Priority Levels" "0,1,2,3,4,5,6,7" group.long 0x45C++0x3 line.long 0x00 "SEC0_CSID1,SEC0 SCI Source ID Register n" hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID" group.long 0x480++0x3 line.long 0x00 "SEC0_CCTL2,SEC0 SCI Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 16. " NMIEN ,NMI Enable" "0,1" bitfld.long 0x00 12. " WFI ,Wait For Idle" "0,1" newline bitfld.long 0x00 1. " RESET ,Reset" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x484++0x3 line.long 0x00 "SEC0_CSTAT2,SEC0 SCI Status Register n" bitfld.long 0x00 16. " NMI ,Non-Maskable Interrupt" "0,1" bitfld.long 0x00 12. " WFI ,Wait For Idle" "0,1" bitfld.long 0x00 10. " SIDV ,SID Valid" "0,1" newline bitfld.long 0x00 9. " ACTV ,ACT Valid" "0,1" bitfld.long 0x00 8. " PNDV ,PND Valid" "0,1" bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" newline bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x488++0x3 line.long 0x00 "SEC0_CPND2,SEC0 Core Pending Register n" hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest Pending IRQ Priority" hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest Pending IRQ Source ID" group.long 0x48C++0x3 line.long 0x00 "SEC0_CACT2,SEC0 SCI Active Register n" hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Highest Active IRQ Priority" hexmask.long.byte 0x00 0.--7. 1. " SID ,Highest Active IRQ Source ID" group.long 0x490++0x3 line.long 0x00 "SEC0_CPMSK2,SEC0 SCI Priority Mask Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " PRIO ,IRQ Priority Mask" group.long 0x494++0x3 line.long 0x00 "SEC0_CGMSK2,SEC0 SCI Group Mask Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 8. " UGRP ,Ungrouped Mask" "0,1" bitfld.long 0x00 0.--3. " GRP ,Grouped Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x498++0x3 line.long 0x00 "SEC0_CPLVL2,SEC0 SCI Priority Level Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 0.--2. " PLVL ,Priority Levels" "0,1,2,3,4,5,6,7" group.long 0x49C++0x3 line.long 0x00 "SEC0_CSID2,SEC0 SCI Source ID Register n" hexmask.long.byte 0x00 0.--7. 1. " SID ,Source ID" group.long 0x800++0x3 line.long 0x00 "SEC0_SCTL0,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x804++0x3 line.long 0x00 "SEC0_SSTAT0,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x808++0x3 line.long 0x00 "SEC0_SCTL1,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x80C++0x3 line.long 0x00 "SEC0_SSTAT1,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x810++0x3 line.long 0x00 "SEC0_SCTL2,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x814++0x3 line.long 0x00 "SEC0_SSTAT2,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x818++0x3 line.long 0x00 "SEC0_SCTL3,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x81C++0x3 line.long 0x00 "SEC0_SSTAT3,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x820++0x3 line.long 0x00 "SEC0_SCTL4,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SEC0_SSTAT4,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x828++0x3 line.long 0x00 "SEC0_SCTL5,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SEC0_SSTAT5,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x830++0x3 line.long 0x00 "SEC0_SCTL6,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SEC0_SSTAT6,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x838++0x3 line.long 0x00 "SEC0_SCTL7,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SEC0_SSTAT7,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x840++0x3 line.long 0x00 "SEC0_SCTL8,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x844++0x3 line.long 0x00 "SEC0_SSTAT8,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x848++0x3 line.long 0x00 "SEC0_SCTL9,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x84C++0x3 line.long 0x00 "SEC0_SSTAT9,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x850++0x3 line.long 0x00 "SEC0_SCTL10,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x854++0x3 line.long 0x00 "SEC0_SSTAT10,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x858++0x3 line.long 0x00 "SEC0_SCTL11,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x85C++0x3 line.long 0x00 "SEC0_SSTAT11,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x860++0x3 line.long 0x00 "SEC0_SCTL12,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x864++0x3 line.long 0x00 "SEC0_SSTAT12,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x868++0x3 line.long 0x00 "SEC0_SCTL13,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x86C++0x3 line.long 0x00 "SEC0_SSTAT13,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x870++0x3 line.long 0x00 "SEC0_SCTL14,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x874++0x3 line.long 0x00 "SEC0_SSTAT14,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x878++0x3 line.long 0x00 "SEC0_SCTL15,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x87C++0x3 line.long 0x00 "SEC0_SSTAT15,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x880++0x3 line.long 0x00 "SEC0_SCTL16,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x884++0x3 line.long 0x00 "SEC0_SSTAT16,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x888++0x3 line.long 0x00 "SEC0_SCTL17,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x88C++0x3 line.long 0x00 "SEC0_SSTAT17,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x890++0x3 line.long 0x00 "SEC0_SCTL18,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x894++0x3 line.long 0x00 "SEC0_SSTAT18,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x898++0x3 line.long 0x00 "SEC0_SCTL19,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x89C++0x3 line.long 0x00 "SEC0_SSTAT19,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8A0++0x3 line.long 0x00 "SEC0_SCTL20,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8A4++0x3 line.long 0x00 "SEC0_SSTAT20,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8A8++0x3 line.long 0x00 "SEC0_SCTL21,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8AC++0x3 line.long 0x00 "SEC0_SSTAT21,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8B0++0x3 line.long 0x00 "SEC0_SCTL22,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8B4++0x3 line.long 0x00 "SEC0_SSTAT22,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8B8++0x3 line.long 0x00 "SEC0_SCTL23,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8BC++0x3 line.long 0x00 "SEC0_SSTAT23,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8C0++0x3 line.long 0x00 "SEC0_SCTL24,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8C4++0x3 line.long 0x00 "SEC0_SSTAT24,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8C8++0x3 line.long 0x00 "SEC0_SCTL25,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8CC++0x3 line.long 0x00 "SEC0_SSTAT25,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8D0++0x3 line.long 0x00 "SEC0_SCTL26,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8D4++0x3 line.long 0x00 "SEC0_SSTAT26,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8D8++0x3 line.long 0x00 "SEC0_SCTL27,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8DC++0x3 line.long 0x00 "SEC0_SSTAT27,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8E0++0x3 line.long 0x00 "SEC0_SCTL28,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8E4++0x3 line.long 0x00 "SEC0_SSTAT28,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8E8++0x3 line.long 0x00 "SEC0_SCTL29,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8EC++0x3 line.long 0x00 "SEC0_SSTAT29,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8F0++0x3 line.long 0x00 "SEC0_SCTL30,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8F4++0x3 line.long 0x00 "SEC0_SSTAT30,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x8F8++0x3 line.long 0x00 "SEC0_SCTL31,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x8FC++0x3 line.long 0x00 "SEC0_SSTAT31,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x900++0x3 line.long 0x00 "SEC0_SCTL32,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x904++0x3 line.long 0x00 "SEC0_SSTAT32,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x908++0x3 line.long 0x00 "SEC0_SCTL33,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x90C++0x3 line.long 0x00 "SEC0_SSTAT33,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x910++0x3 line.long 0x00 "SEC0_SCTL34,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x914++0x3 line.long 0x00 "SEC0_SSTAT34,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x918++0x3 line.long 0x00 "SEC0_SCTL35,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x91C++0x3 line.long 0x00 "SEC0_SSTAT35,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x920++0x3 line.long 0x00 "SEC0_SCTL36,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x924++0x3 line.long 0x00 "SEC0_SSTAT36,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x928++0x3 line.long 0x00 "SEC0_SCTL37,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x92C++0x3 line.long 0x00 "SEC0_SSTAT37,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x930++0x3 line.long 0x00 "SEC0_SCTL38,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x934++0x3 line.long 0x00 "SEC0_SSTAT38,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x938++0x3 line.long 0x00 "SEC0_SCTL39,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x93C++0x3 line.long 0x00 "SEC0_SSTAT39,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x940++0x3 line.long 0x00 "SEC0_SCTL40,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x944++0x3 line.long 0x00 "SEC0_SSTAT40,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x948++0x3 line.long 0x00 "SEC0_SCTL41,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x94C++0x3 line.long 0x00 "SEC0_SSTAT41,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x950++0x3 line.long 0x00 "SEC0_SCTL42,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x954++0x3 line.long 0x00 "SEC0_SSTAT42,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x958++0x3 line.long 0x00 "SEC0_SCTL43,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x95C++0x3 line.long 0x00 "SEC0_SSTAT43,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x960++0x3 line.long 0x00 "SEC0_SCTL44,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x964++0x3 line.long 0x00 "SEC0_SSTAT44,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x968++0x3 line.long 0x00 "SEC0_SCTL45,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x96C++0x3 line.long 0x00 "SEC0_SSTAT45,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x970++0x3 line.long 0x00 "SEC0_SCTL46,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x974++0x3 line.long 0x00 "SEC0_SSTAT46,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x978++0x3 line.long 0x00 "SEC0_SCTL47,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x97C++0x3 line.long 0x00 "SEC0_SSTAT47,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x980++0x3 line.long 0x00 "SEC0_SCTL48,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x984++0x3 line.long 0x00 "SEC0_SSTAT48,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x988++0x3 line.long 0x00 "SEC0_SCTL49,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x98C++0x3 line.long 0x00 "SEC0_SSTAT49,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x990++0x3 line.long 0x00 "SEC0_SCTL50,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x994++0x3 line.long 0x00 "SEC0_SSTAT50,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x998++0x3 line.long 0x00 "SEC0_SCTL51,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x99C++0x3 line.long 0x00 "SEC0_SSTAT51,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9A0++0x3 line.long 0x00 "SEC0_SCTL52,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9A4++0x3 line.long 0x00 "SEC0_SSTAT52,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9A8++0x3 line.long 0x00 "SEC0_SCTL53,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9AC++0x3 line.long 0x00 "SEC0_SSTAT53,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9B0++0x3 line.long 0x00 "SEC0_SCTL54,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9B4++0x3 line.long 0x00 "SEC0_SSTAT54,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9B8++0x3 line.long 0x00 "SEC0_SCTL55,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9BC++0x3 line.long 0x00 "SEC0_SSTAT55,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9C0++0x3 line.long 0x00 "SEC0_SCTL56,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9C4++0x3 line.long 0x00 "SEC0_SSTAT56,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9C8++0x3 line.long 0x00 "SEC0_SCTL57,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9CC++0x3 line.long 0x00 "SEC0_SSTAT57,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9D0++0x3 line.long 0x00 "SEC0_SCTL58,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9D4++0x3 line.long 0x00 "SEC0_SSTAT58,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9D8++0x3 line.long 0x00 "SEC0_SCTL59,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9DC++0x3 line.long 0x00 "SEC0_SSTAT59,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9E0++0x3 line.long 0x00 "SEC0_SCTL60,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9E4++0x3 line.long 0x00 "SEC0_SSTAT60,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9E8++0x3 line.long 0x00 "SEC0_SCTL61,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9EC++0x3 line.long 0x00 "SEC0_SSTAT61,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9F0++0x3 line.long 0x00 "SEC0_SCTL62,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9F4++0x3 line.long 0x00 "SEC0_SSTAT62,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0x9F8++0x3 line.long 0x00 "SEC0_SCTL63,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0x9FC++0x3 line.long 0x00 "SEC0_SSTAT63,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA00++0x3 line.long 0x00 "SEC0_SCTL64,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA04++0x3 line.long 0x00 "SEC0_SSTAT64,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA08++0x3 line.long 0x00 "SEC0_SCTL65,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA0C++0x3 line.long 0x00 "SEC0_SSTAT65,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA10++0x3 line.long 0x00 "SEC0_SCTL66,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA14++0x3 line.long 0x00 "SEC0_SSTAT66,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA18++0x3 line.long 0x00 "SEC0_SCTL67,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA1C++0x3 line.long 0x00 "SEC0_SSTAT67,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA20++0x3 line.long 0x00 "SEC0_SCTL68,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA24++0x3 line.long 0x00 "SEC0_SSTAT68,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA28++0x3 line.long 0x00 "SEC0_SCTL69,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA2C++0x3 line.long 0x00 "SEC0_SSTAT69,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA30++0x3 line.long 0x00 "SEC0_SCTL70,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA34++0x3 line.long 0x00 "SEC0_SSTAT70,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA38++0x3 line.long 0x00 "SEC0_SCTL71,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA3C++0x3 line.long 0x00 "SEC0_SSTAT71,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA40++0x3 line.long 0x00 "SEC0_SCTL72,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA44++0x3 line.long 0x00 "SEC0_SSTAT72,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA48++0x3 line.long 0x00 "SEC0_SCTL73,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA4C++0x3 line.long 0x00 "SEC0_SSTAT73,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA50++0x3 line.long 0x00 "SEC0_SCTL74,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA54++0x3 line.long 0x00 "SEC0_SSTAT74,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA58++0x3 line.long 0x00 "SEC0_SCTL75,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA5C++0x3 line.long 0x00 "SEC0_SSTAT75,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA60++0x3 line.long 0x00 "SEC0_SCTL76,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA64++0x3 line.long 0x00 "SEC0_SSTAT76,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA68++0x3 line.long 0x00 "SEC0_SCTL77,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA6C++0x3 line.long 0x00 "SEC0_SSTAT77,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA70++0x3 line.long 0x00 "SEC0_SCTL78,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA74++0x3 line.long 0x00 "SEC0_SSTAT78,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA78++0x3 line.long 0x00 "SEC0_SCTL79,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA7C++0x3 line.long 0x00 "SEC0_SSTAT79,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA80++0x3 line.long 0x00 "SEC0_SCTL80,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA84++0x3 line.long 0x00 "SEC0_SSTAT80,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA88++0x3 line.long 0x00 "SEC0_SCTL81,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA8C++0x3 line.long 0x00 "SEC0_SSTAT81,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA90++0x3 line.long 0x00 "SEC0_SCTL82,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA94++0x3 line.long 0x00 "SEC0_SSTAT82,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xA98++0x3 line.long 0x00 "SEC0_SCTL83,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xA9C++0x3 line.long 0x00 "SEC0_SSTAT83,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAA0++0x3 line.long 0x00 "SEC0_SCTL84,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAA4++0x3 line.long 0x00 "SEC0_SSTAT84,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAA8++0x3 line.long 0x00 "SEC0_SCTL85,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAAC++0x3 line.long 0x00 "SEC0_SSTAT85,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAB0++0x3 line.long 0x00 "SEC0_SCTL86,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAB4++0x3 line.long 0x00 "SEC0_SSTAT86,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAB8++0x3 line.long 0x00 "SEC0_SCTL87,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xABC++0x3 line.long 0x00 "SEC0_SSTAT87,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAC0++0x3 line.long 0x00 "SEC0_SCTL88,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAC4++0x3 line.long 0x00 "SEC0_SSTAT88,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAC8++0x3 line.long 0x00 "SEC0_SCTL89,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xACC++0x3 line.long 0x00 "SEC0_SSTAT89,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAD0++0x3 line.long 0x00 "SEC0_SCTL90,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAD4++0x3 line.long 0x00 "SEC0_SSTAT90,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAD8++0x3 line.long 0x00 "SEC0_SCTL91,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xADC++0x3 line.long 0x00 "SEC0_SSTAT91,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAE0++0x3 line.long 0x00 "SEC0_SCTL92,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAE4++0x3 line.long 0x00 "SEC0_SSTAT92,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAE8++0x3 line.long 0x00 "SEC0_SCTL93,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAEC++0x3 line.long 0x00 "SEC0_SSTAT93,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAF0++0x3 line.long 0x00 "SEC0_SCTL94,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAF4++0x3 line.long 0x00 "SEC0_SSTAT94,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xAF8++0x3 line.long 0x00 "SEC0_SCTL95,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xAFC++0x3 line.long 0x00 "SEC0_SSTAT95,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB00++0x3 line.long 0x00 "SEC0_SCTL96,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB04++0x3 line.long 0x00 "SEC0_SSTAT96,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB08++0x3 line.long 0x00 "SEC0_SCTL97,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB0C++0x3 line.long 0x00 "SEC0_SSTAT97,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB10++0x3 line.long 0x00 "SEC0_SCTL98,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB14++0x3 line.long 0x00 "SEC0_SSTAT98,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB18++0x3 line.long 0x00 "SEC0_SCTL99,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB1C++0x3 line.long 0x00 "SEC0_SSTAT99,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB20++0x3 line.long 0x00 "SEC0_SCTL100,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB24++0x3 line.long 0x00 "SEC0_SSTAT100,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB28++0x3 line.long 0x00 "SEC0_SCTL101,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB2C++0x3 line.long 0x00 "SEC0_SSTAT101,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB30++0x3 line.long 0x00 "SEC0_SCTL102,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB34++0x3 line.long 0x00 "SEC0_SSTAT102,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB38++0x3 line.long 0x00 "SEC0_SCTL103,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB3C++0x3 line.long 0x00 "SEC0_SSTAT103,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB40++0x3 line.long 0x00 "SEC0_SCTL104,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB44++0x3 line.long 0x00 "SEC0_SSTAT104,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB48++0x3 line.long 0x00 "SEC0_SCTL105,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB4C++0x3 line.long 0x00 "SEC0_SSTAT105,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB50++0x3 line.long 0x00 "SEC0_SCTL106,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB54++0x3 line.long 0x00 "SEC0_SSTAT106,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB58++0x3 line.long 0x00 "SEC0_SCTL107,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB5C++0x3 line.long 0x00 "SEC0_SSTAT107,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB60++0x3 line.long 0x00 "SEC0_SCTL108,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB64++0x3 line.long 0x00 "SEC0_SSTAT108,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB68++0x3 line.long 0x00 "SEC0_SCTL109,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB6C++0x3 line.long 0x00 "SEC0_SSTAT109,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB70++0x3 line.long 0x00 "SEC0_SCTL110,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB74++0x3 line.long 0x00 "SEC0_SSTAT110,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB78++0x3 line.long 0x00 "SEC0_SCTL111,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB7C++0x3 line.long 0x00 "SEC0_SSTAT111,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB80++0x3 line.long 0x00 "SEC0_SCTL112,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB84++0x3 line.long 0x00 "SEC0_SSTAT112,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB88++0x3 line.long 0x00 "SEC0_SCTL113,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB8C++0x3 line.long 0x00 "SEC0_SSTAT113,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB90++0x3 line.long 0x00 "SEC0_SCTL114,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB94++0x3 line.long 0x00 "SEC0_SSTAT114,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xB98++0x3 line.long 0x00 "SEC0_SCTL115,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xB9C++0x3 line.long 0x00 "SEC0_SSTAT115,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBA0++0x3 line.long 0x00 "SEC0_SCTL116,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBA4++0x3 line.long 0x00 "SEC0_SSTAT116,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBA8++0x3 line.long 0x00 "SEC0_SCTL117,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBAC++0x3 line.long 0x00 "SEC0_SSTAT117,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBB0++0x3 line.long 0x00 "SEC0_SCTL118,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBB4++0x3 line.long 0x00 "SEC0_SSTAT118,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBB8++0x3 line.long 0x00 "SEC0_SCTL119,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBBC++0x3 line.long 0x00 "SEC0_SSTAT119,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBC0++0x3 line.long 0x00 "SEC0_SCTL120,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBC4++0x3 line.long 0x00 "SEC0_SSTAT120,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBC8++0x3 line.long 0x00 "SEC0_SCTL121,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBCC++0x3 line.long 0x00 "SEC0_SSTAT121,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBD0++0x3 line.long 0x00 "SEC0_SCTL122,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBD4++0x3 line.long 0x00 "SEC0_SSTAT122,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBD8++0x3 line.long 0x00 "SEC0_SCTL123,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBDC++0x3 line.long 0x00 "SEC0_SSTAT123,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBE0++0x3 line.long 0x00 "SEC0_SCTL124,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBE4++0x3 line.long 0x00 "SEC0_SSTAT124,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBE8++0x3 line.long 0x00 "SEC0_SCTL125,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBEC++0x3 line.long 0x00 "SEC0_SSTAT125,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBF0++0x3 line.long 0x00 "SEC0_SCTL126,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBF4++0x3 line.long 0x00 "SEC0_SSTAT126,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xBF8++0x3 line.long 0x00 "SEC0_SCTL127,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xBFC++0x3 line.long 0x00 "SEC0_SSTAT127,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC00++0x3 line.long 0x00 "SEC0_SCTL128,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC04++0x3 line.long 0x00 "SEC0_SSTAT128,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC08++0x3 line.long 0x00 "SEC0_SCTL129,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC0C++0x3 line.long 0x00 "SEC0_SSTAT129,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC10++0x3 line.long 0x00 "SEC0_SCTL130,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC14++0x3 line.long 0x00 "SEC0_SSTAT130,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC18++0x3 line.long 0x00 "SEC0_SCTL131,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC1C++0x3 line.long 0x00 "SEC0_SSTAT131,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC20++0x3 line.long 0x00 "SEC0_SCTL132,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC24++0x3 line.long 0x00 "SEC0_SSTAT132,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC28++0x3 line.long 0x00 "SEC0_SCTL133,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC2C++0x3 line.long 0x00 "SEC0_SSTAT133,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC30++0x3 line.long 0x00 "SEC0_SCTL134,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC34++0x3 line.long 0x00 "SEC0_SSTAT134,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC38++0x3 line.long 0x00 "SEC0_SCTL135,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC3C++0x3 line.long 0x00 "SEC0_SSTAT135,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC40++0x3 line.long 0x00 "SEC0_SCTL136,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC44++0x3 line.long 0x00 "SEC0_SSTAT136,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC48++0x3 line.long 0x00 "SEC0_SCTL137,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC4C++0x3 line.long 0x00 "SEC0_SSTAT137,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC50++0x3 line.long 0x00 "SEC0_SCTL138,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC54++0x3 line.long 0x00 "SEC0_SSTAT138,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC58++0x3 line.long 0x00 "SEC0_SCTL139,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC5C++0x3 line.long 0x00 "SEC0_SSTAT139,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC60++0x3 line.long 0x00 "SEC0_SCTL140,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC64++0x3 line.long 0x00 "SEC0_SSTAT140,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC68++0x3 line.long 0x00 "SEC0_SCTL141,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC6C++0x3 line.long 0x00 "SEC0_SSTAT141,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC70++0x3 line.long 0x00 "SEC0_SCTL142,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC74++0x3 line.long 0x00 "SEC0_SSTAT142,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC78++0x3 line.long 0x00 "SEC0_SCTL143,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC7C++0x3 line.long 0x00 "SEC0_SSTAT143,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC80++0x3 line.long 0x00 "SEC0_SCTL144,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC84++0x3 line.long 0x00 "SEC0_SSTAT144,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC88++0x3 line.long 0x00 "SEC0_SCTL145,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC8C++0x3 line.long 0x00 "SEC0_SSTAT145,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC90++0x3 line.long 0x00 "SEC0_SCTL146,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC94++0x3 line.long 0x00 "SEC0_SSTAT146,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xC98++0x3 line.long 0x00 "SEC0_SCTL147,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xC9C++0x3 line.long 0x00 "SEC0_SSTAT147,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCA0++0x3 line.long 0x00 "SEC0_SCTL148,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCA4++0x3 line.long 0x00 "SEC0_SSTAT148,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCA8++0x3 line.long 0x00 "SEC0_SCTL149,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCAC++0x3 line.long 0x00 "SEC0_SSTAT149,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCB0++0x3 line.long 0x00 "SEC0_SCTL150,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCB4++0x3 line.long 0x00 "SEC0_SSTAT150,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCB8++0x3 line.long 0x00 "SEC0_SCTL151,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCBC++0x3 line.long 0x00 "SEC0_SSTAT151,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCC0++0x3 line.long 0x00 "SEC0_SCTL152,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCC4++0x3 line.long 0x00 "SEC0_SSTAT152,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCC8++0x3 line.long 0x00 "SEC0_SCTL153,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCCC++0x3 line.long 0x00 "SEC0_SSTAT153,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCD0++0x3 line.long 0x00 "SEC0_SCTL154,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCD4++0x3 line.long 0x00 "SEC0_SSTAT154,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCD8++0x3 line.long 0x00 "SEC0_SCTL155,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCDC++0x3 line.long 0x00 "SEC0_SSTAT155,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCE0++0x3 line.long 0x00 "SEC0_SCTL156,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCE4++0x3 line.long 0x00 "SEC0_SSTAT156,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCE8++0x3 line.long 0x00 "SEC0_SCTL157,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCEC++0x3 line.long 0x00 "SEC0_SSTAT157,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCF0++0x3 line.long 0x00 "SEC0_SCTL158,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCF4++0x3 line.long 0x00 "SEC0_SSTAT158,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xCF8++0x3 line.long 0x00 "SEC0_SCTL159,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xCFC++0x3 line.long 0x00 "SEC0_SSTAT159,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD00++0x3 line.long 0x00 "SEC0_SCTL160,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD04++0x3 line.long 0x00 "SEC0_SSTAT160,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD08++0x3 line.long 0x00 "SEC0_SCTL161,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD0C++0x3 line.long 0x00 "SEC0_SSTAT161,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD10++0x3 line.long 0x00 "SEC0_SCTL162,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD14++0x3 line.long 0x00 "SEC0_SSTAT162,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD18++0x3 line.long 0x00 "SEC0_SCTL163,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD1C++0x3 line.long 0x00 "SEC0_SSTAT163,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD20++0x3 line.long 0x00 "SEC0_SCTL164,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD24++0x3 line.long 0x00 "SEC0_SSTAT164,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD28++0x3 line.long 0x00 "SEC0_SCTL165,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD2C++0x3 line.long 0x00 "SEC0_SSTAT165,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD30++0x3 line.long 0x00 "SEC0_SCTL166,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD34++0x3 line.long 0x00 "SEC0_SSTAT166,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD38++0x3 line.long 0x00 "SEC0_SCTL167,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD3C++0x3 line.long 0x00 "SEC0_SSTAT167,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD40++0x3 line.long 0x00 "SEC0_SCTL168,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD44++0x3 line.long 0x00 "SEC0_SSTAT168,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD48++0x3 line.long 0x00 "SEC0_SCTL169,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD4C++0x3 line.long 0x00 "SEC0_SSTAT169,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD50++0x3 line.long 0x00 "SEC0_SCTL170,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD54++0x3 line.long 0x00 "SEC0_SSTAT170,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD58++0x3 line.long 0x00 "SEC0_SCTL171,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD5C++0x3 line.long 0x00 "SEC0_SSTAT171,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD60++0x3 line.long 0x00 "SEC0_SCTL172,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD64++0x3 line.long 0x00 "SEC0_SSTAT172,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD68++0x3 line.long 0x00 "SEC0_SCTL173,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD6C++0x3 line.long 0x00 "SEC0_SSTAT173,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD70++0x3 line.long 0x00 "SEC0_SCTL174,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD74++0x3 line.long 0x00 "SEC0_SSTAT174,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD78++0x3 line.long 0x00 "SEC0_SCTL175,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD7C++0x3 line.long 0x00 "SEC0_SSTAT175,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD80++0x3 line.long 0x00 "SEC0_SCTL176,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD84++0x3 line.long 0x00 "SEC0_SSTAT176,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD88++0x3 line.long 0x00 "SEC0_SCTL177,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD8C++0x3 line.long 0x00 "SEC0_SSTAT177,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD90++0x3 line.long 0x00 "SEC0_SCTL178,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD94++0x3 line.long 0x00 "SEC0_SSTAT178,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xD98++0x3 line.long 0x00 "SEC0_SCTL179,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xD9C++0x3 line.long 0x00 "SEC0_SSTAT179,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDA0++0x3 line.long 0x00 "SEC0_SCTL180,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDA4++0x3 line.long 0x00 "SEC0_SSTAT180,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDA8++0x3 line.long 0x00 "SEC0_SCTL181,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDAC++0x3 line.long 0x00 "SEC0_SSTAT181,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDB0++0x3 line.long 0x00 "SEC0_SCTL182,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDB4++0x3 line.long 0x00 "SEC0_SSTAT182,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDB8++0x3 line.long 0x00 "SEC0_SCTL183,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDBC++0x3 line.long 0x00 "SEC0_SSTAT183,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDC0++0x3 line.long 0x00 "SEC0_SCTL184,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDC4++0x3 line.long 0x00 "SEC0_SSTAT184,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDC8++0x3 line.long 0x00 "SEC0_SCTL185,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDCC++0x3 line.long 0x00 "SEC0_SSTAT185,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDD0++0x3 line.long 0x00 "SEC0_SCTL186,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDD4++0x3 line.long 0x00 "SEC0_SSTAT186,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDD8++0x3 line.long 0x00 "SEC0_SCTL187,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDDC++0x3 line.long 0x00 "SEC0_SSTAT187,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDE0++0x3 line.long 0x00 "SEC0_SCTL188,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDE4++0x3 line.long 0x00 "SEC0_SSTAT188,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDE8++0x3 line.long 0x00 "SEC0_SCTL189,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDEC++0x3 line.long 0x00 "SEC0_SSTAT189,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDF0++0x3 line.long 0x00 "SEC0_SCTL190,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDF4++0x3 line.long 0x00 "SEC0_SSTAT190,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xDF8++0x3 line.long 0x00 "SEC0_SCTL191,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xDFC++0x3 line.long 0x00 "SEC0_SSTAT191,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE00++0x3 line.long 0x00 "SEC0_SCTL192,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE04++0x3 line.long 0x00 "SEC0_SSTAT192,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE08++0x3 line.long 0x00 "SEC0_SCTL193,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE0C++0x3 line.long 0x00 "SEC0_SSTAT193,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE10++0x3 line.long 0x00 "SEC0_SCTL194,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE14++0x3 line.long 0x00 "SEC0_SSTAT194,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE18++0x3 line.long 0x00 "SEC0_SCTL195,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE1C++0x3 line.long 0x00 "SEC0_SSTAT195,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE20++0x3 line.long 0x00 "SEC0_SCTL196,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE24++0x3 line.long 0x00 "SEC0_SSTAT196,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE28++0x3 line.long 0x00 "SEC0_SCTL197,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE2C++0x3 line.long 0x00 "SEC0_SSTAT197,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE30++0x3 line.long 0x00 "SEC0_SCTL198,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE34++0x3 line.long 0x00 "SEC0_SSTAT198,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE38++0x3 line.long 0x00 "SEC0_SCTL199,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE3C++0x3 line.long 0x00 "SEC0_SSTAT199,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE40++0x3 line.long 0x00 "SEC0_SCTL200,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE44++0x3 line.long 0x00 "SEC0_SSTAT200,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE48++0x3 line.long 0x00 "SEC0_SCTL201,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE4C++0x3 line.long 0x00 "SEC0_SSTAT201,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE50++0x3 line.long 0x00 "SEC0_SCTL202,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE54++0x3 line.long 0x00 "SEC0_SSTAT202,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE58++0x3 line.long 0x00 "SEC0_SCTL203,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE5C++0x3 line.long 0x00 "SEC0_SSTAT203,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE60++0x3 line.long 0x00 "SEC0_SCTL204,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE64++0x3 line.long 0x00 "SEC0_SSTAT204,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE68++0x3 line.long 0x00 "SEC0_SCTL205,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE6C++0x3 line.long 0x00 "SEC0_SSTAT205,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE70++0x3 line.long 0x00 "SEC0_SCTL206,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE74++0x3 line.long 0x00 "SEC0_SSTAT206,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE78++0x3 line.long 0x00 "SEC0_SCTL207,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE7C++0x3 line.long 0x00 "SEC0_SSTAT207,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE80++0x3 line.long 0x00 "SEC0_SCTL208,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE84++0x3 line.long 0x00 "SEC0_SSTAT208,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE88++0x3 line.long 0x00 "SEC0_SCTL209,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE8C++0x3 line.long 0x00 "SEC0_SSTAT209,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE90++0x3 line.long 0x00 "SEC0_SCTL210,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE94++0x3 line.long 0x00 "SEC0_SSTAT210,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xE98++0x3 line.long 0x00 "SEC0_SCTL211,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xE9C++0x3 line.long 0x00 "SEC0_SSTAT211,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEA0++0x3 line.long 0x00 "SEC0_SCTL212,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEA4++0x3 line.long 0x00 "SEC0_SSTAT212,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEA8++0x3 line.long 0x00 "SEC0_SCTL213,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEAC++0x3 line.long 0x00 "SEC0_SSTAT213,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEB0++0x3 line.long 0x00 "SEC0_SCTL214,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEB4++0x3 line.long 0x00 "SEC0_SSTAT214,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEB8++0x3 line.long 0x00 "SEC0_SCTL215,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEBC++0x3 line.long 0x00 "SEC0_SSTAT215,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEC0++0x3 line.long 0x00 "SEC0_SCTL216,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEC4++0x3 line.long 0x00 "SEC0_SSTAT216,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEC8++0x3 line.long 0x00 "SEC0_SCTL217,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xECC++0x3 line.long 0x00 "SEC0_SSTAT217,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xED0++0x3 line.long 0x00 "SEC0_SCTL218,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xED4++0x3 line.long 0x00 "SEC0_SSTAT218,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xED8++0x3 line.long 0x00 "SEC0_SCTL219,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEDC++0x3 line.long 0x00 "SEC0_SSTAT219,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEE0++0x3 line.long 0x00 "SEC0_SCTL220,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEE4++0x3 line.long 0x00 "SEC0_SSTAT220,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEE8++0x3 line.long 0x00 "SEC0_SCTL221,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEEC++0x3 line.long 0x00 "SEC0_SSTAT221,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEF0++0x3 line.long 0x00 "SEC0_SCTL222,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEF4++0x3 line.long 0x00 "SEC0_SSTAT222,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xEF8++0x3 line.long 0x00 "SEC0_SCTL223,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xEFC++0x3 line.long 0x00 "SEC0_SSTAT223,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF00++0x3 line.long 0x00 "SEC0_SCTL224,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF04++0x3 line.long 0x00 "SEC0_SSTAT224,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF08++0x3 line.long 0x00 "SEC0_SCTL225,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF0C++0x3 line.long 0x00 "SEC0_SSTAT225,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF10++0x3 line.long 0x00 "SEC0_SCTL226,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF14++0x3 line.long 0x00 "SEC0_SSTAT226,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF18++0x3 line.long 0x00 "SEC0_SCTL227,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF1C++0x3 line.long 0x00 "SEC0_SSTAT227,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF20++0x3 line.long 0x00 "SEC0_SCTL228,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF24++0x3 line.long 0x00 "SEC0_SSTAT228,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF28++0x3 line.long 0x00 "SEC0_SCTL229,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF2C++0x3 line.long 0x00 "SEC0_SSTAT229,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF30++0x3 line.long 0x00 "SEC0_SCTL230,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF34++0x3 line.long 0x00 "SEC0_SSTAT230,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF38++0x3 line.long 0x00 "SEC0_SCTL231,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF3C++0x3 line.long 0x00 "SEC0_SSTAT231,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF40++0x3 line.long 0x00 "SEC0_SCTL232,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF44++0x3 line.long 0x00 "SEC0_SSTAT232,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF48++0x3 line.long 0x00 "SEC0_SCTL233,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF4C++0x3 line.long 0x00 "SEC0_SSTAT233,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF50++0x3 line.long 0x00 "SEC0_SCTL234,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF54++0x3 line.long 0x00 "SEC0_SSTAT234,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF58++0x3 line.long 0x00 "SEC0_SCTL235,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF5C++0x3 line.long 0x00 "SEC0_SSTAT235,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF60++0x3 line.long 0x00 "SEC0_SCTL236,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF64++0x3 line.long 0x00 "SEC0_SSTAT236,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF68++0x3 line.long 0x00 "SEC0_SCTL237,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF6C++0x3 line.long 0x00 "SEC0_SSTAT237,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF70++0x3 line.long 0x00 "SEC0_SCTL238,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF74++0x3 line.long 0x00 "SEC0_SSTAT238,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF78++0x3 line.long 0x00 "SEC0_SCTL239,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF7C++0x3 line.long 0x00 "SEC0_SSTAT239,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF80++0x3 line.long 0x00 "SEC0_SCTL240,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF84++0x3 line.long 0x00 "SEC0_SSTAT240,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF88++0x3 line.long 0x00 "SEC0_SCTL241,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF8C++0x3 line.long 0x00 "SEC0_SSTAT241,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF90++0x3 line.long 0x00 "SEC0_SCTL242,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF94++0x3 line.long 0x00 "SEC0_SSTAT242,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xF98++0x3 line.long 0x00 "SEC0_SCTL243,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xF9C++0x3 line.long 0x00 "SEC0_SSTAT243,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFA0++0x3 line.long 0x00 "SEC0_SCTL244,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFA4++0x3 line.long 0x00 "SEC0_SSTAT244,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFA8++0x3 line.long 0x00 "SEC0_SCTL245,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFAC++0x3 line.long 0x00 "SEC0_SSTAT245,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFB0++0x3 line.long 0x00 "SEC0_SCTL246,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFB4++0x3 line.long 0x00 "SEC0_SSTAT246,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFB8++0x3 line.long 0x00 "SEC0_SCTL247,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFBC++0x3 line.long 0x00 "SEC0_SSTAT247,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFC0++0x3 line.long 0x00 "SEC0_SCTL248,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFC4++0x3 line.long 0x00 "SEC0_SSTAT248,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFC8++0x3 line.long 0x00 "SEC0_SCTL249,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFCC++0x3 line.long 0x00 "SEC0_SSTAT249,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFD0++0x3 line.long 0x00 "SEC0_SCTL250,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFD4++0x3 line.long 0x00 "SEC0_SSTAT250,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFD8++0x3 line.long 0x00 "SEC0_SCTL251,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFDC++0x3 line.long 0x00 "SEC0_SSTAT251,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFE0++0x3 line.long 0x00 "SEC0_SCTL252,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFE4++0x3 line.long 0x00 "SEC0_SSTAT252,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFE8++0x3 line.long 0x00 "SEC0_SCTL253,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFEC++0x3 line.long 0x00 "SEC0_SSTAT253,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFF0++0x3 line.long 0x00 "SEC0_SCTL254,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFF4++0x3 line.long 0x00 "SEC0_SSTAT254,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" group.long 0xFF8++0x3 line.long 0x00 "SEC0_SCTL255,SEC0 Source Control Register n" bitfld.long 0x00 31. " LOCK ,Lock" "0,1" bitfld.long 0x00 24.--27. " CTG ,Core Target Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " GRP ,Group Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 8.--15. 1. " PRIO ,Priority Level Select" bitfld.long 0x00 4. " ERREN ,Error Enable" "0,1" bitfld.long 0x00 3. " ES ,Edge Select" "0,1" newline bitfld.long 0x00 2. " SEN ,Source (signal) Enable" "0,1" bitfld.long 0x00 1. " FEN ,Fault Enable" "0,1" bitfld.long 0x00 0. " IEN ,Interrupt Enable" "0,1" group.long 0xFFC++0x3 line.long 0x00 "SEC0_SSTAT255,SEC0 Source Status Register n" hexmask.long.byte 0x00 16.--23. 1. " CHID ,Channel ID" bitfld.long 0x00 9. " ACT ,Active Source" "0,1" bitfld.long 0x00 8. " PND ,Pending Source" "0,1" newline bitfld.long 0x00 4.--5. " ERRC ,Error Cause" "0,1,2,3" bitfld.long 0x00 1. " ERR ,Error" "0,1" tree.end tree "SMPU (System Memory Protection Unit)" tree "SMPU11" base ad:0x310A1000 width 20. group.long 0x0++0x3 line.long 0x00 "SMPU11_CTL,SMPU11 SMPU Control Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "0,1" bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "0,1" newline bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "0,1" bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "0,1" bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "0,1" group.long 0x4++0x3 line.long 0x00 "SMPU11_STAT,SMPU11 SMPU Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "0,1" newline bitfld.long 0x00 2. " BERR ,Bus Error" "0,1" bitfld.long 0x00 1. " IOVR ,Interrupt Overrun" "0,1" bitfld.long 0x00 0. " IRQ ,Interrupt Request" "0,1" group.long 0x8++0x3 line.long 0x00 "SMPU11_IADDR,SMPU11 Interrupt Address Register" group.long 0xC++0x3 line.long 0x00 "SMPU11_IDTLS,SMPU11 Interrupt Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status" "0,1" group.long 0x10++0x3 line.long 0x00 "SMPU11_BADDR,SMPU11 Bus Error Address Register" group.long 0x14++0x3 line.long 0x00 "SMPU11_BDTLS,SMPU11 Bus Error Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status Register" "0,1" group.long 0x20++0x3 line.long 0x00 "SMPU11_RCTL0,SMPU11 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SMPU11_RADDR0,SMPU11 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x28++0x3 line.long 0x00 "SMPU11_RIDA0,SMPU11 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x2C++0x3 line.long 0x00 "SMPU11_RIDMSKA0,SMPU11 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x30++0x3 line.long 0x00 "SMPU11_RIDB0,SMPU11 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x34++0x3 line.long 0x00 "SMPU11_RIDMSKB0,SMPU11 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x38++0x3 line.long 0x00 "SMPU11_RCTL1,SMPU11 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "SMPU11_RADDR1,SMPU11 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x40++0x3 line.long 0x00 "SMPU11_RIDA1,SMPU11 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x44++0x3 line.long 0x00 "SMPU11_RIDMSKA1,SMPU11 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x48++0x3 line.long 0x00 "SMPU11_RIDB1,SMPU11 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x4C++0x3 line.long 0x00 "SMPU11_RIDMSKB1,SMPU11 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x50++0x3 line.long 0x00 "SMPU11_RCTL2,SMPU11 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "SMPU11_RADDR2,SMPU11 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x58++0x3 line.long 0x00 "SMPU11_RIDA2,SMPU11 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x5C++0x3 line.long 0x00 "SMPU11_RIDMSKA2,SMPU11 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x60++0x3 line.long 0x00 "SMPU11_RIDB2,SMPU11 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x64++0x3 line.long 0x00 "SMPU11_RIDMSKB2,SMPU11 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x68++0x3 line.long 0x00 "SMPU11_RCTL3,SMPU11 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x6C++0x3 line.long 0x00 "SMPU11_RADDR3,SMPU11 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x70++0x3 line.long 0x00 "SMPU11_RIDA3,SMPU11 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x74++0x3 line.long 0x00 "SMPU11_RIDMSKA3,SMPU11 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x78++0x3 line.long 0x00 "SMPU11_RIDB3,SMPU11 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x7C++0x3 line.long 0x00 "SMPU11_RIDMSKB3,SMPU11 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x80++0x3 line.long 0x00 "SMPU11_RCTL4,SMPU11 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x84++0x3 line.long 0x00 "SMPU11_RADDR4,SMPU11 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x88++0x3 line.long 0x00 "SMPU11_RIDA4,SMPU11 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x8C++0x3 line.long 0x00 "SMPU11_RIDMSKA4,SMPU11 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x90++0x3 line.long 0x00 "SMPU11_RIDB4,SMPU11 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x94++0x3 line.long 0x00 "SMPU11_RIDMSKB4,SMPU11 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x98++0x3 line.long 0x00 "SMPU11_RCTL5,SMPU11 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x9C++0x3 line.long 0x00 "SMPU11_RADDR5,SMPU11 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xA0++0x3 line.long 0x00 "SMPU11_RIDA5,SMPU11 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xA4++0x3 line.long 0x00 "SMPU11_RIDMSKA5,SMPU11 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xA8++0x3 line.long 0x00 "SMPU11_RIDB5,SMPU11 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xAC++0x3 line.long 0x00 "SMPU11_RIDMSKB5,SMPU11 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xB0++0x3 line.long 0x00 "SMPU11_RCTL6,SMPU11 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xB4++0x3 line.long 0x00 "SMPU11_RADDR6,SMPU11 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xB8++0x3 line.long 0x00 "SMPU11_RIDA6,SMPU11 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xBC++0x3 line.long 0x00 "SMPU11_RIDMSKA6,SMPU11 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xC0++0x3 line.long 0x00 "SMPU11_RIDB6,SMPU11 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xC4++0x3 line.long 0x00 "SMPU11_RIDMSKB6,SMPU11 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xC8++0x3 line.long 0x00 "SMPU11_RCTL7,SMPU11 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xCC++0x3 line.long 0x00 "SMPU11_RADDR7,SMPU11 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xD0++0x3 line.long 0x00 "SMPU11_RIDA7,SMPU11 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xD4++0x3 line.long 0x00 "SMPU11_RIDMSKA7,SMPU11 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xD8++0x3 line.long 0x00 "SMPU11_RIDB7,SMPU11 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xDC++0x3 line.long 0x00 "SMPU11_RIDMSKB7,SMPU11 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x220++0x3 line.long 0x00 "SMPU11_REVID,SMPU11 SMPU Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x00 "SMPU11_SECURECTL,SMPU11 SMPU Control Secure Accesses Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "0,1" newline bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "0,1" bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "0,1" bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "0,1" newline bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "0,1" bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "0,1" bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "0,1" group.long 0x820++0x3 line.long 0x00 "SMPU11_SECURERCTL0,SMPU11 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SMPU11_SECURERCTL1,SMPU11 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x828++0x3 line.long 0x00 "SMPU11_SECURERCTL2,SMPU11 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SMPU11_SECURERCTL3,SMPU11 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x830++0x3 line.long 0x00 "SMPU11_SECURERCTL4,SMPU11 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SMPU11_SECURERCTL5,SMPU11 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x838++0x3 line.long 0x00 "SMPU11_SECURERCTL6,SMPU11 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SMPU11_SECURERCTL7,SMPU11 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" tree.end tree "SMPU12" base ad:0x31012000 width 20. group.long 0x0++0x3 line.long 0x00 "SMPU12_CTL,SMPU12 SMPU Control Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "0,1" bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "0,1" newline bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "0,1" bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "0,1" bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "0,1" group.long 0x4++0x3 line.long 0x00 "SMPU12_STAT,SMPU12 SMPU Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "0,1" newline bitfld.long 0x00 2. " BERR ,Bus Error" "0,1" bitfld.long 0x00 1. " IOVR ,Interrupt Overrun" "0,1" bitfld.long 0x00 0. " IRQ ,Interrupt Request" "0,1" group.long 0x8++0x3 line.long 0x00 "SMPU12_IADDR,SMPU12 Interrupt Address Register" group.long 0xC++0x3 line.long 0x00 "SMPU12_IDTLS,SMPU12 Interrupt Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status" "0,1" group.long 0x10++0x3 line.long 0x00 "SMPU12_BADDR,SMPU12 Bus Error Address Register" group.long 0x14++0x3 line.long 0x00 "SMPU12_BDTLS,SMPU12 Bus Error Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status Register" "0,1" group.long 0x20++0x3 line.long 0x00 "SMPU12_RCTL0,SMPU12 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SMPU12_RADDR0,SMPU12 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x28++0x3 line.long 0x00 "SMPU12_RIDA0,SMPU12 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x2C++0x3 line.long 0x00 "SMPU12_RIDMSKA0,SMPU12 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x30++0x3 line.long 0x00 "SMPU12_RIDB0,SMPU12 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x34++0x3 line.long 0x00 "SMPU12_RIDMSKB0,SMPU12 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x38++0x3 line.long 0x00 "SMPU12_RCTL1,SMPU12 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "SMPU12_RADDR1,SMPU12 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x40++0x3 line.long 0x00 "SMPU12_RIDA1,SMPU12 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x44++0x3 line.long 0x00 "SMPU12_RIDMSKA1,SMPU12 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x48++0x3 line.long 0x00 "SMPU12_RIDB1,SMPU12 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x4C++0x3 line.long 0x00 "SMPU12_RIDMSKB1,SMPU12 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x50++0x3 line.long 0x00 "SMPU12_RCTL2,SMPU12 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "SMPU12_RADDR2,SMPU12 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x58++0x3 line.long 0x00 "SMPU12_RIDA2,SMPU12 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x5C++0x3 line.long 0x00 "SMPU12_RIDMSKA2,SMPU12 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x60++0x3 line.long 0x00 "SMPU12_RIDB2,SMPU12 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x64++0x3 line.long 0x00 "SMPU12_RIDMSKB2,SMPU12 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x68++0x3 line.long 0x00 "SMPU12_RCTL3,SMPU12 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x6C++0x3 line.long 0x00 "SMPU12_RADDR3,SMPU12 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x70++0x3 line.long 0x00 "SMPU12_RIDA3,SMPU12 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x74++0x3 line.long 0x00 "SMPU12_RIDMSKA3,SMPU12 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x78++0x3 line.long 0x00 "SMPU12_RIDB3,SMPU12 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x7C++0x3 line.long 0x00 "SMPU12_RIDMSKB3,SMPU12 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x80++0x3 line.long 0x00 "SMPU12_RCTL4,SMPU12 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x84++0x3 line.long 0x00 "SMPU12_RADDR4,SMPU12 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x88++0x3 line.long 0x00 "SMPU12_RIDA4,SMPU12 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x8C++0x3 line.long 0x00 "SMPU12_RIDMSKA4,SMPU12 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x90++0x3 line.long 0x00 "SMPU12_RIDB4,SMPU12 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x94++0x3 line.long 0x00 "SMPU12_RIDMSKB4,SMPU12 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x98++0x3 line.long 0x00 "SMPU12_RCTL5,SMPU12 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x9C++0x3 line.long 0x00 "SMPU12_RADDR5,SMPU12 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xA0++0x3 line.long 0x00 "SMPU12_RIDA5,SMPU12 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xA4++0x3 line.long 0x00 "SMPU12_RIDMSKA5,SMPU12 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xA8++0x3 line.long 0x00 "SMPU12_RIDB5,SMPU12 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xAC++0x3 line.long 0x00 "SMPU12_RIDMSKB5,SMPU12 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xB0++0x3 line.long 0x00 "SMPU12_RCTL6,SMPU12 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xB4++0x3 line.long 0x00 "SMPU12_RADDR6,SMPU12 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xB8++0x3 line.long 0x00 "SMPU12_RIDA6,SMPU12 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xBC++0x3 line.long 0x00 "SMPU12_RIDMSKA6,SMPU12 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xC0++0x3 line.long 0x00 "SMPU12_RIDB6,SMPU12 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xC4++0x3 line.long 0x00 "SMPU12_RIDMSKB6,SMPU12 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xC8++0x3 line.long 0x00 "SMPU12_RCTL7,SMPU12 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xCC++0x3 line.long 0x00 "SMPU12_RADDR7,SMPU12 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xD0++0x3 line.long 0x00 "SMPU12_RIDA7,SMPU12 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xD4++0x3 line.long 0x00 "SMPU12_RIDMSKA7,SMPU12 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xD8++0x3 line.long 0x00 "SMPU12_RIDB7,SMPU12 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xDC++0x3 line.long 0x00 "SMPU12_RIDMSKB7,SMPU12 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x220++0x3 line.long 0x00 "SMPU12_REVID,SMPU12 SMPU Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x00 "SMPU12_SECURECTL,SMPU12 SMPU Control Secure Accesses Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "0,1" newline bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "0,1" bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "0,1" bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "0,1" newline bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "0,1" bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "0,1" bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "0,1" group.long 0x820++0x3 line.long 0x00 "SMPU12_SECURERCTL0,SMPU12 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SMPU12_SECURERCTL1,SMPU12 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x828++0x3 line.long 0x00 "SMPU12_SECURERCTL2,SMPU12 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SMPU12_SECURERCTL3,SMPU12 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x830++0x3 line.long 0x00 "SMPU12_SECURERCTL4,SMPU12 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SMPU12_SECURERCTL5,SMPU12 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x838++0x3 line.long 0x00 "SMPU12_SECURERCTL6,SMPU12 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SMPU12_SECURERCTL7,SMPU12 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" tree.end tree "SMPU2" base ad:0x31083000 width 19. group.long 0x0++0x3 line.long 0x00 "SMPU2_CTL,SMPU2 SMPU Control Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "0,1" bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "0,1" newline bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "0,1" bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "0,1" bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "0,1" group.long 0x4++0x3 line.long 0x00 "SMPU2_STAT,SMPU2 SMPU Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "0,1" newline bitfld.long 0x00 2. " BERR ,Bus Error" "0,1" bitfld.long 0x00 1. " IOVR ,Interrupt Overrun" "0,1" bitfld.long 0x00 0. " IRQ ,Interrupt Request" "0,1" group.long 0x8++0x3 line.long 0x00 "SMPU2_IADDR,SMPU2 Interrupt Address Register" group.long 0xC++0x3 line.long 0x00 "SMPU2_IDTLS,SMPU2 Interrupt Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status" "0,1" group.long 0x10++0x3 line.long 0x00 "SMPU2_BADDR,SMPU2 Bus Error Address Register" group.long 0x14++0x3 line.long 0x00 "SMPU2_BDTLS,SMPU2 Bus Error Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status Register" "0,1" group.long 0x20++0x3 line.long 0x00 "SMPU2_RCTL0,SMPU2 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SMPU2_RADDR0,SMPU2 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x28++0x3 line.long 0x00 "SMPU2_RIDA0,SMPU2 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x2C++0x3 line.long 0x00 "SMPU2_RIDMSKA0,SMPU2 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x30++0x3 line.long 0x00 "SMPU2_RIDB0,SMPU2 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x34++0x3 line.long 0x00 "SMPU2_RIDMSKB0,SMPU2 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x38++0x3 line.long 0x00 "SMPU2_RCTL1,SMPU2 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "SMPU2_RADDR1,SMPU2 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x40++0x3 line.long 0x00 "SMPU2_RIDA1,SMPU2 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x44++0x3 line.long 0x00 "SMPU2_RIDMSKA1,SMPU2 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x48++0x3 line.long 0x00 "SMPU2_RIDB1,SMPU2 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x4C++0x3 line.long 0x00 "SMPU2_RIDMSKB1,SMPU2 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x50++0x3 line.long 0x00 "SMPU2_RCTL2,SMPU2 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "SMPU2_RADDR2,SMPU2 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x58++0x3 line.long 0x00 "SMPU2_RIDA2,SMPU2 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x5C++0x3 line.long 0x00 "SMPU2_RIDMSKA2,SMPU2 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x60++0x3 line.long 0x00 "SMPU2_RIDB2,SMPU2 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x64++0x3 line.long 0x00 "SMPU2_RIDMSKB2,SMPU2 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x68++0x3 line.long 0x00 "SMPU2_RCTL3,SMPU2 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x6C++0x3 line.long 0x00 "SMPU2_RADDR3,SMPU2 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x70++0x3 line.long 0x00 "SMPU2_RIDA3,SMPU2 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x74++0x3 line.long 0x00 "SMPU2_RIDMSKA3,SMPU2 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x78++0x3 line.long 0x00 "SMPU2_RIDB3,SMPU2 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x7C++0x3 line.long 0x00 "SMPU2_RIDMSKB3,SMPU2 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x80++0x3 line.long 0x00 "SMPU2_RCTL4,SMPU2 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x84++0x3 line.long 0x00 "SMPU2_RADDR4,SMPU2 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x88++0x3 line.long 0x00 "SMPU2_RIDA4,SMPU2 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x8C++0x3 line.long 0x00 "SMPU2_RIDMSKA4,SMPU2 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x90++0x3 line.long 0x00 "SMPU2_RIDB4,SMPU2 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x94++0x3 line.long 0x00 "SMPU2_RIDMSKB4,SMPU2 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x98++0x3 line.long 0x00 "SMPU2_RCTL5,SMPU2 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x9C++0x3 line.long 0x00 "SMPU2_RADDR5,SMPU2 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xA0++0x3 line.long 0x00 "SMPU2_RIDA5,SMPU2 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xA4++0x3 line.long 0x00 "SMPU2_RIDMSKA5,SMPU2 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xA8++0x3 line.long 0x00 "SMPU2_RIDB5,SMPU2 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xAC++0x3 line.long 0x00 "SMPU2_RIDMSKB5,SMPU2 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xB0++0x3 line.long 0x00 "SMPU2_RCTL6,SMPU2 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xB4++0x3 line.long 0x00 "SMPU2_RADDR6,SMPU2 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xB8++0x3 line.long 0x00 "SMPU2_RIDA6,SMPU2 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xBC++0x3 line.long 0x00 "SMPU2_RIDMSKA6,SMPU2 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xC0++0x3 line.long 0x00 "SMPU2_RIDB6,SMPU2 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xC4++0x3 line.long 0x00 "SMPU2_RIDMSKB6,SMPU2 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xC8++0x3 line.long 0x00 "SMPU2_RCTL7,SMPU2 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xCC++0x3 line.long 0x00 "SMPU2_RADDR7,SMPU2 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xD0++0x3 line.long 0x00 "SMPU2_RIDA7,SMPU2 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xD4++0x3 line.long 0x00 "SMPU2_RIDMSKA7,SMPU2 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xD8++0x3 line.long 0x00 "SMPU2_RIDB7,SMPU2 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xDC++0x3 line.long 0x00 "SMPU2_RIDMSKB7,SMPU2 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x1A0++0x3 line.long 0x00 "SMPU2_EXACADD0,SMPU2 Exclusive Access IDn Address" group.long 0x1A4++0x3 line.long 0x00 "SMPU2_EXACSTAT0,SMPU2 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x1A8++0x3 line.long 0x00 "SMPU2_EXACADD1,SMPU2 Exclusive Access IDn Address" group.long 0x1AC++0x3 line.long 0x00 "SMPU2_EXACSTAT1,SMPU2 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x1B0++0x3 line.long 0x00 "SMPU2_EXACADD2,SMPU2 Exclusive Access IDn Address" group.long 0x1B4++0x3 line.long 0x00 "SMPU2_EXACSTAT2,SMPU2 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x220++0x3 line.long 0x00 "SMPU2_REVID,SMPU2 SMPU Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x00 "SMPU2_SECURECTL,SMPU2 SMPU Control Secure Accesses Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "0,1" newline bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "0,1" bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "0,1" bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "0,1" newline bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "0,1" bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "0,1" bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "0,1" group.long 0x820++0x3 line.long 0x00 "SMPU2_SECURERCTL0,SMPU2 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SMPU2_SECURERCTL1,SMPU2 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x828++0x3 line.long 0x00 "SMPU2_SECURERCTL2,SMPU2 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SMPU2_SECURERCTL3,SMPU2 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x830++0x3 line.long 0x00 "SMPU2_SECURERCTL4,SMPU2 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SMPU2_SECURERCTL5,SMPU2 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x838++0x3 line.long 0x00 "SMPU2_SECURERCTL6,SMPU2 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SMPU2_SECURERCTL7,SMPU2 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" tree.end tree "SMPU3" base ad:0x31084000 width 19. group.long 0x0++0x3 line.long 0x00 "SMPU3_CTL,SMPU3 SMPU Control Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "0,1" bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "0,1" newline bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "0,1" bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "0,1" bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "0,1" group.long 0x4++0x3 line.long 0x00 "SMPU3_STAT,SMPU3 SMPU Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "0,1" newline bitfld.long 0x00 2. " BERR ,Bus Error" "0,1" bitfld.long 0x00 1. " IOVR ,Interrupt Overrun" "0,1" bitfld.long 0x00 0. " IRQ ,Interrupt Request" "0,1" group.long 0x8++0x3 line.long 0x00 "SMPU3_IADDR,SMPU3 Interrupt Address Register" group.long 0xC++0x3 line.long 0x00 "SMPU3_IDTLS,SMPU3 Interrupt Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status" "0,1" group.long 0x10++0x3 line.long 0x00 "SMPU3_BADDR,SMPU3 Bus Error Address Register" group.long 0x14++0x3 line.long 0x00 "SMPU3_BDTLS,SMPU3 Bus Error Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status Register" "0,1" group.long 0x20++0x3 line.long 0x00 "SMPU3_RCTL0,SMPU3 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SMPU3_RADDR0,SMPU3 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x28++0x3 line.long 0x00 "SMPU3_RIDA0,SMPU3 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x2C++0x3 line.long 0x00 "SMPU3_RIDMSKA0,SMPU3 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x30++0x3 line.long 0x00 "SMPU3_RIDB0,SMPU3 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x34++0x3 line.long 0x00 "SMPU3_RIDMSKB0,SMPU3 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x38++0x3 line.long 0x00 "SMPU3_RCTL1,SMPU3 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "SMPU3_RADDR1,SMPU3 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x40++0x3 line.long 0x00 "SMPU3_RIDA1,SMPU3 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x44++0x3 line.long 0x00 "SMPU3_RIDMSKA1,SMPU3 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x48++0x3 line.long 0x00 "SMPU3_RIDB1,SMPU3 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x4C++0x3 line.long 0x00 "SMPU3_RIDMSKB1,SMPU3 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x50++0x3 line.long 0x00 "SMPU3_RCTL2,SMPU3 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "SMPU3_RADDR2,SMPU3 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x58++0x3 line.long 0x00 "SMPU3_RIDA2,SMPU3 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x5C++0x3 line.long 0x00 "SMPU3_RIDMSKA2,SMPU3 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x60++0x3 line.long 0x00 "SMPU3_RIDB2,SMPU3 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x64++0x3 line.long 0x00 "SMPU3_RIDMSKB2,SMPU3 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x68++0x3 line.long 0x00 "SMPU3_RCTL3,SMPU3 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x6C++0x3 line.long 0x00 "SMPU3_RADDR3,SMPU3 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x70++0x3 line.long 0x00 "SMPU3_RIDA3,SMPU3 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x74++0x3 line.long 0x00 "SMPU3_RIDMSKA3,SMPU3 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x78++0x3 line.long 0x00 "SMPU3_RIDB3,SMPU3 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x7C++0x3 line.long 0x00 "SMPU3_RIDMSKB3,SMPU3 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x80++0x3 line.long 0x00 "SMPU3_RCTL4,SMPU3 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x84++0x3 line.long 0x00 "SMPU3_RADDR4,SMPU3 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x88++0x3 line.long 0x00 "SMPU3_RIDA4,SMPU3 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x8C++0x3 line.long 0x00 "SMPU3_RIDMSKA4,SMPU3 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x90++0x3 line.long 0x00 "SMPU3_RIDB4,SMPU3 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x94++0x3 line.long 0x00 "SMPU3_RIDMSKB4,SMPU3 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x98++0x3 line.long 0x00 "SMPU3_RCTL5,SMPU3 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x9C++0x3 line.long 0x00 "SMPU3_RADDR5,SMPU3 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xA0++0x3 line.long 0x00 "SMPU3_RIDA5,SMPU3 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xA4++0x3 line.long 0x00 "SMPU3_RIDMSKA5,SMPU3 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xA8++0x3 line.long 0x00 "SMPU3_RIDB5,SMPU3 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xAC++0x3 line.long 0x00 "SMPU3_RIDMSKB5,SMPU3 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xB0++0x3 line.long 0x00 "SMPU3_RCTL6,SMPU3 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xB4++0x3 line.long 0x00 "SMPU3_RADDR6,SMPU3 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xB8++0x3 line.long 0x00 "SMPU3_RIDA6,SMPU3 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xBC++0x3 line.long 0x00 "SMPU3_RIDMSKA6,SMPU3 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xC0++0x3 line.long 0x00 "SMPU3_RIDB6,SMPU3 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xC4++0x3 line.long 0x00 "SMPU3_RIDMSKB6,SMPU3 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xC8++0x3 line.long 0x00 "SMPU3_RCTL7,SMPU3 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xCC++0x3 line.long 0x00 "SMPU3_RADDR7,SMPU3 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xD0++0x3 line.long 0x00 "SMPU3_RIDA7,SMPU3 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xD4++0x3 line.long 0x00 "SMPU3_RIDMSKA7,SMPU3 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xD8++0x3 line.long 0x00 "SMPU3_RIDB7,SMPU3 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xDC++0x3 line.long 0x00 "SMPU3_RIDMSKB7,SMPU3 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x220++0x3 line.long 0x00 "SMPU3_REVID,SMPU3 SMPU Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x00 "SMPU3_SECURECTL,SMPU3 SMPU Control Secure Accesses Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "0,1" newline bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "0,1" bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "0,1" bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "0,1" newline bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "0,1" bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "0,1" bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "0,1" group.long 0x820++0x3 line.long 0x00 "SMPU3_SECURERCTL0,SMPU3 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SMPU3_SECURERCTL1,SMPU3 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x828++0x3 line.long 0x00 "SMPU3_SECURERCTL2,SMPU3 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SMPU3_SECURERCTL3,SMPU3 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x830++0x3 line.long 0x00 "SMPU3_SECURERCTL4,SMPU3 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SMPU3_SECURERCTL5,SMPU3 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x838++0x3 line.long 0x00 "SMPU3_SECURERCTL6,SMPU3 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SMPU3_SECURERCTL7,SMPU3 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" tree.end tree "SMPU4" base ad:0x31085000 width 19. group.long 0x0++0x3 line.long 0x00 "SMPU4_CTL,SMPU4 SMPU Control Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "0,1" bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "0,1" newline bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "0,1" bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "0,1" bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "0,1" group.long 0x4++0x3 line.long 0x00 "SMPU4_STAT,SMPU4 SMPU Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "0,1" newline bitfld.long 0x00 2. " BERR ,Bus Error" "0,1" bitfld.long 0x00 1. " IOVR ,Interrupt Overrun" "0,1" bitfld.long 0x00 0. " IRQ ,Interrupt Request" "0,1" group.long 0x8++0x3 line.long 0x00 "SMPU4_IADDR,SMPU4 Interrupt Address Register" group.long 0xC++0x3 line.long 0x00 "SMPU4_IDTLS,SMPU4 Interrupt Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status" "0,1" group.long 0x10++0x3 line.long 0x00 "SMPU4_BADDR,SMPU4 Bus Error Address Register" group.long 0x14++0x3 line.long 0x00 "SMPU4_BDTLS,SMPU4 Bus Error Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status Register" "0,1" group.long 0x20++0x3 line.long 0x00 "SMPU4_RCTL0,SMPU4 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SMPU4_RADDR0,SMPU4 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x28++0x3 line.long 0x00 "SMPU4_RIDA0,SMPU4 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x2C++0x3 line.long 0x00 "SMPU4_RIDMSKA0,SMPU4 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x30++0x3 line.long 0x00 "SMPU4_RIDB0,SMPU4 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x34++0x3 line.long 0x00 "SMPU4_RIDMSKB0,SMPU4 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x38++0x3 line.long 0x00 "SMPU4_RCTL1,SMPU4 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "SMPU4_RADDR1,SMPU4 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x40++0x3 line.long 0x00 "SMPU4_RIDA1,SMPU4 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x44++0x3 line.long 0x00 "SMPU4_RIDMSKA1,SMPU4 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x48++0x3 line.long 0x00 "SMPU4_RIDB1,SMPU4 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x4C++0x3 line.long 0x00 "SMPU4_RIDMSKB1,SMPU4 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x50++0x3 line.long 0x00 "SMPU4_RCTL2,SMPU4 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "SMPU4_RADDR2,SMPU4 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x58++0x3 line.long 0x00 "SMPU4_RIDA2,SMPU4 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x5C++0x3 line.long 0x00 "SMPU4_RIDMSKA2,SMPU4 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x60++0x3 line.long 0x00 "SMPU4_RIDB2,SMPU4 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x64++0x3 line.long 0x00 "SMPU4_RIDMSKB2,SMPU4 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x68++0x3 line.long 0x00 "SMPU4_RCTL3,SMPU4 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x6C++0x3 line.long 0x00 "SMPU4_RADDR3,SMPU4 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x70++0x3 line.long 0x00 "SMPU4_RIDA3,SMPU4 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x74++0x3 line.long 0x00 "SMPU4_RIDMSKA3,SMPU4 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x78++0x3 line.long 0x00 "SMPU4_RIDB3,SMPU4 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x7C++0x3 line.long 0x00 "SMPU4_RIDMSKB3,SMPU4 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x80++0x3 line.long 0x00 "SMPU4_RCTL4,SMPU4 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x84++0x3 line.long 0x00 "SMPU4_RADDR4,SMPU4 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x88++0x3 line.long 0x00 "SMPU4_RIDA4,SMPU4 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x8C++0x3 line.long 0x00 "SMPU4_RIDMSKA4,SMPU4 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x90++0x3 line.long 0x00 "SMPU4_RIDB4,SMPU4 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x94++0x3 line.long 0x00 "SMPU4_RIDMSKB4,SMPU4 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x98++0x3 line.long 0x00 "SMPU4_RCTL5,SMPU4 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x9C++0x3 line.long 0x00 "SMPU4_RADDR5,SMPU4 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xA0++0x3 line.long 0x00 "SMPU4_RIDA5,SMPU4 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xA4++0x3 line.long 0x00 "SMPU4_RIDMSKA5,SMPU4 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xA8++0x3 line.long 0x00 "SMPU4_RIDB5,SMPU4 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xAC++0x3 line.long 0x00 "SMPU4_RIDMSKB5,SMPU4 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xB0++0x3 line.long 0x00 "SMPU4_RCTL6,SMPU4 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xB4++0x3 line.long 0x00 "SMPU4_RADDR6,SMPU4 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xB8++0x3 line.long 0x00 "SMPU4_RIDA6,SMPU4 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xBC++0x3 line.long 0x00 "SMPU4_RIDMSKA6,SMPU4 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xC0++0x3 line.long 0x00 "SMPU4_RIDB6,SMPU4 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xC4++0x3 line.long 0x00 "SMPU4_RIDMSKB6,SMPU4 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xC8++0x3 line.long 0x00 "SMPU4_RCTL7,SMPU4 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xCC++0x3 line.long 0x00 "SMPU4_RADDR7,SMPU4 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xD0++0x3 line.long 0x00 "SMPU4_RIDA7,SMPU4 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xD4++0x3 line.long 0x00 "SMPU4_RIDMSKA7,SMPU4 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xD8++0x3 line.long 0x00 "SMPU4_RIDB7,SMPU4 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xDC++0x3 line.long 0x00 "SMPU4_RIDMSKB7,SMPU4 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x1A0++0x3 line.long 0x00 "SMPU4_EXACADD0,SMPU4 Exclusive Access IDn Address" group.long 0x1A4++0x3 line.long 0x00 "SMPU4_EXACSTAT0,SMPU4 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x1A8++0x3 line.long 0x00 "SMPU4_EXACADD1,SMPU4 Exclusive Access IDn Address" group.long 0x1AC++0x3 line.long 0x00 "SMPU4_EXACSTAT1,SMPU4 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x1B0++0x3 line.long 0x00 "SMPU4_EXACADD2,SMPU4 Exclusive Access IDn Address" group.long 0x1B4++0x3 line.long 0x00 "SMPU4_EXACSTAT2,SMPU4 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x220++0x3 line.long 0x00 "SMPU4_REVID,SMPU4 SMPU Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x00 "SMPU4_SECURECTL,SMPU4 SMPU Control Secure Accesses Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "0,1" newline bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "0,1" bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "0,1" bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "0,1" newline bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "0,1" bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "0,1" bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "0,1" group.long 0x820++0x3 line.long 0x00 "SMPU4_SECURERCTL0,SMPU4 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SMPU4_SECURERCTL1,SMPU4 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x828++0x3 line.long 0x00 "SMPU4_SECURERCTL2,SMPU4 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SMPU4_SECURERCTL3,SMPU4 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x830++0x3 line.long 0x00 "SMPU4_SECURERCTL4,SMPU4 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SMPU4_SECURERCTL5,SMPU4 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x838++0x3 line.long 0x00 "SMPU4_SECURERCTL6,SMPU4 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SMPU4_SECURERCTL7,SMPU4 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" tree.end tree "SMPU5" base ad:0x31086000 width 19. group.long 0x0++0x3 line.long 0x00 "SMPU5_CTL,SMPU5 SMPU Control Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "0,1" bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "0,1" newline bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "0,1" bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "0,1" bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "0,1" group.long 0x4++0x3 line.long 0x00 "SMPU5_STAT,SMPU5 SMPU Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "0,1" newline bitfld.long 0x00 2. " BERR ,Bus Error" "0,1" bitfld.long 0x00 1. " IOVR ,Interrupt Overrun" "0,1" bitfld.long 0x00 0. " IRQ ,Interrupt Request" "0,1" group.long 0x8++0x3 line.long 0x00 "SMPU5_IADDR,SMPU5 Interrupt Address Register" group.long 0xC++0x3 line.long 0x00 "SMPU5_IDTLS,SMPU5 Interrupt Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status" "0,1" group.long 0x10++0x3 line.long 0x00 "SMPU5_BADDR,SMPU5 Bus Error Address Register" group.long 0x14++0x3 line.long 0x00 "SMPU5_BDTLS,SMPU5 Bus Error Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status Register" "0,1" group.long 0x20++0x3 line.long 0x00 "SMPU5_RCTL0,SMPU5 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SMPU5_RADDR0,SMPU5 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x28++0x3 line.long 0x00 "SMPU5_RIDA0,SMPU5 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x2C++0x3 line.long 0x00 "SMPU5_RIDMSKA0,SMPU5 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x30++0x3 line.long 0x00 "SMPU5_RIDB0,SMPU5 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x34++0x3 line.long 0x00 "SMPU5_RIDMSKB0,SMPU5 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x38++0x3 line.long 0x00 "SMPU5_RCTL1,SMPU5 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "SMPU5_RADDR1,SMPU5 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x40++0x3 line.long 0x00 "SMPU5_RIDA1,SMPU5 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x44++0x3 line.long 0x00 "SMPU5_RIDMSKA1,SMPU5 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x48++0x3 line.long 0x00 "SMPU5_RIDB1,SMPU5 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x4C++0x3 line.long 0x00 "SMPU5_RIDMSKB1,SMPU5 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x50++0x3 line.long 0x00 "SMPU5_RCTL2,SMPU5 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "SMPU5_RADDR2,SMPU5 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x58++0x3 line.long 0x00 "SMPU5_RIDA2,SMPU5 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x5C++0x3 line.long 0x00 "SMPU5_RIDMSKA2,SMPU5 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x60++0x3 line.long 0x00 "SMPU5_RIDB2,SMPU5 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x64++0x3 line.long 0x00 "SMPU5_RIDMSKB2,SMPU5 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x68++0x3 line.long 0x00 "SMPU5_RCTL3,SMPU5 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x6C++0x3 line.long 0x00 "SMPU5_RADDR3,SMPU5 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x70++0x3 line.long 0x00 "SMPU5_RIDA3,SMPU5 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x74++0x3 line.long 0x00 "SMPU5_RIDMSKA3,SMPU5 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x78++0x3 line.long 0x00 "SMPU5_RIDB3,SMPU5 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x7C++0x3 line.long 0x00 "SMPU5_RIDMSKB3,SMPU5 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x80++0x3 line.long 0x00 "SMPU5_RCTL4,SMPU5 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x84++0x3 line.long 0x00 "SMPU5_RADDR4,SMPU5 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x88++0x3 line.long 0x00 "SMPU5_RIDA4,SMPU5 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x8C++0x3 line.long 0x00 "SMPU5_RIDMSKA4,SMPU5 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x90++0x3 line.long 0x00 "SMPU5_RIDB4,SMPU5 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x94++0x3 line.long 0x00 "SMPU5_RIDMSKB4,SMPU5 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x98++0x3 line.long 0x00 "SMPU5_RCTL5,SMPU5 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x9C++0x3 line.long 0x00 "SMPU5_RADDR5,SMPU5 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xA0++0x3 line.long 0x00 "SMPU5_RIDA5,SMPU5 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xA4++0x3 line.long 0x00 "SMPU5_RIDMSKA5,SMPU5 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xA8++0x3 line.long 0x00 "SMPU5_RIDB5,SMPU5 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xAC++0x3 line.long 0x00 "SMPU5_RIDMSKB5,SMPU5 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xB0++0x3 line.long 0x00 "SMPU5_RCTL6,SMPU5 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xB4++0x3 line.long 0x00 "SMPU5_RADDR6,SMPU5 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xB8++0x3 line.long 0x00 "SMPU5_RIDA6,SMPU5 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xBC++0x3 line.long 0x00 "SMPU5_RIDMSKA6,SMPU5 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xC0++0x3 line.long 0x00 "SMPU5_RIDB6,SMPU5 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xC4++0x3 line.long 0x00 "SMPU5_RIDMSKB6,SMPU5 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xC8++0x3 line.long 0x00 "SMPU5_RCTL7,SMPU5 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xCC++0x3 line.long 0x00 "SMPU5_RADDR7,SMPU5 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xD0++0x3 line.long 0x00 "SMPU5_RIDA7,SMPU5 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xD4++0x3 line.long 0x00 "SMPU5_RIDMSKA7,SMPU5 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xD8++0x3 line.long 0x00 "SMPU5_RIDB7,SMPU5 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xDC++0x3 line.long 0x00 "SMPU5_RIDMSKB7,SMPU5 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x220++0x3 line.long 0x00 "SMPU5_REVID,SMPU5 SMPU Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x00 "SMPU5_SECURECTL,SMPU5 SMPU Control Secure Accesses Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "0,1" newline bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "0,1" bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "0,1" bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "0,1" newline bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "0,1" bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "0,1" bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "0,1" group.long 0x820++0x3 line.long 0x00 "SMPU5_SECURERCTL0,SMPU5 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SMPU5_SECURERCTL1,SMPU5 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x828++0x3 line.long 0x00 "SMPU5_SECURERCTL2,SMPU5 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SMPU5_SECURERCTL3,SMPU5 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x830++0x3 line.long 0x00 "SMPU5_SECURERCTL4,SMPU5 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SMPU5_SECURERCTL5,SMPU5 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x838++0x3 line.long 0x00 "SMPU5_SECURERCTL6,SMPU5 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SMPU5_SECURERCTL7,SMPU5 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" tree.end tree "SMPU6" base ad:0x31087000 width 19. group.long 0x0++0x3 line.long 0x00 "SMPU6_CTL,SMPU6 SMPU Control Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "0,1" bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "0,1" newline bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "0,1" bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "0,1" bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "0,1" group.long 0x4++0x3 line.long 0x00 "SMPU6_STAT,SMPU6 SMPU Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "0,1" newline bitfld.long 0x00 2. " BERR ,Bus Error" "0,1" bitfld.long 0x00 1. " IOVR ,Interrupt Overrun" "0,1" bitfld.long 0x00 0. " IRQ ,Interrupt Request" "0,1" group.long 0x8++0x3 line.long 0x00 "SMPU6_IADDR,SMPU6 Interrupt Address Register" group.long 0xC++0x3 line.long 0x00 "SMPU6_IDTLS,SMPU6 Interrupt Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status" "0,1" group.long 0x10++0x3 line.long 0x00 "SMPU6_BADDR,SMPU6 Bus Error Address Register" group.long 0x14++0x3 line.long 0x00 "SMPU6_BDTLS,SMPU6 Bus Error Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status Register" "0,1" group.long 0x20++0x3 line.long 0x00 "SMPU6_RCTL0,SMPU6 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SMPU6_RADDR0,SMPU6 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x28++0x3 line.long 0x00 "SMPU6_RIDA0,SMPU6 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x2C++0x3 line.long 0x00 "SMPU6_RIDMSKA0,SMPU6 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x30++0x3 line.long 0x00 "SMPU6_RIDB0,SMPU6 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x34++0x3 line.long 0x00 "SMPU6_RIDMSKB0,SMPU6 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x38++0x3 line.long 0x00 "SMPU6_RCTL1,SMPU6 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "SMPU6_RADDR1,SMPU6 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x40++0x3 line.long 0x00 "SMPU6_RIDA1,SMPU6 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x44++0x3 line.long 0x00 "SMPU6_RIDMSKA1,SMPU6 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x48++0x3 line.long 0x00 "SMPU6_RIDB1,SMPU6 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x4C++0x3 line.long 0x00 "SMPU6_RIDMSKB1,SMPU6 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x50++0x3 line.long 0x00 "SMPU6_RCTL2,SMPU6 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "SMPU6_RADDR2,SMPU6 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x58++0x3 line.long 0x00 "SMPU6_RIDA2,SMPU6 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x5C++0x3 line.long 0x00 "SMPU6_RIDMSKA2,SMPU6 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x60++0x3 line.long 0x00 "SMPU6_RIDB2,SMPU6 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x64++0x3 line.long 0x00 "SMPU6_RIDMSKB2,SMPU6 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x68++0x3 line.long 0x00 "SMPU6_RCTL3,SMPU6 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x6C++0x3 line.long 0x00 "SMPU6_RADDR3,SMPU6 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x70++0x3 line.long 0x00 "SMPU6_RIDA3,SMPU6 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x74++0x3 line.long 0x00 "SMPU6_RIDMSKA3,SMPU6 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x78++0x3 line.long 0x00 "SMPU6_RIDB3,SMPU6 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x7C++0x3 line.long 0x00 "SMPU6_RIDMSKB3,SMPU6 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x80++0x3 line.long 0x00 "SMPU6_RCTL4,SMPU6 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x84++0x3 line.long 0x00 "SMPU6_RADDR4,SMPU6 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x88++0x3 line.long 0x00 "SMPU6_RIDA4,SMPU6 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x8C++0x3 line.long 0x00 "SMPU6_RIDMSKA4,SMPU6 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x90++0x3 line.long 0x00 "SMPU6_RIDB4,SMPU6 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x94++0x3 line.long 0x00 "SMPU6_RIDMSKB4,SMPU6 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x98++0x3 line.long 0x00 "SMPU6_RCTL5,SMPU6 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x9C++0x3 line.long 0x00 "SMPU6_RADDR5,SMPU6 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xA0++0x3 line.long 0x00 "SMPU6_RIDA5,SMPU6 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xA4++0x3 line.long 0x00 "SMPU6_RIDMSKA5,SMPU6 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xA8++0x3 line.long 0x00 "SMPU6_RIDB5,SMPU6 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xAC++0x3 line.long 0x00 "SMPU6_RIDMSKB5,SMPU6 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xB0++0x3 line.long 0x00 "SMPU6_RCTL6,SMPU6 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xB4++0x3 line.long 0x00 "SMPU6_RADDR6,SMPU6 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xB8++0x3 line.long 0x00 "SMPU6_RIDA6,SMPU6 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xBC++0x3 line.long 0x00 "SMPU6_RIDMSKA6,SMPU6 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xC0++0x3 line.long 0x00 "SMPU6_RIDB6,SMPU6 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xC4++0x3 line.long 0x00 "SMPU6_RIDMSKB6,SMPU6 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xC8++0x3 line.long 0x00 "SMPU6_RCTL7,SMPU6 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xCC++0x3 line.long 0x00 "SMPU6_RADDR7,SMPU6 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xD0++0x3 line.long 0x00 "SMPU6_RIDA7,SMPU6 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xD4++0x3 line.long 0x00 "SMPU6_RIDMSKA7,SMPU6 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xD8++0x3 line.long 0x00 "SMPU6_RIDB7,SMPU6 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xDC++0x3 line.long 0x00 "SMPU6_RIDMSKB7,SMPU6 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x220++0x3 line.long 0x00 "SMPU6_REVID,SMPU6 SMPU Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x00 "SMPU6_SECURECTL,SMPU6 SMPU Control Secure Accesses Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "0,1" newline bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "0,1" bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "0,1" bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "0,1" newline bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "0,1" bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "0,1" bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "0,1" group.long 0x820++0x3 line.long 0x00 "SMPU6_SECURERCTL0,SMPU6 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SMPU6_SECURERCTL1,SMPU6 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x828++0x3 line.long 0x00 "SMPU6_SECURERCTL2,SMPU6 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SMPU6_SECURERCTL3,SMPU6 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x830++0x3 line.long 0x00 "SMPU6_SECURERCTL4,SMPU6 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SMPU6_SECURERCTL5,SMPU6 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x838++0x3 line.long 0x00 "SMPU6_SECURERCTL6,SMPU6 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SMPU6_SECURERCTL7,SMPU6 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" tree.end tree "SMPU9" base ad:0x310A0000 width 19. group.long 0x0++0x3 line.long 0x00 "SMPU9_CTL,SMPU9 SMPU Control Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 4. " RLOCK ,RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit" "0,1" bitfld.long 0x00 3. " PINTEN ,Protection Violation Interrupt Enable" "0,1" newline bitfld.long 0x00 2. " PBETYPE ,Protection Violation Bus Error Type" "0,1" bitfld.long 0x00 1. " PBEDIS ,Protection Violation Bus Error Disable" "0,1" bitfld.long 0x00 0. " RSDIS ,Read Speculation Disable" "0,1" group.long 0x4++0x3 line.long 0x00 "SMPU9_STAT,SMPU9 SMPU Status Register" bitfld.long 0x00 17. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 16. " ADRERR ,Address Error" "0,1" bitfld.long 0x00 3. " BEOVR ,Bus Error Overrun" "0,1" newline bitfld.long 0x00 2. " BERR ,Bus Error" "0,1" bitfld.long 0x00 1. " IOVR ,Interrupt Overrun" "0,1" bitfld.long 0x00 0. " IRQ ,Interrupt Request" "0,1" group.long 0x8++0x3 line.long 0x00 "SMPU9_IADDR,SMPU9 Interrupt Address Register" group.long 0xC++0x3 line.long 0x00 "SMPU9_IDTLS,SMPU9 Interrupt Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status" "0,1" group.long 0x10++0x3 line.long 0x00 "SMPU9_BADDR,SMPU9 Bus Error Address Register" group.long 0x14++0x3 line.long 0x00 "SMPU9_BDTLS,SMPU9 Bus Error Details Register" hexmask.long.word 0x00 8.--20. 1. " ID ,ID of Transaction" bitfld.long 0x00 1. " RNW ,Read/Write Status" "0,1" bitfld.long 0x00 0. " SECURE ,Secure Status Register" "0,1" group.long 0x20++0x3 line.long 0x00 "SMPU9_RCTL0,SMPU9 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SMPU9_RADDR0,SMPU9 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x28++0x3 line.long 0x00 "SMPU9_RIDA0,SMPU9 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x2C++0x3 line.long 0x00 "SMPU9_RIDMSKA0,SMPU9 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x30++0x3 line.long 0x00 "SMPU9_RIDB0,SMPU9 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x34++0x3 line.long 0x00 "SMPU9_RIDMSKB0,SMPU9 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x38++0x3 line.long 0x00 "SMPU9_RCTL1,SMPU9 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x3C++0x3 line.long 0x00 "SMPU9_RADDR1,SMPU9 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x40++0x3 line.long 0x00 "SMPU9_RIDA1,SMPU9 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x44++0x3 line.long 0x00 "SMPU9_RIDMSKA1,SMPU9 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x48++0x3 line.long 0x00 "SMPU9_RIDB1,SMPU9 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x4C++0x3 line.long 0x00 "SMPU9_RIDMSKB1,SMPU9 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x50++0x3 line.long 0x00 "SMPU9_RCTL2,SMPU9 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x54++0x3 line.long 0x00 "SMPU9_RADDR2,SMPU9 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x58++0x3 line.long 0x00 "SMPU9_RIDA2,SMPU9 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x5C++0x3 line.long 0x00 "SMPU9_RIDMSKA2,SMPU9 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x60++0x3 line.long 0x00 "SMPU9_RIDB2,SMPU9 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x64++0x3 line.long 0x00 "SMPU9_RIDMSKB2,SMPU9 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x68++0x3 line.long 0x00 "SMPU9_RCTL3,SMPU9 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x6C++0x3 line.long 0x00 "SMPU9_RADDR3,SMPU9 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x70++0x3 line.long 0x00 "SMPU9_RIDA3,SMPU9 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x74++0x3 line.long 0x00 "SMPU9_RIDMSKA3,SMPU9 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x78++0x3 line.long 0x00 "SMPU9_RIDB3,SMPU9 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x7C++0x3 line.long 0x00 "SMPU9_RIDMSKB3,SMPU9 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x80++0x3 line.long 0x00 "SMPU9_RCTL4,SMPU9 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x84++0x3 line.long 0x00 "SMPU9_RADDR4,SMPU9 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0x88++0x3 line.long 0x00 "SMPU9_RIDA4,SMPU9 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0x8C++0x3 line.long 0x00 "SMPU9_RIDMSKA4,SMPU9 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0x90++0x3 line.long 0x00 "SMPU9_RIDB4,SMPU9 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0x94++0x3 line.long 0x00 "SMPU9_RIDMSKB4,SMPU9 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x98++0x3 line.long 0x00 "SMPU9_RCTL5,SMPU9 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0x9C++0x3 line.long 0x00 "SMPU9_RADDR5,SMPU9 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xA0++0x3 line.long 0x00 "SMPU9_RIDA5,SMPU9 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xA4++0x3 line.long 0x00 "SMPU9_RIDMSKA5,SMPU9 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xA8++0x3 line.long 0x00 "SMPU9_RIDB5,SMPU9 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xAC++0x3 line.long 0x00 "SMPU9_RIDMSKB5,SMPU9 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xB0++0x3 line.long 0x00 "SMPU9_RCTL6,SMPU9 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xB4++0x3 line.long 0x00 "SMPU9_RADDR6,SMPU9 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xB8++0x3 line.long 0x00 "SMPU9_RIDA6,SMPU9 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xBC++0x3 line.long 0x00 "SMPU9_RIDMSKA6,SMPU9 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xC0++0x3 line.long 0x00 "SMPU9_RIDB6,SMPU9 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xC4++0x3 line.long 0x00 "SMPU9_RIDMSKB6,SMPU9 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0xC8++0x3 line.long 0x00 "SMPU9_RCTL7,SMPU9 Region n Control Register" bitfld.long 0x00 11. " WIDCINV ,Write Transaction ID Compare Invert" "0,1" bitfld.long 0x00 10. " WPROTEN ,Write Transaction Protection Enable" "0,1" bitfld.long 0x00 9. " RIDCINV ,Read Transaction ID Compare Invert" "0,1" newline bitfld.long 0x00 8. " RPROTEN ,Read Transaction Protection Enable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Memory Region Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0. " EN ,Region Enable" "0,1" group.long 0xCC++0x3 line.long 0x00 "SMPU9_RADDR7,SMPU9 Region n Address Register" hexmask.long.tbyte 0x00 12.--31. 1. " BADDR ,Region n Base Address 20 Most Significant Bits" group.long 0xD0++0x3 line.long 0x00 "SMPU9_RIDA7,SMPU9 Region n ID A Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register A" group.long 0xD4++0x3 line.long 0x00 "SMPU9_RIDMSKA7,SMPU9 Region n ID Mask A Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register A" group.long 0xD8++0x3 line.long 0x00 "SMPU9_RIDB7,SMPU9 Region n ID B Register" hexmask.long.word 0x00 0.--12. 1. " ID ,Region n ID Register B" group.long 0xDC++0x3 line.long 0x00 "SMPU9_RIDMSKB7,SMPU9 Region n ID Mask B Register" hexmask.long.word 0x00 0.--12. 1. " MSK ,Region n ID Mask Register B" group.long 0x1A0++0x3 line.long 0x00 "SMPU9_EXACADD0,SMPU9 Exclusive Access IDn Address" group.long 0x1A4++0x3 line.long 0x00 "SMPU9_EXACSTAT0,SMPU9 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x1A8++0x3 line.long 0x00 "SMPU9_EXACADD1,SMPU9 Exclusive Access IDn Address" group.long 0x1AC++0x3 line.long 0x00 "SMPU9_EXACSTAT1,SMPU9 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x1B0++0x3 line.long 0x00 "SMPU9_EXACADD2,SMPU9 Exclusive Access IDn Address" group.long 0x1B4++0x3 line.long 0x00 "SMPU9_EXACSTAT2,SMPU9 Exclusive Access Status" hexmask.long.word 0x00 8.--20. 1. " ARID ,Exclusive Access ID" bitfld.long 0x00 5.--7. " ARSIZE ,Exclusive Access Read Size" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--4. " ARLEN ,Exclusive Access Read Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. " VALID ,Valid Exclusive Access Read" "0,1" group.long 0x220++0x3 line.long 0x00 "SMPU9_REVID,SMPU9 SMPU Revision ID Register" bitfld.long 0x00 4.--7. " MAJOR ,Major Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " REV ,Incremental Version ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x800++0x3 line.long 0x00 "SMPU9_SECURECTL,SMPU9 SMPU Control Secure Accesses Register" bitfld.long 0x00 31. " LOCK ,Lock Bit" "0,1" bitfld.long 0x00 11. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 10. " WNSEN ,Non-secure Write Transaction Enable" "0,1" newline bitfld.long 0x00 9. " RSECDIS ,Secure Read Transaction Disable" "0,1" bitfld.long 0x00 8. " RNSEN ,Non-secure Read Transaction Enable" "0,1" bitfld.long 0x00 3. " RLOCK ,Secure Region Registers Lock Bit" "0,1" newline bitfld.long 0x00 2. " SINTEN ,Security Violation Interrupt Enable" "0,1" bitfld.long 0x00 1. " SBETYPE ,Security Violation Bus Error Type" "0,1" bitfld.long 0x00 0. " SBEDIS ,Security Violation Bus Error Disable" "0,1" group.long 0x820++0x3 line.long 0x00 "SMPU9_SECURERCTL0,SMPU9 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x824++0x3 line.long 0x00 "SMPU9_SECURERCTL1,SMPU9 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x828++0x3 line.long 0x00 "SMPU9_SECURERCTL2,SMPU9 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x82C++0x3 line.long 0x00 "SMPU9_SECURERCTL3,SMPU9 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x830++0x3 line.long 0x00 "SMPU9_SECURERCTL4,SMPU9 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x834++0x3 line.long 0x00 "SMPU9_SECURERCTL5,SMPU9 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x838++0x3 line.long 0x00 "SMPU9_SECURERCTL6,SMPU9 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" group.long 0x83C++0x3 line.long 0x00 "SMPU9_SECURERCTL7,SMPU9 Region n Control Secure Accesses Register" bitfld.long 0x00 3. " WSECDIS ,Secure Write Transaction Disable" "0,1" bitfld.long 0x00 2. " WNSEN ,Non-secure Write Transaction Enable" "0,1" bitfld.long 0x00 1. " RSECDIS ,Secure Read Transaction Disable" "0,1" newline bitfld.long 0x00 0. " RNSEN ,Non-secure Read Transaction Enable" "0,1" tree.end tree.end tree "S/PDIF (Sony/Philips Digital Interface)" tree "SPDIF0" base ad:0x310C9280 width 20. group.long 0x0++0x3 line.long 0x00 "SPDIF0_TX_CTL,SPDIF0 Transmit Control Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE0B ,Channel Status Byte for Subframe B" hexmask.long.byte 0x00 16.--23. 1. " BYTE0A ,Channel Status Byte for Subframe A" bitfld.long 0x00 15. " EXTSYNC ,External Sync Enable" "0,1" newline bitfld.long 0x00 13. " USRPEND ,User Bits Pending" "0,1" bitfld.long 0x00 12. " BLKSTART ,Block Start" "0,1" bitfld.long 0x00 11. " VALIDR ,Validity Bit B" "0,1" newline bitfld.long 0x00 10. " VALIDL ,Validity Bit A" "0,1" bitfld.long 0x00 9. " AUTO ,Automatically Generate Block Start" "0,1" bitfld.long 0x00 6.--8. " SMODEIN ,Serial Data Input Format" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " SCDFLR ,Select L/R Single-Channel, Double-Frequency Mode" "0,1" bitfld.long 0x00 4. " SCDF ,Single-Channel, Double-Frequency Mode Enable" "0,1" bitfld.long 0x00 2.--3. " FREQ ,Frequency Multiplier" "0,1,2,3" newline bitfld.long 0x00 1. " MUTE ,Mute" "0,1" bitfld.long 0x00 0. " EN ,Transmitter Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SPDIF0_TX_STAT_A0,SPDIF0 Transmit Status A0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE4 ,Byte 4 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE3 ,Byte 3 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE2 ,Byte 2 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE1 ,Byte 1 Sub Frame A" group.long 0x8++0x3 line.long 0x00 "SPDIF0_TX_STAT_B0,SPDIF0 Transmit Status B0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE4 ,Byte 4 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE3 ,Byte 3 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE2 ,Byte 2 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE1 ,Byte 1 Sub Frame B" group.long 0x20++0x3 line.long 0x00 "SPDIF0_RX_CTL,SPDIF0 Receive Control" bitfld.long 0x00 13. " INVTDM ,Invert TDM clock" "0,1" bitfld.long 0x00 9.--10. " TDMSEL ,Select TDM clock frequency" "0,1,2,3" bitfld.long 0x00 4. " RST ,Reset SPDIF Receiver" "0,1" newline bitfld.long 0x00 3. " RSTRTAUDIO ,Restart Audio" "0,1" bitfld.long 0x00 2. " FASTLOCK ,Fast Lock Select" "0,1" bitfld.long 0x00 1. " STRENGTH ,FS strength Control" "0,1" newline bitfld.long 0x00 0. " EN ,SPDIF Receiver Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SPDIF0_RX_STAT,SPDIF0 Receive Status Register" hexmask.long.word 0x00 16.--31. 1. " COMPMODE ,Compression Mode" bitfld.long 0x00 12.--15. " WLCHANB ,Word Length Channel B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " WLCHANA ,Word Length Channel A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. " LOCKLOSS ,Loss of Lock (sticky)" "0,1" bitfld.long 0x00 3. " LOCK ,Lock Receiver" "0,1" bitfld.long 0x00 2. " VALID ,Validity Bit" "0,1" newline bitfld.long 0x00 1. " COMPTYPE ,Compression Type" "0,1" bitfld.long 0x00 0. " AUDIOTYPE ,Audio Type" "0,1" group.long 0x28++0x3 line.long 0x00 "SPDIF0_RX_STAT0_A,SPDIF0 Receive Status A0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,CS Byte 3" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,CS Byte 2" hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,CS Byte 1" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,CS Byte 0" group.long 0x2C++0x3 line.long 0x00 "SPDIF0_RX_STAT0_B,SPDIF0 Receive Status B0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,CS Byte 3" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,CS Byte 2" hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,CS Byte 1" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,CS Byte 0" group.long 0x30++0x3 line.long 0x00 "SPDIF0_RX_STAT1_A,SPDIF0 Receive Status A1 Register" hexmask.long.byte 0x00 0.--7. 1. " BYTE4 ,CS Byte 4" group.long 0x34++0x3 line.long 0x00 "SPDIF0_RX_STAT1_B,SPDIF0 Receive Status B1 Register" hexmask.long.byte 0x00 0.--7. 1. " BYTE4 ,CS Byte 4" group.long 0xD0++0x3 line.long 0x00 "SPDIF0_TX_STAT_A1,SPDIF0 Transmit Status A1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE8 ,Byte 8 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE7 ,Byte 7 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE6 ,Byte 6 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE5 ,Byte 5 Sub Frame A" group.long 0xD4++0x3 line.long 0x00 "SPDIF0_TX_STAT_A2,SPDIF0 Transmit Status A2 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE12 ,Byte 12 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE11 ,Byte 11 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE10 ,Byte 10 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE9 ,Byte 9 Sub Frame A" group.long 0xD8++0x3 line.long 0x00 "SPDIF0_TX_STAT_A3,SPDIF0 Transmit Status A3 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE16 ,Byte 16 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE15 ,Byte 15 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE14 ,Byte 14 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE13 ,Byte 13 Sub Frame A" group.long 0xDC++0x3 line.long 0x00 "SPDIF0_TX_STAT_A4,SPDIF0 Transmit Status A4 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE20 ,Byte 20 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE19 ,Byte 19 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE18 ,Byte 18 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE17 ,Byte 17 Sub Frame A" group.long 0xE0++0x3 line.long 0x00 "SPDIF0_TX_STAT_A5,SPDIF0 Transmit Status A5 Register" hexmask.long.byte 0x00 16.--23. 1. " BYTE23 ,Byte 23 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE22 ,Byte 22 Sub Frame A" hexmask.long.byte 0x00 0.--7. 1. " BYTE21 ,Byte 21 Sub Frame A" group.long 0xE8++0x3 line.long 0x00 "SPDIF0_TX_STAT_B1,SPDIF0 Transmit Status B1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE8 ,Byte 8 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE7 ,Byte 7 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE6 ,Byte 6 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE5 ,Byte 5 Sub Frame B" group.long 0xEC++0x3 line.long 0x00 "SPDIF0_TX_STAT_B2,SPDIF0 Transmit Status B2 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE12 ,Byte 12 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE11 ,Byte 11 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE10 ,Byte 10 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE9 ,Byte 9 Sub Frame B" group.long 0xF0++0x3 line.long 0x00 "SPDIF0_TX_STAT_B3,SPDIF0 Transmit Status B3 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE16 ,Byte 16 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE15 ,Byte 15 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE14 ,Byte 14 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE13 ,Byte 13 Sub Frame B" group.long 0xF4++0x3 line.long 0x00 "SPDIF0_TX_STAT_B4,SPDIF0 Transmit Status B4 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE20 ,Byte 20 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE19 ,Byte 19 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE18 ,Byte 18 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE17 ,Byte 17 Sub Frame B" group.long 0xF8++0x3 line.long 0x00 "SPDIF0_TX_STAT_B5,SPDIF0 Transmit Status B5 Register" hexmask.long.byte 0x00 16.--23. 1. " BYTE23 ,Byte 23 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE22 ,Byte 22 Sub Frame B" hexmask.long.byte 0x00 0.--7. 1. " BYTE21 ,Byte 21 Sub Frame B" group.long 0x100++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_A0,SPDIF0 Transmit User Buffer A0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Byte 3 of Subframe A User Bit Buffer" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Byte 2 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Byte 1 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,Byte 0 Sub Frame A" group.long 0x104++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_A1,SPDIF0 Transmit User Buffer A1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE7 ,Byte 7 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE6 ,Byte 6 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE5 ,Byte 5 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE4 ,Byte 4 Sub Frame A" group.long 0x108++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_A2,SPDIF0 Transmit User Buffer A2 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE11 ,Byte 11 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE10 ,Byte 10 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE9 ,Byte 9 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE8 ,Byte 8 Sub Frame A" group.long 0x10C++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_A3,SPDIF0 Transmit User Buffer A3 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE15 ,Byte 15 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE14 ,Byte 14 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE13 ,Byte 13 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE12 ,Byte 12 Sub Frame A" group.long 0x110++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_A4,SPDIF0 Transmit User Buffer A4 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE19 ,Byte 19 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE18 ,Byte 18 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE17 ,Byte 17 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE16 ,Byte 16 Sub Frame A" group.long 0x114++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_A5,SPDIF0 Transmit User Buffer A5 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE23 ,Byte 23 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE22 ,Byte 22 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE21 ,Byte 21 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE20 ,Byte 20 Sub Frame A" group.long 0x120++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_B0,SPDIF0 Transmit User Buffer B0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Byte 3 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Byte 2 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Byte 1 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,Byte 0 Sub Frame B" group.long 0x124++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_B1,SPDIF0 Transmit User Buffer B1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE7 ,Byte 7 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE6 ,Byte 6 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE5 ,Byte 5 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE4 ,Byte 4 Sub Frame B" group.long 0x128++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_B2,SPDIF0 Transmit User Buffer B2 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE11 ,Byte 11 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE10 ,Byte 10 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE9 ,Byte 9 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE8 ,Byte 8 Sub Frame B" group.long 0x12C++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_B3,SPDIF0 Transmit User Buffer B3 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE15 ,Byte 15 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE14 ,Byte 14 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE13 ,Byte 13 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE12 ,Byte 12 Sub Frame B" group.long 0x130++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_B4,SPDIF0 Transmit User Buffer B4 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE19 ,Byte 19 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE18 ,Byte 18 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE17 ,Byte 17 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE16 ,Byte 16 Sub Frame B" group.long 0x134++0x3 line.long 0x00 "SPDIF0_TX_UBUFF_B5,SPDIF0 Transmit User Buffer B5 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE23 ,Byte 23 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE22 ,Byte 22 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE21 ,Byte 21 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE20 ,Byte 20 Sub Frame B" group.long 0x13C++0x3 line.long 0x00 "SPDIF0_TX_USRUPDT,SPDIF0 User Bit Update Register" bitfld.long 0x00 0. " EN ,Enable" "0,1" tree.end tree "SPDIF1" base ad:0x310CA280 width 20. group.long 0x0++0x3 line.long 0x00 "SPDIF1_TX_CTL,SPDIF1 Transmit Control Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE0B ,Channel Status Byte for Subframe B" hexmask.long.byte 0x00 16.--23. 1. " BYTE0A ,Channel Status Byte for Subframe A" bitfld.long 0x00 15. " EXTSYNC ,External Sync Enable" "0,1" newline bitfld.long 0x00 13. " USRPEND ,User Bits Pending" "0,1" bitfld.long 0x00 12. " BLKSTART ,Block Start" "0,1" bitfld.long 0x00 11. " VALIDR ,Validity Bit B" "0,1" newline bitfld.long 0x00 10. " VALIDL ,Validity Bit A" "0,1" bitfld.long 0x00 9. " AUTO ,Automatically Generate Block Start" "0,1" bitfld.long 0x00 6.--8. " SMODEIN ,Serial Data Input Format" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 5. " SCDFLR ,Select L/R Single-Channel, Double-Frequency Mode" "0,1" bitfld.long 0x00 4. " SCDF ,Single-Channel, Double-Frequency Mode Enable" "0,1" bitfld.long 0x00 2.--3. " FREQ ,Frequency Multiplier" "0,1,2,3" newline bitfld.long 0x00 1. " MUTE ,Mute" "0,1" bitfld.long 0x00 0. " EN ,Transmitter Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SPDIF1_TX_STAT_A0,SPDIF1 Transmit Status A0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE4 ,Byte 4 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE3 ,Byte 3 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE2 ,Byte 2 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE1 ,Byte 1 Sub Frame A" group.long 0x8++0x3 line.long 0x00 "SPDIF1_TX_STAT_B0,SPDIF1 Transmit Status B0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE4 ,Byte 4 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE3 ,Byte 3 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE2 ,Byte 2 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE1 ,Byte 1 Sub Frame B" group.long 0x20++0x3 line.long 0x00 "SPDIF1_RX_CTL,SPDIF1 Receive Control" bitfld.long 0x00 13. " INVTDM ,Invert TDM clock" "0,1" bitfld.long 0x00 9.--12. " TDMSEL ,Select TDM clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. " RST ,Reset SPDIF Receiver" "0,1" newline bitfld.long 0x00 3. " RSTRTAUDIO ,Restart Audio" "0,1" bitfld.long 0x00 2. " FASTLOCK ,Fast Lock Select" "0,1" bitfld.long 0x00 1. " STRENGTH ,FS strength Control" "0,1" newline bitfld.long 0x00 0. " EN ,SPDIF Receiver Enable" "0,1" group.long 0x24++0x3 line.long 0x00 "SPDIF1_RX_STAT,SPDIF1 Receive Status Register" hexmask.long.word 0x00 16.--31. 1. " COMPMODE ,Compression Mode" bitfld.long 0x00 12.--15. " WLCHANB ,Word Length Channel B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " WLCHANA ,Word Length Channel A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. " LOCKLOSS ,Loss of Lock (sticky)" "0,1" bitfld.long 0x00 3. " LOCK ,Lock Receiver" "0,1" bitfld.long 0x00 2. " VALID ,Validity Bit" "0,1" newline bitfld.long 0x00 1. " COMPTYPE ,Compression Type" "0,1" bitfld.long 0x00 0. " AUDIOTYPE ,Audio Type" "0,1" group.long 0x28++0x3 line.long 0x00 "SPDIF1_RX_STAT0_A,SPDIF1 Receive Status A0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,CS Byte 3" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,CS Byte 2" hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,CS Byte 1" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,CS Byte 0" group.long 0x2C++0x3 line.long 0x00 "SPDIF1_RX_STAT0_B,SPDIF1 Receive Status B0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,CS Byte 3" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,CS Byte 2" hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,CS Byte 1" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,CS Byte 0" group.long 0x30++0x3 line.long 0x00 "SPDIF1_RX_STAT1_A,SPDIF1 Receive Status A1 Register" hexmask.long.byte 0x00 0.--7. 1. " BYTE4 ,CS Byte 4" group.long 0x34++0x3 line.long 0x00 "SPDIF1_RX_STAT1_B,SPDIF1 Receive Status B1 Register" hexmask.long.byte 0x00 0.--7. 1. " BYTE4 ,CS Byte 4" group.long 0xD0++0x3 line.long 0x00 "SPDIF1_TX_STAT_A1,SPDIF1 Transmit Status A1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE8 ,Byte 8 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE7 ,Byte 7 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE6 ,Byte 6 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE5 ,Byte 5 Sub Frame A" group.long 0xD4++0x3 line.long 0x00 "SPDIF1_TX_STAT_A2,SPDIF1 Transmit Status A2 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE12 ,Byte 12 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE11 ,Byte 11 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE10 ,Byte 10 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE9 ,Byte 9 Sub Frame A" group.long 0xD8++0x3 line.long 0x00 "SPDIF1_TX_STAT_A3,SPDIF1 Transmit Status A3 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE16 ,Byte 16 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE15 ,Byte 15 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE14 ,Byte 14 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE13 ,Byte 13 Sub Frame A" group.long 0xDC++0x3 line.long 0x00 "SPDIF1_TX_STAT_A4,SPDIF1 Transmit Status A4 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE20 ,Byte 20 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE19 ,Byte 19 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE18 ,Byte 18 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE17 ,Byte 17 Sub Frame A" group.long 0xE0++0x3 line.long 0x00 "SPDIF1_TX_STAT_A5,SPDIF1 Transmit Status A5 Register" hexmask.long.byte 0x00 16.--23. 1. " BYTE23 ,Byte 23 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE22 ,Byte 22 Sub Frame A" hexmask.long.byte 0x00 0.--7. 1. " BYTE21 ,Byte 21 Sub Frame A" group.long 0xE8++0x3 line.long 0x00 "SPDIF1_TX_STAT_B1,SPDIF1 Transmit Status B1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE8 ,Byte 8 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE7 ,Byte 7 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE6 ,Byte 6 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE5 ,Byte 5 Sub Frame B" group.long 0xEC++0x3 line.long 0x00 "SPDIF1_TX_STAT_B2,SPDIF1 Transmit Status B2 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE12 ,Byte 12 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE11 ,Byte 11 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE10 ,Byte 10 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE9 ,Byte 9 Sub Frame B" group.long 0xF0++0x3 line.long 0x00 "SPDIF1_TX_STAT_B3,SPDIF1 Transmit Status B3 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE16 ,Byte 16 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE15 ,Byte 15 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE14 ,Byte 14 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE13 ,Byte 13 Sub Frame B" group.long 0xF4++0x3 line.long 0x00 "SPDIF1_TX_STAT_B4,SPDIF1 Transmit Status B4 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE20 ,Byte 20 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE19 ,Byte 19 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE18 ,Byte 18 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE17 ,Byte 17 Sub Frame B" group.long 0xF8++0x3 line.long 0x00 "SPDIF1_TX_STAT_B5,SPDIF1 Transmit Status B5 Register" hexmask.long.byte 0x00 16.--23. 1. " BYTE23 ,Byte 23 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE22 ,Byte 22 Sub Frame B" hexmask.long.byte 0x00 0.--7. 1. " BYTE21 ,Byte 21 Sub Frame B" group.long 0x100++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_A0,SPDIF1 Transmit User Buffer A0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Byte 3 of Subframe A User Bit Buffer" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Byte 2 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Byte 1 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,Byte 0 Sub Frame A" group.long 0x104++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_A1,SPDIF1 Transmit User Buffer A1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE7 ,Byte 7 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE6 ,Byte 6 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE5 ,Byte 5 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE4 ,Byte 4 Sub Frame A" group.long 0x108++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_A2,SPDIF1 Transmit User Buffer A2 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE11 ,Byte 11 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE10 ,Byte 10 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE9 ,Byte 9 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE8 ,Byte 8 Sub Frame A" group.long 0x10C++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_A3,SPDIF1 Transmit User Buffer A3 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE15 ,Byte 15 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE14 ,Byte 14 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE13 ,Byte 13 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE12 ,Byte 12 Sub Frame A" group.long 0x110++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_A4,SPDIF1 Transmit User Buffer A4 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE19 ,Byte 19 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE18 ,Byte 18 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE17 ,Byte 17 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE16 ,Byte 16 Sub Frame A" group.long 0x114++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_A5,SPDIF1 Transmit User Buffer A5 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE23 ,Byte 23 Sub Frame A" hexmask.long.byte 0x00 16.--23. 1. " BYTE22 ,Byte 22 Sub Frame A" hexmask.long.byte 0x00 8.--15. 1. " BYTE21 ,Byte 21 Sub Frame A" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE20 ,Byte 20 Sub Frame A" group.long 0x120++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_B0,SPDIF1 Transmit User Buffer B0 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE3 ,Byte 3 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE2 ,Byte 2 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE1 ,Byte 1 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE0 ,Byte 0 Sub Frame B" group.long 0x124++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_B1,SPDIF1 Transmit User Buffer B1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE7 ,Byte 7 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE6 ,Byte 6 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE5 ,Byte 5 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE4 ,Byte 4 Sub Frame B" group.long 0x128++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_B2,SPDIF1 Transmit User Buffer B2 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE11 ,Byte 11 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE10 ,Byte 10 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE9 ,Byte 9 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE8 ,Byte 8 Sub Frame B" group.long 0x12C++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_B3,SPDIF1 Transmit User Buffer B3 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE15 ,Byte 15 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE14 ,Byte 14 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE13 ,Byte 13 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE12 ,Byte 12 Sub Frame B" group.long 0x130++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_B4,SPDIF1 Transmit User Buffer B4 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE19 ,Byte 19 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE18 ,Byte 18 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE17 ,Byte 17 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE16 ,Byte 16 Sub Frame B" group.long 0x134++0x3 line.long 0x00 "SPDIF1_TX_UBUFF_B5,SPDIF1 Transmit User Buffer B5 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE23 ,Byte 23 Sub Frame B" hexmask.long.byte 0x00 16.--23. 1. " BYTE22 ,Byte 22 Sub Frame B" hexmask.long.byte 0x00 8.--15. 1. " BYTE21 ,Byte 21 Sub Frame B" newline hexmask.long.byte 0x00 0.--7. 1. " BYTE20 ,Byte 20 Sub Frame B" group.long 0x13C++0x3 line.long 0x00 "SPDIF1_TX_USRUPDT,SPDIF1 User Bit Update Register" bitfld.long 0x00 0. " EN ,Enable" "0,1" tree.end tree.end tree "SPI (Serial Peripheral Interface)" tree "SPI0" base ad:0x3102E004 width 15. group.long 0x0++0x3 line.long 0x00 "SPI0_CTL,SPI0 Control Register" bitfld.long 0x00 22. " SOSI ,Start on MOSI" "0,1" bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O Mode" "0,1,2,3" bitfld.long 0x00 18. " FMODE ,Fast-Mode Enable" "0,1" newline bitfld.long 0x00 16.--17. " FCWM ,Flow Control Watermark" "0,1,2,3" bitfld.long 0x00 15. " FCPL ,Flow Control Polarity" "0,1" bitfld.long 0x00 14. " FCCH ,Flow Control Channel Selection" "0,1" newline bitfld.long 0x00 13. " FCEN ,Flow Control Enable" "0,1" bitfld.long 0x00 12. " LSBF ,Least Significant Bit First" "0,1" bitfld.long 0x00 9.--10. " SIZE ,Word Transfer Size" "0,1,2,3" newline bitfld.long 0x00 8. " EMISO ,Enable MISO" "0,1" bitfld.long 0x00 7. " SELST ,Slave Select Polarity Between Transfers" "0,1" bitfld.long 0x00 6. " ASSEL ,Slave Select Pin Control" "0,1" newline bitfld.long 0x00 5. " CPOL ,Clock Polarity" "0,1" bitfld.long 0x00 4. " CPHA ,Clock Phase" "0,1" bitfld.long 0x00 3. " ODM ,Open Drain Mode" "0,1" newline bitfld.long 0x00 2. " PSSE ,Protected Slave Select Enable" "0,1" bitfld.long 0x00 1. " MSTR ,Master/Slave" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SPI0_RXCTL,SPI0 Receive Control Register" bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO Urgent Watermark" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO Regular Watermark" "0,1,2,3" bitfld.long 0x00 8. " RDO ,Receive Data Overrun" "0,1" newline bitfld.long 0x00 4.--6. " RDR ,Receive Data Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " RWCEN ,Receive Word Counter Enable" "0,1" bitfld.long 0x00 2. " RTI ,Receive Transfer Initiate" "0,1" newline bitfld.long 0x00 0. " REN ,Receive Enable" "0,1" group.long 0x8++0x3 line.long 0x00 "SPI0_TXCTL,SPI0 Transmit Control Register" bitfld.long 0x00 16.--18. " TUWM ,FIFO Urgent Watermark" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " TRWM ,FIFO Regular Watermark" "0,1,2,3" bitfld.long 0x00 8. " TDU ,Transmit Data Underrun" "0,1" newline bitfld.long 0x00 4.--6. " TDR ,Transmit Data Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " TWCEN ,Transmit Word Counter Enable" "0,1" bitfld.long 0x00 2. " TTI ,Transmit Transfer Initiate" "0,1" newline bitfld.long 0x00 0. " TEN ,Transmit Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPI0_CLK,SPI0 Clock Rate Register" hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate" group.long 0x10++0x3 line.long 0x00 "SPI0_DLY,SPI0 Delay Register" bitfld.long 0x00 9. " LAGX ,Extended SPI Clock Lag Control" "0,1" bitfld.long 0x00 8. " LEADX ,Extended SPI Clock Lead Control" "0,1" hexmask.long.byte 0x00 0.--7. 1. " STOP ,Transfer Delay Time in Multiples of SPI Clock Period" group.long 0x14++0x3 line.long 0x00 "SPI0_SLVSEL,SPI0 Slave Select Register" bitfld.long 0x00 15. " SSEL7 ,Slave Select 7 Output" "0,1" bitfld.long 0x00 14. " SSEL6 ,Slave Select 6 Output" "0,1" bitfld.long 0x00 13. " SSEL5 ,Slave Select 5 Output" "0,1" newline bitfld.long 0x00 12. " SSEL4 ,Slave Select 4 Output" "0,1" bitfld.long 0x00 11. " SSEL3 ,Slave Select 3 Output" "0,1" bitfld.long 0x00 10. " SSEL2 ,Slave Select 2 Output" "0,1" newline bitfld.long 0x00 9. " SSEL1 ,Slave Select 1 Output" "0,1" bitfld.long 0x00 7. " SSE7 ,Slave Select 7 Enable" "0,1" bitfld.long 0x00 6. " SSE6 ,Slave Select 6 Enable" "0,1" newline bitfld.long 0x00 5. " SSE5 ,Slave Select 5 Enable" "0,1" bitfld.long 0x00 4. " SSE4 ,Slave Select 4 Enable" "0,1" bitfld.long 0x00 3. " SSE3 ,Slave Select 3 Enable" "0,1" newline bitfld.long 0x00 2. " SSE2 ,Slave Select 2 Enable" "0,1" bitfld.long 0x00 1. " SSE1 ,Slave Select 1 Enable" "0,1" group.long 0x18++0x3 line.long 0x00 "SPI0_RWC,SPI0 Received Word Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received Word Count" group.long 0x1C++0x3 line.long 0x00 "SPI0_RWCR,SPI0 Received Word Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received Word Count Reload" group.long 0x20++0x3 line.long 0x00 "SPI0_TWC,SPI0 Transmitted Word Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Transmitted Word Count" group.long 0x24++0x3 line.long 0x00 "SPI0_TWCR,SPI0 Transmitted Word Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Transmitted Word Count Reload" group.long 0x2C++0x3 line.long 0x00 "SPI0_IMSK,SPI0 Interrupt Mask Register" bitfld.long 0x00 11. " TF ,Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark" "0,1" group.long 0x30++0x3 line.long 0x00 "SPI0_IMSK_CLR,SPI0 Interrupt Mask Clear Register" bitfld.long 0x00 11. " TF ,Clear Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Clear Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Clear Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Clear Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Clear Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Clear Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Clear Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Clear Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Clear Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Clear Receive Urgent Watermark" "0,1" group.long 0x34++0x3 line.long 0x00 "SPI0_IMSK_SET,SPI0 Interrupt Mask Set Register" bitfld.long 0x00 11. " TF ,Set Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Set Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Set Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Set Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Set Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Set Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Set Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Set Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Set Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Set Receive Urgent Watermark" "0,1" group.long 0x3C++0x3 line.long 0x00 "SPI0_STAT,SPI0 Status Register" bitfld.long 0x00 23. " TFF ,SPI_TFIFO Full" "0,1" bitfld.long 0x00 22. " RFE ,SPI_RFIFO Empty" "0,1" bitfld.long 0x00 20. " FCS ,Flow Control Stall Indication" "0,1" newline bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " TF ,Transmit Finish Indication" "0,1" newline bitfld.long 0x00 10. " RF ,Receive Finish Indication" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start" "0,1" bitfld.long 0x00 8. " RS ,Receive Start" "0,1" newline bitfld.long 0x00 7. " MF ,Mode Fault Indication" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision Indication" "0,1" bitfld.long 0x00 5. " TUR ,Transmit Underrun Indication" "0,1" newline bitfld.long 0x00 4. " ROR ,Receive Overrun Indication" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark Breached" "0,1" bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark Breached" "0,1" newline bitfld.long 0x00 0. " SPIF ,SPI Finished" "0,1" group.long 0x40++0x3 line.long 0x00 "SPI0_ILAT,SPI0 Masked Interrupt Condition Register" bitfld.long 0x00 11. " TF ,Transmit Finish Interrupt Latch" "0,1" bitfld.long 0x00 10. " RF ,Receive Finish Interrupt Latch" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start Interrupt Latch" "0,1" newline bitfld.long 0x00 8. " RS ,Receive Start Interrupt Latch" "0,1" bitfld.long 0x00 7. " MF ,Mode Fault Interrupt Latch" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision Interrupt Latch" "0,1" newline bitfld.long 0x00 5. " TUR ,Transmit Underrun Interrupt Latch" "0,1" bitfld.long 0x00 4. " ROR ,Receive Overrun Interrupt Latch" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark Interrupt Latch" "0,1" newline bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark Interrupt Latch" "0,1" group.long 0x44++0x3 line.long 0x00 "SPI0_ILAT_CLR,SPI0 Masked Interrupt Clear Register" bitfld.long 0x00 11. " TF ,Clear Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Clear Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Clear Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Clear Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Clear Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Clear Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Clear Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Clear Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Clear Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Clear Receive Urgent Watermark" "0,1" group.long 0x4C++0x3 line.long 0x00 "SPI0_RFIFO,SPI0 Receive FIFO Data Register" group.long 0x54++0x3 line.long 0x00 "SPI0_TFIFO,SPI0 Transmit FIFO Data Register" tree.end tree "SPI1" base ad:0x3102F004 width 15. group.long 0x0++0x3 line.long 0x00 "SPI1_CTL,SPI1 Control Register" bitfld.long 0x00 22. " SOSI ,Start on MOSI" "0,1" bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O Mode" "0,1,2,3" bitfld.long 0x00 18. " FMODE ,Fast-Mode Enable" "0,1" newline bitfld.long 0x00 16.--17. " FCWM ,Flow Control Watermark" "0,1,2,3" bitfld.long 0x00 15. " FCPL ,Flow Control Polarity" "0,1" bitfld.long 0x00 14. " FCCH ,Flow Control Channel Selection" "0,1" newline bitfld.long 0x00 13. " FCEN ,Flow Control Enable" "0,1" bitfld.long 0x00 12. " LSBF ,Least Significant Bit First" "0,1" bitfld.long 0x00 9.--10. " SIZE ,Word Transfer Size" "0,1,2,3" newline bitfld.long 0x00 8. " EMISO ,Enable MISO" "0,1" bitfld.long 0x00 7. " SELST ,Slave Select Polarity Between Transfers" "0,1" bitfld.long 0x00 6. " ASSEL ,Slave Select Pin Control" "0,1" newline bitfld.long 0x00 5. " CPOL ,Clock Polarity" "0,1" bitfld.long 0x00 4. " CPHA ,Clock Phase" "0,1" bitfld.long 0x00 3. " ODM ,Open Drain Mode" "0,1" newline bitfld.long 0x00 2. " PSSE ,Protected Slave Select Enable" "0,1" bitfld.long 0x00 1. " MSTR ,Master/Slave" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SPI1_RXCTL,SPI1 Receive Control Register" bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO Urgent Watermark" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO Regular Watermark" "0,1,2,3" bitfld.long 0x00 8. " RDO ,Receive Data Overrun" "0,1" newline bitfld.long 0x00 4.--6. " RDR ,Receive Data Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " RWCEN ,Receive Word Counter Enable" "0,1" bitfld.long 0x00 2. " RTI ,Receive Transfer Initiate" "0,1" newline bitfld.long 0x00 0. " REN ,Receive Enable" "0,1" group.long 0x8++0x3 line.long 0x00 "SPI1_TXCTL,SPI1 Transmit Control Register" bitfld.long 0x00 16.--18. " TUWM ,FIFO Urgent Watermark" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " TRWM ,FIFO Regular Watermark" "0,1,2,3" bitfld.long 0x00 8. " TDU ,Transmit Data Underrun" "0,1" newline bitfld.long 0x00 4.--6. " TDR ,Transmit Data Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " TWCEN ,Transmit Word Counter Enable" "0,1" bitfld.long 0x00 2. " TTI ,Transmit Transfer Initiate" "0,1" newline bitfld.long 0x00 0. " TEN ,Transmit Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPI1_CLK,SPI1 Clock Rate Register" hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate" group.long 0x10++0x3 line.long 0x00 "SPI1_DLY,SPI1 Delay Register" bitfld.long 0x00 9. " LAGX ,Extended SPI Clock Lag Control" "0,1" bitfld.long 0x00 8. " LEADX ,Extended SPI Clock Lead Control" "0,1" hexmask.long.byte 0x00 0.--7. 1. " STOP ,Transfer Delay Time in Multiples of SPI Clock Period" group.long 0x14++0x3 line.long 0x00 "SPI1_SLVSEL,SPI1 Slave Select Register" bitfld.long 0x00 15. " SSEL7 ,Slave Select 7 Output" "0,1" bitfld.long 0x00 14. " SSEL6 ,Slave Select 6 Output" "0,1" bitfld.long 0x00 13. " SSEL5 ,Slave Select 5 Output" "0,1" newline bitfld.long 0x00 12. " SSEL4 ,Slave Select 4 Output" "0,1" bitfld.long 0x00 11. " SSEL3 ,Slave Select 3 Output" "0,1" bitfld.long 0x00 10. " SSEL2 ,Slave Select 2 Output" "0,1" newline bitfld.long 0x00 9. " SSEL1 ,Slave Select 1 Output" "0,1" bitfld.long 0x00 7. " SSE7 ,Slave Select 7 Enable" "0,1" bitfld.long 0x00 6. " SSE6 ,Slave Select 6 Enable" "0,1" newline bitfld.long 0x00 5. " SSE5 ,Slave Select 5 Enable" "0,1" bitfld.long 0x00 4. " SSE4 ,Slave Select 4 Enable" "0,1" bitfld.long 0x00 3. " SSE3 ,Slave Select 3 Enable" "0,1" newline bitfld.long 0x00 2. " SSE2 ,Slave Select 2 Enable" "0,1" bitfld.long 0x00 1. " SSE1 ,Slave Select 1 Enable" "0,1" group.long 0x18++0x3 line.long 0x00 "SPI1_RWC,SPI1 Received Word Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received Word Count" group.long 0x1C++0x3 line.long 0x00 "SPI1_RWCR,SPI1 Received Word Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received Word Count Reload" group.long 0x20++0x3 line.long 0x00 "SPI1_TWC,SPI1 Transmitted Word Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Transmitted Word Count" group.long 0x24++0x3 line.long 0x00 "SPI1_TWCR,SPI1 Transmitted Word Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Transmitted Word Count Reload" group.long 0x2C++0x3 line.long 0x00 "SPI1_IMSK,SPI1 Interrupt Mask Register" bitfld.long 0x00 11. " TF ,Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark" "0,1" group.long 0x30++0x3 line.long 0x00 "SPI1_IMSK_CLR,SPI1 Interrupt Mask Clear Register" bitfld.long 0x00 11. " TF ,Clear Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Clear Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Clear Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Clear Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Clear Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Clear Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Clear Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Clear Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Clear Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Clear Receive Urgent Watermark" "0,1" group.long 0x34++0x3 line.long 0x00 "SPI1_IMSK_SET,SPI1 Interrupt Mask Set Register" bitfld.long 0x00 11. " TF ,Set Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Set Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Set Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Set Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Set Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Set Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Set Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Set Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Set Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Set Receive Urgent Watermark" "0,1" group.long 0x3C++0x3 line.long 0x00 "SPI1_STAT,SPI1 Status Register" bitfld.long 0x00 23. " TFF ,SPI_TFIFO Full" "0,1" bitfld.long 0x00 22. " RFE ,SPI_RFIFO Empty" "0,1" bitfld.long 0x00 20. " FCS ,Flow Control Stall Indication" "0,1" newline bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " TF ,Transmit Finish Indication" "0,1" newline bitfld.long 0x00 10. " RF ,Receive Finish Indication" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start" "0,1" bitfld.long 0x00 8. " RS ,Receive Start" "0,1" newline bitfld.long 0x00 7. " MF ,Mode Fault Indication" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision Indication" "0,1" bitfld.long 0x00 5. " TUR ,Transmit Underrun Indication" "0,1" newline bitfld.long 0x00 4. " ROR ,Receive Overrun Indication" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark Breached" "0,1" bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark Breached" "0,1" newline bitfld.long 0x00 0. " SPIF ,SPI Finished" "0,1" group.long 0x40++0x3 line.long 0x00 "SPI1_ILAT,SPI1 Masked Interrupt Condition Register" bitfld.long 0x00 11. " TF ,Transmit Finish Interrupt Latch" "0,1" bitfld.long 0x00 10. " RF ,Receive Finish Interrupt Latch" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start Interrupt Latch" "0,1" newline bitfld.long 0x00 8. " RS ,Receive Start Interrupt Latch" "0,1" bitfld.long 0x00 7. " MF ,Mode Fault Interrupt Latch" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision Interrupt Latch" "0,1" newline bitfld.long 0x00 5. " TUR ,Transmit Underrun Interrupt Latch" "0,1" bitfld.long 0x00 4. " ROR ,Receive Overrun Interrupt Latch" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark Interrupt Latch" "0,1" newline bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark Interrupt Latch" "0,1" group.long 0x44++0x3 line.long 0x00 "SPI1_ILAT_CLR,SPI1 Masked Interrupt Clear Register" bitfld.long 0x00 11. " TF ,Clear Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Clear Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Clear Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Clear Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Clear Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Clear Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Clear Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Clear Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Clear Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Clear Receive Urgent Watermark" "0,1" group.long 0x4C++0x3 line.long 0x00 "SPI1_RFIFO,SPI1 Receive FIFO Data Register" group.long 0x54++0x3 line.long 0x00 "SPI1_TFIFO,SPI1 Transmit FIFO Data Register" tree.end tree "SPI2" base ad:0x31030004 width 15. group.long 0x0++0x3 line.long 0x00 "SPI2_CTL,SPI2 Control Register" bitfld.long 0x00 31. " MMSE ,Memory-Mapped SPI Enable" "0,1" bitfld.long 0x00 30. " MMWEM ,Memory Mapped Write Error Mask" "0,1" bitfld.long 0x00 22. " SOSI ,Start on MOSI" "0,1" newline bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O Mode" "0,1,2,3" bitfld.long 0x00 18. " FMODE ,Fast-Mode Enable" "0,1" bitfld.long 0x00 16.--17. " FCWM ,Flow Control Watermark" "0,1,2,3" newline bitfld.long 0x00 15. " FCPL ,Flow Control Polarity" "0,1" bitfld.long 0x00 14. " FCCH ,Flow Control Channel Selection" "0,1" bitfld.long 0x00 13. " FCEN ,Flow Control Enable" "0,1" newline bitfld.long 0x00 12. " LSBF ,Least Significant Bit First" "0,1" bitfld.long 0x00 9.--10. " SIZE ,Word Transfer Size" "0,1,2,3" bitfld.long 0x00 8. " EMISO ,Enable MISO" "0,1" newline bitfld.long 0x00 7. " SELST ,Slave Select Polarity Between Transfers" "0,1" bitfld.long 0x00 6. " ASSEL ,Slave Select Pin Control" "0,1" bitfld.long 0x00 5. " CPOL ,Clock Polarity" "0,1" newline bitfld.long 0x00 4. " CPHA ,Clock Phase" "0,1" bitfld.long 0x00 3. " ODM ,Open Drain Mode" "0,1" bitfld.long 0x00 2. " PSSE ,Protected Slave Select Enable" "0,1" newline bitfld.long 0x00 1. " MSTR ,Master/Slave" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SPI2_RXCTL,SPI2 Receive Control Register" bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO Urgent Watermark" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO Regular Watermark" "0,1,2,3" bitfld.long 0x00 8. " RDO ,Receive Data Overrun" "0,1" newline bitfld.long 0x00 4.--6. " RDR ,Receive Data Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " RWCEN ,Receive Word Counter Enable" "0,1" bitfld.long 0x00 2. " RTI ,Receive Transfer Initiate" "0,1" newline bitfld.long 0x00 0. " REN ,Receive Enable" "0,1" group.long 0x8++0x3 line.long 0x00 "SPI2_TXCTL,SPI2 Transmit Control Register" bitfld.long 0x00 16.--18. " TUWM ,FIFO Urgent Watermark" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " TRWM ,FIFO Regular Watermark" "0,1,2,3" bitfld.long 0x00 8. " TDU ,Transmit Data Underrun" "0,1" newline bitfld.long 0x00 4.--6. " TDR ,Transmit Data Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " TWCEN ,Transmit Word Counter Enable" "0,1" bitfld.long 0x00 2. " TTI ,Transmit Transfer Initiate" "0,1" newline bitfld.long 0x00 0. " TEN ,Transmit Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPI2_CLK,SPI2 Clock Rate Register" hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate" group.long 0x10++0x3 line.long 0x00 "SPI2_DLY,SPI2 Delay Register" bitfld.long 0x00 9. " LAGX ,Extended SPI Clock Lag Control" "0,1" bitfld.long 0x00 8. " LEADX ,Extended SPI Clock Lead Control" "0,1" hexmask.long.byte 0x00 0.--7. 1. " STOP ,Transfer Delay Time in Multiples of SPI Clock Period" group.long 0x14++0x3 line.long 0x00 "SPI2_SLVSEL,SPI2 Slave Select Register" bitfld.long 0x00 15. " SSEL7 ,Slave Select 7 Output" "0,1" bitfld.long 0x00 14. " SSEL6 ,Slave Select 6 Output" "0,1" bitfld.long 0x00 13. " SSEL5 ,Slave Select 5 Output" "0,1" newline bitfld.long 0x00 12. " SSEL4 ,Slave Select 4 Output" "0,1" bitfld.long 0x00 11. " SSEL3 ,Slave Select 3 Output" "0,1" bitfld.long 0x00 10. " SSEL2 ,Slave Select 2 Output" "0,1" newline bitfld.long 0x00 9. " SSEL1 ,Slave Select 1 Output" "0,1" bitfld.long 0x00 7. " SSE7 ,Slave Select 7 Enable" "0,1" bitfld.long 0x00 6. " SSE6 ,Slave Select 6 Enable" "0,1" newline bitfld.long 0x00 5. " SSE5 ,Slave Select 5 Enable" "0,1" bitfld.long 0x00 4. " SSE4 ,Slave Select 4 Enable" "0,1" bitfld.long 0x00 3. " SSE3 ,Slave Select 3 Enable" "0,1" newline bitfld.long 0x00 2. " SSE2 ,Slave Select 2 Enable" "0,1" bitfld.long 0x00 1. " SSE1 ,Slave Select 1 Enable" "0,1" group.long 0x18++0x3 line.long 0x00 "SPI2_RWC,SPI2 Received Word Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received Word Count" group.long 0x1C++0x3 line.long 0x00 "SPI2_RWCR,SPI2 Received Word Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received Word Count Reload" group.long 0x20++0x3 line.long 0x00 "SPI2_TWC,SPI2 Transmitted Word Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Transmitted Word Count" group.long 0x24++0x3 line.long 0x00 "SPI2_TWCR,SPI2 Transmitted Word Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Transmitted Word Count Reload" group.long 0x2C++0x3 line.long 0x00 "SPI2_IMSK,SPI2 Interrupt Mask Register" bitfld.long 0x00 11. " TF ,Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark" "0,1" group.long 0x30++0x3 line.long 0x00 "SPI2_IMSK_CLR,SPI2 Interrupt Mask Clear Register" bitfld.long 0x00 11. " TF ,Clear Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Clear Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Clear Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Clear Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Clear Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Clear Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Clear Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Clear Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Clear Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Clear Receive Urgent Watermark" "0,1" group.long 0x34++0x3 line.long 0x00 "SPI2_IMSK_SET,SPI2 Interrupt Mask Set Register" bitfld.long 0x00 11. " TF ,Set Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Set Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Set Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Set Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Set Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Set Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Set Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Set Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Set Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Set Receive Urgent Watermark" "0,1" group.long 0x3C++0x3 line.long 0x00 "SPI2_STAT,SPI2 Status Register" bitfld.long 0x00 31. " MMAE ,Memory Mapped Access Error" "0,1" bitfld.long 0x00 29. " MMRE ,Memory Mapped Read Error" "0,1" bitfld.long 0x00 28. " MMWE ,Memory Mapped Write Error" "0,1" newline bitfld.long 0x00 23. " TFF ,SPI_TFIFO Full" "0,1" bitfld.long 0x00 22. " RFE ,SPI_RFIFO Empty" "0,1" bitfld.long 0x00 20. " FCS ,Flow Control Stall Indication" "0,1" newline bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " TF ,Transmit Finish Indication" "0,1" newline bitfld.long 0x00 10. " RF ,Receive Finish Indication" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start" "0,1" bitfld.long 0x00 8. " RS ,Receive Start" "0,1" newline bitfld.long 0x00 7. " MF ,Mode Fault Indication" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision Indication" "0,1" bitfld.long 0x00 5. " TUR ,Transmit Underrun Indication" "0,1" newline bitfld.long 0x00 4. " ROR ,Receive Overrun Indication" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark Breached" "0,1" bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark Breached" "0,1" newline bitfld.long 0x00 0. " SPIF ,SPI Finished" "0,1" group.long 0x40++0x3 line.long 0x00 "SPI2_ILAT,SPI2 Masked Interrupt Condition Register" bitfld.long 0x00 11. " TF ,Transmit Finish Interrupt Latch" "0,1" bitfld.long 0x00 10. " RF ,Receive Finish Interrupt Latch" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start Interrupt Latch" "0,1" newline bitfld.long 0x00 8. " RS ,Receive Start Interrupt Latch" "0,1" bitfld.long 0x00 7. " MF ,Mode Fault Interrupt Latch" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision Interrupt Latch" "0,1" newline bitfld.long 0x00 5. " TUR ,Transmit Underrun Interrupt Latch" "0,1" bitfld.long 0x00 4. " ROR ,Receive Overrun Interrupt Latch" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark Interrupt Latch" "0,1" newline bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark Interrupt Latch" "0,1" group.long 0x44++0x3 line.long 0x00 "SPI2_ILAT_CLR,SPI2 Masked Interrupt Clear Register" bitfld.long 0x00 11. " TF ,Clear Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Clear Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Clear Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Clear Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Clear Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Clear Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Clear Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Clear Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Clear Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Clear Receive Urgent Watermark" "0,1" group.long 0x4C++0x3 line.long 0x00 "SPI2_RFIFO,SPI2 Receive FIFO Data Register" group.long 0x54++0x3 line.long 0x00 "SPI2_TFIFO,SPI2 Transmit FIFO Data Register" group.long 0x5C++0x3 line.long 0x00 "SPI2_MMRDH,SPI2 Memory Mapped Read Header" bitfld.long 0x00 29. " CMDPINS ,Pins Used for Command" "0,1" bitfld.long 0x00 28. " CMDSKIP ,Command Skip Enable" "0,1" bitfld.long 0x00 27. " WRAP ,SPI Memory Wrap Indicator" "0,1" newline bitfld.long 0x00 26. " MERGE ,Merge Enable" "0,1" bitfld.long 0x00 24.--25. " TRIDMY ,Tristate Dummy Timing" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " MODE ,Mode Field" newline bitfld.long 0x00 12.--14. " DMYSIZE ,Bytes of Dummy/Mode" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " ADRPINS ,Pins Used for Address" "0,1" bitfld.long 0x00 8.--10. " ADRSIZE ,Bytes of Read Address" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x00 0.--7. 1. " OPCODE ,Read Opcode" group.long 0x60++0x3 line.long 0x00 "SPI2_MMTOP,SPI2 SPI Memory Top Address" tree.end tree "SPI3" base ad:0x31031004 width 15. group.long 0x0++0x3 line.long 0x00 "SPI3_CTL,SPI3 Control Register" bitfld.long 0x00 22. " SOSI ,Start on MOSI" "0,1" bitfld.long 0x00 20.--21. " MIOM ,Multiple I/O Mode" "0,1,2,3" bitfld.long 0x00 18. " FMODE ,Fast-Mode Enable" "0,1" newline bitfld.long 0x00 16.--17. " FCWM ,Flow Control Watermark" "0,1,2,3" bitfld.long 0x00 15. " FCPL ,Flow Control Polarity" "0,1" bitfld.long 0x00 14. " FCCH ,Flow Control Channel Selection" "0,1" newline bitfld.long 0x00 13. " FCEN ,Flow Control Enable" "0,1" bitfld.long 0x00 12. " LSBF ,Least Significant Bit First" "0,1" bitfld.long 0x00 9.--10. " SIZE ,Word Transfer Size" "0,1,2,3" newline bitfld.long 0x00 8. " EMISO ,Enable MISO" "0,1" bitfld.long 0x00 7. " SELST ,Slave Select Polarity Between Transfers" "0,1" bitfld.long 0x00 6. " ASSEL ,Slave Select Pin Control" "0,1" newline bitfld.long 0x00 5. " CPOL ,Clock Polarity" "0,1" bitfld.long 0x00 4. " CPHA ,Clock Phase" "0,1" bitfld.long 0x00 3. " ODM ,Open Drain Mode" "0,1" newline bitfld.long 0x00 2. " PSSE ,Protected Slave Select Enable" "0,1" bitfld.long 0x00 1. " MSTR ,Master/Slave" "0,1" bitfld.long 0x00 0. " EN ,Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SPI3_RXCTL,SPI3 Receive Control Register" bitfld.long 0x00 16.--18. " RUWM ,Receive FIFO Urgent Watermark" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " RRWM ,Receive FIFO Regular Watermark" "0,1,2,3" bitfld.long 0x00 8. " RDO ,Receive Data Overrun" "0,1" newline bitfld.long 0x00 4.--6. " RDR ,Receive Data Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " RWCEN ,Receive Word Counter Enable" "0,1" bitfld.long 0x00 2. " RTI ,Receive Transfer Initiate" "0,1" newline bitfld.long 0x00 0. " REN ,Receive Enable" "0,1" group.long 0x8++0x3 line.long 0x00 "SPI3_TXCTL,SPI3 Transmit Control Register" bitfld.long 0x00 16.--18. " TUWM ,FIFO Urgent Watermark" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " TRWM ,FIFO Regular Watermark" "0,1,2,3" bitfld.long 0x00 8. " TDU ,Transmit Data Underrun" "0,1" newline bitfld.long 0x00 4.--6. " TDR ,Transmit Data Request" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " TWCEN ,Transmit Word Counter Enable" "0,1" bitfld.long 0x00 2. " TTI ,Transmit Transfer Initiate" "0,1" newline bitfld.long 0x00 0. " TEN ,Transmit Enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPI3_CLK,SPI3 Clock Rate Register" hexmask.long.word 0x00 0.--15. 1. " BAUD ,Baud Rate" group.long 0x10++0x3 line.long 0x00 "SPI3_DLY,SPI3 Delay Register" bitfld.long 0x00 9. " LAGX ,Extended SPI Clock Lag Control" "0,1" bitfld.long 0x00 8. " LEADX ,Extended SPI Clock Lead Control" "0,1" hexmask.long.byte 0x00 0.--7. 1. " STOP ,Transfer Delay Time in Multiples of SPI Clock Period" group.long 0x14++0x3 line.long 0x00 "SPI3_SLVSEL,SPI3 Slave Select Register" bitfld.long 0x00 15. " SSEL7 ,Slave Select 7 Output" "0,1" bitfld.long 0x00 14. " SSEL6 ,Slave Select 6 Output" "0,1" bitfld.long 0x00 13. " SSEL5 ,Slave Select 5 Output" "0,1" newline bitfld.long 0x00 12. " SSEL4 ,Slave Select 4 Output" "0,1" bitfld.long 0x00 11. " SSEL3 ,Slave Select 3 Output" "0,1" bitfld.long 0x00 10. " SSEL2 ,Slave Select 2 Output" "0,1" newline bitfld.long 0x00 9. " SSEL1 ,Slave Select 1 Output" "0,1" bitfld.long 0x00 7. " SSE7 ,Slave Select 7 Enable" "0,1" bitfld.long 0x00 6. " SSE6 ,Slave Select 6 Enable" "0,1" newline bitfld.long 0x00 5. " SSE5 ,Slave Select 5 Enable" "0,1" bitfld.long 0x00 4. " SSE4 ,Slave Select 4 Enable" "0,1" bitfld.long 0x00 3. " SSE3 ,Slave Select 3 Enable" "0,1" newline bitfld.long 0x00 2. " SSE2 ,Slave Select 2 Enable" "0,1" bitfld.long 0x00 1. " SSE1 ,Slave Select 1 Enable" "0,1" group.long 0x18++0x3 line.long 0x00 "SPI3_RWC,SPI3 Received Word Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received Word Count" group.long 0x1C++0x3 line.long 0x00 "SPI3_RWCR,SPI3 Received Word Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Received Word Count Reload" group.long 0x20++0x3 line.long 0x00 "SPI3_TWC,SPI3 Transmitted Word Count Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Transmitted Word Count" group.long 0x24++0x3 line.long 0x00 "SPI3_TWCR,SPI3 Transmitted Word Count Reload Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Transmitted Word Count Reload" group.long 0x2C++0x3 line.long 0x00 "SPI3_IMSK,SPI3 Interrupt Mask Register" bitfld.long 0x00 11. " TF ,Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark" "0,1" group.long 0x30++0x3 line.long 0x00 "SPI3_IMSK_CLR,SPI3 Interrupt Mask Clear Register" bitfld.long 0x00 11. " TF ,Clear Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Clear Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Clear Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Clear Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Clear Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Clear Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Clear Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Clear Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Clear Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Clear Receive Urgent Watermark" "0,1" group.long 0x34++0x3 line.long 0x00 "SPI3_IMSK_SET,SPI3 Interrupt Mask Set Register" bitfld.long 0x00 11. " TF ,Set Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Set Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Set Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Set Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Set Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Set Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Set Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Set Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Set Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Set Receive Urgent Watermark" "0,1" group.long 0x3C++0x3 line.long 0x00 "SPI3_STAT,SPI3 Status Register" bitfld.long 0x00 23. " TFF ,SPI_TFIFO Full" "0,1" bitfld.long 0x00 22. " RFE ,SPI_RFIFO Empty" "0,1" bitfld.long 0x00 20. " FCS ,Flow Control Stall Indication" "0,1" newline bitfld.long 0x00 16.--18. " TFS ,SPI_TFIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " RFS ,SPI_RFIFO Status" "0,1,2,3,4,5,6,7" bitfld.long 0x00 11. " TF ,Transmit Finish Indication" "0,1" newline bitfld.long 0x00 10. " RF ,Receive Finish Indication" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start" "0,1" bitfld.long 0x00 8. " RS ,Receive Start" "0,1" newline bitfld.long 0x00 7. " MF ,Mode Fault Indication" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision Indication" "0,1" bitfld.long 0x00 5. " TUR ,Transmit Underrun Indication" "0,1" newline bitfld.long 0x00 4. " ROR ,Receive Overrun Indication" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark Breached" "0,1" bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark Breached" "0,1" newline bitfld.long 0x00 0. " SPIF ,SPI Finished" "0,1" group.long 0x40++0x3 line.long 0x00 "SPI3_ILAT,SPI3 Masked Interrupt Condition Register" bitfld.long 0x00 11. " TF ,Transmit Finish Interrupt Latch" "0,1" bitfld.long 0x00 10. " RF ,Receive Finish Interrupt Latch" "0,1" bitfld.long 0x00 9. " TS ,Transmit Start Interrupt Latch" "0,1" newline bitfld.long 0x00 8. " RS ,Receive Start Interrupt Latch" "0,1" bitfld.long 0x00 7. " MF ,Mode Fault Interrupt Latch" "0,1" bitfld.long 0x00 6. " TC ,Transmit Collision Interrupt Latch" "0,1" newline bitfld.long 0x00 5. " TUR ,Transmit Underrun Interrupt Latch" "0,1" bitfld.long 0x00 4. " ROR ,Receive Overrun Interrupt Latch" "0,1" bitfld.long 0x00 2. " TUWM ,Transmit Urgent Watermark Interrupt Latch" "0,1" newline bitfld.long 0x00 1. " RUWM ,Receive Urgent Watermark Interrupt Latch" "0,1" group.long 0x44++0x3 line.long 0x00 "SPI3_ILAT_CLR,SPI3 Masked Interrupt Clear Register" bitfld.long 0x00 11. " TF ,Clear Transmit Finish" "0,1" bitfld.long 0x00 10. " RF ,Clear Receive Finish" "0,1" bitfld.long 0x00 9. " TS ,Clear Transmit Start" "0,1" newline bitfld.long 0x00 8. " RS ,Clear Receive Start" "0,1" bitfld.long 0x00 7. " MF ,Clear Mode Fault" "0,1" bitfld.long 0x00 6. " TC ,Clear Transmit Collision" "0,1" newline bitfld.long 0x00 5. " TUR ,Clear Transmit Underrun" "0,1" bitfld.long 0x00 4. " ROR ,Clear Receive Overrun" "0,1" bitfld.long 0x00 2. " TUWM ,Clear Transmit Urgent Watermark" "0,1" newline bitfld.long 0x00 1. " RUWM ,Clear Receive Urgent Watermark" "0,1" group.long 0x4C++0x3 line.long 0x00 "SPI3_RFIFO,SPI3 Receive FIFO Data Register" group.long 0x54++0x3 line.long 0x00 "SPI3_TFIFO,SPI3 Transmit FIFO Data Register" tree.end tree.end tree "SPORT (Serial Port)" tree "SPORT0" base ad:0x31002000 width 16. group.long 0x0++0x3 line.long 0x00 "SPORT0_CTL_A,SPORT0 Half SPORT 'A' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x4++0x3 line.long 0x00 "SPORT0_DIV_A,SPORT0 Half SPORT 'A' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "SPORT0_MCTL_A,SPORT0 Half SPORT 'A' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPORT0_CS0_A,SPORT0 Half SPORT 'A' Multichannel 0-31 Select Register" group.long 0x10++0x3 line.long 0x00 "SPORT0_CS1_A,SPORT0 Half SPORT 'A' Multichannel 32-63 Select Register" group.long 0x14++0x3 line.long 0x00 "SPORT0_CS2_A,SPORT0 Half SPORT 'A' Multichannel 64-95 Select Register" group.long 0x18++0x3 line.long 0x00 "SPORT0_CS3_A,SPORT0 Half SPORT 'A' Multichannel 96-127 Select Register" group.long 0x20++0x3 line.long 0x00 "SPORT0_ERR_A,SPORT0 Half SPORT 'A' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "SPORT0_MSTAT_A,SPORT0 Half SPORT 'A' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0x28++0x3 line.long 0x00 "SPORT0_CTL2_A,SPORT0 Half SPORT 'A' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0x40++0x3 line.long 0x00 "SPORT0_TXPRI_A,SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register" group.long 0x44++0x3 line.long 0x00 "SPORT0_RXPRI_A,SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register" group.long 0x48++0x3 line.long 0x00 "SPORT0_TXSEC_A,SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register" group.long 0x4C++0x3 line.long 0x00 "SPORT0_RXSEC_A,SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register" group.long 0x80++0x3 line.long 0x00 "SPORT0_CTL_B,SPORT0 Half SPORT 'B' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation Mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x84++0x3 line.long 0x00 "SPORT0_DIV_B,SPORT0 Half SPORT 'B' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x88++0x3 line.long 0x00 "SPORT0_MCTL_B,SPORT0 Half SPORT 'B' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel Enable" "0,1" group.long 0x8C++0x3 line.long 0x00 "SPORT0_CS0_B,SPORT0 Half SPORT 'B' Multichannel 0-31 Select Register" group.long 0x90++0x3 line.long 0x00 "SPORT0_CS1_B,SPORT0 Half SPORT 'B' Multichannel 32-63 Select Register" group.long 0x94++0x3 line.long 0x00 "SPORT0_CS2_B,SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register" group.long 0x98++0x3 line.long 0x00 "SPORT0_CS3_B,SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register" group.long 0xA0++0x3 line.long 0x00 "SPORT0_ERR_B,SPORT0 Half SPORT 'B' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0xA4++0x3 line.long 0x00 "SPORT0_MSTAT_B,SPORT0 Half SPORT 'B' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0xA8++0x3 line.long 0x00 "SPORT0_CTL2_B,SPORT0 Half SPORT 'B' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0xC0++0x3 line.long 0x00 "SPORT0_TXPRI_B,SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register" group.long 0xC4++0x3 line.long 0x00 "SPORT0_RXPRI_B,SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register" group.long 0xC8++0x3 line.long 0x00 "SPORT0_TXSEC_B,SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register" group.long 0xCC++0x3 line.long 0x00 "SPORT0_RXSEC_B,SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register" tree.end tree "SPORT1" base ad:0x31002100 width 16. group.long 0x0++0x3 line.long 0x00 "SPORT1_CTL_A,SPORT1 Half SPORT 'A' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x4++0x3 line.long 0x00 "SPORT1_DIV_A,SPORT1 Half SPORT 'A' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "SPORT1_MCTL_A,SPORT1 Half SPORT 'A' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPORT1_CS0_A,SPORT1 Half SPORT 'A' Multichannel 0-31 Select Register" group.long 0x10++0x3 line.long 0x00 "SPORT1_CS1_A,SPORT1 Half SPORT 'A' Multichannel 32-63 Select Register" group.long 0x14++0x3 line.long 0x00 "SPORT1_CS2_A,SPORT1 Half SPORT 'A' Multichannel 64-95 Select Register" group.long 0x18++0x3 line.long 0x00 "SPORT1_CS3_A,SPORT1 Half SPORT 'A' Multichannel 96-127 Select Register" group.long 0x20++0x3 line.long 0x00 "SPORT1_ERR_A,SPORT1 Half SPORT 'A' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "SPORT1_MSTAT_A,SPORT1 Half SPORT 'A' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0x28++0x3 line.long 0x00 "SPORT1_CTL2_A,SPORT1 Half SPORT 'A' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0x40++0x3 line.long 0x00 "SPORT1_TXPRI_A,SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register" group.long 0x44++0x3 line.long 0x00 "SPORT1_RXPRI_A,SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register" group.long 0x48++0x3 line.long 0x00 "SPORT1_TXSEC_A,SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register" group.long 0x4C++0x3 line.long 0x00 "SPORT1_RXSEC_A,SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register" group.long 0x80++0x3 line.long 0x00 "SPORT1_CTL_B,SPORT1 Half SPORT 'B' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation Mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x84++0x3 line.long 0x00 "SPORT1_DIV_B,SPORT1 Half SPORT 'B' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x88++0x3 line.long 0x00 "SPORT1_MCTL_B,SPORT1 Half SPORT 'B' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel Enable" "0,1" group.long 0x8C++0x3 line.long 0x00 "SPORT1_CS0_B,SPORT1 Half SPORT 'B' Multichannel 0-31 Select Register" group.long 0x90++0x3 line.long 0x00 "SPORT1_CS1_B,SPORT1 Half SPORT 'B' Multichannel 32-63 Select Register" group.long 0x94++0x3 line.long 0x00 "SPORT1_CS2_B,SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register" group.long 0x98++0x3 line.long 0x00 "SPORT1_CS3_B,SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register" group.long 0xA0++0x3 line.long 0x00 "SPORT1_ERR_B,SPORT1 Half SPORT 'B' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0xA4++0x3 line.long 0x00 "SPORT1_MSTAT_B,SPORT1 Half SPORT 'B' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0xA8++0x3 line.long 0x00 "SPORT1_CTL2_B,SPORT1 Half SPORT 'B' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0xC0++0x3 line.long 0x00 "SPORT1_TXPRI_B,SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register" group.long 0xC4++0x3 line.long 0x00 "SPORT1_RXPRI_B,SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register" group.long 0xC8++0x3 line.long 0x00 "SPORT1_TXSEC_B,SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register" group.long 0xCC++0x3 line.long 0x00 "SPORT1_RXSEC_B,SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register" tree.end tree "SPORT2" base ad:0x31002200 width 16. group.long 0x0++0x3 line.long 0x00 "SPORT2_CTL_A,SPORT2 Half SPORT 'A' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x4++0x3 line.long 0x00 "SPORT2_DIV_A,SPORT2 Half SPORT 'A' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "SPORT2_MCTL_A,SPORT2 Half SPORT 'A' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPORT2_CS0_A,SPORT2 Half SPORT 'A' Multichannel 0-31 Select Register" group.long 0x10++0x3 line.long 0x00 "SPORT2_CS1_A,SPORT2 Half SPORT 'A' Multichannel 32-63 Select Register" group.long 0x14++0x3 line.long 0x00 "SPORT2_CS2_A,SPORT2 Half SPORT 'A' Multichannel 64-95 Select Register" group.long 0x18++0x3 line.long 0x00 "SPORT2_CS3_A,SPORT2 Half SPORT 'A' Multichannel 96-127 Select Register" group.long 0x20++0x3 line.long 0x00 "SPORT2_ERR_A,SPORT2 Half SPORT 'A' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "SPORT2_MSTAT_A,SPORT2 Half SPORT 'A' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0x28++0x3 line.long 0x00 "SPORT2_CTL2_A,SPORT2 Half SPORT 'A' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0x40++0x3 line.long 0x00 "SPORT2_TXPRI_A,SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register" group.long 0x44++0x3 line.long 0x00 "SPORT2_RXPRI_A,SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register" group.long 0x48++0x3 line.long 0x00 "SPORT2_TXSEC_A,SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register" group.long 0x4C++0x3 line.long 0x00 "SPORT2_RXSEC_A,SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register" group.long 0x80++0x3 line.long 0x00 "SPORT2_CTL_B,SPORT2 Half SPORT 'B' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation Mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x84++0x3 line.long 0x00 "SPORT2_DIV_B,SPORT2 Half SPORT 'B' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x88++0x3 line.long 0x00 "SPORT2_MCTL_B,SPORT2 Half SPORT 'B' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel Enable" "0,1" group.long 0x8C++0x3 line.long 0x00 "SPORT2_CS0_B,SPORT2 Half SPORT 'B' Multichannel 0-31 Select Register" group.long 0x90++0x3 line.long 0x00 "SPORT2_CS1_B,SPORT2 Half SPORT 'B' Multichannel 32-63 Select Register" group.long 0x94++0x3 line.long 0x00 "SPORT2_CS2_B,SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register" group.long 0x98++0x3 line.long 0x00 "SPORT2_CS3_B,SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register" group.long 0xA0++0x3 line.long 0x00 "SPORT2_ERR_B,SPORT2 Half SPORT 'B' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0xA4++0x3 line.long 0x00 "SPORT2_MSTAT_B,SPORT2 Half SPORT 'B' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0xA8++0x3 line.long 0x00 "SPORT2_CTL2_B,SPORT2 Half SPORT 'B' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0xC0++0x3 line.long 0x00 "SPORT2_TXPRI_B,SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register" group.long 0xC4++0x3 line.long 0x00 "SPORT2_RXPRI_B,SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register" group.long 0xC8++0x3 line.long 0x00 "SPORT2_TXSEC_B,SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register" group.long 0xCC++0x3 line.long 0x00 "SPORT2_RXSEC_B,SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register" tree.end tree "SPORT3" base ad:0x31002300 width 16. group.long 0x0++0x3 line.long 0x00 "SPORT3_CTL_A,SPORT3 Half SPORT 'A' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x4++0x3 line.long 0x00 "SPORT3_DIV_A,SPORT3 Half SPORT 'A' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "SPORT3_MCTL_A,SPORT3 Half SPORT 'A' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPORT3_CS0_A,SPORT3 Half SPORT 'A' Multichannel 0-31 Select Register" group.long 0x10++0x3 line.long 0x00 "SPORT3_CS1_A,SPORT3 Half SPORT 'A' Multichannel 32-63 Select Register" group.long 0x14++0x3 line.long 0x00 "SPORT3_CS2_A,SPORT3 Half SPORT 'A' Multichannel 64-95 Select Register" group.long 0x18++0x3 line.long 0x00 "SPORT3_CS3_A,SPORT3 Half SPORT 'A' Multichannel 96-127 Select Register" group.long 0x20++0x3 line.long 0x00 "SPORT3_ERR_A,SPORT3 Half SPORT 'A' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "SPORT3_MSTAT_A,SPORT3 Half SPORT 'A' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0x28++0x3 line.long 0x00 "SPORT3_CTL2_A,SPORT3 Half SPORT 'A' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0x40++0x3 line.long 0x00 "SPORT3_TXPRI_A,SPORT3 Half SPORT 'A' Tx Buffer (Primary) Register" group.long 0x44++0x3 line.long 0x00 "SPORT3_RXPRI_A,SPORT3 Half SPORT 'A' Rx Buffer (Primary) Register" group.long 0x48++0x3 line.long 0x00 "SPORT3_TXSEC_A,SPORT3 Half SPORT 'A' Tx Buffer (Secondary) Register" group.long 0x4C++0x3 line.long 0x00 "SPORT3_RXSEC_A,SPORT3 Half SPORT 'A' Rx Buffer (Secondary) Register" group.long 0x80++0x3 line.long 0x00 "SPORT3_CTL_B,SPORT3 Half SPORT 'B' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation Mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x84++0x3 line.long 0x00 "SPORT3_DIV_B,SPORT3 Half SPORT 'B' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x88++0x3 line.long 0x00 "SPORT3_MCTL_B,SPORT3 Half SPORT 'B' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel Enable" "0,1" group.long 0x8C++0x3 line.long 0x00 "SPORT3_CS0_B,SPORT3 Half SPORT 'B' Multichannel 0-31 Select Register" group.long 0x90++0x3 line.long 0x00 "SPORT3_CS1_B,SPORT3 Half SPORT 'B' Multichannel 32-63 Select Register" group.long 0x94++0x3 line.long 0x00 "SPORT3_CS2_B,SPORT3 Half SPORT 'B' Multichannel 64-95 Select Register" group.long 0x98++0x3 line.long 0x00 "SPORT3_CS3_B,SPORT3 Half SPORT 'B' Multichannel 96-127 Select Register" group.long 0xA0++0x3 line.long 0x00 "SPORT3_ERR_B,SPORT3 Half SPORT 'B' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0xA4++0x3 line.long 0x00 "SPORT3_MSTAT_B,SPORT3 Half SPORT 'B' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0xA8++0x3 line.long 0x00 "SPORT3_CTL2_B,SPORT3 Half SPORT 'B' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0xC0++0x3 line.long 0x00 "SPORT3_TXPRI_B,SPORT3 Half SPORT 'B' Tx Buffer (Primary) Register" group.long 0xC4++0x3 line.long 0x00 "SPORT3_RXPRI_B,SPORT3 Half SPORT 'B' Rx Buffer (Primary) Register" group.long 0xC8++0x3 line.long 0x00 "SPORT3_TXSEC_B,SPORT3 Half SPORT 'B' Tx Buffer (Secondary) Register" group.long 0xCC++0x3 line.long 0x00 "SPORT3_RXSEC_B,SPORT3 Half SPORT 'B' Rx Buffer (Secondary) Register" tree.end tree "SPORT4" base ad:0x31002400 width 16. group.long 0x0++0x3 line.long 0x00 "SPORT4_CTL_A,SPORT4 Half SPORT 'A' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x4++0x3 line.long 0x00 "SPORT4_DIV_A,SPORT4 Half SPORT 'A' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "SPORT4_MCTL_A,SPORT4 Half SPORT 'A' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPORT4_CS0_A,SPORT4 Half SPORT 'A' Multichannel 0-31 Select Register" group.long 0x10++0x3 line.long 0x00 "SPORT4_CS1_A,SPORT4 Half SPORT 'A' Multichannel 32-63 Select Register" group.long 0x14++0x3 line.long 0x00 "SPORT4_CS2_A,SPORT4 Half SPORT 'A' Multichannel 64-95 Select Register" group.long 0x18++0x3 line.long 0x00 "SPORT4_CS3_A,SPORT4 Half SPORT 'A' Multichannel 96-127 Select Register" group.long 0x20++0x3 line.long 0x00 "SPORT4_ERR_A,SPORT4 Half SPORT 'A' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "SPORT4_MSTAT_A,SPORT4 Half SPORT 'A' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0x28++0x3 line.long 0x00 "SPORT4_CTL2_A,SPORT4 Half SPORT 'A' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0x40++0x3 line.long 0x00 "SPORT4_TXPRI_A,SPORT4 Half SPORT 'A' Tx Buffer (Primary) Register" group.long 0x44++0x3 line.long 0x00 "SPORT4_RXPRI_A,SPORT4 Half SPORT 'A' Rx Buffer (Primary) Register" group.long 0x48++0x3 line.long 0x00 "SPORT4_TXSEC_A,SPORT4 Half SPORT 'A' Tx Buffer (Secondary) Register" group.long 0x4C++0x3 line.long 0x00 "SPORT4_RXSEC_A,SPORT4 Half SPORT 'A' Rx Buffer (Secondary) Register" group.long 0x80++0x3 line.long 0x00 "SPORT4_CTL_B,SPORT4 Half SPORT 'B' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation Mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x84++0x3 line.long 0x00 "SPORT4_DIV_B,SPORT4 Half SPORT 'B' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x88++0x3 line.long 0x00 "SPORT4_MCTL_B,SPORT4 Half SPORT 'B' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel Enable" "0,1" group.long 0x8C++0x3 line.long 0x00 "SPORT4_CS0_B,SPORT4 Half SPORT 'B' Multichannel 0-31 Select Register" group.long 0x90++0x3 line.long 0x00 "SPORT4_CS1_B,SPORT4 Half SPORT 'B' Multichannel 32-63 Select Register" group.long 0x94++0x3 line.long 0x00 "SPORT4_CS2_B,SPORT4 Half SPORT 'B' Multichannel 64-95 Select Register" group.long 0x98++0x3 line.long 0x00 "SPORT4_CS3_B,SPORT4 Half SPORT 'B' Multichannel 96-127 Select Register" group.long 0xA0++0x3 line.long 0x00 "SPORT4_ERR_B,SPORT4 Half SPORT 'B' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0xA4++0x3 line.long 0x00 "SPORT4_MSTAT_B,SPORT4 Half SPORT 'B' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0xA8++0x3 line.long 0x00 "SPORT4_CTL2_B,SPORT4 Half SPORT 'B' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0xC0++0x3 line.long 0x00 "SPORT4_TXPRI_B,SPORT4 Half SPORT 'B' Tx Buffer (Primary) Register" group.long 0xC4++0x3 line.long 0x00 "SPORT4_RXPRI_B,SPORT4 Half SPORT 'B' Rx Buffer (Primary) Register" group.long 0xC8++0x3 line.long 0x00 "SPORT4_TXSEC_B,SPORT4 Half SPORT 'B' Tx Buffer (Secondary) Register" group.long 0xCC++0x3 line.long 0x00 "SPORT4_RXSEC_B,SPORT4 Half SPORT 'B' Rx Buffer (Secondary) Register" tree.end tree "SPORT5" base ad:0x31002500 width 16. group.long 0x0++0x3 line.long 0x00 "SPORT5_CTL_A,SPORT5 Half SPORT 'A' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x4++0x3 line.long 0x00 "SPORT5_DIV_A,SPORT5 Half SPORT 'A' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "SPORT5_MCTL_A,SPORT5 Half SPORT 'A' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPORT5_CS0_A,SPORT5 Half SPORT 'A' Multichannel 0-31 Select Register" group.long 0x10++0x3 line.long 0x00 "SPORT5_CS1_A,SPORT5 Half SPORT 'A' Multichannel 32-63 Select Register" group.long 0x14++0x3 line.long 0x00 "SPORT5_CS2_A,SPORT5 Half SPORT 'A' Multichannel 64-95 Select Register" group.long 0x18++0x3 line.long 0x00 "SPORT5_CS3_A,SPORT5 Half SPORT 'A' Multichannel 96-127 Select Register" group.long 0x20++0x3 line.long 0x00 "SPORT5_ERR_A,SPORT5 Half SPORT 'A' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "SPORT5_MSTAT_A,SPORT5 Half SPORT 'A' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0x28++0x3 line.long 0x00 "SPORT5_CTL2_A,SPORT5 Half SPORT 'A' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0x40++0x3 line.long 0x00 "SPORT5_TXPRI_A,SPORT5 Half SPORT 'A' Tx Buffer (Primary) Register" group.long 0x44++0x3 line.long 0x00 "SPORT5_RXPRI_A,SPORT5 Half SPORT 'A' Rx Buffer (Primary) Register" group.long 0x48++0x3 line.long 0x00 "SPORT5_TXSEC_A,SPORT5 Half SPORT 'A' Tx Buffer (Secondary) Register" group.long 0x4C++0x3 line.long 0x00 "SPORT5_RXSEC_A,SPORT5 Half SPORT 'A' Rx Buffer (Secondary) Register" group.long 0x80++0x3 line.long 0x00 "SPORT5_CTL_B,SPORT5 Half SPORT 'B' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation Mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x84++0x3 line.long 0x00 "SPORT5_DIV_B,SPORT5 Half SPORT 'B' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x88++0x3 line.long 0x00 "SPORT5_MCTL_B,SPORT5 Half SPORT 'B' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel Enable" "0,1" group.long 0x8C++0x3 line.long 0x00 "SPORT5_CS0_B,SPORT5 Half SPORT 'B' Multichannel 0-31 Select Register" group.long 0x90++0x3 line.long 0x00 "SPORT5_CS1_B,SPORT5 Half SPORT 'B' Multichannel 32-63 Select Register" group.long 0x94++0x3 line.long 0x00 "SPORT5_CS2_B,SPORT5 Half SPORT 'B' Multichannel 64-95 Select Register" group.long 0x98++0x3 line.long 0x00 "SPORT5_CS3_B,SPORT5 Half SPORT 'B' Multichannel 96-127 Select Register" group.long 0xA0++0x3 line.long 0x00 "SPORT5_ERR_B,SPORT5 Half SPORT 'B' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0xA4++0x3 line.long 0x00 "SPORT5_MSTAT_B,SPORT5 Half SPORT 'B' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0xA8++0x3 line.long 0x00 "SPORT5_CTL2_B,SPORT5 Half SPORT 'B' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0xC0++0x3 line.long 0x00 "SPORT5_TXPRI_B,SPORT5 Half SPORT 'B' Tx Buffer (Primary) Register" group.long 0xC4++0x3 line.long 0x00 "SPORT5_RXPRI_B,SPORT5 Half SPORT 'B' Rx Buffer (Primary) Register" group.long 0xC8++0x3 line.long 0x00 "SPORT5_TXSEC_B,SPORT5 Half SPORT 'B' Tx Buffer (Secondary) Register" group.long 0xCC++0x3 line.long 0x00 "SPORT5_RXSEC_B,SPORT5 Half SPORT 'B' Rx Buffer (Secondary) Register" tree.end tree "SPORT6" base ad:0x31002600 width 16. group.long 0x0++0x3 line.long 0x00 "SPORT6_CTL_A,SPORT6 Half SPORT 'A' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x4++0x3 line.long 0x00 "SPORT6_DIV_A,SPORT6 Half SPORT 'A' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "SPORT6_MCTL_A,SPORT6 Half SPORT 'A' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPORT6_CS0_A,SPORT6 Half SPORT 'A' Multichannel 0-31 Select Register" group.long 0x10++0x3 line.long 0x00 "SPORT6_CS1_A,SPORT6 Half SPORT 'A' Multichannel 32-63 Select Register" group.long 0x14++0x3 line.long 0x00 "SPORT6_CS2_A,SPORT6 Half SPORT 'A' Multichannel 64-95 Select Register" group.long 0x18++0x3 line.long 0x00 "SPORT6_CS3_A,SPORT6 Half SPORT 'A' Multichannel 96-127 Select Register" group.long 0x20++0x3 line.long 0x00 "SPORT6_ERR_A,SPORT6 Half SPORT 'A' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "SPORT6_MSTAT_A,SPORT6 Half SPORT 'A' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0x28++0x3 line.long 0x00 "SPORT6_CTL2_A,SPORT6 Half SPORT 'A' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0x40++0x3 line.long 0x00 "SPORT6_TXPRI_A,SPORT6 Half SPORT 'A' Tx Buffer (Primary) Register" group.long 0x44++0x3 line.long 0x00 "SPORT6_RXPRI_A,SPORT6 Half SPORT 'A' Rx Buffer (Primary) Register" group.long 0x48++0x3 line.long 0x00 "SPORT6_TXSEC_A,SPORT6 Half SPORT 'A' Tx Buffer (Secondary) Register" group.long 0x4C++0x3 line.long 0x00 "SPORT6_RXSEC_A,SPORT6 Half SPORT 'A' Rx Buffer (Secondary) Register" group.long 0x80++0x3 line.long 0x00 "SPORT6_CTL_B,SPORT6 Half SPORT 'B' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation Mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x84++0x3 line.long 0x00 "SPORT6_DIV_B,SPORT6 Half SPORT 'B' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x88++0x3 line.long 0x00 "SPORT6_MCTL_B,SPORT6 Half SPORT 'B' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel Enable" "0,1" group.long 0x8C++0x3 line.long 0x00 "SPORT6_CS0_B,SPORT6 Half SPORT 'B' Multichannel 0-31 Select Register" group.long 0x90++0x3 line.long 0x00 "SPORT6_CS1_B,SPORT6 Half SPORT 'B' Multichannel 32-63 Select Register" group.long 0x94++0x3 line.long 0x00 "SPORT6_CS2_B,SPORT6 Half SPORT 'B' Multichannel 64-95 Select Register" group.long 0x98++0x3 line.long 0x00 "SPORT6_CS3_B,SPORT6 Half SPORT 'B' Multichannel 96-127 Select Register" group.long 0xA0++0x3 line.long 0x00 "SPORT6_ERR_B,SPORT6 Half SPORT 'B' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0xA4++0x3 line.long 0x00 "SPORT6_MSTAT_B,SPORT6 Half SPORT 'B' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0xA8++0x3 line.long 0x00 "SPORT6_CTL2_B,SPORT6 Half SPORT 'B' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0xC0++0x3 line.long 0x00 "SPORT6_TXPRI_B,SPORT6 Half SPORT 'B' Tx Buffer (Primary) Register" group.long 0xC4++0x3 line.long 0x00 "SPORT6_RXPRI_B,SPORT6 Half SPORT 'B' Rx Buffer (Primary) Register" group.long 0xC8++0x3 line.long 0x00 "SPORT6_TXSEC_B,SPORT6 Half SPORT 'B' Tx Buffer (Secondary) Register" group.long 0xCC++0x3 line.long 0x00 "SPORT6_RXSEC_B,SPORT6 Half SPORT 'B' Rx Buffer (Secondary) Register" tree.end tree "SPORT7" base ad:0x31002700 width 16. group.long 0x0++0x3 line.long 0x00 "SPORT7_CTL_A,SPORT7 Half SPORT 'A' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x4++0x3 line.long 0x00 "SPORT7_DIV_A,SPORT7 Half SPORT 'A' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x8++0x3 line.long 0x00 "SPORT7_MCTL_A,SPORT7 Half SPORT 'A' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel enable" "0,1" group.long 0xC++0x3 line.long 0x00 "SPORT7_CS0_A,SPORT7 Half SPORT 'A' Multichannel 0-31 Select Register" group.long 0x10++0x3 line.long 0x00 "SPORT7_CS1_A,SPORT7 Half SPORT 'A' Multichannel 32-63 Select Register" group.long 0x14++0x3 line.long 0x00 "SPORT7_CS2_A,SPORT7 Half SPORT 'A' Multichannel 64-95 Select Register" group.long 0x18++0x3 line.long 0x00 "SPORT7_CS3_A,SPORT7 Half SPORT 'A' Multichannel 96-127 Select Register" group.long 0x20++0x3 line.long 0x00 "SPORT7_ERR_A,SPORT7 Half SPORT 'A' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "SPORT7_MSTAT_A,SPORT7 Half SPORT 'A' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0x28++0x3 line.long 0x00 "SPORT7_CTL2_A,SPORT7 Half SPORT 'A' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0x40++0x3 line.long 0x00 "SPORT7_TXPRI_A,SPORT7 Half SPORT 'A' Tx Buffer (Primary) Register" group.long 0x44++0x3 line.long 0x00 "SPORT7_RXPRI_A,SPORT7 Half SPORT 'A' Rx Buffer (Primary) Register" group.long 0x48++0x3 line.long 0x00 "SPORT7_TXSEC_A,SPORT7 Half SPORT 'A' Tx Buffer (Secondary) Register" group.long 0x4C++0x3 line.long 0x00 "SPORT7_RXSEC_A,SPORT7 Half SPORT 'A' Rx Buffer (Secondary) Register" group.long 0x80++0x3 line.long 0x00 "SPORT7_CTL_B,SPORT7 Half SPORT 'B' Control Register" bitfld.long 0x00 30.--31. " DXSPRI ,Data Transfer Buffer Status (Primary)" "0,1,2,3" bitfld.long 0x00 29. " DERRPRI ,Data Error Status (Primary)" "0,1" bitfld.long 0x00 27.--28. " DXSSEC ,Data Transfer Buffer Status (Secondary)" "0,1,2,3" newline bitfld.long 0x00 26. " DERRSEC ,Data Error Status (Secondary)" "0,1" bitfld.long 0x00 25. " SPTRAN ,Serial Port Transfer Direction" "0,1" bitfld.long 0x00 24. " SPENSEC ,Serial Port Enable (Secondary)" "0,1" newline bitfld.long 0x00 21. " GCLKEN ,Gated Clock Enable" "0,1" bitfld.long 0x00 20. " TFIEN ,Transmit Finish Interrupt Enable" "0,1" bitfld.long 0x00 19. " FSED ,Frame Sync Edge Detect" "0,1" newline bitfld.long 0x00 18. " RJUST ,Right-Justified Operation Mode" "0,1" bitfld.long 0x00 17. " LAFS ,Late Frame Sync / OPMODE2" "0,1" bitfld.long 0x00 16. " LFS ,Active-Low Frame Sync / L_FIRST / PLFS" "0,1" newline bitfld.long 0x00 15. " DIFS ,Data-Independent Frame Sync" "0,1" bitfld.long 0x00 14. " IFS ,Internal Frame Sync" "0,1" bitfld.long 0x00 13. " FSR ,Frame Sync Required" "0,1" newline bitfld.long 0x00 12. " CKRE ,Clock Rising Edge" "0,1" bitfld.long 0x00 11. " OPMODE ,Operation Mode" "0,1" bitfld.long 0x00 10. " ICLK ,Internal Clock" "0,1" newline bitfld.long 0x00 9. " PACK ,Packing Enable" "0,1" bitfld.long 0x00 4.--8. " SLEN ,Serial Word Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 3. " LSBF ,Least-Significant Bit First" "0,1" newline bitfld.long 0x00 1.--2. " DTYPE ,Data Type" "0,1,2,3" bitfld.long 0x00 0. " SPENPRI ,Serial Port Enable (Primary)" "0,1" group.long 0x84++0x3 line.long 0x00 "SPORT7_DIV_B,SPORT7 Half SPORT 'B' Divisor Register" hexmask.long.word 0x00 16.--31. 1. " FSDIV ,Frame Sync Divisor" hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divisor" group.long 0x88++0x3 line.long 0x00 "SPORT7_MCTL_B,SPORT7 Half SPORT 'B' Multichannel Control Register" hexmask.long.word 0x00 16.--25. 1. " WOFFSET ,Window Offset" hexmask.long.byte 0x00 8.--14. 1. " WSIZE ,Window Size" bitfld.long 0x00 4.--7. " MFD ,Multichannel Frame Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 2. " MCPDE ,Multichannel Packing DMA Enable" "0,1" bitfld.long 0x00 0. " MCE ,Multichannel Enable" "0,1" group.long 0x8C++0x3 line.long 0x00 "SPORT7_CS0_B,SPORT7 Half SPORT 'B' Multichannel 0-31 Select Register" group.long 0x90++0x3 line.long 0x00 "SPORT7_CS1_B,SPORT7 Half SPORT 'B' Multichannel 32-63 Select Register" group.long 0x94++0x3 line.long 0x00 "SPORT7_CS2_B,SPORT7 Half SPORT 'B' Multichannel 64-95 Select Register" group.long 0x98++0x3 line.long 0x00 "SPORT7_CS3_B,SPORT7 Half SPORT 'B' Multichannel 96-127 Select Register" group.long 0xA0++0x3 line.long 0x00 "SPORT7_ERR_B,SPORT7 Half SPORT 'B' Error Register" bitfld.long 0x00 6. " FSERRSTAT ,Frame Sync Error Status" "0,1" bitfld.long 0x00 5. " DERRSSTAT ,Data Error Secondary Status" "0,1" bitfld.long 0x00 4. " DERRPSTAT ,Data Error Primary Status" "0,1" newline bitfld.long 0x00 2. " FSERRMSK ,Frame Sync Error (Interrupt) Mask" "0,1" bitfld.long 0x00 1. " DERRSMSK ,Data Error Secondary (Interrupt) Mask" "0,1" bitfld.long 0x00 0. " DERRPMSK ,Data Error Primary (Interrupt) Mask" "0,1" group.long 0xA4++0x3 line.long 0x00 "SPORT7_MSTAT_B,SPORT7 Half SPORT 'B' Multichannel Status Register" hexmask.long.word 0x00 0.--9. 1. " CURCHAN ,Current Channel" group.long 0xA8++0x3 line.long 0x00 "SPORT7_CTL2_B,SPORT7 Half SPORT 'B' Control 2 Register" bitfld.long 0x00 1. " CKMUXSEL ,Clock Multiplexer Select" "0,1" bitfld.long 0x00 0. " FSMUXSEL ,Frame Sync Multiplexer Select" "0,1" group.long 0xC0++0x3 line.long 0x00 "SPORT7_TXPRI_B,SPORT7 Half SPORT 'B' Tx Buffer (Primary) Register" group.long 0xC4++0x3 line.long 0x00 "SPORT7_RXPRI_B,SPORT7 Half SPORT 'B' Rx Buffer (Primary) Register" group.long 0xC8++0x3 line.long 0x00 "SPORT7_TXSEC_B,SPORT7 Half SPORT 'B' Tx Buffer (Secondary) Register" group.long 0xCC++0x3 line.long 0x00 "SPORT7_RXSEC_B,SPORT7 Half SPORT 'B' Rx Buffer (Secondary) Register" tree.end tree.end tree "SPU (System Protection Unit)" base ad:0x3108B000 width 17. group.long 0x0++0x3 line.long 0x00 "SPU0_CTL,SPU0 Control Register" bitfld.long 0x00 16. " WPLCK ,Write Protect Register Lock" "0,1" bitfld.long 0x00 14. " PINTEN ,Protection Violation Interrupt Enable" "0,1" hexmask.long.byte 0x00 0.--7. 1. " GLCK ,Global Lock" group.long 0x4++0x3 line.long 0x00 "SPU0_STAT,SPU0 Status Register" bitfld.long 0x00 31. " LWERR ,Lock Write Error" "0,1" bitfld.long 0x00 30. " ADDRERR ,Address Error" "0,1" bitfld.long 0x00 12. " VIRQ ,Violation Interrupt Request" "0,1" newline bitfld.long 0x00 0. " GLCK ,Global Lock Status" "0,1" group.long 0x400++0x3 line.long 0x00 "SPU0_WP0,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x404++0x3 line.long 0x00 "SPU0_WP1,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x408++0x3 line.long 0x00 "SPU0_WP2,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x40C++0x3 line.long 0x00 "SPU0_WP3,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x410++0x3 line.long 0x00 "SPU0_WP4,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x414++0x3 line.long 0x00 "SPU0_WP5,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x418++0x3 line.long 0x00 "SPU0_WP6,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x41C++0x3 line.long 0x00 "SPU0_WP7,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x420++0x3 line.long 0x00 "SPU0_WP8,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x424++0x3 line.long 0x00 "SPU0_WP9,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x428++0x3 line.long 0x00 "SPU0_WP10,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x42C++0x3 line.long 0x00 "SPU0_WP11,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x430++0x3 line.long 0x00 "SPU0_WP12,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x434++0x3 line.long 0x00 "SPU0_WP13,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x438++0x3 line.long 0x00 "SPU0_WP14,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x43C++0x3 line.long 0x00 "SPU0_WP15,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x440++0x3 line.long 0x00 "SPU0_WP16,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x444++0x3 line.long 0x00 "SPU0_WP17,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x448++0x3 line.long 0x00 "SPU0_WP18,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x44C++0x3 line.long 0x00 "SPU0_WP19,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x450++0x3 line.long 0x00 "SPU0_WP20,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x454++0x3 line.long 0x00 "SPU0_WP21,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x458++0x3 line.long 0x00 "SPU0_WP22,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x45C++0x3 line.long 0x00 "SPU0_WP23,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x460++0x3 line.long 0x00 "SPU0_WP24,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x464++0x3 line.long 0x00 "SPU0_WP25,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x468++0x3 line.long 0x00 "SPU0_WP26,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x46C++0x3 line.long 0x00 "SPU0_WP27,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x470++0x3 line.long 0x00 "SPU0_WP28,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x474++0x3 line.long 0x00 "SPU0_WP29,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x478++0x3 line.long 0x00 "SPU0_WP30,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x47C++0x3 line.long 0x00 "SPU0_WP31,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x480++0x3 line.long 0x00 "SPU0_WP32,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x484++0x3 line.long 0x00 "SPU0_WP33,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x488++0x3 line.long 0x00 "SPU0_WP34,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x48C++0x3 line.long 0x00 "SPU0_WP35,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x490++0x3 line.long 0x00 "SPU0_WP36,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x494++0x3 line.long 0x00 "SPU0_WP37,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x498++0x3 line.long 0x00 "SPU0_WP38,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x49C++0x3 line.long 0x00 "SPU0_WP39,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4A0++0x3 line.long 0x00 "SPU0_WP40,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4A4++0x3 line.long 0x00 "SPU0_WP41,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4A8++0x3 line.long 0x00 "SPU0_WP42,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4AC++0x3 line.long 0x00 "SPU0_WP43,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4B0++0x3 line.long 0x00 "SPU0_WP44,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4B4++0x3 line.long 0x00 "SPU0_WP45,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4B8++0x3 line.long 0x00 "SPU0_WP46,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4BC++0x3 line.long 0x00 "SPU0_WP47,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4C0++0x3 line.long 0x00 "SPU0_WP48,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4C4++0x3 line.long 0x00 "SPU0_WP49,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4C8++0x3 line.long 0x00 "SPU0_WP50,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4CC++0x3 line.long 0x00 "SPU0_WP51,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4D0++0x3 line.long 0x00 "SPU0_WP52,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4D4++0x3 line.long 0x00 "SPU0_WP53,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4D8++0x3 line.long 0x00 "SPU0_WP54,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4DC++0x3 line.long 0x00 "SPU0_WP55,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4E0++0x3 line.long 0x00 "SPU0_WP56,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4E4++0x3 line.long 0x00 "SPU0_WP57,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4E8++0x3 line.long 0x00 "SPU0_WP58,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4EC++0x3 line.long 0x00 "SPU0_WP59,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4F0++0x3 line.long 0x00 "SPU0_WP60,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4F4++0x3 line.long 0x00 "SPU0_WP61,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4F8++0x3 line.long 0x00 "SPU0_WP62,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x4FC++0x3 line.long 0x00 "SPU0_WP63,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x500++0x3 line.long 0x00 "SPU0_WP64,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x504++0x3 line.long 0x00 "SPU0_WP65,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x508++0x3 line.long 0x00 "SPU0_WP66,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x50C++0x3 line.long 0x00 "SPU0_WP67,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x510++0x3 line.long 0x00 "SPU0_WP68,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x514++0x3 line.long 0x00 "SPU0_WP69,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x518++0x3 line.long 0x00 "SPU0_WP70,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x51C++0x3 line.long 0x00 "SPU0_WP71,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x520++0x3 line.long 0x00 "SPU0_WP72,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x524++0x3 line.long 0x00 "SPU0_WP73,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x528++0x3 line.long 0x00 "SPU0_WP74,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x52C++0x3 line.long 0x00 "SPU0_WP75,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x530++0x3 line.long 0x00 "SPU0_WP76,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x534++0x3 line.long 0x00 "SPU0_WP77,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x538++0x3 line.long 0x00 "SPU0_WP78,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x53C++0x3 line.long 0x00 "SPU0_WP79,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x540++0x3 line.long 0x00 "SPU0_WP80,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x544++0x3 line.long 0x00 "SPU0_WP81,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x548++0x3 line.long 0x00 "SPU0_WP82,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x54C++0x3 line.long 0x00 "SPU0_WP83,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x550++0x3 line.long 0x00 "SPU0_WP84,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x554++0x3 line.long 0x00 "SPU0_WP85,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x558++0x3 line.long 0x00 "SPU0_WP86,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x55C++0x3 line.long 0x00 "SPU0_WP87,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x560++0x3 line.long 0x00 "SPU0_WP88,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x564++0x3 line.long 0x00 "SPU0_WP89,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x568++0x3 line.long 0x00 "SPU0_WP90,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x56C++0x3 line.long 0x00 "SPU0_WP91,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x570++0x3 line.long 0x00 "SPU0_WP92,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x574++0x3 line.long 0x00 "SPU0_WP93,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x578++0x3 line.long 0x00 "SPU0_WP94,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x57C++0x3 line.long 0x00 "SPU0_WP95,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x580++0x3 line.long 0x00 "SPU0_WP96,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x584++0x3 line.long 0x00 "SPU0_WP97,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x588++0x3 line.long 0x00 "SPU0_WP98,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x58C++0x3 line.long 0x00 "SPU0_WP99,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x590++0x3 line.long 0x00 "SPU0_WP100,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x594++0x3 line.long 0x00 "SPU0_WP101,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x598++0x3 line.long 0x00 "SPU0_WP102,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x59C++0x3 line.long 0x00 "SPU0_WP103,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5A0++0x3 line.long 0x00 "SPU0_WP104,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5A4++0x3 line.long 0x00 "SPU0_WP105,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5A8++0x3 line.long 0x00 "SPU0_WP106,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5AC++0x3 line.long 0x00 "SPU0_WP107,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5B0++0x3 line.long 0x00 "SPU0_WP108,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5B4++0x3 line.long 0x00 "SPU0_WP109,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5B8++0x3 line.long 0x00 "SPU0_WP110,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5BC++0x3 line.long 0x00 "SPU0_WP111,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5C0++0x3 line.long 0x00 "SPU0_WP112,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5C4++0x3 line.long 0x00 "SPU0_WP113,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5C8++0x3 line.long 0x00 "SPU0_WP114,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5CC++0x3 line.long 0x00 "SPU0_WP115,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5D0++0x3 line.long 0x00 "SPU0_WP116,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5D4++0x3 line.long 0x00 "SPU0_WP117,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5D8++0x3 line.long 0x00 "SPU0_WP118,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5DC++0x3 line.long 0x00 "SPU0_WP119,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5E0++0x3 line.long 0x00 "SPU0_WP120,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5E4++0x3 line.long 0x00 "SPU0_WP121,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5E8++0x3 line.long 0x00 "SPU0_WP122,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5EC++0x3 line.long 0x00 "SPU0_WP123,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5F0++0x3 line.long 0x00 "SPU0_WP124,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5F4++0x3 line.long 0x00 "SPU0_WP125,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5F8++0x3 line.long 0x00 "SPU0_WP126,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x5FC++0x3 line.long 0x00 "SPU0_WP127,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x600++0x3 line.long 0x00 "SPU0_WP128,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x604++0x3 line.long 0x00 "SPU0_WP129,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x608++0x3 line.long 0x00 "SPU0_WP130,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x60C++0x3 line.long 0x00 "SPU0_WP131,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x610++0x3 line.long 0x00 "SPU0_WP132,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x614++0x3 line.long 0x00 "SPU0_WP133,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x618++0x3 line.long 0x00 "SPU0_WP134,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x61C++0x3 line.long 0x00 "SPU0_WP135,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x620++0x3 line.long 0x00 "SPU0_WP136,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x624++0x3 line.long 0x00 "SPU0_WP137,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x628++0x3 line.long 0x00 "SPU0_WP138,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x62C++0x3 line.long 0x00 "SPU0_WP139,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x630++0x3 line.long 0x00 "SPU0_WP140,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x634++0x3 line.long 0x00 "SPU0_WP141,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x638++0x3 line.long 0x00 "SPU0_WP142,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x63C++0x3 line.long 0x00 "SPU0_WP143,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x640++0x3 line.long 0x00 "SPU0_WP144,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x644++0x3 line.long 0x00 "SPU0_WP145,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x648++0x3 line.long 0x00 "SPU0_WP146,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x64C++0x3 line.long 0x00 "SPU0_WP147,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x650++0x3 line.long 0x00 "SPU0_WP148,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x654++0x3 line.long 0x00 "SPU0_WP149,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x658++0x3 line.long 0x00 "SPU0_WP150,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x65C++0x3 line.long 0x00 "SPU0_WP151,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x660++0x3 line.long 0x00 "SPU0_WP152,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x664++0x3 line.long 0x00 "SPU0_WP153,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x668++0x3 line.long 0x00 "SPU0_WP154,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x66C++0x3 line.long 0x00 "SPU0_WP155,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x670++0x3 line.long 0x00 "SPU0_WP156,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x674++0x3 line.long 0x00 "SPU0_WP157,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x678++0x3 line.long 0x00 "SPU0_WP158,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x67C++0x3 line.long 0x00 "SPU0_WP159,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x680++0x3 line.long 0x00 "SPU0_WP160,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x684++0x3 line.long 0x00 "SPU0_WP161,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x688++0x3 line.long 0x00 "SPU0_WP162,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x68C++0x3 line.long 0x00 "SPU0_WP163,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x690++0x3 line.long 0x00 "SPU0_WP164,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x694++0x3 line.long 0x00 "SPU0_WP165,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x698++0x3 line.long 0x00 "SPU0_WP166,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x69C++0x3 line.long 0x00 "SPU0_WP167,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6A0++0x3 line.long 0x00 "SPU0_WP168,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6A4++0x3 line.long 0x00 "SPU0_WP169,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6A8++0x3 line.long 0x00 "SPU0_WP170,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6AC++0x3 line.long 0x00 "SPU0_WP171,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6B0++0x3 line.long 0x00 "SPU0_WP172,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6B4++0x3 line.long 0x00 "SPU0_WP173,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6B8++0x3 line.long 0x00 "SPU0_WP174,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6BC++0x3 line.long 0x00 "SPU0_WP175,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6C0++0x3 line.long 0x00 "SPU0_WP176,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6C4++0x3 line.long 0x00 "SPU0_WP177,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6C8++0x3 line.long 0x00 "SPU0_WP178,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6CC++0x3 line.long 0x00 "SPU0_WP179,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6D0++0x3 line.long 0x00 "SPU0_WP180,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6D4++0x3 line.long 0x00 "SPU0_WP181,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6D8++0x3 line.long 0x00 "SPU0_WP182,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6DC++0x3 line.long 0x00 "SPU0_WP183,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6E0++0x3 line.long 0x00 "SPU0_WP184,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6E4++0x3 line.long 0x00 "SPU0_WP185,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6E8++0x3 line.long 0x00 "SPU0_WP186,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6EC++0x3 line.long 0x00 "SPU0_WP187,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6F0++0x3 line.long 0x00 "SPU0_WP188,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6F4++0x3 line.long 0x00 "SPU0_WP189,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6F8++0x3 line.long 0x00 "SPU0_WP190,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x6FC++0x3 line.long 0x00 "SPU0_WP191,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x700++0x3 line.long 0x00 "SPU0_WP192,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x704++0x3 line.long 0x00 "SPU0_WP193,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x708++0x3 line.long 0x00 "SPU0_WP194,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x70C++0x3 line.long 0x00 "SPU0_WP195,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x710++0x3 line.long 0x00 "SPU0_WP196,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x714++0x3 line.long 0x00 "SPU0_WP197,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x718++0x3 line.long 0x00 "SPU0_WP198,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x71C++0x3 line.long 0x00 "SPU0_WP199,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x720++0x3 line.long 0x00 "SPU0_WP200,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x724++0x3 line.long 0x00 "SPU0_WP201,SPU0 Write Protect Register n" bitfld.long 0x00 18. " SM2 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 17. " SM1 ,System Master x Write Protect Enable" "0,1" bitfld.long 0x00 16. " SM0 ,System Master x Write Protect Enable" "0,1" newline bitfld.long 0x00 2. " CM2 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 1. " CM1 ,Core Master x Write Protect Enable" "0,1" bitfld.long 0x00 0. " CM0 ,Core Master x Write Protect Enable" "0,1" group.long 0x840++0x3 line.long 0x00 "SPU0_SECURECTL,SPU0 Secure Control Register" bitfld.long 0x00 16. " SCRLCK ,Secure Register Lock" "0,1" bitfld.long 0x00 14. " SINTEN ,Secure Violation Interrupt Enable" "0,1" bitfld.long 0x00 5. " MSECCLR ,Master Secure Clear" "0,1" newline bitfld.long 0x00 4. " SSECCLR ,Slave Secure Clear" "0,1" group.long 0x84C++0x3 line.long 0x00 "SPU0_SECURECHK,SPU0 Secure Check Register" group.long 0x980++0x3 line.long 0x00 "SPU0_SECUREC0,SPU0 Secure Core Registers" bitfld.long 0x00 0. " CSEC0 ,Core Secure" "0,1" group.long 0x984++0x3 line.long 0x00 "SPU0_SECUREC1,SPU0 Secure Core Registers" bitfld.long 0x00 0. " CSEC0 ,Core Secure" "0,1" group.long 0x988++0x3 line.long 0x00 "SPU0_SECUREC2,SPU0 Secure Core Registers" bitfld.long 0x00 0. " CSEC0 ,Core Secure" "0,1" group.long 0xA00++0x3 line.long 0x00 "SPU0_SECUREP0,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA04++0x3 line.long 0x00 "SPU0_SECUREP1,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA08++0x3 line.long 0x00 "SPU0_SECUREP2,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA0C++0x3 line.long 0x00 "SPU0_SECUREP3,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA10++0x3 line.long 0x00 "SPU0_SECUREP4,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA14++0x3 line.long 0x00 "SPU0_SECUREP5,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA18++0x3 line.long 0x00 "SPU0_SECUREP6,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA1C++0x3 line.long 0x00 "SPU0_SECUREP7,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA20++0x3 line.long 0x00 "SPU0_SECUREP8,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA24++0x3 line.long 0x00 "SPU0_SECUREP9,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA28++0x3 line.long 0x00 "SPU0_SECUREP10,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA2C++0x3 line.long 0x00 "SPU0_SECUREP11,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA30++0x3 line.long 0x00 "SPU0_SECUREP12,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA34++0x3 line.long 0x00 "SPU0_SECUREP13,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA38++0x3 line.long 0x00 "SPU0_SECUREP14,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA3C++0x3 line.long 0x00 "SPU0_SECUREP15,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA40++0x3 line.long 0x00 "SPU0_SECUREP16,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA44++0x3 line.long 0x00 "SPU0_SECUREP17,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA48++0x3 line.long 0x00 "SPU0_SECUREP18,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA4C++0x3 line.long 0x00 "SPU0_SECUREP19,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA50++0x3 line.long 0x00 "SPU0_SECUREP20,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA54++0x3 line.long 0x00 "SPU0_SECUREP21,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA58++0x3 line.long 0x00 "SPU0_SECUREP22,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA5C++0x3 line.long 0x00 "SPU0_SECUREP23,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA60++0x3 line.long 0x00 "SPU0_SECUREP24,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA64++0x3 line.long 0x00 "SPU0_SECUREP25,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA68++0x3 line.long 0x00 "SPU0_SECUREP26,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA6C++0x3 line.long 0x00 "SPU0_SECUREP27,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA70++0x3 line.long 0x00 "SPU0_SECUREP28,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA74++0x3 line.long 0x00 "SPU0_SECUREP29,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA78++0x3 line.long 0x00 "SPU0_SECUREP30,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA7C++0x3 line.long 0x00 "SPU0_SECUREP31,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA80++0x3 line.long 0x00 "SPU0_SECUREP32,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA84++0x3 line.long 0x00 "SPU0_SECUREP33,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA88++0x3 line.long 0x00 "SPU0_SECUREP34,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA8C++0x3 line.long 0x00 "SPU0_SECUREP35,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA90++0x3 line.long 0x00 "SPU0_SECUREP36,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA94++0x3 line.long 0x00 "SPU0_SECUREP37,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA98++0x3 line.long 0x00 "SPU0_SECUREP38,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xA9C++0x3 line.long 0x00 "SPU0_SECUREP39,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAA0++0x3 line.long 0x00 "SPU0_SECUREP40,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAA4++0x3 line.long 0x00 "SPU0_SECUREP41,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAA8++0x3 line.long 0x00 "SPU0_SECUREP42,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAAC++0x3 line.long 0x00 "SPU0_SECUREP43,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAB0++0x3 line.long 0x00 "SPU0_SECUREP44,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAB4++0x3 line.long 0x00 "SPU0_SECUREP45,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAB8++0x3 line.long 0x00 "SPU0_SECUREP46,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xABC++0x3 line.long 0x00 "SPU0_SECUREP47,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAC0++0x3 line.long 0x00 "SPU0_SECUREP48,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAC4++0x3 line.long 0x00 "SPU0_SECUREP49,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAC8++0x3 line.long 0x00 "SPU0_SECUREP50,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xACC++0x3 line.long 0x00 "SPU0_SECUREP51,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAD0++0x3 line.long 0x00 "SPU0_SECUREP52,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAD4++0x3 line.long 0x00 "SPU0_SECUREP53,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAD8++0x3 line.long 0x00 "SPU0_SECUREP54,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xADC++0x3 line.long 0x00 "SPU0_SECUREP55,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAE0++0x3 line.long 0x00 "SPU0_SECUREP56,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAE4++0x3 line.long 0x00 "SPU0_SECUREP57,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAE8++0x3 line.long 0x00 "SPU0_SECUREP58,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAEC++0x3 line.long 0x00 "SPU0_SECUREP59,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAF0++0x3 line.long 0x00 "SPU0_SECUREP60,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAF4++0x3 line.long 0x00 "SPU0_SECUREP61,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAF8++0x3 line.long 0x00 "SPU0_SECUREP62,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xAFC++0x3 line.long 0x00 "SPU0_SECUREP63,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB00++0x3 line.long 0x00 "SPU0_SECUREP64,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB04++0x3 line.long 0x00 "SPU0_SECUREP65,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB08++0x3 line.long 0x00 "SPU0_SECUREP66,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB0C++0x3 line.long 0x00 "SPU0_SECUREP67,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB10++0x3 line.long 0x00 "SPU0_SECUREP68,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB14++0x3 line.long 0x00 "SPU0_SECUREP69,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB18++0x3 line.long 0x00 "SPU0_SECUREP70,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB1C++0x3 line.long 0x00 "SPU0_SECUREP71,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB20++0x3 line.long 0x00 "SPU0_SECUREP72,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB24++0x3 line.long 0x00 "SPU0_SECUREP73,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB28++0x3 line.long 0x00 "SPU0_SECUREP74,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB2C++0x3 line.long 0x00 "SPU0_SECUREP75,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB30++0x3 line.long 0x00 "SPU0_SECUREP76,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB34++0x3 line.long 0x00 "SPU0_SECUREP77,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB38++0x3 line.long 0x00 "SPU0_SECUREP78,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB3C++0x3 line.long 0x00 "SPU0_SECUREP79,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB40++0x3 line.long 0x00 "SPU0_SECUREP80,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB44++0x3 line.long 0x00 "SPU0_SECUREP81,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB48++0x3 line.long 0x00 "SPU0_SECUREP82,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB4C++0x3 line.long 0x00 "SPU0_SECUREP83,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB50++0x3 line.long 0x00 "SPU0_SECUREP84,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB54++0x3 line.long 0x00 "SPU0_SECUREP85,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB58++0x3 line.long 0x00 "SPU0_SECUREP86,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB5C++0x3 line.long 0x00 "SPU0_SECUREP87,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB60++0x3 line.long 0x00 "SPU0_SECUREP88,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB64++0x3 line.long 0x00 "SPU0_SECUREP89,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB68++0x3 line.long 0x00 "SPU0_SECUREP90,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB6C++0x3 line.long 0x00 "SPU0_SECUREP91,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB70++0x3 line.long 0x00 "SPU0_SECUREP92,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB74++0x3 line.long 0x00 "SPU0_SECUREP93,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB78++0x3 line.long 0x00 "SPU0_SECUREP94,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB7C++0x3 line.long 0x00 "SPU0_SECUREP95,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB80++0x3 line.long 0x00 "SPU0_SECUREP96,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB84++0x3 line.long 0x00 "SPU0_SECUREP97,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB88++0x3 line.long 0x00 "SPU0_SECUREP98,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB8C++0x3 line.long 0x00 "SPU0_SECUREP99,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB90++0x3 line.long 0x00 "SPU0_SECUREP100,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB94++0x3 line.long 0x00 "SPU0_SECUREP101,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB98++0x3 line.long 0x00 "SPU0_SECUREP102,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xB9C++0x3 line.long 0x00 "SPU0_SECUREP103,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBA0++0x3 line.long 0x00 "SPU0_SECUREP104,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBA4++0x3 line.long 0x00 "SPU0_SECUREP105,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBA8++0x3 line.long 0x00 "SPU0_SECUREP106,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBAC++0x3 line.long 0x00 "SPU0_SECUREP107,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBB0++0x3 line.long 0x00 "SPU0_SECUREP108,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBB4++0x3 line.long 0x00 "SPU0_SECUREP109,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBB8++0x3 line.long 0x00 "SPU0_SECUREP110,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBBC++0x3 line.long 0x00 "SPU0_SECUREP111,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBC0++0x3 line.long 0x00 "SPU0_SECUREP112,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBC4++0x3 line.long 0x00 "SPU0_SECUREP113,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBC8++0x3 line.long 0x00 "SPU0_SECUREP114,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBCC++0x3 line.long 0x00 "SPU0_SECUREP115,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBD0++0x3 line.long 0x00 "SPU0_SECUREP116,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBD4++0x3 line.long 0x00 "SPU0_SECUREP117,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBD8++0x3 line.long 0x00 "SPU0_SECUREP118,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBDC++0x3 line.long 0x00 "SPU0_SECUREP119,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBE0++0x3 line.long 0x00 "SPU0_SECUREP120,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBE4++0x3 line.long 0x00 "SPU0_SECUREP121,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBE8++0x3 line.long 0x00 "SPU0_SECUREP122,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBEC++0x3 line.long 0x00 "SPU0_SECUREP123,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBF0++0x3 line.long 0x00 "SPU0_SECUREP124,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBF4++0x3 line.long 0x00 "SPU0_SECUREP125,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBF8++0x3 line.long 0x00 "SPU0_SECUREP126,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xBFC++0x3 line.long 0x00 "SPU0_SECUREP127,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC00++0x3 line.long 0x00 "SPU0_SECUREP128,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC04++0x3 line.long 0x00 "SPU0_SECUREP129,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC08++0x3 line.long 0x00 "SPU0_SECUREP130,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC0C++0x3 line.long 0x00 "SPU0_SECUREP131,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC10++0x3 line.long 0x00 "SPU0_SECUREP132,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC14++0x3 line.long 0x00 "SPU0_SECUREP133,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC18++0x3 line.long 0x00 "SPU0_SECUREP134,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC1C++0x3 line.long 0x00 "SPU0_SECUREP135,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC20++0x3 line.long 0x00 "SPU0_SECUREP136,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC24++0x3 line.long 0x00 "SPU0_SECUREP137,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC28++0x3 line.long 0x00 "SPU0_SECUREP138,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC2C++0x3 line.long 0x00 "SPU0_SECUREP139,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC30++0x3 line.long 0x00 "SPU0_SECUREP140,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC34++0x3 line.long 0x00 "SPU0_SECUREP141,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC38++0x3 line.long 0x00 "SPU0_SECUREP142,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC3C++0x3 line.long 0x00 "SPU0_SECUREP143,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC40++0x3 line.long 0x00 "SPU0_SECUREP144,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC44++0x3 line.long 0x00 "SPU0_SECUREP145,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC48++0x3 line.long 0x00 "SPU0_SECUREP146,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC4C++0x3 line.long 0x00 "SPU0_SECUREP147,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC50++0x3 line.long 0x00 "SPU0_SECUREP148,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC54++0x3 line.long 0x00 "SPU0_SECUREP149,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC58++0x3 line.long 0x00 "SPU0_SECUREP150,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC5C++0x3 line.long 0x00 "SPU0_SECUREP151,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC60++0x3 line.long 0x00 "SPU0_SECUREP152,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC64++0x3 line.long 0x00 "SPU0_SECUREP153,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC68++0x3 line.long 0x00 "SPU0_SECUREP154,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC6C++0x3 line.long 0x00 "SPU0_SECUREP155,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC70++0x3 line.long 0x00 "SPU0_SECUREP156,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC74++0x3 line.long 0x00 "SPU0_SECUREP157,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC78++0x3 line.long 0x00 "SPU0_SECUREP158,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC7C++0x3 line.long 0x00 "SPU0_SECUREP159,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC80++0x3 line.long 0x00 "SPU0_SECUREP160,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC84++0x3 line.long 0x00 "SPU0_SECUREP161,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC88++0x3 line.long 0x00 "SPU0_SECUREP162,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC8C++0x3 line.long 0x00 "SPU0_SECUREP163,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC90++0x3 line.long 0x00 "SPU0_SECUREP164,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC94++0x3 line.long 0x00 "SPU0_SECUREP165,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC98++0x3 line.long 0x00 "SPU0_SECUREP166,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xC9C++0x3 line.long 0x00 "SPU0_SECUREP167,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCA0++0x3 line.long 0x00 "SPU0_SECUREP168,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCA4++0x3 line.long 0x00 "SPU0_SECUREP169,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCA8++0x3 line.long 0x00 "SPU0_SECUREP170,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCAC++0x3 line.long 0x00 "SPU0_SECUREP171,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCB0++0x3 line.long 0x00 "SPU0_SECUREP172,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCB4++0x3 line.long 0x00 "SPU0_SECUREP173,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCB8++0x3 line.long 0x00 "SPU0_SECUREP174,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCBC++0x3 line.long 0x00 "SPU0_SECUREP175,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCC0++0x3 line.long 0x00 "SPU0_SECUREP176,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCC4++0x3 line.long 0x00 "SPU0_SECUREP177,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCC8++0x3 line.long 0x00 "SPU0_SECUREP178,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCCC++0x3 line.long 0x00 "SPU0_SECUREP179,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCD0++0x3 line.long 0x00 "SPU0_SECUREP180,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCD4++0x3 line.long 0x00 "SPU0_SECUREP181,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCD8++0x3 line.long 0x00 "SPU0_SECUREP182,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCDC++0x3 line.long 0x00 "SPU0_SECUREP183,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCE0++0x3 line.long 0x00 "SPU0_SECUREP184,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCE4++0x3 line.long 0x00 "SPU0_SECUREP185,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCE8++0x3 line.long 0x00 "SPU0_SECUREP186,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCEC++0x3 line.long 0x00 "SPU0_SECUREP187,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCF0++0x3 line.long 0x00 "SPU0_SECUREP188,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCF4++0x3 line.long 0x00 "SPU0_SECUREP189,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCF8++0x3 line.long 0x00 "SPU0_SECUREP190,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xCFC++0x3 line.long 0x00 "SPU0_SECUREP191,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD00++0x3 line.long 0x00 "SPU0_SECUREP192,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD04++0x3 line.long 0x00 "SPU0_SECUREP193,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD08++0x3 line.long 0x00 "SPU0_SECUREP194,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD0C++0x3 line.long 0x00 "SPU0_SECUREP195,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD10++0x3 line.long 0x00 "SPU0_SECUREP196,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD14++0x3 line.long 0x00 "SPU0_SECUREP197,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD18++0x3 line.long 0x00 "SPU0_SECUREP198,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD1C++0x3 line.long 0x00 "SPU0_SECUREP199,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD20++0x3 line.long 0x00 "SPU0_SECUREP200,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" group.long 0xD24++0x3 line.long 0x00 "SPU0_SECUREP201,SPU0 Secure Peripheral Register" bitfld.long 0x00 1. " MSEC ,Master Secure Enable" "0,1" bitfld.long 0x00 0. " SSEC ,Slave Secure Enable" "0,1" tree.end tree "SWU (System Watchpoint Unit)" tree "SWU1" base ad:0x31093000 width 12. group.long 0x0++0x3 line.long 0x00 "SWU1_GCTL,SWU1 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU1_GSTAT,SWU1 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU1_CTL0,SWU1 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU1_LA0,SWU1 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU1_UA0,SWU1 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU1_ID0,SWU1 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU1_CNT0,SWU1 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU1_TARG0,SWU1 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU1_HIST0,SWU1 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU1_CUR0,SWU1 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU1_CTL1,SWU1 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU1_LA1,SWU1 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU1_UA1,SWU1 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU1_ID1,SWU1 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU1_CNT1,SWU1 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU1_TARG1,SWU1 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU1_HIST1,SWU1 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU1_CUR1,SWU1 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU1_CTL2,SWU1 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU1_LA2,SWU1 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU1_UA2,SWU1 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU1_ID2,SWU1 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU1_CNT2,SWU1 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU1_TARG2,SWU1 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU1_HIST2,SWU1 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU1_CUR2,SWU1 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU1_CTL3,SWU1 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU1_LA3,SWU1 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU1_UA3,SWU1 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU1_ID3,SWU1 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU1_CNT3,SWU1 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU1_TARG3,SWU1 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU1_HIST3,SWU1 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU1_CUR3,SWU1 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU2" base ad:0x31094000 width 12. group.long 0x0++0x3 line.long 0x00 "SWU2_GCTL,SWU2 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU2_GSTAT,SWU2 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU2_CTL0,SWU2 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU2_LA0,SWU2 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU2_UA0,SWU2 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU2_ID0,SWU2 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU2_CNT0,SWU2 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU2_TARG0,SWU2 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU2_HIST0,SWU2 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU2_CUR0,SWU2 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU2_CTL1,SWU2 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU2_LA1,SWU2 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU2_UA1,SWU2 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU2_ID1,SWU2 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU2_CNT1,SWU2 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU2_TARG1,SWU2 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU2_HIST1,SWU2 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU2_CUR1,SWU2 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU2_CTL2,SWU2 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU2_LA2,SWU2 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU2_UA2,SWU2 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU2_ID2,SWU2 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU2_CNT2,SWU2 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU2_TARG2,SWU2 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU2_HIST2,SWU2 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU2_CUR2,SWU2 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU2_CTL3,SWU2 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU2_LA3,SWU2 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU2_UA3,SWU2 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU2_ID3,SWU2 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU2_CNT3,SWU2 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU2_TARG3,SWU2 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU2_HIST3,SWU2 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU2_CUR3,SWU2 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU3" base ad:0x31095000 width 12. group.long 0x0++0x3 line.long 0x00 "SWU3_GCTL,SWU3 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU3_GSTAT,SWU3 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU3_CTL0,SWU3 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU3_LA0,SWU3 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU3_UA0,SWU3 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU3_ID0,SWU3 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU3_CNT0,SWU3 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU3_TARG0,SWU3 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU3_HIST0,SWU3 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU3_CUR0,SWU3 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU3_CTL1,SWU3 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU3_LA1,SWU3 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU3_UA1,SWU3 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU3_ID1,SWU3 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU3_CNT1,SWU3 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU3_TARG1,SWU3 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU3_HIST1,SWU3 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU3_CUR1,SWU3 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU3_CTL2,SWU3 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU3_LA2,SWU3 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU3_UA2,SWU3 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU3_ID2,SWU3 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU3_CNT2,SWU3 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU3_TARG2,SWU3 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU3_HIST2,SWU3 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU3_CUR2,SWU3 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU3_CTL3,SWU3 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU3_LA3,SWU3 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU3_UA3,SWU3 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU3_ID3,SWU3 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU3_CNT3,SWU3 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU3_TARG3,SWU3 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU3_HIST3,SWU3 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU3_CUR3,SWU3 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU4" base ad:0x31096000 width 12. group.long 0x0++0x3 line.long 0x00 "SWU4_GCTL,SWU4 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU4_GSTAT,SWU4 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU4_CTL0,SWU4 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU4_LA0,SWU4 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU4_UA0,SWU4 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU4_ID0,SWU4 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU4_CNT0,SWU4 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU4_TARG0,SWU4 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU4_HIST0,SWU4 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU4_CUR0,SWU4 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU4_CTL1,SWU4 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU4_LA1,SWU4 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU4_UA1,SWU4 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU4_ID1,SWU4 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU4_CNT1,SWU4 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU4_TARG1,SWU4 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU4_HIST1,SWU4 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU4_CUR1,SWU4 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU4_CTL2,SWU4 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU4_LA2,SWU4 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU4_UA2,SWU4 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU4_ID2,SWU4 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU4_CNT2,SWU4 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU4_TARG2,SWU4 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU4_HIST2,SWU4 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU4_CUR2,SWU4 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU4_CTL3,SWU4 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU4_LA3,SWU4 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU4_UA3,SWU4 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU4_ID3,SWU4 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU4_CNT3,SWU4 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU4_TARG3,SWU4 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU4_HIST3,SWU4 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU4_CUR3,SWU4 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU5" base ad:0x31098000 width 12. group.long 0x0++0x3 line.long 0x00 "SWU5_GCTL,SWU5 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU5_GSTAT,SWU5 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU5_CTL0,SWU5 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU5_LA0,SWU5 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU5_UA0,SWU5 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU5_ID0,SWU5 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU5_CNT0,SWU5 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU5_TARG0,SWU5 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU5_HIST0,SWU5 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU5_CUR0,SWU5 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU5_CTL1,SWU5 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU5_LA1,SWU5 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU5_UA1,SWU5 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU5_ID1,SWU5 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU5_CNT1,SWU5 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU5_TARG1,SWU5 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU5_HIST1,SWU5 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU5_CUR1,SWU5 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU5_CTL2,SWU5 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU5_LA2,SWU5 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU5_UA2,SWU5 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU5_ID2,SWU5 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU5_CNT2,SWU5 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU5_TARG2,SWU5 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU5_HIST2,SWU5 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU5_CUR2,SWU5 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU5_CTL3,SWU5 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU5_LA3,SWU5 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU5_UA3,SWU5 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU5_ID3,SWU5 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU5_CNT3,SWU5 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU5_TARG3,SWU5 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU5_HIST3,SWU5 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU5_CUR3,SWU5 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU7" base ad:0x31140000 width 12. group.long 0x0++0x3 line.long 0x00 "SWU7_GCTL,SWU7 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU7_GSTAT,SWU7 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU7_CTL0,SWU7 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU7_LA0,SWU7 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU7_UA0,SWU7 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU7_ID0,SWU7 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU7_CNT0,SWU7 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU7_TARG0,SWU7 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU7_HIST0,SWU7 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU7_CUR0,SWU7 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU7_CTL1,SWU7 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU7_LA1,SWU7 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU7_UA1,SWU7 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU7_ID1,SWU7 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU7_CNT1,SWU7 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU7_TARG1,SWU7 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU7_HIST1,SWU7 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU7_CUR1,SWU7 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU7_CTL2,SWU7 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU7_LA2,SWU7 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU7_UA2,SWU7 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU7_ID2,SWU7 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU7_CNT2,SWU7 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU7_TARG2,SWU7 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU7_HIST2,SWU7 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU7_CUR2,SWU7 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU7_CTL3,SWU7 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU7_LA3,SWU7 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU7_UA3,SWU7 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU7_ID3,SWU7 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU7_CNT3,SWU7 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU7_TARG3,SWU7 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU7_HIST3,SWU7 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU7_CUR3,SWU7 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU8" base ad:0x31141000 width 12. group.long 0x0++0x3 line.long 0x00 "SWU8_GCTL,SWU8 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU8_GSTAT,SWU8 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU8_CTL0,SWU8 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU8_LA0,SWU8 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU8_UA0,SWU8 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU8_ID0,SWU8 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU8_CNT0,SWU8 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU8_TARG0,SWU8 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU8_HIST0,SWU8 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU8_CUR0,SWU8 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU8_CTL1,SWU8 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU8_LA1,SWU8 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU8_UA1,SWU8 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU8_ID1,SWU8 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU8_CNT1,SWU8 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU8_TARG1,SWU8 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU8_HIST1,SWU8 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU8_CUR1,SWU8 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU8_CTL2,SWU8 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU8_LA2,SWU8 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU8_UA2,SWU8 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU8_ID2,SWU8 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU8_CNT2,SWU8 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU8_TARG2,SWU8 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU8_HIST2,SWU8 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU8_CUR2,SWU8 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU8_CTL3,SWU8 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU8_LA3,SWU8 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU8_UA3,SWU8 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU8_ID3,SWU8 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU8_CNT3,SWU8 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU8_TARG3,SWU8 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU8_HIST3,SWU8 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU8_CUR3,SWU8 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU9" base ad:0x31142000 width 12. group.long 0x0++0x3 line.long 0x00 "SWU9_GCTL,SWU9 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU9_GSTAT,SWU9 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU9_CTL0,SWU9 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU9_LA0,SWU9 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU9_UA0,SWU9 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU9_ID0,SWU9 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU9_CNT0,SWU9 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU9_TARG0,SWU9 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU9_HIST0,SWU9 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU9_CUR0,SWU9 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU9_CTL1,SWU9 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU9_LA1,SWU9 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU9_UA1,SWU9 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU9_ID1,SWU9 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU9_CNT1,SWU9 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU9_TARG1,SWU9 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU9_HIST1,SWU9 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU9_CUR1,SWU9 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU9_CTL2,SWU9 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU9_LA2,SWU9 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU9_UA2,SWU9 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU9_ID2,SWU9 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU9_CNT2,SWU9 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU9_TARG2,SWU9 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU9_HIST2,SWU9 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU9_CUR2,SWU9 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU9_CTL3,SWU9 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU9_LA3,SWU9 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU9_UA3,SWU9 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU9_ID3,SWU9 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU9_CNT3,SWU9 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU9_TARG3,SWU9 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU9_HIST3,SWU9 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU9_CUR3,SWU9 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU10" base ad:0x31143000 width 13. group.long 0x0++0x3 line.long 0x00 "SWU10_GCTL,SWU10 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU10_GSTAT,SWU10 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU10_CTL0,SWU10 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU10_LA0,SWU10 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU10_UA0,SWU10 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU10_ID0,SWU10 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU10_CNT0,SWU10 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU10_TARG0,SWU10 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU10_HIST0,SWU10 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU10_CUR0,SWU10 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU10_CTL1,SWU10 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU10_LA1,SWU10 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU10_UA1,SWU10 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU10_ID1,SWU10 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU10_CNT1,SWU10 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU10_TARG1,SWU10 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU10_HIST1,SWU10 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU10_CUR1,SWU10 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU10_CTL2,SWU10 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU10_LA2,SWU10 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU10_UA2,SWU10 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU10_ID2,SWU10 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU10_CNT2,SWU10 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU10_TARG2,SWU10 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU10_HIST2,SWU10 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU10_CUR2,SWU10 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU10_CTL3,SWU10 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU10_LA3,SWU10 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU10_UA3,SWU10 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU10_ID3,SWU10 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU10_CNT3,SWU10 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU10_TARG3,SWU10 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU10_HIST3,SWU10 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU10_CUR3,SWU10 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU11" base ad:0x31097000 width 13. group.long 0x0++0x3 line.long 0x00 "SWU11_GCTL,SWU11 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU11_GSTAT,SWU11 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU11_CTL0,SWU11 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU11_LA0,SWU11 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU11_UA0,SWU11 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU11_ID0,SWU11 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU11_CNT0,SWU11 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU11_TARG0,SWU11 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU11_HIST0,SWU11 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU11_CUR0,SWU11 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU11_CTL1,SWU11 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU11_LA1,SWU11 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU11_UA1,SWU11 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU11_ID1,SWU11 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU11_CNT1,SWU11 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU11_TARG1,SWU11 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU11_HIST1,SWU11 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU11_CUR1,SWU11 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU11_CTL2,SWU11 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU11_LA2,SWU11 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU11_UA2,SWU11 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU11_ID2,SWU11 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU11_CNT2,SWU11 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU11_TARG2,SWU11 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU11_HIST2,SWU11 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU11_CUR2,SWU11 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU11_CTL3,SWU11 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU11_LA3,SWU11 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU11_UA3,SWU11 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU11_ID3,SWU11 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU11_CNT3,SWU11 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU11_TARG3,SWU11 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU11_HIST3,SWU11 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU11_CUR3,SWU11 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU12" base ad:0x310A8000 width 13. group.long 0x0++0x3 line.long 0x00 "SWU12_GCTL,SWU12 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU12_GSTAT,SWU12 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU12_CTL0,SWU12 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU12_LA0,SWU12 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU12_UA0,SWU12 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU12_ID0,SWU12 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU12_CNT0,SWU12 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU12_TARG0,SWU12 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU12_HIST0,SWU12 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU12_CUR0,SWU12 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU12_CTL1,SWU12 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU12_LA1,SWU12 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU12_UA1,SWU12 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU12_ID1,SWU12 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU12_CNT1,SWU12 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU12_TARG1,SWU12 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU12_HIST1,SWU12 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU12_CUR1,SWU12 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU12_CTL2,SWU12 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU12_LA2,SWU12 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU12_UA2,SWU12 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU12_ID2,SWU12 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU12_CNT2,SWU12 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU12_TARG2,SWU12 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU12_HIST2,SWU12 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU12_CUR2,SWU12 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU12_CTL3,SWU12 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU12_LA3,SWU12 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU12_UA3,SWU12 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU12_ID3,SWU12 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU12_CNT3,SWU12 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU12_TARG3,SWU12 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU12_HIST3,SWU12 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU12_CUR3,SWU12 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree "SWU13" base ad:0x3109E000 width 13. group.long 0x0++0x3 line.long 0x00 "SWU13_GCTL,SWU13 Global Control Register" bitfld.long 0x00 1. " RST ,Global Reset" "0,1" bitfld.long 0x00 0. " EN ,Global Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "SWU13_GSTAT,SWU13 Global Status Register" bitfld.long 0x00 30. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 15. " OVRBW3 ,Group 3 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 14. " UNDRBW3 ,Group 3 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 13. " OVRBW2 ,Group 2 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 12. " UNDRBW2 ,Group 2 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 11. " OVRBW1 ,Group 1 Bandwidth Above Maximum Target" "0,1" newline bitfld.long 0x00 10. " UNDRBW1 ,Group 1 Bandwidth Below Minimum Target" "0,1" bitfld.long 0x00 9. " OVRBW0 ,Group 0 Bandwidth Above Maximum Target" "0,1" bitfld.long 0x00 8. " UNDRBW0 ,Group 0 Bandwidth Below Minimum Target" "0,1" newline bitfld.long 0x00 7. " INT3 ,Group 3 Interrupt Status" "0,1" bitfld.long 0x00 6. " INT2 ,Group 2 Interrupt Status" "0,1" bitfld.long 0x00 5. " INT1 ,Group 1 Interrupt Status" "0,1" newline bitfld.long 0x00 4. " INT0 ,Group 0 Interrupt Status" "0,1" bitfld.long 0x00 3. " MTCH3 ,Group 3 Match" "0,1" bitfld.long 0x00 2. " MTCH2 ,Group 2 Match" "0,1" newline bitfld.long 0x00 1. " MTCH1 ,Group 1 Match" "0,1" bitfld.long 0x00 0. " MTCH0 ,Group 0 Match" "0,1" group.long 0x10++0x3 line.long 0x00 "SWU13_CTL0,SWU13 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x14++0x3 line.long 0x00 "SWU13_LA0,SWU13 Lower Address Register n" group.long 0x18++0x3 line.long 0x00 "SWU13_UA0,SWU13 Upper Address Register n" group.long 0x1C++0x3 line.long 0x00 "SWU13_ID0,SWU13 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x20++0x3 line.long 0x00 "SWU13_CNT0,SWU13 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x24++0x3 line.long 0x00 "SWU13_TARG0,SWU13 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x28++0x3 line.long 0x00 "SWU13_HIST0,SWU13 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x2C++0x3 line.long 0x00 "SWU13_CUR0,SWU13 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x30++0x3 line.long 0x00 "SWU13_CTL1,SWU13 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x34++0x3 line.long 0x00 "SWU13_LA1,SWU13 Lower Address Register n" group.long 0x38++0x3 line.long 0x00 "SWU13_UA1,SWU13 Upper Address Register n" group.long 0x3C++0x3 line.long 0x00 "SWU13_ID1,SWU13 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x40++0x3 line.long 0x00 "SWU13_CNT1,SWU13 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x44++0x3 line.long 0x00 "SWU13_TARG1,SWU13 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x48++0x3 line.long 0x00 "SWU13_HIST1,SWU13 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x4C++0x3 line.long 0x00 "SWU13_CUR1,SWU13 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x50++0x3 line.long 0x00 "SWU13_CTL2,SWU13 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x54++0x3 line.long 0x00 "SWU13_LA2,SWU13 Lower Address Register n" group.long 0x58++0x3 line.long 0x00 "SWU13_UA2,SWU13 Upper Address Register n" group.long 0x5C++0x3 line.long 0x00 "SWU13_ID2,SWU13 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x60++0x3 line.long 0x00 "SWU13_CNT2,SWU13 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x64++0x3 line.long 0x00 "SWU13_TARG2,SWU13 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x68++0x3 line.long 0x00 "SWU13_HIST2,SWU13 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x6C++0x3 line.long 0x00 "SWU13_CUR2,SWU13 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" group.long 0x70++0x3 line.long 0x00 "SWU13_CTL3,SWU13 Control Register n" bitfld.long 0x00 24. " DATACNTMODE ,Data Channel Monitor" "0,1" bitfld.long 0x00 21.--23. " SCALE ,Scale the number of transactions" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20. " STALLCNTMODE ,Stall Count Mode" "0,1" newline bitfld.long 0x00 19. " MAXACT ,Action for Bandwidth Above Maximum" "0,1" bitfld.long 0x00 18. " MINACT ,Action for Bandwidth Below Minimum" "0,1" bitfld.long 0x00 17. " BLENINC ,Increment Bandwidth Count by Burst Length" "0,1" newline bitfld.long 0x00 16. " BWEN ,Bandwidth Mode Enable" "0,1" bitfld.long 0x00 14. " TRGEN ,Trigger Enable" "0,1" bitfld.long 0x00 13. " INTEN ,Interrupt Enable" "0,1" newline bitfld.long 0x00 12. " DBGEN ,Debug Event Enable" "0,1" bitfld.long 0x00 9. " CNTRPTEN ,Count Repeat Enable" "0,1" bitfld.long 0x00 8. " CNTEN ,Count Enable" "0,1" newline bitfld.long 0x00 5. " SCMPEN ,Secure Comparison Enable" "0,1" bitfld.long 0x00 4. " IDCMPEN ,ID Comparison Enable" "0,1" bitfld.long 0x00 2.--3. " ACMPM ,Address Comparison Mode" "0,1,2,3" newline bitfld.long 0x00 1. " DIR ,Transaction Direction for Match" "0,1" bitfld.long 0x00 0. " EN ,Enable Watchpoint" "0,1" group.long 0x74++0x3 line.long 0x00 "SWU13_LA3,SWU13 Lower Address Register n" group.long 0x78++0x3 line.long 0x00 "SWU13_UA3,SWU13 Upper Address Register n" group.long 0x7C++0x3 line.long 0x00 "SWU13_ID3,SWU13 ID Register n" hexmask.long.word 0x00 16.--31. 1. " IDMASK ,Identity Mask (for Or with ID)" hexmask.long.word 0x00 0.--15. 1. " ID ,Identity" group.long 0x80++0x3 line.long 0x00 "SWU13_CNT3,SWU13 Count Register n" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Count" group.long 0x84++0x3 line.long 0x00 "SWU13_TARG3,SWU13 Target Register n" hexmask.long.word 0x00 16.--31. 1. " BWMAX ,Maximum Bandwidth Target" hexmask.long.word 0x00 0.--15. 1. " BWMIN ,Minimum Bandwidth Target" group.long 0x88++0x3 line.long 0x00 "SWU13_HIST3,SWU13 Bandwidth History Register n" hexmask.long.word 0x00 16.--31. 1. " BWHIST1 ,Bandwidth from Window Before Last" hexmask.long.word 0x00 0.--15. 1. " BWHIST0 ,Bandwidth from Last Window" group.long 0x8C++0x3 line.long 0x00 "SWU13_CUR3,SWU13 Current Register n" hexmask.long.word 0x00 16.--31. 1. " CURBW ,Current Bandwidth" hexmask.long.word 0x00 0.--15. 1. " CURCNT ,Current Count" tree.end tree.end tree "TAPC" base ad:0x31130000 width 19. group.long 0x0++0x3 line.long 0x00 "TAPC_IDCODE,TAPC IDCODE Register" bitfld.long 0x00 28.--31. " REVID ,Silicon Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 12.--27. 1. " JTAGID ,JTAG ID" hexmask.long.word 0x00 1.--11. 1. " MNFID ,Manufacturer ID" newline bitfld.long 0x00 0. " LSB ,IDCODE LSB" "0,1" group.long 0x4++0x3 line.long 0x00 "TAPC_USERCODE,TAPC USERCODE Register" group.long 0x8++0x3 line.long 0x00 "TAPC_SDBGKEY_CTL,TAPC Secure Debug Key Control Register" bitfld.long 0x00 0. " VALID ,SDBGKEY Valid bit" "0,1" group.long 0xC++0x3 line.long 0x00 "TAPC_SDBGKEY_STAT,TAPC Secure Debug Key Status Register" bitfld.long 0x00 1. " FAIL ,SDBGKEY MATCH FAILED" "0,1" bitfld.long 0x00 0. " PASS ,SDBGKEY MATCH PASSED" "0,1" group.long 0x10++0x3 line.long 0x00 "TAPC_SDBGKEY0,TAPC Secure Debug Key 0 Register" group.long 0x14++0x3 line.long 0x00 "TAPC_SDBGKEY1,TAPC Secure Debug Key 1 Register" group.long 0x18++0x3 line.long 0x00 "TAPC_SDBGKEY2,TAPC Secure Debug Key 2 Register" group.long 0x1C++0x3 line.long 0x00 "TAPC_SDBGKEY3,TAPC Secure Debug Key 3 Register" group.long 0x1000++0x3 line.long 0x00 "TAPC_DBGCTL,TAPC Debug Control Register" bitfld.long 0x00 15. " SPIDENTRACE ,SPIDEN for Coresight trace modules" "0,1" bitfld.long 0x00 14. " NIDENTRACE ,NIDEN for Coresight trace modules" "0,1" bitfld.long 0x00 13. " DBGENTRACE ,DBGEN for Coresight trace modules" "0,1" newline bitfld.long 0x00 12. " NIDENCTISYS ,NIDEN for System CTI" "0,1" bitfld.long 0x00 11. " DBGENCTISYS ,DBGEN for System CTI" "0,1" bitfld.long 0x00 10. " SPIDENSTM ,SPIDEN for STM" "0,1" newline bitfld.long 0x00 9. " SPNIDENSTM ,SPNIDEN for STM" "0,1" bitfld.long 0x00 8. " NIDENSTM ,NIDEN for STM" "0,1" bitfld.long 0x00 7. " DBGENSTM ,DBGEN for STM" "0,1" newline bitfld.long 0x00 6. " DBGENC2 ,DBGEN for Core 2" "0,1" bitfld.long 0x00 5. " DBGENC1 ,DBGEN for Core 1" "0,1" bitfld.long 0x00 4. " SPIDENC0 ,SPIDEN for Core 0" "0,1" newline bitfld.long 0x00 3. " SPNIDENC0 ,SPNIDEN for Core 0" "0,1" bitfld.long 0x00 2. " NIDENC0 ,NIDEN for Core 0" "0,1" bitfld.long 0x00 1. " DBGENC0 ,DBGEN for Core 0" "0,1" newline bitfld.long 0x00 0. " SPIDENDAP ,SPIDEN for DAP" "0,1" tree.end tree "TIMER0" base ad:0x31018004 width 21. group.long 0x0++0x3 line.long 0x00 "TIMER0_RUN,TIMER0 Run Register" bitfld.long 0x00 15. " TMR15 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 14. " TMR14 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 13. " TMR13 ,Start/Stop Timer n" "0,1" newline bitfld.long 0x00 12. " TMR12 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 11. " TMR11 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 10. " TMR10 ,Start/Stop Timer n" "0,1" newline bitfld.long 0x00 9. " TMR09 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 8. " TMR08 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 7. " TMR07 ,Start/Stop Timer n" "0,1" newline bitfld.long 0x00 6. " TMR06 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 5. " TMR05 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 4. " TMR04 ,Start/Stop Timer n" "0,1" newline bitfld.long 0x00 3. " TMR03 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 2. " TMR02 ,Start/Stop Timer n" "0,1" bitfld.long 0x00 1. " TMR01 ,Start/Stop Timer n" "0,1" newline bitfld.long 0x00 0. " TMR00 ,Start/Stop Timer n" "0,1" group.long 0x4++0x3 line.long 0x00 "TIMER0_RUN_SET,TIMER0 Run Set Register" bitfld.long 0x00 15. " TMR15 ,RUN Set Alias" "0,1" bitfld.long 0x00 14. " TMR14 ,RUN Set Alias" "0,1" bitfld.long 0x00 13. " TMR13 ,RUN Set Alias" "0,1" newline bitfld.long 0x00 12. " TMR12 ,RUN Set Alias" "0,1" bitfld.long 0x00 11. " TMR11 ,RUN Set Alias" "0,1" bitfld.long 0x00 10. " TMR10 ,RUN Set Alias" "0,1" newline bitfld.long 0x00 9. " TMR09 ,RUN Set Alias" "0,1" bitfld.long 0x00 8. " TMR08 ,RUN Set Alias" "0,1" bitfld.long 0x00 7. " TMR07 ,RUN Set Alias" "0,1" newline bitfld.long 0x00 6. " TMR06 ,RUN Set Alias" "0,1" bitfld.long 0x00 5. " TMR05 ,RUN Set Alias" "0,1" bitfld.long 0x00 4. " TMR04 ,RUN Set Alias" "0,1" newline bitfld.long 0x00 3. " TMR03 ,RUN Set Alias" "0,1" bitfld.long 0x00 2. " TMR02 ,RUN Set Alias" "0,1" bitfld.long 0x00 1. " TMR01 ,RUN Set Alias" "0,1" newline bitfld.long 0x00 0. " TMR00 ,RUN Set Alias" "0,1" group.long 0x8++0x3 line.long 0x00 "TIMER0_RUN_CLR,TIMER0 Run Clear Register" bitfld.long 0x00 15. " TMR15 ,RUN Clear Alias" "0,1" bitfld.long 0x00 14. " TMR14 ,RUN Clear Alias" "0,1" bitfld.long 0x00 13. " TMR13 ,RUN Clear Alias" "0,1" newline bitfld.long 0x00 12. " TMR12 ,RUN Clear Alias" "0,1" bitfld.long 0x00 11. " TMR11 ,RUN Clear Alias" "0,1" bitfld.long 0x00 10. " TMR10 ,RUN Clear Alias" "0,1" newline bitfld.long 0x00 9. " TMR09 ,RUN Clear Alias" "0,1" bitfld.long 0x00 8. " TMR08 ,RUN Clear Alias" "0,1" bitfld.long 0x00 7. " TMR07 ,RUN Clear Alias" "0,1" newline bitfld.long 0x00 6. " TMR06 ,RUN Clear Alias" "0,1" bitfld.long 0x00 5. " TMR05 ,RUN Clear Alias" "0,1" bitfld.long 0x00 4. " TMR04 ,RUN Clear Alias" "0,1" newline bitfld.long 0x00 3. " TMR03 ,RUN Clear Alias" "0,1" bitfld.long 0x00 2. " TMR02 ,RUN Clear Alias" "0,1" bitfld.long 0x00 1. " TMR01 ,RUN Clear Alias" "0,1" newline bitfld.long 0x00 0. " TMR00 ,RUN Clear Alias" "0,1" group.long 0xC++0x3 line.long 0x00 "TIMER0_STOP_CFG,TIMER0 Stop Configuration Register" bitfld.long 0x00 15. " TMR15 ,Stop Mode Select" "0,1" bitfld.long 0x00 14. " TMR14 ,Stop Mode Select" "0,1" bitfld.long 0x00 13. " TMR13 ,Stop Mode Select" "0,1" newline bitfld.long 0x00 12. " TMR12 ,Stop Mode Select" "0,1" bitfld.long 0x00 11. " TMR11 ,Stop Mode Select" "0,1" bitfld.long 0x00 10. " TMR10 ,Stop Mode Select" "0,1" newline bitfld.long 0x00 9. " TMR09 ,Stop Mode Select" "0,1" bitfld.long 0x00 8. " TMR08 ,Stop Mode Select" "0,1" bitfld.long 0x00 7. " TMR07 ,Stop Mode Select" "0,1" newline bitfld.long 0x00 6. " TMR06 ,Stop Mode Select" "0,1" bitfld.long 0x00 5. " TMR05 ,Stop Mode Select" "0,1" bitfld.long 0x00 4. " TMR04 ,Stop Mode Select" "0,1" newline bitfld.long 0x00 3. " TMR03 ,Stop Mode Select" "0,1" bitfld.long 0x00 2. " TMR02 ,Stop Mode Select" "0,1" bitfld.long 0x00 1. " TMR01 ,Stop Mode Select" "0,1" newline bitfld.long 0x00 0. " TMR00 ,Stop Mode Select" "0,1" group.long 0x10++0x3 line.long 0x00 "TIMER0_STOP_CFG_SET,TIMER0 Stop Configuration Set Register" bitfld.long 0x00 15. " TMR15 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 14. " TMR14 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 13. " TMR13 ,STOP_CFG Set Alias" "0,1" newline bitfld.long 0x00 12. " TMR12 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 11. " TMR11 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 10. " TMR10 ,STOP_CFG Set Alias" "0,1" newline bitfld.long 0x00 9. " TMR09 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 8. " TMR08 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 7. " TMR07 ,STOP_CFG Set Alias" "0,1" newline bitfld.long 0x00 6. " TMR06 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 5. " TMR05 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 4. " TMR04 ,STOP_CFG Set Alias" "0,1" newline bitfld.long 0x00 3. " TMR03 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 2. " TMR02 ,STOP_CFG Set Alias" "0,1" bitfld.long 0x00 1. " TMR01 ,STOP_CFG Set Alias" "0,1" newline bitfld.long 0x00 0. " TMR00 ,STOP_CFG Set Alias" "0,1" group.long 0x14++0x3 line.long 0x00 "TIMER0_STOP_CFG_CLR,TIMER0 Stop Configuration Clear Register" bitfld.long 0x00 15. " TMR15 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 14. " TMR14 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 13. " TMR13 ,STOP_CFG Clear Alias" "0,1" newline bitfld.long 0x00 12. " TMR12 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 11. " TMR11 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 10. " TMR10 ,STOP_CFG Clear Alias" "0,1" newline bitfld.long 0x00 9. " TMR09 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 8. " TMR08 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 7. " TMR07 ,STOP_CFG Clear Alias" "0,1" newline bitfld.long 0x00 6. " TMR06 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 5. " TMR05 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 4. " TMR04 ,STOP_CFG Clear Alias" "0,1" newline bitfld.long 0x00 3. " TMR03 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 2. " TMR02 ,STOP_CFG Clear Alias" "0,1" bitfld.long 0x00 1. " TMR01 ,STOP_CFG Clear Alias" "0,1" newline bitfld.long 0x00 0. " TMR00 ,STOP_CFG Clear Alias" "0,1" group.long 0x18++0x3 line.long 0x00 "TIMER0_DATA_IMSK,TIMER0 Data Interrupt Mask Register" bitfld.long 0x00 15. " TMR15 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 14. " TMR14 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 13. " TMR13 ,Data Interrupt Mask" "0,1" newline bitfld.long 0x00 12. " TMR12 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 11. " TMR11 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 10. " TMR10 ,Data Interrupt Mask" "0,1" newline bitfld.long 0x00 9. " TMR09 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 8. " TMR08 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 7. " TMR07 ,Data Interrupt Mask" "0,1" newline bitfld.long 0x00 6. " TMR06 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 5. " TMR05 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 4. " TMR04 ,Data Interrupt Mask" "0,1" newline bitfld.long 0x00 3. " TMR03 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 2. " TMR02 ,Data Interrupt Mask" "0,1" bitfld.long 0x00 1. " TMR01 ,Data Interrupt Mask" "0,1" newline bitfld.long 0x00 0. " TMR00 ,Data Interrupt Mask" "0,1" group.long 0x1C++0x3 line.long 0x00 "TIMER0_STAT_IMSK,TIMER0 Status Interrupt Mask Register" bitfld.long 0x00 15. " TMR15 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 14. " TMR14 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 13. " TMR13 ,Status Interrupt Mask" "0,1" newline bitfld.long 0x00 12. " TMR12 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 11. " TMR11 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 10. " TMR10 ,Status Interrupt Mask" "0,1" newline bitfld.long 0x00 9. " TMR09 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 8. " TMR08 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 7. " TMR07 ,Status Interrupt Mask" "0,1" newline bitfld.long 0x00 6. " TMR06 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 5. " TMR05 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 4. " TMR04 ,Status Interrupt Mask" "0,1" newline bitfld.long 0x00 3. " TMR03 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 2. " TMR02 ,Status Interrupt Mask" "0,1" bitfld.long 0x00 1. " TMR01 ,Status Interrupt Mask" "0,1" newline bitfld.long 0x00 0. " TMR00 ,Status Interrupt Mask" "0,1" group.long 0x20++0x3 line.long 0x00 "TIMER0_TRG_MSK,TIMER0 Trigger Master Mask Register" bitfld.long 0x00 15. " TMR15 ,Trigger Output Mask" "0,1" bitfld.long 0x00 14. " TMR14 ,Trigger Output Mask" "0,1" bitfld.long 0x00 13. " TMR13 ,Trigger Output Mask" "0,1" newline bitfld.long 0x00 12. " TMR12 ,Trigger Output Mask" "0,1" bitfld.long 0x00 11. " TMR11 ,Trigger Output Mask" "0,1" bitfld.long 0x00 10. " TMR10 ,Trigger Output Mask" "0,1" newline bitfld.long 0x00 9. " TMR09 ,Trigger Output Mask" "0,1" bitfld.long 0x00 8. " TMR08 ,Trigger Output Mask" "0,1" bitfld.long 0x00 7. " TMR07 ,Trigger Output Mask" "0,1" newline bitfld.long 0x00 6. " TMR06 ,Trigger Output Mask" "0,1" bitfld.long 0x00 5. " TMR05 ,Trigger Output Mask" "0,1" bitfld.long 0x00 4. " TMR04 ,Trigger Output Mask" "0,1" newline bitfld.long 0x00 3. " TMR03 ,Trigger Output Mask" "0,1" bitfld.long 0x00 2. " TMR02 ,Trigger Output Mask" "0,1" bitfld.long 0x00 1. " TMR01 ,Trigger Output Mask" "0,1" newline bitfld.long 0x00 0. " TMR00 ,Trigger Output Mask" "0,1" group.long 0x24++0x3 line.long 0x00 "TIMER0_TRG_IE,TIMER0 Trigger Slave Enable Register" bitfld.long 0x00 15. " TMR15 ,Trigger Input Enable" "0,1" bitfld.long 0x00 14. " TMR14 ,Trigger Input Enable" "0,1" bitfld.long 0x00 13. " TMR13 ,Trigger Input Enable" "0,1" newline bitfld.long 0x00 12. " TMR12 ,Trigger Input Enable" "0,1" bitfld.long 0x00 11. " TMR11 ,Trigger Input Enable" "0,1" bitfld.long 0x00 10. " TMR10 ,Trigger Input Enable" "0,1" newline bitfld.long 0x00 9. " TMR09 ,Trigger Input Enable" "0,1" bitfld.long 0x00 8. " TMR08 ,Trigger Input Enable" "0,1" bitfld.long 0x00 7. " TMR07 ,Trigger Input Enable" "0,1" newline bitfld.long 0x00 6. " TMR06 ,Trigger Input Enable" "0,1" bitfld.long 0x00 5. " TMR05 ,Trigger Input Enable" "0,1" bitfld.long 0x00 4. " TMR04 ,Trigger Input Enable" "0,1" newline bitfld.long 0x00 3. " TMR03 ,Trigger Input Enable" "0,1" bitfld.long 0x00 2. " TMR02 ,Trigger Input Enable" "0,1" bitfld.long 0x00 1. " TMR01 ,Trigger Input Enable" "0,1" newline bitfld.long 0x00 0. " TMR00 ,Trigger Input Enable" "0,1" group.long 0x28++0x3 line.long 0x00 "TIMER0_DATA_ILAT,TIMER0 Data Interrupt Latch Register" bitfld.long 0x00 15. " TMR15 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 14. " TMR14 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 13. " TMR13 ,Data Interrupt Latch" "0,1" newline bitfld.long 0x00 12. " TMR12 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 11. " TMR11 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 10. " TMR10 ,Data Interrupt Latch" "0,1" newline bitfld.long 0x00 9. " TMR09 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 8. " TMR08 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 7. " TMR07 ,Data Interrupt Latch" "0,1" newline bitfld.long 0x00 6. " TMR06 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 5. " TMR05 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 4. " TMR04 ,Data Interrupt Latch" "0,1" newline bitfld.long 0x00 3. " TMR03 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 2. " TMR02 ,Data Interrupt Latch" "0,1" bitfld.long 0x00 1. " TMR01 ,Data Interrupt Latch" "0,1" newline bitfld.long 0x00 0. " TMR00 ,Data Interrupt Latch" "0,1" group.long 0x2C++0x3 line.long 0x00 "TIMER0_STAT_ILAT,TIMER0 Status Interrupt Latch Register" bitfld.long 0x00 15. " TMR15 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 14. " TMR14 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 13. " TMR13 ,Status Interrupt Latch" "0,1" newline bitfld.long 0x00 12. " TMR12 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 11. " TMR11 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 10. " TMR10 ,Status Interrupt Latch" "0,1" newline bitfld.long 0x00 9. " TMR09 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 8. " TMR08 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 7. " TMR07 ,Status Interrupt Latch" "0,1" newline bitfld.long 0x00 6. " TMR06 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 5. " TMR05 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 4. " TMR04 ,Status Interrupt Latch" "0,1" newline bitfld.long 0x00 3. " TMR03 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 2. " TMR02 ,Status Interrupt Latch" "0,1" bitfld.long 0x00 1. " TMR01 ,Status Interrupt Latch" "0,1" newline bitfld.long 0x00 0. " TMR00 ,Status Interrupt Latch" "0,1" group.long 0x30++0x3 line.long 0x00 "TIMER0_ERR_TYPE,TIMER0 Error Type Status Register" bitfld.long 0x00 30.--31. " TERR15 ,Error Type for Timer 15" "0,1,2,3" bitfld.long 0x00 28.--29. " TERR14 ,Error Type for Timer 14" "0,1,2,3" bitfld.long 0x00 26.--27. " TERR13 ,Error Type for Timer 13" "0,1,2,3" newline bitfld.long 0x00 24.--25. " TERR12 ,Error Type for Timer 12" "0,1,2,3" bitfld.long 0x00 22.--23. " TERR11 ,Error Type for Timer 11" "0,1,2,3" bitfld.long 0x00 20.--21. " TERR10 ,Error Type for Timer 10" "0,1,2,3" newline bitfld.long 0x00 16.--17. " TERR8 ,Error Type for Timer 8" "0,1,2,3" bitfld.long 0x00 14.--15. " TERR7 ,Error Type for Timer 7" "0,1,2,3" bitfld.long 0x00 12.--13. " TERR6 ,Error Type for Timer 6" "0,1,2,3" newline bitfld.long 0x00 10.--11. " TERR5 ,Error Type for Timer 5" "0,1,2,3" bitfld.long 0x00 8.--9. " TERR4 ,Error Type for Timer 4" "0,1,2,3" bitfld.long 0x00 6.--7. " TERR3 ,Error Type for Timer 3" "0,1,2,3" newline bitfld.long 0x00 4.--5. " TERR2 ,Error Type for Timer 2" "0,1,2,3" bitfld.long 0x00 2.--3. " TERR1 ,Error Type for Timer 1" "0,1,2,3" bitfld.long 0x00 0.--1. " TERR0 ,Error Type for Timer 0" "0,1,2,3" group.long 0x34++0x3 line.long 0x00 "TIMER0_BCAST_PER,TIMER0 Broadcast Period Register" group.long 0x38++0x3 line.long 0x00 "TIMER0_BCAST_WID,TIMER0 Broadcast Width Register" group.long 0x3C++0x3 line.long 0x00 "TIMER0_BCAST_DLY,TIMER0 Broadcast Delay Register" group.long 0x5C++0x3 line.long 0x00 "TIMER0_TMR0_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x60++0x3 line.long 0x00 "TIMER0_TMR0_CNT,TIMER0 Timer n Counter Register" group.long 0x64++0x3 line.long 0x00 "TIMER0_TMR0_PER,TIMER0 Timer n Period Register" group.long 0x68++0x3 line.long 0x00 "TIMER0_TMR0_WID,TIMER0 Timer n Width Register" group.long 0x6C++0x3 line.long 0x00 "TIMER0_TMR0_DLY,TIMER0 Timer n Delay Register" group.long 0x7C++0x3 line.long 0x00 "TIMER0_TMR1_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x80++0x3 line.long 0x00 "TIMER0_TMR1_CNT,TIMER0 Timer n Counter Register" group.long 0x84++0x3 line.long 0x00 "TIMER0_TMR1_PER,TIMER0 Timer n Period Register" group.long 0x88++0x3 line.long 0x00 "TIMER0_TMR1_WID,TIMER0 Timer n Width Register" group.long 0x8C++0x3 line.long 0x00 "TIMER0_TMR1_DLY,TIMER0 Timer n Delay Register" group.long 0x9C++0x3 line.long 0x00 "TIMER0_TMR2_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xA0++0x3 line.long 0x00 "TIMER0_TMR2_CNT,TIMER0 Timer n Counter Register" group.long 0xA4++0x3 line.long 0x00 "TIMER0_TMR2_PER,TIMER0 Timer n Period Register" group.long 0xA8++0x3 line.long 0x00 "TIMER0_TMR2_WID,TIMER0 Timer n Width Register" group.long 0xAC++0x3 line.long 0x00 "TIMER0_TMR2_DLY,TIMER0 Timer n Delay Register" group.long 0xBC++0x3 line.long 0x00 "TIMER0_TMR3_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xC0++0x3 line.long 0x00 "TIMER0_TMR3_CNT,TIMER0 Timer n Counter Register" group.long 0xC4++0x3 line.long 0x00 "TIMER0_TMR3_PER,TIMER0 Timer n Period Register" group.long 0xC8++0x3 line.long 0x00 "TIMER0_TMR3_WID,TIMER0 Timer n Width Register" group.long 0xCC++0x3 line.long 0x00 "TIMER0_TMR3_DLY,TIMER0 Timer n Delay Register" group.long 0xDC++0x3 line.long 0x00 "TIMER0_TMR4_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xE0++0x3 line.long 0x00 "TIMER0_TMR4_CNT,TIMER0 Timer n Counter Register" group.long 0xE4++0x3 line.long 0x00 "TIMER0_TMR4_PER,TIMER0 Timer n Period Register" group.long 0xE8++0x3 line.long 0x00 "TIMER0_TMR4_WID,TIMER0 Timer n Width Register" group.long 0xEC++0x3 line.long 0x00 "TIMER0_TMR4_DLY,TIMER0 Timer n Delay Register" group.long 0xFC++0x3 line.long 0x00 "TIMER0_TMR5_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x100++0x3 line.long 0x00 "TIMER0_TMR5_CNT,TIMER0 Timer n Counter Register" group.long 0x104++0x3 line.long 0x00 "TIMER0_TMR5_PER,TIMER0 Timer n Period Register" group.long 0x108++0x3 line.long 0x00 "TIMER0_TMR5_WID,TIMER0 Timer n Width Register" group.long 0x10C++0x3 line.long 0x00 "TIMER0_TMR5_DLY,TIMER0 Timer n Delay Register" group.long 0x11C++0x3 line.long 0x00 "TIMER0_TMR6_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x3 line.long 0x00 "TIMER0_TMR6_CNT,TIMER0 Timer n Counter Register" group.long 0x124++0x3 line.long 0x00 "TIMER0_TMR6_PER,TIMER0 Timer n Period Register" group.long 0x128++0x3 line.long 0x00 "TIMER0_TMR6_WID,TIMER0 Timer n Width Register" group.long 0x12C++0x3 line.long 0x00 "TIMER0_TMR6_DLY,TIMER0 Timer n Delay Register" group.long 0x13C++0x3 line.long 0x00 "TIMER0_TMR7_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x140++0x3 line.long 0x00 "TIMER0_TMR7_CNT,TIMER0 Timer n Counter Register" group.long 0x144++0x3 line.long 0x00 "TIMER0_TMR7_PER,TIMER0 Timer n Period Register" group.long 0x148++0x3 line.long 0x00 "TIMER0_TMR7_WID,TIMER0 Timer n Width Register" group.long 0x14C++0x3 line.long 0x00 "TIMER0_TMR7_DLY,TIMER0 Timer n Delay Register" group.long 0x15C++0x3 line.long 0x00 "TIMER0_TMR8_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x160++0x3 line.long 0x00 "TIMER0_TMR8_CNT,TIMER0 Timer n Counter Register" group.long 0x164++0x3 line.long 0x00 "TIMER0_TMR8_PER,TIMER0 Timer n Period Register" group.long 0x168++0x3 line.long 0x00 "TIMER0_TMR8_WID,TIMER0 Timer n Width Register" group.long 0x16C++0x3 line.long 0x00 "TIMER0_TMR8_DLY,TIMER0 Timer n Delay Register" group.long 0x17C++0x3 line.long 0x00 "TIMER0_TMR9_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x180++0x3 line.long 0x00 "TIMER0_TMR9_CNT,TIMER0 Timer n Counter Register" group.long 0x184++0x3 line.long 0x00 "TIMER0_TMR9_PER,TIMER0 Timer n Period Register" group.long 0x188++0x3 line.long 0x00 "TIMER0_TMR9_WID,TIMER0 Timer n Width Register" group.long 0x18C++0x3 line.long 0x00 "TIMER0_TMR9_DLY,TIMER0 Timer n Delay Register" group.long 0x19C++0x3 line.long 0x00 "TIMER0_TMR10_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1A0++0x3 line.long 0x00 "TIMER0_TMR10_CNT,TIMER0 Timer n Counter Register" group.long 0x1A4++0x3 line.long 0x00 "TIMER0_TMR10_PER,TIMER0 Timer n Period Register" group.long 0x1A8++0x3 line.long 0x00 "TIMER0_TMR10_WID,TIMER0 Timer n Width Register" group.long 0x1AC++0x3 line.long 0x00 "TIMER0_TMR10_DLY,TIMER0 Timer n Delay Register" group.long 0x1BC++0x3 line.long 0x00 "TIMER0_TMR11_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1C0++0x3 line.long 0x00 "TIMER0_TMR11_CNT,TIMER0 Timer n Counter Register" group.long 0x1C4++0x3 line.long 0x00 "TIMER0_TMR11_PER,TIMER0 Timer n Period Register" group.long 0x1C8++0x3 line.long 0x00 "TIMER0_TMR11_WID,TIMER0 Timer n Width Register" group.long 0x1CC++0x3 line.long 0x00 "TIMER0_TMR11_DLY,TIMER0 Timer n Delay Register" group.long 0x1DC++0x3 line.long 0x00 "TIMER0_TMR12_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1E0++0x3 line.long 0x00 "TIMER0_TMR12_CNT,TIMER0 Timer n Counter Register" group.long 0x1E4++0x3 line.long 0x00 "TIMER0_TMR12_PER,TIMER0 Timer n Period Register" group.long 0x1E8++0x3 line.long 0x00 "TIMER0_TMR12_WID,TIMER0 Timer n Width Register" group.long 0x1EC++0x3 line.long 0x00 "TIMER0_TMR12_DLY,TIMER0 Timer n Delay Register" group.long 0x1FC++0x3 line.long 0x00 "TIMER0_TMR13_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x200++0x3 line.long 0x00 "TIMER0_TMR13_CNT,TIMER0 Timer n Counter Register" group.long 0x204++0x3 line.long 0x00 "TIMER0_TMR13_PER,TIMER0 Timer n Period Register" group.long 0x208++0x3 line.long 0x00 "TIMER0_TMR13_WID,TIMER0 Timer n Width Register" group.long 0x20C++0x3 line.long 0x00 "TIMER0_TMR13_DLY,TIMER0 Timer n Delay Register" group.long 0x21C++0x3 line.long 0x00 "TIMER0_TMR14_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x220++0x3 line.long 0x00 "TIMER0_TMR14_CNT,TIMER0 Timer n Counter Register" group.long 0x224++0x3 line.long 0x00 "TIMER0_TMR14_PER,TIMER0 Timer n Period Register" group.long 0x228++0x3 line.long 0x00 "TIMER0_TMR14_WID,TIMER0 Timer n Width Register" group.long 0x22C++0x3 line.long 0x00 "TIMER0_TMR14_DLY,TIMER0 Timer n Delay Register" group.long 0x23C++0x3 line.long 0x00 "TIMER0_TMR15_CFG,TIMER0 Timer n Configuration Register" bitfld.long 0x00 17. " ORDTGLTRIG ,Ordered Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 16. " TGLTRIG ,Slave Trigger Toggle Enable" "0,1" bitfld.long 0x00 15. " EMURUN ,Emulation Run" "0,1" newline bitfld.long 0x00 14. " BPEREN ,Broadcast Period Enable" "0,1" bitfld.long 0x00 13. " BWIDEN ,Broadcast Width Enable" "0,1" bitfld.long 0x00 12. " BDLYEN ,Broadcast Delay Enable" "0,1" newline bitfld.long 0x00 11. " OUTDIS ,Output Disable" "0,1" bitfld.long 0x00 10. " TINSEL ,Timer Input Select (for WIDCAP, WATCHDOG, PININT modes)" "0,1" bitfld.long 0x00 8.--9. " CLKSEL ,Clock Select" "0,1,2,3" newline bitfld.long 0x00 7. " PULSEHI ,Polarity Response Select" "0,1" bitfld.long 0x00 6. " SLAVETRIG ,Slave Trigger Response." "0,1" bitfld.long 0x00 4.--5. " IRQMODE ,Interrupt Modes" "0,1,2,3" newline bitfld.long 0x00 0.--3. " TMODE ,Timer Mode Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x240++0x3 line.long 0x00 "TIMER0_TMR15_CNT,TIMER0 Timer n Counter Register" group.long 0x244++0x3 line.long 0x00 "TIMER0_TMR15_PER,TIMER0 Timer n Period Register" group.long 0x248++0x3 line.long 0x00 "TIMER0_TMR15_WID,TIMER0 Timer n Width Register" group.long 0x24C++0x3 line.long 0x00 "TIMER0_TMR15_DLY,TIMER0 Timer n Delay Register" tree.end tree "TMU (Thermal Monitoring Unit)" base ad:0x31016800 width 18. group.long 0x0++0x3 line.long 0x00 "TMU0_CTL,TMU0 TMU Control Register" bitfld.long 0x00 13. " TMEN_FORCE ,Indefinite Enable" "0,1" hexmask.long.byte 0x00 4.--11. 1. " SCLKDIV ,System Clock Divide" bitfld.long 0x00 3. " TMEN ,Periodic Enable" "0,1" newline bitfld.long 0x00 0. " TMPU ,TMU Enable" "0,1" group.long 0x4++0x3 line.long 0x00 "TMU0_TEMP,TMU0 Temperature Value Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,Value" group.long 0x8++0x3 line.long 0x00 "TMU0_AVG,TMU0 Averaging Register" bitfld.long 0x00 0. " EN ,Value" "0,1" group.long 0xC++0x3 line.long 0x00 "TMU0_FLT_LIM_HI,TMU0 Fault High Limit Register" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Value" group.long 0x10++0x3 line.long 0x00 "TMU0_ALRT_LIM_HI,TMU0 Alert High Limit Register" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Value" group.long 0x14++0x3 line.long 0x00 "TMU0_FLT_LIM_LO,TMU0 Fault Low Limit Register" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Value" group.long 0x18++0x3 line.long 0x00 "TMU0_ALRT_LIM_LO,TMU0 Alert Low Limit Register" hexmask.long.word 0x00 0.--8. 1. " VALUE ,Value" group.long 0x1C++0x3 line.long 0x00 "TMU0_STAT,TMU0 Status Register" bitfld.long 0x00 7. " ALRTLO ,Alert Low" "0,1" bitfld.long 0x00 6. " FLTLO ,Fault Low" "0,1" bitfld.long 0x00 5. " ALRTHI ,Alert High" "0,1" newline bitfld.long 0x00 4. " FLTHI ,Fault High" "0,1" group.long 0x24++0x3 line.long 0x00 "TMU0_GAIN,TMU0 Gain Value Register" hexmask.long.word 0x00 0.--9. 1. " VALUE ,Value" group.long 0x28++0x3 line.long 0x00 "TMU0_IMSK,TMU0 Interrupt Mask Register" bitfld.long 0x00 3. " ALRTLO ,Alert Low Mask" "0,1" bitfld.long 0x00 2. " FLTLO ,Fault Low Mask" "0,1" bitfld.long 0x00 1. " ALRTHI ,Alert High Mask" "0,1" newline bitfld.long 0x00 0. " FLTHI ,Fault High Mask" "0,1" group.long 0x2C++0x3 line.long 0x00 "TMU0_OFFSET,TMU0 Offset Register" hexmask.long.word 0x00 0.--14. 1. " VALUE ,Value" group.long 0x34++0x3 line.long 0x00 "TMU0_CNV_BLANK,TMU0 Temperature conversion blank register" bitfld.long 0x00 24.--28. " PERIOD ,Blanking Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x38++0x3 line.long 0x00 "TMU0_REFR_CNTR,TMU0 Temperature Refresh Counter" bitfld.long 0x00 0.--5. " VALUE ,Refresh Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "TRNG0" base ad:0x310D0000 width 18. group.long 0x0++0x3 line.long 0x00 "TRNG0_OUTPUT0,TRNG0 TRNG Output Registers" group.long 0x0++0x3 line.long 0x00 "TRNG0_INPUT0,TRNG0 TRNG Input Registers" group.long 0x4++0x3 line.long 0x00 "TRNG0_OUTPUT1,TRNG0 TRNG Output Registers" group.long 0x4++0x3 line.long 0x00 "TRNG0_INPUT1,TRNG0 TRNG Input Registers" group.long 0x8++0x3 line.long 0x00 "TRNG0_OUTPUT2,TRNG0 TRNG Output Registers" group.long 0xC++0x3 line.long 0x00 "TRNG0_OUTPUT3,TRNG0 TRNG Output Registers" group.long 0x10++0x3 line.long 0x00 "TRNG0_STAT,TRNG0 TRNG Status Register" bitfld.long 0x00 24. " NEEDCLK ,Need Clock" "0,1" hexmask.long.byte 0x00 16.--23. 1. " BLKAVAIL ,Blocks Available" bitfld.long 0x00 8. " TSTRDY ,Test Ready" "0,1" newline bitfld.long 0x00 7. " MBITFAIL ,Monobit Fail" "0,1" bitfld.long 0x00 6. " PKRFAIL ,Poker Fail" "0,1" bitfld.long 0x00 5. " LRUNFAIL ,Long Run Fail" "0,1" newline bitfld.long 0x00 4. " RUNFAIL ,Run Fail" "0,1" bitfld.long 0x00 3. " NOISEFAIL ,Noise Fail" "0,1" bitfld.long 0x00 2. " STUCKOUT ,Stuck Out" "0,1" newline bitfld.long 0x00 1. " SHDNOVR ,Shutdown Overflow" "0,1" bitfld.long 0x00 0. " RDY ,Ready" "0,1" group.long 0x10++0x3 line.long 0x00 "TRNG0_INTACK,TRNG0 TRNG Interrupt Acknowledge Register" bitfld.long 0x00 7. " MBITFAIL ,Monobit Fail Acknowledge" "0,1" hexmask.long.byte 0x00 0.--7. 1. " OPENRDGATE ,Open Read Gate" bitfld.long 0x00 6. " PKRFAIL ,Poker Fail Acknowledge" "0,1" newline bitfld.long 0x00 5. " LRUNFAIL ,Long Run Fail Acknowledge" "0,1" bitfld.long 0x00 4. " RUNFAIL ,Run Fail Acknowledge" "0,1" bitfld.long 0x00 3. " NOISEFAIL ,Noise Fail Acknowledge" "0,1" newline bitfld.long 0x00 2. " STUCKOUT ,Stuck Out Acknowledge" "0,1" bitfld.long 0x00 1. " SHDNOVR ,Shutdown Overflow Acknowledge" "0,1" bitfld.long 0x00 0. " RDY ,Ready Acknowledge" "0,1" group.long 0x14++0x3 line.long 0x00 "TRNG0_CTL,TRNG0 TRNG Control Register" hexmask.long.word 0x00 16.--31. 1. " STARTUPCYC ,Startup Cycles" bitfld.long 0x00 15. " RESEED ,Re-seed" "0,1" bitfld.long 0x00 12. " PPROCEN ,Post Processor Enable" "0,1" newline bitfld.long 0x00 10. " TRNGEN ,Enable TRNG" "0,1" bitfld.long 0x00 8. " TSTMODE ,Test Mode" "0,1" bitfld.long 0x00 7. " MBITFAILMSK ,Monobit Fail Mask" "0,1" newline bitfld.long 0x00 6. " PKRFAILMSK ,Poker Fail Mask" "0,1" bitfld.long 0x00 5. " LRUNFAILMSK ,Long Run Fail Mask" "0,1" bitfld.long 0x00 4. " RUNFAILMSK ,Run Fail Mask" "0,1" newline bitfld.long 0x00 3. " NOISEFAILMSK ,Noise Fail Mask" "0,1" bitfld.long 0x00 2. " STUCKOUTMSK ,Stuck Out Mask" "0,1" bitfld.long 0x00 1. " SHDNOVRMSK ,Shutdown Overflow Mask" "0,1" newline bitfld.long 0x00 0. " RDYMSK ,Ready Mask" "0,1" group.long 0x18++0x3 line.long 0x00 "TRNG0_CFG,TRNG0 TRNG Configuration Register" hexmask.long.word 0x00 16.--31. 1. " MAXREFCYC ,Max Refill Cycles" bitfld.long 0x00 12.--15. " RDTIMEOUT ,Read Timeout" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " SAMPLEDIV ,Sample Div" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--7. 1. " MINREFCYC ,Min Refill Cycles" group.long 0x1C++0x3 line.long 0x00 "TRNG0_ALMCNT,TRNG0 TRNG Alarm Counter Register" bitfld.long 0x00 24.--29. " SHDNCNT ,Shutdown Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " SHDNFATAL ,Shutdown Fatal" "0,1" bitfld.long 0x00 16.--20. " SHDNTHRESH ,Shutdown Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 15. " STALLRUNPKR ,Stall Run Poker" "0,1" hexmask.long.byte 0x00 0.--7. 1. " ALMTHRESH ,Alarm Threshold" group.long 0x20++0x3 line.long 0x00 "TRNG0_FROEN,TRNG0 TRNG FRO Enable Register" hexmask.long.byte 0x00 0.--7. 1. " FROS ,Enable Free-Running Oscillators" group.long 0x24++0x3 line.long 0x00 "TRNG0_FRODETUNE,TRNG0 TRNG FRO De-tune Register" hexmask.long.byte 0x00 0.--7. 1. " FROS ,FRO De-tune Bits" group.long 0x28++0x3 line.long 0x00 "TRNG0_ALMMSK,TRNG0 TRNG Alarm Mask Register" hexmask.long.byte 0x00 0.--7. 1. " FROS ,FRO Alarm Mask" group.long 0x2C++0x3 line.long 0x00 "TRNG0_ALMSTP,TRNG0 TRNG Alarm Stop Register" hexmask.long.byte 0x00 0.--7. 1. " FROS ,FRO Alarm Stop Bits" group.long 0x30++0x3 line.long 0x00 "TRNG0_LFSR_L,TRNG0 TRNG LFSR Access Register" group.long 0x34++0x3 line.long 0x00 "TRNG0_LFSR_M,TRNG0 TRNG LFSR Access Register" group.long 0x38++0x3 line.long 0x00 "TRNG0_LFSR_H,TRNG0 TRNG LFSR Access Register" hexmask.long.tbyte 0x00 0.--16. 1. " VALUE ,LFSR[80:64]" group.long 0x3C++0x3 line.long 0x00 "TRNG0_CNT,TRNG0 Counter Register" hexmask.long.tbyte 0x00 0.--23. 1. " VALUE ,Sample Counter" group.long 0x40++0x3 line.long 0x00 "TRNG0_RUNCNT,TRNG0 TRNG Run Count Registers" bitfld.long 0x00 24.--29. " LENMAX ,Run Length Max" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. " LENCNT ,Run Length Br Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 15. " STATE ,Run State" "0,1" newline hexmask.long.word 0x00 0.--14. 1. " TSTCNT ,Run Test Count" group.long 0x40++0x3 line.long 0x00 "TRNG0_KEY0,TRNG0 Post-Process Key Registers" group.long 0x44++0x3 line.long 0x00 "TRNG0_KEY1,TRNG0 Post-Process Key Registers" group.long 0x44++0x3 line.long 0x00 "TRNG0_RUN1,TRNG0 TRNG Run Test State and Result Registers" hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count Ones" hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count Zeros" group.long 0x48++0x3 line.long 0x00 "TRNG0_RUN2,TRNG0 TRNG Run Test State and Result Registers" hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count Ones" hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count Zeros" group.long 0x48++0x3 line.long 0x00 "TRNG0_KEY2,TRNG0 Post-Process Key Registers" group.long 0x4C++0x3 line.long 0x00 "TRNG0_KEY3,TRNG0 Post-Process Key Registers" group.long 0x4C++0x3 line.long 0x00 "TRNG0_RUN3,TRNG0 TRNG Run Test State and Result Registers" hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count Ones" hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count Zeros" group.long 0x50++0x3 line.long 0x00 "TRNG0_KEY4,TRNG0 Post-Process Key Registers" group.long 0x50++0x3 line.long 0x00 "TRNG0_RUN4,TRNG0 TRNG Run Test State and Result Registers" hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count Ones" hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count Zeros" group.long 0x54++0x3 line.long 0x00 "TRNG0_RUN5,TRNG0 TRNG Run Test State and Result Registers" hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count Ones" hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count Zeros" group.long 0x54++0x3 line.long 0x00 "TRNG0_KEY5,TRNG0 Post-Process Key Registers" group.long 0x58++0x3 line.long 0x00 "TRNG0_RUN6,TRNG0 TRNG Run Test State and Result Registers" hexmask.long.word 0x00 16.--27. 1. " CNTONES ,Count Ones" hexmask.long.word 0x00 0.--11. 1. " CNTZEROS ,Count Zeros" group.long 0x5C++0x3 line.long 0x00 "TRNG0_MONOBITCNT,TRNG0 TRNG Monobit Test Result Register" hexmask.long.tbyte 0x00 0.--16. 1. " VALUE ,Monobit Count" group.long 0x60++0x3 line.long 0x00 "TRNG0_POKER0,TRNG0 TRNG Poker Test Result Registers" hexmask.long.byte 0x00 24.--31. 1. " CNT3 ,Poker Count n + 3" hexmask.long.byte 0x00 16.--23. 1. " CNT2 ,Poker Count n + 2" hexmask.long.byte 0x00 8.--15. 1. " CNT1 ,Poker Count n + 1" newline hexmask.long.byte 0x00 0.--7. 1. " CNT0 ,Poker Count n" group.long 0x60++0x3 line.long 0x00 "TRNG0_V0,TRNG0 TRNG Post-Process 'V' Value Registers" group.long 0x64++0x3 line.long 0x00 "TRNG0_POKER1,TRNG0 TRNG Poker Test Result Registers" hexmask.long.byte 0x00 24.--31. 1. " CNT3 ,Poker Count n + 3" hexmask.long.byte 0x00 16.--23. 1. " CNT2 ,Poker Count n + 2" hexmask.long.byte 0x00 8.--15. 1. " CNT1 ,Poker Count n + 1" newline hexmask.long.byte 0x00 0.--7. 1. " CNT0 ,Poker Count n" group.long 0x64++0x3 line.long 0x00 "TRNG0_V1,TRNG0 TRNG Post-Process 'V' Value Registers" group.long 0x68++0x3 line.long 0x00 "TRNG0_POKER2,TRNG0 TRNG Poker Test Result Registers" hexmask.long.byte 0x00 24.--31. 1. " CNT3 ,Poker Count n + 3" hexmask.long.byte 0x00 16.--23. 1. " CNT2 ,Poker Count n + 2" hexmask.long.byte 0x00 8.--15. 1. " CNT1 ,Poker Count n + 1" newline hexmask.long.byte 0x00 0.--7. 1. " CNT0 ,Poker Count n" group.long 0x6C++0x3 line.long 0x00 "TRNG0_POKER3,TRNG0 TRNG Poker Test Result Registers" hexmask.long.byte 0x00 24.--31. 1. " CNT3 ,Poker Count n + 3" hexmask.long.byte 0x00 16.--23. 1. " CNT2 ,Poker Count n + 2" hexmask.long.byte 0x00 8.--15. 1. " CNT1 ,Poker Count n + 1" newline hexmask.long.byte 0x00 0.--7. 1. " CNT0 ,Poker Count n" group.long 0x70++0x3 line.long 0x00 "TRNG0_TEST,TRNG0 TRNG Test Register" bitfld.long 0x00 31. " IRQ ,Test IRQ" "0,1" hexmask.long.word 0x00 16.--27. 1. " PATTERN ,Test Pattern" bitfld.long 0x00 8.--12. " SEL ,Test Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 6. " PPROC ,Test Post Proc" "0,1" bitfld.long 0x00 5. " RUNPKR ,Test Run Poker" "0,1" bitfld.long 0x00 4. " CONTPKR ,Continue Poker" "0,1" newline bitfld.long 0x00 3. " NOLFSRFB ,No LFSR Feedback" "0,1" bitfld.long 0x00 2. " PATTDET ,Test Pattern Detect" "0,1" bitfld.long 0x00 1. " PATTFRO ,Test Pattern FRO" "0,1" newline bitfld.long 0x00 0. " ENOUT ,Test Enable Out" "0,1" group.long 0x74++0x3 line.long 0x00 "TRNG0_BLKCNT,TRNG0 TRNG Block Count Register" hexmask.long 0x00 4.--31. 1. " VALUE ,Block Count" tree.end tree "TRU (Trigger Routing Unit)" base ad:0x3108A000 width 14. group.long 0x0++0x3 line.long 0x00 "TRU0_SSR0,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x4++0x3 line.long 0x00 "TRU0_SSR1,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x8++0x3 line.long 0x00 "TRU0_SSR2,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xC++0x3 line.long 0x00 "TRU0_SSR3,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x10++0x3 line.long 0x00 "TRU0_SSR4,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x14++0x3 line.long 0x00 "TRU0_SSR5,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x18++0x3 line.long 0x00 "TRU0_SSR6,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1C++0x3 line.long 0x00 "TRU0_SSR7,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x20++0x3 line.long 0x00 "TRU0_SSR8,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x24++0x3 line.long 0x00 "TRU0_SSR9,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x28++0x3 line.long 0x00 "TRU0_SSR10,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2C++0x3 line.long 0x00 "TRU0_SSR11,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x30++0x3 line.long 0x00 "TRU0_SSR12,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x34++0x3 line.long 0x00 "TRU0_SSR13,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x38++0x3 line.long 0x00 "TRU0_SSR14,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x3C++0x3 line.long 0x00 "TRU0_SSR15,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x40++0x3 line.long 0x00 "TRU0_SSR16,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x44++0x3 line.long 0x00 "TRU0_SSR17,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x48++0x3 line.long 0x00 "TRU0_SSR18,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x4C++0x3 line.long 0x00 "TRU0_SSR19,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x50++0x3 line.long 0x00 "TRU0_SSR20,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x54++0x3 line.long 0x00 "TRU0_SSR21,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x58++0x3 line.long 0x00 "TRU0_SSR22,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x5C++0x3 line.long 0x00 "TRU0_SSR23,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x60++0x3 line.long 0x00 "TRU0_SSR24,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x64++0x3 line.long 0x00 "TRU0_SSR25,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x68++0x3 line.long 0x00 "TRU0_SSR26,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x6C++0x3 line.long 0x00 "TRU0_SSR27,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x70++0x3 line.long 0x00 "TRU0_SSR28,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x74++0x3 line.long 0x00 "TRU0_SSR29,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x78++0x3 line.long 0x00 "TRU0_SSR30,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x7C++0x3 line.long 0x00 "TRU0_SSR31,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x80++0x3 line.long 0x00 "TRU0_SSR32,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x84++0x3 line.long 0x00 "TRU0_SSR33,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x88++0x3 line.long 0x00 "TRU0_SSR34,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x8C++0x3 line.long 0x00 "TRU0_SSR35,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x90++0x3 line.long 0x00 "TRU0_SSR36,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x94++0x3 line.long 0x00 "TRU0_SSR37,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x98++0x3 line.long 0x00 "TRU0_SSR38,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x9C++0x3 line.long 0x00 "TRU0_SSR39,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xA0++0x3 line.long 0x00 "TRU0_SSR40,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xA4++0x3 line.long 0x00 "TRU0_SSR41,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xA8++0x3 line.long 0x00 "TRU0_SSR42,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xAC++0x3 line.long 0x00 "TRU0_SSR43,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xB0++0x3 line.long 0x00 "TRU0_SSR44,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xB4++0x3 line.long 0x00 "TRU0_SSR45,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xB8++0x3 line.long 0x00 "TRU0_SSR46,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xBC++0x3 line.long 0x00 "TRU0_SSR47,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xC0++0x3 line.long 0x00 "TRU0_SSR48,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xC4++0x3 line.long 0x00 "TRU0_SSR49,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xC8++0x3 line.long 0x00 "TRU0_SSR50,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xCC++0x3 line.long 0x00 "TRU0_SSR51,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xD0++0x3 line.long 0x00 "TRU0_SSR52,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xD4++0x3 line.long 0x00 "TRU0_SSR53,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xD8++0x3 line.long 0x00 "TRU0_SSR54,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xDC++0x3 line.long 0x00 "TRU0_SSR55,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xE0++0x3 line.long 0x00 "TRU0_SSR56,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xE4++0x3 line.long 0x00 "TRU0_SSR57,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xE8++0x3 line.long 0x00 "TRU0_SSR58,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xEC++0x3 line.long 0x00 "TRU0_SSR59,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xF0++0x3 line.long 0x00 "TRU0_SSR60,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xF4++0x3 line.long 0x00 "TRU0_SSR61,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xF8++0x3 line.long 0x00 "TRU0_SSR62,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0xFC++0x3 line.long 0x00 "TRU0_SSR63,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x100++0x3 line.long 0x00 "TRU0_SSR64,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x104++0x3 line.long 0x00 "TRU0_SSR65,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x108++0x3 line.long 0x00 "TRU0_SSR66,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x10C++0x3 line.long 0x00 "TRU0_SSR67,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x110++0x3 line.long 0x00 "TRU0_SSR68,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x114++0x3 line.long 0x00 "TRU0_SSR69,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x118++0x3 line.long 0x00 "TRU0_SSR70,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x11C++0x3 line.long 0x00 "TRU0_SSR71,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x120++0x3 line.long 0x00 "TRU0_SSR72,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x124++0x3 line.long 0x00 "TRU0_SSR73,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x128++0x3 line.long 0x00 "TRU0_SSR74,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x12C++0x3 line.long 0x00 "TRU0_SSR75,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x130++0x3 line.long 0x00 "TRU0_SSR76,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x134++0x3 line.long 0x00 "TRU0_SSR77,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x138++0x3 line.long 0x00 "TRU0_SSR78,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x13C++0x3 line.long 0x00 "TRU0_SSR79,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x140++0x3 line.long 0x00 "TRU0_SSR80,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x144++0x3 line.long 0x00 "TRU0_SSR81,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x148++0x3 line.long 0x00 "TRU0_SSR82,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x14C++0x3 line.long 0x00 "TRU0_SSR83,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x150++0x3 line.long 0x00 "TRU0_SSR84,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x154++0x3 line.long 0x00 "TRU0_SSR85,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x158++0x3 line.long 0x00 "TRU0_SSR86,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x15C++0x3 line.long 0x00 "TRU0_SSR87,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x160++0x3 line.long 0x00 "TRU0_SSR88,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x164++0x3 line.long 0x00 "TRU0_SSR89,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x168++0x3 line.long 0x00 "TRU0_SSR90,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x16C++0x3 line.long 0x00 "TRU0_SSR91,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x170++0x3 line.long 0x00 "TRU0_SSR92,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x174++0x3 line.long 0x00 "TRU0_SSR93,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x178++0x3 line.long 0x00 "TRU0_SSR94,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x17C++0x3 line.long 0x00 "TRU0_SSR95,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x180++0x3 line.long 0x00 "TRU0_SSR96,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x184++0x3 line.long 0x00 "TRU0_SSR97,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x188++0x3 line.long 0x00 "TRU0_SSR98,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x18C++0x3 line.long 0x00 "TRU0_SSR99,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x190++0x3 line.long 0x00 "TRU0_SSR100,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x194++0x3 line.long 0x00 "TRU0_SSR101,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x198++0x3 line.long 0x00 "TRU0_SSR102,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x19C++0x3 line.long 0x00 "TRU0_SSR103,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1A0++0x3 line.long 0x00 "TRU0_SSR104,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1A4++0x3 line.long 0x00 "TRU0_SSR105,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1A8++0x3 line.long 0x00 "TRU0_SSR106,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1AC++0x3 line.long 0x00 "TRU0_SSR107,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1B0++0x3 line.long 0x00 "TRU0_SSR108,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1B4++0x3 line.long 0x00 "TRU0_SSR109,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1B8++0x3 line.long 0x00 "TRU0_SSR110,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1BC++0x3 line.long 0x00 "TRU0_SSR111,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1C0++0x3 line.long 0x00 "TRU0_SSR112,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1C4++0x3 line.long 0x00 "TRU0_SSR113,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1C8++0x3 line.long 0x00 "TRU0_SSR114,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1CC++0x3 line.long 0x00 "TRU0_SSR115,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1D0++0x3 line.long 0x00 "TRU0_SSR116,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1D4++0x3 line.long 0x00 "TRU0_SSR117,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1D8++0x3 line.long 0x00 "TRU0_SSR118,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1DC++0x3 line.long 0x00 "TRU0_SSR119,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1E0++0x3 line.long 0x00 "TRU0_SSR120,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1E4++0x3 line.long 0x00 "TRU0_SSR121,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1E8++0x3 line.long 0x00 "TRU0_SSR122,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1EC++0x3 line.long 0x00 "TRU0_SSR123,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1F0++0x3 line.long 0x00 "TRU0_SSR124,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1F4++0x3 line.long 0x00 "TRU0_SSR125,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1F8++0x3 line.long 0x00 "TRU0_SSR126,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x1FC++0x3 line.long 0x00 "TRU0_SSR127,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x200++0x3 line.long 0x00 "TRU0_SSR128,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x204++0x3 line.long 0x00 "TRU0_SSR129,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x208++0x3 line.long 0x00 "TRU0_SSR130,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x20C++0x3 line.long 0x00 "TRU0_SSR131,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x210++0x3 line.long 0x00 "TRU0_SSR132,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x214++0x3 line.long 0x00 "TRU0_SSR133,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x218++0x3 line.long 0x00 "TRU0_SSR134,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x21C++0x3 line.long 0x00 "TRU0_SSR135,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x220++0x3 line.long 0x00 "TRU0_SSR136,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x224++0x3 line.long 0x00 "TRU0_SSR137,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x228++0x3 line.long 0x00 "TRU0_SSR138,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x22C++0x3 line.long 0x00 "TRU0_SSR139,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x230++0x3 line.long 0x00 "TRU0_SSR140,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x234++0x3 line.long 0x00 "TRU0_SSR141,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x238++0x3 line.long 0x00 "TRU0_SSR142,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x23C++0x3 line.long 0x00 "TRU0_SSR143,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x240++0x3 line.long 0x00 "TRU0_SSR144,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x244++0x3 line.long 0x00 "TRU0_SSR145,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x248++0x3 line.long 0x00 "TRU0_SSR146,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x24C++0x3 line.long 0x00 "TRU0_SSR147,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x250++0x3 line.long 0x00 "TRU0_SSR148,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x254++0x3 line.long 0x00 "TRU0_SSR149,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x258++0x3 line.long 0x00 "TRU0_SSR150,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x25C++0x3 line.long 0x00 "TRU0_SSR151,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x260++0x3 line.long 0x00 "TRU0_SSR152,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x264++0x3 line.long 0x00 "TRU0_SSR153,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x268++0x3 line.long 0x00 "TRU0_SSR154,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x26C++0x3 line.long 0x00 "TRU0_SSR155,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x270++0x3 line.long 0x00 "TRU0_SSR156,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x274++0x3 line.long 0x00 "TRU0_SSR157,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x278++0x3 line.long 0x00 "TRU0_SSR158,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x27C++0x3 line.long 0x00 "TRU0_SSR159,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x280++0x3 line.long 0x00 "TRU0_SSR160,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x284++0x3 line.long 0x00 "TRU0_SSR161,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x288++0x3 line.long 0x00 "TRU0_SSR162,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x28C++0x3 line.long 0x00 "TRU0_SSR163,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x290++0x3 line.long 0x00 "TRU0_SSR164,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x294++0x3 line.long 0x00 "TRU0_SSR165,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x298++0x3 line.long 0x00 "TRU0_SSR166,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x29C++0x3 line.long 0x00 "TRU0_SSR167,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2A0++0x3 line.long 0x00 "TRU0_SSR168,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2A4++0x3 line.long 0x00 "TRU0_SSR169,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2A8++0x3 line.long 0x00 "TRU0_SSR170,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2AC++0x3 line.long 0x00 "TRU0_SSR171,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2B0++0x3 line.long 0x00 "TRU0_SSR172,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2B4++0x3 line.long 0x00 "TRU0_SSR173,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2B8++0x3 line.long 0x00 "TRU0_SSR174,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2BC++0x3 line.long 0x00 "TRU0_SSR175,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2C0++0x3 line.long 0x00 "TRU0_SSR176,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2C4++0x3 line.long 0x00 "TRU0_SSR177,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2C8++0x3 line.long 0x00 "TRU0_SSR178,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2CC++0x3 line.long 0x00 "TRU0_SSR179,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2D0++0x3 line.long 0x00 "TRU0_SSR180,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2D4++0x3 line.long 0x00 "TRU0_SSR181,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2D8++0x3 line.long 0x00 "TRU0_SSR182,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2DC++0x3 line.long 0x00 "TRU0_SSR183,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2E0++0x3 line.long 0x00 "TRU0_SSR184,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2E4++0x3 line.long 0x00 "TRU0_SSR185,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2E8++0x3 line.long 0x00 "TRU0_SSR186,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x2EC++0x3 line.long 0x00 "TRU0_SSR187,TRU0 Slave Select Register" bitfld.long 0x00 31. " LOCK ,SSRn Lock" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSR ,SSRn Slave Select" group.long 0x7E0++0x3 line.long 0x00 "TRU0_MTR,TRU0 Master Trigger Register" hexmask.long.byte 0x00 24.--31. 1. " MTR3 ,Master Trigger Register 3" hexmask.long.byte 0x00 16.--23. 1. " MTR2 ,Master Trigger Register 2" hexmask.long.byte 0x00 8.--15. 1. " MTR1 ,Master Trigger Register 1" newline hexmask.long.byte 0x00 0.--7. 1. " MTR0 ,Master Trigger Register 0" group.long 0x7E8++0x3 line.long 0x00 "TRU0_ERRADDR,TRU0 Error Address Register" hexmask.long.word 0x00 0.--11. 1. " ADDR ,Error Address" group.long 0x7EC++0x3 line.long 0x00 "TRU0_STAT,TRU0 Status Information Register" bitfld.long 0x00 1. " ADDRERR ,Address Error Status" "0,1" bitfld.long 0x00 0. " LWERR ,Lock Write Error Status" "0,1" group.long 0x7F4++0x3 line.long 0x00 "TRU0_GCTL,TRU0 Global Control Register" bitfld.long 0x00 31. " LOCK ,GCTL Lock Bit" "0,1" bitfld.long 0x00 2. " MTRL ,MTR Lock Bit" "0,1" bitfld.long 0x00 1. " RESET ,Soft Reset" "0,1" newline bitfld.long 0x00 0. " EN ,Non-MMR Enable" "0,1" tree.end tree "TWI (Two-Wire Interface)" tree "TWI0" base ad:0x31001400 width 15. group.word 0x0++0x1 line.word 0x00 "TWI0_CLKDIV,TWI0 SCL Clock Divider Register" hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL Clock High Periods" hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL Clock Low Periods" group.word 0x4++0x1 line.word 0x00 "TWI0_CTL,TWI0 Control Register" bitfld.word 0x00 9. " SCCB ,SCCB Compatibility" "0,1" bitfld.word 0x00 7. " EN ,Enable Module" "0,1" hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK0 Prescale Value" group.word 0x8++0x1 line.word 0x00 "TWI0_SLVCTL,TWI0 Slave Mode Control Register" bitfld.word 0x00 4. " GEN ,General Call Enable" "0,1" bitfld.word 0x00 3. " NAK ,Not Acknowledge" "0,1" bitfld.word 0x00 2. " TDVAL ,Transmit Data Valid for Slave" "0,1" newline bitfld.word 0x00 0. " EN ,Enable Slave Mode" "0,1" group.word 0xC++0x1 line.word 0x00 "TWI0_SLVSTAT,TWI0 Slave Mode Status Register" bitfld.word 0x00 1. " GCALL ,General Call" "0,1" bitfld.word 0x00 0. " DIR ,Transfer Direction for Slave" "0,1" group.word 0x10++0x1 line.word 0x00 "TWI0_SLVADDR,TWI0 Slave Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave Mode Address" group.word 0x14++0x1 line.word 0x00 "TWI0_MSTRCTL,TWI0 Master Mode Control Registers" bitfld.word 0x00 15. " SCLOVR ,Serial Clock Override" "0,1" bitfld.word 0x00 14. " SDAOVR ,Serial Data Override" "0,1" hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data Transfer Count" newline bitfld.word 0x00 5. " RSTART ,Repeat Start" "0,1" bitfld.word 0x00 4. " STOP ,Issue Stop Condition" "0,1" bitfld.word 0x00 3. " FAST ,Fast Mode" "0,1" newline bitfld.word 0x00 2. " DIR ,Transfer Direction for Master" "0,1" bitfld.word 0x00 0. " EN ,Enable Master Mode" "0,1" group.word 0x18++0x1 line.word 0x00 "TWI0_MSTRSTAT,TWI0 Master Mode Status Register" bitfld.word 0x00 8. " BUSBUSY ,Bus Busy" "0,1" bitfld.word 0x00 7. " SCLSEN ,Serial Clock Sense" "0,1" bitfld.word 0x00 6. " SDASEN ,Serial Data Sense" "0,1" newline bitfld.word 0x00 5. " BUFWRERR ,Buffer Write Error" "0,1" bitfld.word 0x00 4. " BUFRDERR ,Buffer Read Error" "0,1" bitfld.word 0x00 3. " DNAK ,Data Not Acknowledged" "0,1" newline bitfld.word 0x00 2. " ANAK ,Address Not Acknowledged" "0,1" bitfld.word 0x00 1. " LOSTARB ,Lost Arbitration" "0,1" bitfld.word 0x00 0. " MPROG ,Master Transfer in Progress" "0,1" group.word 0x1C++0x1 line.word 0x00 "TWI0_MSTRADDR,TWI0 Master Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master Mode Address" group.word 0x20++0x1 line.word 0x00 "TWI0_ISTAT,TWI0 Interrupt Status Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated" "0,1" group.word 0x24++0x1 line.word 0x00 "TWI0_IMSK,TWI0 Interrupt Mask Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt Mask" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt Mask" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service Interrupt Mask" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service Interrupt Mask" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow Interrupt Mask" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated Interrupt Mask" "0,1" group.word 0x28++0x1 line.word 0x00 "TWI0_FIFOCTL,TWI0 FIFO Control Register" bitfld.word 0x00 3. " RXILEN ,Rx Buffer Interrupt Length" "0,1" bitfld.word 0x00 2. " TXILEN ,Tx Buffer Interrupt Length" "0,1" bitfld.word 0x00 1. " RXFLUSH ,Rx Buffer Flush" "0,1" newline bitfld.word 0x00 0. " TXFLUSH ,Tx Buffer Flush" "0,1" group.word 0x2C++0x1 line.word 0x00 "TWI0_FIFOSTAT,TWI0 FIFO Status Register" bitfld.word 0x00 2.--3. " RXSTAT ,Rx FIFO Status" "0,1,2,3" bitfld.word 0x00 0.--1. " TXSTAT ,Tx FIFO Status" "0,1,2,3" group.word 0x80++0x1 line.word 0x00 "TWI0_TXDATA8,TWI0 Tx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value" group.word 0x84++0x1 line.word 0x00 "TWI0_TXDATA16,TWI0 Tx Data Double-Byte Register" group.word 0x88++0x1 line.word 0x00 "TWI0_RXDATA8,TWI0 Rx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Rx Data 8-Bit Value" group.word 0x8C++0x1 line.word 0x00 "TWI0_RXDATA16,TWI0 Rx Data Double-Byte Register" tree.end tree "TWI1" base ad:0x31001500 width 15. group.word 0x0++0x1 line.word 0x00 "TWI1_CLKDIV,TWI1 SCL Clock Divider Register" hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL Clock High Periods" hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL Clock Low Periods" group.word 0x4++0x1 line.word 0x00 "TWI1_CTL,TWI1 Control Register" bitfld.word 0x00 9. " SCCB ,SCCB Compatibility" "0,1" bitfld.word 0x00 7. " EN ,Enable Module" "0,1" hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK0 Prescale Value" group.word 0x8++0x1 line.word 0x00 "TWI1_SLVCTL,TWI1 Slave Mode Control Register" bitfld.word 0x00 4. " GEN ,General Call Enable" "0,1" bitfld.word 0x00 3. " NAK ,Not Acknowledge" "0,1" bitfld.word 0x00 2. " TDVAL ,Transmit Data Valid for Slave" "0,1" newline bitfld.word 0x00 0. " EN ,Enable Slave Mode" "0,1" group.word 0xC++0x1 line.word 0x00 "TWI1_SLVSTAT,TWI1 Slave Mode Status Register" bitfld.word 0x00 1. " GCALL ,General Call" "0,1" bitfld.word 0x00 0. " DIR ,Transfer Direction for Slave" "0,1" group.word 0x10++0x1 line.word 0x00 "TWI1_SLVADDR,TWI1 Slave Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave Mode Address" group.word 0x14++0x1 line.word 0x00 "TWI1_MSTRCTL,TWI1 Master Mode Control Registers" bitfld.word 0x00 15. " SCLOVR ,Serial Clock Override" "0,1" bitfld.word 0x00 14. " SDAOVR ,Serial Data Override" "0,1" hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data Transfer Count" newline bitfld.word 0x00 5. " RSTART ,Repeat Start" "0,1" bitfld.word 0x00 4. " STOP ,Issue Stop Condition" "0,1" bitfld.word 0x00 3. " FAST ,Fast Mode" "0,1" newline bitfld.word 0x00 2. " DIR ,Transfer Direction for Master" "0,1" bitfld.word 0x00 0. " EN ,Enable Master Mode" "0,1" group.word 0x18++0x1 line.word 0x00 "TWI1_MSTRSTAT,TWI1 Master Mode Status Register" bitfld.word 0x00 8. " BUSBUSY ,Bus Busy" "0,1" bitfld.word 0x00 7. " SCLSEN ,Serial Clock Sense" "0,1" bitfld.word 0x00 6. " SDASEN ,Serial Data Sense" "0,1" newline bitfld.word 0x00 5. " BUFWRERR ,Buffer Write Error" "0,1" bitfld.word 0x00 4. " BUFRDERR ,Buffer Read Error" "0,1" bitfld.word 0x00 3. " DNAK ,Data Not Acknowledged" "0,1" newline bitfld.word 0x00 2. " ANAK ,Address Not Acknowledged" "0,1" bitfld.word 0x00 1. " LOSTARB ,Lost Arbitration" "0,1" bitfld.word 0x00 0. " MPROG ,Master Transfer in Progress" "0,1" group.word 0x1C++0x1 line.word 0x00 "TWI1_MSTRADDR,TWI1 Master Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master Mode Address" group.word 0x20++0x1 line.word 0x00 "TWI1_ISTAT,TWI1 Interrupt Status Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated" "0,1" group.word 0x24++0x1 line.word 0x00 "TWI1_IMSK,TWI1 Interrupt Mask Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt Mask" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt Mask" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service Interrupt Mask" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service Interrupt Mask" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow Interrupt Mask" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated Interrupt Mask" "0,1" group.word 0x28++0x1 line.word 0x00 "TWI1_FIFOCTL,TWI1 FIFO Control Register" bitfld.word 0x00 3. " RXILEN ,Rx Buffer Interrupt Length" "0,1" bitfld.word 0x00 2. " TXILEN ,Tx Buffer Interrupt Length" "0,1" bitfld.word 0x00 1. " RXFLUSH ,Rx Buffer Flush" "0,1" newline bitfld.word 0x00 0. " TXFLUSH ,Tx Buffer Flush" "0,1" group.word 0x2C++0x1 line.word 0x00 "TWI1_FIFOSTAT,TWI1 FIFO Status Register" bitfld.word 0x00 2.--3. " RXSTAT ,Rx FIFO Status" "0,1,2,3" bitfld.word 0x00 0.--1. " TXSTAT ,Tx FIFO Status" "0,1,2,3" group.word 0x80++0x1 line.word 0x00 "TWI1_TXDATA8,TWI1 Tx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value" group.word 0x84++0x1 line.word 0x00 "TWI1_TXDATA16,TWI1 Tx Data Double-Byte Register" group.word 0x88++0x1 line.word 0x00 "TWI1_RXDATA8,TWI1 Rx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Rx Data 8-Bit Value" group.word 0x8C++0x1 line.word 0x00 "TWI1_RXDATA16,TWI1 Rx Data Double-Byte Register" tree.end tree "TWI2" base ad:0x31001600 width 15. group.word 0x0++0x1 line.word 0x00 "TWI2_CLKDIV,TWI2 SCL Clock Divider Register" hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL Clock High Periods" hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL Clock Low Periods" group.word 0x4++0x1 line.word 0x00 "TWI2_CTL,TWI2 Control Register" bitfld.word 0x00 9. " SCCB ,SCCB Compatibility" "0,1" bitfld.word 0x00 7. " EN ,Enable Module" "0,1" hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK0 Prescale Value" group.word 0x8++0x1 line.word 0x00 "TWI2_SLVCTL,TWI2 Slave Mode Control Register" bitfld.word 0x00 4. " GEN ,General Call Enable" "0,1" bitfld.word 0x00 3. " NAK ,Not Acknowledge" "0,1" bitfld.word 0x00 2. " TDVAL ,Transmit Data Valid for Slave" "0,1" newline bitfld.word 0x00 0. " EN ,Enable Slave Mode" "0,1" group.word 0xC++0x1 line.word 0x00 "TWI2_SLVSTAT,TWI2 Slave Mode Status Register" bitfld.word 0x00 1. " GCALL ,General Call" "0,1" bitfld.word 0x00 0. " DIR ,Transfer Direction for Slave" "0,1" group.word 0x10++0x1 line.word 0x00 "TWI2_SLVADDR,TWI2 Slave Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave Mode Address" group.word 0x14++0x1 line.word 0x00 "TWI2_MSTRCTL,TWI2 Master Mode Control Registers" bitfld.word 0x00 15. " SCLOVR ,Serial Clock Override" "0,1" bitfld.word 0x00 14. " SDAOVR ,Serial Data Override" "0,1" hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data Transfer Count" newline bitfld.word 0x00 5. " RSTART ,Repeat Start" "0,1" bitfld.word 0x00 4. " STOP ,Issue Stop Condition" "0,1" bitfld.word 0x00 3. " FAST ,Fast Mode" "0,1" newline bitfld.word 0x00 2. " DIR ,Transfer Direction for Master" "0,1" bitfld.word 0x00 0. " EN ,Enable Master Mode" "0,1" group.word 0x18++0x1 line.word 0x00 "TWI2_MSTRSTAT,TWI2 Master Mode Status Register" bitfld.word 0x00 8. " BUSBUSY ,Bus Busy" "0,1" bitfld.word 0x00 7. " SCLSEN ,Serial Clock Sense" "0,1" bitfld.word 0x00 6. " SDASEN ,Serial Data Sense" "0,1" newline bitfld.word 0x00 5. " BUFWRERR ,Buffer Write Error" "0,1" bitfld.word 0x00 4. " BUFRDERR ,Buffer Read Error" "0,1" bitfld.word 0x00 3. " DNAK ,Data Not Acknowledged" "0,1" newline bitfld.word 0x00 2. " ANAK ,Address Not Acknowledged" "0,1" bitfld.word 0x00 1. " LOSTARB ,Lost Arbitration" "0,1" bitfld.word 0x00 0. " MPROG ,Master Transfer in Progress" "0,1" group.word 0x1C++0x1 line.word 0x00 "TWI2_MSTRADDR,TWI2 Master Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master Mode Address" group.word 0x20++0x1 line.word 0x00 "TWI2_ISTAT,TWI2 Interrupt Status Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated" "0,1" group.word 0x24++0x1 line.word 0x00 "TWI2_IMSK,TWI2 Interrupt Mask Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt Mask" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt Mask" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service Interrupt Mask" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service Interrupt Mask" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow Interrupt Mask" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated Interrupt Mask" "0,1" group.word 0x28++0x1 line.word 0x00 "TWI2_FIFOCTL,TWI2 FIFO Control Register" bitfld.word 0x00 3. " RXILEN ,Rx Buffer Interrupt Length" "0,1" bitfld.word 0x00 2. " TXILEN ,Tx Buffer Interrupt Length" "0,1" bitfld.word 0x00 1. " RXFLUSH ,Rx Buffer Flush" "0,1" newline bitfld.word 0x00 0. " TXFLUSH ,Tx Buffer Flush" "0,1" group.word 0x2C++0x1 line.word 0x00 "TWI2_FIFOSTAT,TWI2 FIFO Status Register" bitfld.word 0x00 2.--3. " RXSTAT ,Rx FIFO Status" "0,1,2,3" bitfld.word 0x00 0.--1. " TXSTAT ,Tx FIFO Status" "0,1,2,3" group.word 0x80++0x1 line.word 0x00 "TWI2_TXDATA8,TWI2 Tx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value" group.word 0x84++0x1 line.word 0x00 "TWI2_TXDATA16,TWI2 Tx Data Double-Byte Register" group.word 0x88++0x1 line.word 0x00 "TWI2_RXDATA8,TWI2 Rx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Rx Data 8-Bit Value" group.word 0x8C++0x1 line.word 0x00 "TWI2_RXDATA16,TWI2 Rx Data Double-Byte Register" tree.end tree "TWI3" base ad:0x31001000 width 15. group.word 0x0++0x1 line.word 0x00 "TWI3_CLKDIV,TWI3 SCL Clock Divider Register" hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL Clock High Periods" hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL Clock Low Periods" group.word 0x4++0x1 line.word 0x00 "TWI3_CTL,TWI3 Control Register" bitfld.word 0x00 9. " SCCB ,SCCB Compatibility" "0,1" bitfld.word 0x00 7. " EN ,Enable Module" "0,1" hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK0 Prescale Value" group.word 0x8++0x1 line.word 0x00 "TWI3_SLVCTL,TWI3 Slave Mode Control Register" bitfld.word 0x00 4. " GEN ,General Call Enable" "0,1" bitfld.word 0x00 3. " NAK ,Not Acknowledge" "0,1" bitfld.word 0x00 2. " TDVAL ,Transmit Data Valid for Slave" "0,1" newline bitfld.word 0x00 0. " EN ,Enable Slave Mode" "0,1" group.word 0xC++0x1 line.word 0x00 "TWI3_SLVSTAT,TWI3 Slave Mode Status Register" bitfld.word 0x00 1. " GCALL ,General Call" "0,1" bitfld.word 0x00 0. " DIR ,Transfer Direction for Slave" "0,1" group.word 0x10++0x1 line.word 0x00 "TWI3_SLVADDR,TWI3 Slave Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave Mode Address" group.word 0x14++0x1 line.word 0x00 "TWI3_MSTRCTL,TWI3 Master Mode Control Registers" bitfld.word 0x00 15. " SCLOVR ,Serial Clock Override" "0,1" bitfld.word 0x00 14. " SDAOVR ,Serial Data Override" "0,1" hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data Transfer Count" newline bitfld.word 0x00 5. " RSTART ,Repeat Start" "0,1" bitfld.word 0x00 4. " STOP ,Issue Stop Condition" "0,1" bitfld.word 0x00 3. " FAST ,Fast Mode" "0,1" newline bitfld.word 0x00 2. " DIR ,Transfer Direction for Master" "0,1" bitfld.word 0x00 0. " EN ,Enable Master Mode" "0,1" group.word 0x18++0x1 line.word 0x00 "TWI3_MSTRSTAT,TWI3 Master Mode Status Register" bitfld.word 0x00 8. " BUSBUSY ,Bus Busy" "0,1" bitfld.word 0x00 7. " SCLSEN ,Serial Clock Sense" "0,1" bitfld.word 0x00 6. " SDASEN ,Serial Data Sense" "0,1" newline bitfld.word 0x00 5. " BUFWRERR ,Buffer Write Error" "0,1" bitfld.word 0x00 4. " BUFRDERR ,Buffer Read Error" "0,1" bitfld.word 0x00 3. " DNAK ,Data Not Acknowledged" "0,1" newline bitfld.word 0x00 2. " ANAK ,Address Not Acknowledged" "0,1" bitfld.word 0x00 1. " LOSTARB ,Lost Arbitration" "0,1" bitfld.word 0x00 0. " MPROG ,Master Transfer in Progress" "0,1" group.word 0x1C++0x1 line.word 0x00 "TWI3_MSTRADDR,TWI3 Master Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master Mode Address" group.word 0x20++0x1 line.word 0x00 "TWI3_ISTAT,TWI3 Interrupt Status Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated" "0,1" group.word 0x24++0x1 line.word 0x00 "TWI3_IMSK,TWI3 Interrupt Mask Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt Mask" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt Mask" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service Interrupt Mask" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service Interrupt Mask" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow Interrupt Mask" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated Interrupt Mask" "0,1" group.word 0x28++0x1 line.word 0x00 "TWI3_FIFOCTL,TWI3 FIFO Control Register" bitfld.word 0x00 3. " RXILEN ,Rx Buffer Interrupt Length" "0,1" bitfld.word 0x00 2. " TXILEN ,Tx Buffer Interrupt Length" "0,1" bitfld.word 0x00 1. " RXFLUSH ,Rx Buffer Flush" "0,1" newline bitfld.word 0x00 0. " TXFLUSH ,Tx Buffer Flush" "0,1" group.word 0x2C++0x1 line.word 0x00 "TWI3_FIFOSTAT,TWI3 FIFO Status Register" bitfld.word 0x00 2.--3. " RXSTAT ,Rx FIFO Status" "0,1,2,3" bitfld.word 0x00 0.--1. " TXSTAT ,Tx FIFO Status" "0,1,2,3" group.word 0x80++0x1 line.word 0x00 "TWI3_TXDATA8,TWI3 Tx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value" group.word 0x84++0x1 line.word 0x00 "TWI3_TXDATA16,TWI3 Tx Data Double-Byte Register" group.word 0x88++0x1 line.word 0x00 "TWI3_RXDATA8,TWI3 Rx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Rx Data 8-Bit Value" group.word 0x8C++0x1 line.word 0x00 "TWI3_RXDATA16,TWI3 Rx Data Double-Byte Register" tree.end tree "TWI4" base ad:0x31001100 width 15. group.word 0x0++0x1 line.word 0x00 "TWI4_CLKDIV,TWI4 SCL Clock Divider Register" hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL Clock High Periods" hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL Clock Low Periods" group.word 0x4++0x1 line.word 0x00 "TWI4_CTL,TWI4 Control Register" bitfld.word 0x00 9. " SCCB ,SCCB Compatibility" "0,1" bitfld.word 0x00 7. " EN ,Enable Module" "0,1" hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK0 Prescale Value" group.word 0x8++0x1 line.word 0x00 "TWI4_SLVCTL,TWI4 Slave Mode Control Register" bitfld.word 0x00 4. " GEN ,General Call Enable" "0,1" bitfld.word 0x00 3. " NAK ,Not Acknowledge" "0,1" bitfld.word 0x00 2. " TDVAL ,Transmit Data Valid for Slave" "0,1" newline bitfld.word 0x00 0. " EN ,Enable Slave Mode" "0,1" group.word 0xC++0x1 line.word 0x00 "TWI4_SLVSTAT,TWI4 Slave Mode Status Register" bitfld.word 0x00 1. " GCALL ,General Call" "0,1" bitfld.word 0x00 0. " DIR ,Transfer Direction for Slave" "0,1" group.word 0x10++0x1 line.word 0x00 "TWI4_SLVADDR,TWI4 Slave Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave Mode Address" group.word 0x14++0x1 line.word 0x00 "TWI4_MSTRCTL,TWI4 Master Mode Control Registers" bitfld.word 0x00 15. " SCLOVR ,Serial Clock Override" "0,1" bitfld.word 0x00 14. " SDAOVR ,Serial Data Override" "0,1" hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data Transfer Count" newline bitfld.word 0x00 5. " RSTART ,Repeat Start" "0,1" bitfld.word 0x00 4. " STOP ,Issue Stop Condition" "0,1" bitfld.word 0x00 3. " FAST ,Fast Mode" "0,1" newline bitfld.word 0x00 2. " DIR ,Transfer Direction for Master" "0,1" bitfld.word 0x00 0. " EN ,Enable Master Mode" "0,1" group.word 0x18++0x1 line.word 0x00 "TWI4_MSTRSTAT,TWI4 Master Mode Status Register" bitfld.word 0x00 8. " BUSBUSY ,Bus Busy" "0,1" bitfld.word 0x00 7. " SCLSEN ,Serial Clock Sense" "0,1" bitfld.word 0x00 6. " SDASEN ,Serial Data Sense" "0,1" newline bitfld.word 0x00 5. " BUFWRERR ,Buffer Write Error" "0,1" bitfld.word 0x00 4. " BUFRDERR ,Buffer Read Error" "0,1" bitfld.word 0x00 3. " DNAK ,Data Not Acknowledged" "0,1" newline bitfld.word 0x00 2. " ANAK ,Address Not Acknowledged" "0,1" bitfld.word 0x00 1. " LOSTARB ,Lost Arbitration" "0,1" bitfld.word 0x00 0. " MPROG ,Master Transfer in Progress" "0,1" group.word 0x1C++0x1 line.word 0x00 "TWI4_MSTRADDR,TWI4 Master Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master Mode Address" group.word 0x20++0x1 line.word 0x00 "TWI4_ISTAT,TWI4 Interrupt Status Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated" "0,1" group.word 0x24++0x1 line.word 0x00 "TWI4_IMSK,TWI4 Interrupt Mask Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt Mask" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt Mask" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service Interrupt Mask" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service Interrupt Mask" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow Interrupt Mask" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated Interrupt Mask" "0,1" group.word 0x28++0x1 line.word 0x00 "TWI4_FIFOCTL,TWI4 FIFO Control Register" bitfld.word 0x00 3. " RXILEN ,Rx Buffer Interrupt Length" "0,1" bitfld.word 0x00 2. " TXILEN ,Tx Buffer Interrupt Length" "0,1" bitfld.word 0x00 1. " RXFLUSH ,Rx Buffer Flush" "0,1" newline bitfld.word 0x00 0. " TXFLUSH ,Tx Buffer Flush" "0,1" group.word 0x2C++0x1 line.word 0x00 "TWI4_FIFOSTAT,TWI4 FIFO Status Register" bitfld.word 0x00 2.--3. " RXSTAT ,Rx FIFO Status" "0,1,2,3" bitfld.word 0x00 0.--1. " TXSTAT ,Tx FIFO Status" "0,1,2,3" group.word 0x80++0x1 line.word 0x00 "TWI4_TXDATA8,TWI4 Tx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value" group.word 0x84++0x1 line.word 0x00 "TWI4_TXDATA16,TWI4 Tx Data Double-Byte Register" group.word 0x88++0x1 line.word 0x00 "TWI4_RXDATA8,TWI4 Rx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Rx Data 8-Bit Value" group.word 0x8C++0x1 line.word 0x00 "TWI4_RXDATA16,TWI4 Rx Data Double-Byte Register" tree.end tree "TWI5" base ad:0x31001200 width 15. group.word 0x0++0x1 line.word 0x00 "TWI5_CLKDIV,TWI5 SCL Clock Divider Register" hexmask.word.byte 0x00 8.--15. 1. " CLKHI ,SCL Clock High Periods" hexmask.word.byte 0x00 0.--7. 1. " CLKLO ,SCL Clock Low Periods" group.word 0x4++0x1 line.word 0x00 "TWI5_CTL,TWI5 Control Register" bitfld.word 0x00 9. " SCCB ,SCCB Compatibility" "0,1" bitfld.word 0x00 7. " EN ,Enable Module" "0,1" hexmask.word.byte 0x00 0.--6. 1. " PRESCALE ,SCLK0 Prescale Value" group.word 0x8++0x1 line.word 0x00 "TWI5_SLVCTL,TWI5 Slave Mode Control Register" bitfld.word 0x00 4. " GEN ,General Call Enable" "0,1" bitfld.word 0x00 3. " NAK ,Not Acknowledge" "0,1" bitfld.word 0x00 2. " TDVAL ,Transmit Data Valid for Slave" "0,1" newline bitfld.word 0x00 0. " EN ,Enable Slave Mode" "0,1" group.word 0xC++0x1 line.word 0x00 "TWI5_SLVSTAT,TWI5 Slave Mode Status Register" bitfld.word 0x00 1. " GCALL ,General Call" "0,1" bitfld.word 0x00 0. " DIR ,Transfer Direction for Slave" "0,1" group.word 0x10++0x1 line.word 0x00 "TWI5_SLVADDR,TWI5 Slave Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Slave Mode Address" group.word 0x14++0x1 line.word 0x00 "TWI5_MSTRCTL,TWI5 Master Mode Control Registers" bitfld.word 0x00 15. " SCLOVR ,Serial Clock Override" "0,1" bitfld.word 0x00 14. " SDAOVR ,Serial Data Override" "0,1" hexmask.word.byte 0x00 6.--13. 1. " DCNT ,Data Transfer Count" newline bitfld.word 0x00 5. " RSTART ,Repeat Start" "0,1" bitfld.word 0x00 4. " STOP ,Issue Stop Condition" "0,1" bitfld.word 0x00 3. " FAST ,Fast Mode" "0,1" newline bitfld.word 0x00 2. " DIR ,Transfer Direction for Master" "0,1" bitfld.word 0x00 0. " EN ,Enable Master Mode" "0,1" group.word 0x18++0x1 line.word 0x00 "TWI5_MSTRSTAT,TWI5 Master Mode Status Register" bitfld.word 0x00 8. " BUSBUSY ,Bus Busy" "0,1" bitfld.word 0x00 7. " SCLSEN ,Serial Clock Sense" "0,1" bitfld.word 0x00 6. " SDASEN ,Serial Data Sense" "0,1" newline bitfld.word 0x00 5. " BUFWRERR ,Buffer Write Error" "0,1" bitfld.word 0x00 4. " BUFRDERR ,Buffer Read Error" "0,1" bitfld.word 0x00 3. " DNAK ,Data Not Acknowledged" "0,1" newline bitfld.word 0x00 2. " ANAK ,Address Not Acknowledged" "0,1" bitfld.word 0x00 1. " LOSTARB ,Lost Arbitration" "0,1" bitfld.word 0x00 0. " MPROG ,Master Transfer in Progress" "0,1" group.word 0x1C++0x1 line.word 0x00 "TWI5_MSTRADDR,TWI5 Master Mode Address Register" hexmask.word.byte 0x00 0.--6. 1. " ADDR ,Master Mode Address" group.word 0x20++0x1 line.word 0x00 "TWI5_ISTAT,TWI5 Interrupt Status Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated" "0,1" group.word 0x24++0x1 line.word 0x00 "TWI5_IMSK,TWI5 Interrupt Mask Register" bitfld.word 0x00 15. " SCLI ,Serial Clock Interrupt Mask" "0,1" bitfld.word 0x00 14. " SDAI ,Serial Data Interrupt Mask" "0,1" bitfld.word 0x00 7. " RXSERV ,Rx FIFO Service Interrupt Mask" "0,1" newline bitfld.word 0x00 6. " TXSERV ,Tx FIFO Service Interrupt Mask" "0,1" bitfld.word 0x00 5. " MERR ,Master Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 4. " MCOMP ,Master Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 3. " SOVF ,Slave Overflow Interrupt Mask" "0,1" bitfld.word 0x00 2. " SERR ,Slave Transfer Error Interrupt Mask" "0,1" bitfld.word 0x00 1. " SCOMP ,Slave Transfer Complete Interrupt Mask" "0,1" newline bitfld.word 0x00 0. " SINIT ,Slave Transfer Initiated Interrupt Mask" "0,1" group.word 0x28++0x1 line.word 0x00 "TWI5_FIFOCTL,TWI5 FIFO Control Register" bitfld.word 0x00 3. " RXILEN ,Rx Buffer Interrupt Length" "0,1" bitfld.word 0x00 2. " TXILEN ,Tx Buffer Interrupt Length" "0,1" bitfld.word 0x00 1. " RXFLUSH ,Rx Buffer Flush" "0,1" newline bitfld.word 0x00 0. " TXFLUSH ,Tx Buffer Flush" "0,1" group.word 0x2C++0x1 line.word 0x00 "TWI5_FIFOSTAT,TWI5 FIFO Status Register" bitfld.word 0x00 2.--3. " RXSTAT ,Rx FIFO Status" "0,1,2,3" bitfld.word 0x00 0.--1. " TXSTAT ,Tx FIFO Status" "0,1,2,3" group.word 0x80++0x1 line.word 0x00 "TWI5_TXDATA8,TWI5 Tx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Tx Data 8-Bit Value" group.word 0x84++0x1 line.word 0x00 "TWI5_TXDATA16,TWI5 Tx Data Double-Byte Register" group.word 0x88++0x1 line.word 0x00 "TWI5_RXDATA8,TWI5 Rx Data Single-Byte Register" hexmask.word.byte 0x00 0.--7. 1. " VALUE ,Rx Data 8-Bit Value" group.word 0x8C++0x1 line.word 0x00 "TWI5_RXDATA16,TWI5 Rx Data Double-Byte Register" tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" tree "UART0" base ad:0x31003004 width 16. group.long 0x0++0x3 line.long 0x00 "UART0_CTL,UART0 Control Register" bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1" bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "0,1" bitfld.long 0x00 28. " ACTS ,Automatic CTS" "0,1" newline bitfld.long 0x00 27. " ARTS ,Automatic RTS" "0,1" bitfld.long 0x00 26. " XOFF ,Transmitter off" "0,1" bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "0,1" newline bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "0,1" bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "0,1" bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "0,1" newline bitfld.long 0x00 19. " SB ,Set Break" "0,1" bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "0,1" bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "0,1" newline bitfld.long 0x00 16. " STP ,Sticky Parity" "0,1" bitfld.long 0x00 15. " EPS ,Even Parity Select" "0,1" bitfld.long 0x00 14. " PEN ,Parity Enable" "0,1" newline bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1" bitfld.long 0x00 12. " STB ,Stop Bits" "0,1" bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "0,1,2,3" newline bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "0,1,2,3" bitfld.long 0x00 1. " LOOP_EN ,Loopback Enable" "0,1" bitfld.long 0x00 0. " EN ,Enable UART" "0,1" group.long 0x4++0x3 line.long 0x00 "UART0_STAT,UART0 Status Register" bitfld.long 0x00 17. " RFCS ,Receive FIFO Count Status" "0,1" bitfld.long 0x00 16. " CTS ,Clear to Send" "0,1" bitfld.long 0x00 12. " SCTS ,Sticky CTS" "0,1" newline bitfld.long 0x00 11. " RO ,Reception On-going" "0,1" bitfld.long 0x00 10. " ADDR ,Address Bit Status" "0,1" bitfld.long 0x00 9. " ASTKY ,Address Sticky" "0,1" newline bitfld.long 0x00 8. " TFI ,Transmission Finished Indicator" "0,1" bitfld.long 0x00 7. " TEMT ,TSR and THR Empty" "0,1" bitfld.long 0x00 5. " THRE ,Transmit Hold Register Empty" "0,1" newline bitfld.long 0x00 4. " BI ,Break Indicator" "0,1" bitfld.long 0x00 3. " FE ,Framing Error" "0,1" bitfld.long 0x00 2. " PE ,Parity Error" "0,1" newline bitfld.long 0x00 1. " OE ,Overrun Error" "0,1" bitfld.long 0x00 0. " DR ,Data Ready" "0,1" group.long 0x8++0x3 line.long 0x00 "UART0_SCR,UART0 Scratch Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Stored 8-bit Data" group.long 0xC++0x3 line.long 0x00 "UART0_CLK,UART0 Clock Rate Register" bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "0,1" hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor" group.long 0x10++0x3 line.long 0x00 "UART0_IMSK,UART0 Interrupt Mask Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Status" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Status" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "0,1" group.long 0x14++0x3 line.long 0x00 "UART0_IMSK_SET,UART0 Interrupt Mask Set Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Set" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Set" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Set" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Set" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Set" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Set" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Set" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Set" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Set" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Set" "0,1" group.long 0x18++0x3 line.long 0x00 "UART0_IMSK_CLR,UART0 Interrupt Mask Clear Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Clear" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Clear" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Clear" "0,1" group.long 0x1C++0x3 line.long 0x00 "UART0_RBR,UART0 Receive Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data" group.long 0x20++0x3 line.long 0x00 "UART0_THR,UART0 Transmit Hold Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data" group.long 0x24++0x3 line.long 0x00 "UART0_TAIP,UART0 Transmit Address/Insert Pulse Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data" group.long 0x28++0x3 line.long 0x00 "UART0_TSR,UART0 Transmit Shift Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR" group.long 0x2C++0x3 line.long 0x00 "UART0_RSR,UART0 Receive Shift Register" hexmask.long.word 0x00 0.--9. 1. " VALUE ,Contents of RSR" group.long 0x30++0x3 line.long 0x00 "UART0_TXCNT,UART0 Transmit Counter Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value" group.long 0x34++0x3 line.long 0x00 "UART0_RXCNT,UART0 Receive Counter Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value" tree.end tree "UART1" base ad:0x31003404 width 16. group.long 0x0++0x3 line.long 0x00 "UART1_CTL,UART1 Control Register" bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1" bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "0,1" bitfld.long 0x00 28. " ACTS ,Automatic CTS" "0,1" newline bitfld.long 0x00 27. " ARTS ,Automatic RTS" "0,1" bitfld.long 0x00 26. " XOFF ,Transmitter off" "0,1" bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "0,1" newline bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "0,1" bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "0,1" bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "0,1" newline bitfld.long 0x00 19. " SB ,Set Break" "0,1" bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "0,1" bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "0,1" newline bitfld.long 0x00 16. " STP ,Sticky Parity" "0,1" bitfld.long 0x00 15. " EPS ,Even Parity Select" "0,1" bitfld.long 0x00 14. " PEN ,Parity Enable" "0,1" newline bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1" bitfld.long 0x00 12. " STB ,Stop Bits" "0,1" bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "0,1,2,3" newline bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "0,1,2,3" bitfld.long 0x00 1. " LOOP_EN ,Loopback Enable" "0,1" bitfld.long 0x00 0. " EN ,Enable UART" "0,1" group.long 0x4++0x3 line.long 0x00 "UART1_STAT,UART1 Status Register" bitfld.long 0x00 17. " RFCS ,Receive FIFO Count Status" "0,1" bitfld.long 0x00 16. " CTS ,Clear to Send" "0,1" bitfld.long 0x00 12. " SCTS ,Sticky CTS" "0,1" newline bitfld.long 0x00 11. " RO ,Reception On-going" "0,1" bitfld.long 0x00 10. " ADDR ,Address Bit Status" "0,1" bitfld.long 0x00 9. " ASTKY ,Address Sticky" "0,1" newline bitfld.long 0x00 8. " TFI ,Transmission Finished Indicator" "0,1" bitfld.long 0x00 7. " TEMT ,TSR and THR Empty" "0,1" bitfld.long 0x00 5. " THRE ,Transmit Hold Register Empty" "0,1" newline bitfld.long 0x00 4. " BI ,Break Indicator" "0,1" bitfld.long 0x00 3. " FE ,Framing Error" "0,1" bitfld.long 0x00 2. " PE ,Parity Error" "0,1" newline bitfld.long 0x00 1. " OE ,Overrun Error" "0,1" bitfld.long 0x00 0. " DR ,Data Ready" "0,1" group.long 0x8++0x3 line.long 0x00 "UART1_SCR,UART1 Scratch Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Stored 8-bit Data" group.long 0xC++0x3 line.long 0x00 "UART1_CLK,UART1 Clock Rate Register" bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "0,1" hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor" group.long 0x10++0x3 line.long 0x00 "UART1_IMSK,UART1 Interrupt Mask Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Status" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Status" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "0,1" group.long 0x14++0x3 line.long 0x00 "UART1_IMSK_SET,UART1 Interrupt Mask Set Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Set" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Set" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Set" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Set" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Set" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Set" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Set" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Set" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Set" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Set" "0,1" group.long 0x18++0x3 line.long 0x00 "UART1_IMSK_CLR,UART1 Interrupt Mask Clear Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Clear" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Clear" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Clear" "0,1" group.long 0x1C++0x3 line.long 0x00 "UART1_RBR,UART1 Receive Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data" group.long 0x20++0x3 line.long 0x00 "UART1_THR,UART1 Transmit Hold Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data" group.long 0x24++0x3 line.long 0x00 "UART1_TAIP,UART1 Transmit Address/Insert Pulse Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data" group.long 0x28++0x3 line.long 0x00 "UART1_TSR,UART1 Transmit Shift Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR" group.long 0x2C++0x3 line.long 0x00 "UART1_RSR,UART1 Receive Shift Register" hexmask.long.word 0x00 0.--9. 1. " VALUE ,Contents of RSR" group.long 0x30++0x3 line.long 0x00 "UART1_TXCNT,UART1 Transmit Counter Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value" group.long 0x34++0x3 line.long 0x00 "UART1_RXCNT,UART1 Receive Counter Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value" tree.end tree "UART2" base ad:0x31003804 width 16. group.long 0x0++0x3 line.long 0x00 "UART2_CTL,UART2 Control Register" bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1" bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "0,1" bitfld.long 0x00 28. " ACTS ,Automatic CTS" "0,1" newline bitfld.long 0x00 27. " ARTS ,Automatic RTS" "0,1" bitfld.long 0x00 26. " XOFF ,Transmitter off" "0,1" bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "0,1" newline bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "0,1" bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "0,1" bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "0,1" newline bitfld.long 0x00 19. " SB ,Set Break" "0,1" bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "0,1" bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "0,1" newline bitfld.long 0x00 16. " STP ,Sticky Parity" "0,1" bitfld.long 0x00 15. " EPS ,Even Parity Select" "0,1" bitfld.long 0x00 14. " PEN ,Parity Enable" "0,1" newline bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1" bitfld.long 0x00 12. " STB ,Stop Bits" "0,1" bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "0,1,2,3" newline bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "0,1,2,3" bitfld.long 0x00 1. " LOOP_EN ,Loopback Enable" "0,1" bitfld.long 0x00 0. " EN ,Enable UART" "0,1" group.long 0x4++0x3 line.long 0x00 "UART2_STAT,UART2 Status Register" bitfld.long 0x00 17. " RFCS ,Receive FIFO Count Status" "0,1" bitfld.long 0x00 16. " CTS ,Clear to Send" "0,1" bitfld.long 0x00 12. " SCTS ,Sticky CTS" "0,1" newline bitfld.long 0x00 11. " RO ,Reception On-going" "0,1" bitfld.long 0x00 10. " ADDR ,Address Bit Status" "0,1" bitfld.long 0x00 9. " ASTKY ,Address Sticky" "0,1" newline bitfld.long 0x00 8. " TFI ,Transmission Finished Indicator" "0,1" bitfld.long 0x00 7. " TEMT ,TSR and THR Empty" "0,1" bitfld.long 0x00 5. " THRE ,Transmit Hold Register Empty" "0,1" newline bitfld.long 0x00 4. " BI ,Break Indicator" "0,1" bitfld.long 0x00 3. " FE ,Framing Error" "0,1" bitfld.long 0x00 2. " PE ,Parity Error" "0,1" newline bitfld.long 0x00 1. " OE ,Overrun Error" "0,1" bitfld.long 0x00 0. " DR ,Data Ready" "0,1" group.long 0x8++0x3 line.long 0x00 "UART2_SCR,UART2 Scratch Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Stored 8-bit Data" group.long 0xC++0x3 line.long 0x00 "UART2_CLK,UART2 Clock Rate Register" bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "0,1" hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor" group.long 0x10++0x3 line.long 0x00 "UART2_IMSK,UART2 Interrupt Mask Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Status" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Status" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "0,1" group.long 0x14++0x3 line.long 0x00 "UART2_IMSK_SET,UART2 Interrupt Mask Set Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Set" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Set" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Set" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Set" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Set" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Set" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Set" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Set" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Set" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Set" "0,1" group.long 0x18++0x3 line.long 0x00 "UART2_IMSK_CLR,UART2 Interrupt Mask Clear Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Clear" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Clear" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Clear" "0,1" group.long 0x1C++0x3 line.long 0x00 "UART2_RBR,UART2 Receive Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data" group.long 0x20++0x3 line.long 0x00 "UART2_THR,UART2 Transmit Hold Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data" group.long 0x24++0x3 line.long 0x00 "UART2_TAIP,UART2 Transmit Address/Insert Pulse Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data" group.long 0x28++0x3 line.long 0x00 "UART2_TSR,UART2 Transmit Shift Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR" group.long 0x2C++0x3 line.long 0x00 "UART2_RSR,UART2 Receive Shift Register" hexmask.long.word 0x00 0.--9. 1. " VALUE ,Contents of RSR" group.long 0x30++0x3 line.long 0x00 "UART2_TXCNT,UART2 Transmit Counter Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value" group.long 0x34++0x3 line.long 0x00 "UART2_RXCNT,UART2 Receive Counter Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value" tree.end tree "UART3" base ad:0x31003C04 width 16. group.long 0x0++0x3 line.long 0x00 "UART3_CTL,UART3 Control Register" bitfld.long 0x00 30. " RFRT ,Receive FIFO RTS Threshold" "0,1" bitfld.long 0x00 29. " RFIT ,Receive FIFO IRQ Threshold" "0,1" bitfld.long 0x00 28. " ACTS ,Automatic CTS" "0,1" newline bitfld.long 0x00 27. " ARTS ,Automatic RTS" "0,1" bitfld.long 0x00 26. " XOFF ,Transmitter off" "0,1" bitfld.long 0x00 25. " MRTS ,Manual Request to Send" "0,1" newline bitfld.long 0x00 24. " TPOLC ,IrDA TX Polarity Change" "0,1" bitfld.long 0x00 23. " RPOLC ,IrDA RX Polarity Change" "0,1" bitfld.long 0x00 22. " FCPOL ,Flow Control Pin Polarity" "0,1" newline bitfld.long 0x00 19. " SB ,Set Break" "0,1" bitfld.long 0x00 18. " FFE ,Force Framing Error on Transmit" "0,1" bitfld.long 0x00 17. " FPE ,Force Parity Error on Transmit" "0,1" newline bitfld.long 0x00 16. " STP ,Sticky Parity" "0,1" bitfld.long 0x00 15. " EPS ,Even Parity Select" "0,1" bitfld.long 0x00 14. " PEN ,Parity Enable" "0,1" newline bitfld.long 0x00 13. " STBH ,Stop Bits (Half Bit Time)" "0,1" bitfld.long 0x00 12. " STB ,Stop Bits" "0,1" bitfld.long 0x00 8.--9. " WLS ,Word Length Select" "0,1,2,3" newline bitfld.long 0x00 4.--5. " MOD ,Mode of Operation" "0,1,2,3" bitfld.long 0x00 1. " LOOP_EN ,Loopback Enable" "0,1" bitfld.long 0x00 0. " EN ,Enable UART" "0,1" group.long 0x4++0x3 line.long 0x00 "UART3_STAT,UART3 Status Register" bitfld.long 0x00 17. " RFCS ,Receive FIFO Count Status" "0,1" bitfld.long 0x00 16. " CTS ,Clear to Send" "0,1" bitfld.long 0x00 12. " SCTS ,Sticky CTS" "0,1" newline bitfld.long 0x00 11. " RO ,Reception On-going" "0,1" bitfld.long 0x00 10. " ADDR ,Address Bit Status" "0,1" bitfld.long 0x00 9. " ASTKY ,Address Sticky" "0,1" newline bitfld.long 0x00 8. " TFI ,Transmission Finished Indicator" "0,1" bitfld.long 0x00 7. " TEMT ,TSR and THR Empty" "0,1" bitfld.long 0x00 5. " THRE ,Transmit Hold Register Empty" "0,1" newline bitfld.long 0x00 4. " BI ,Break Indicator" "0,1" bitfld.long 0x00 3. " FE ,Framing Error" "0,1" bitfld.long 0x00 2. " PE ,Parity Error" "0,1" newline bitfld.long 0x00 1. " OE ,Overrun Error" "0,1" bitfld.long 0x00 0. " DR ,Data Ready" "0,1" group.long 0x8++0x3 line.long 0x00 "UART3_SCR,UART3 Scratch Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,Stored 8-bit Data" group.long 0xC++0x3 line.long 0x00 "UART3_CLK,UART3 Clock Rate Register" bitfld.long 0x00 31. " EDBO ,Enable Divide By One" "0,1" hexmask.long.word 0x00 0.--15. 1. " DIV ,Divisor" group.long 0x10++0x3 line.long 0x00 "UART3_IMSK,UART3 Interrupt Mask Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Status" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Status" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Status" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Status" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Status" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Status" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Status" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Status" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Status" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Status" "0,1" group.long 0x14++0x3 line.long 0x00 "UART3_IMSK_SET,UART3 Interrupt Mask Set Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Set" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Set" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Set" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Set" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Set" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Set" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Set" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Set" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Set" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Set" "0,1" group.long 0x18++0x3 line.long 0x00 "UART3_IMSK_CLR,UART3 Interrupt Mask Clear Register" bitfld.long 0x00 9. " ETXS ,Enable TX to Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 8. " ERXS ,Enable RX to Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 7. " EAWI ,Enable Address Word Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 6. " ERFCI ,Enable Receive FIFO Count Interrupt Mask Clear" "0,1" bitfld.long 0x00 5. " ETFI ,Enable Transmission Finished Interrupt Mask Clear" "0,1" bitfld.long 0x00 4. " EDTPTI ,Enable DMA TX Peripheral Triggered Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 3. " EDSSI ,Enable Modem Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 2. " ELSI ,Enable Line Status Interrupt Mask Clear" "0,1" bitfld.long 0x00 1. " ETBEI ,Enable Transmit Buffer Empty Interrupt Mask Clear" "0,1" newline bitfld.long 0x00 0. " ERBFI ,Enable Receive Buffer Full Interrupt Mask Clear" "0,1" group.long 0x1C++0x3 line.long 0x00 "UART3_RBR,UART3 Receive Buffer Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data" group.long 0x20++0x3 line.long 0x00 "UART3_THR,UART3 Transmit Hold Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8 bit data" group.long 0x24++0x3 line.long 0x00 "UART3_TAIP,UART3 Transmit Address/Insert Pulse Register" hexmask.long.byte 0x00 0.--7. 1. " VALUE ,8-bit data" group.long 0x28++0x3 line.long 0x00 "UART3_TSR,UART3 Transmit Shift Register" hexmask.long.word 0x00 0.--10. 1. " VALUE ,Contents of TSR" group.long 0x2C++0x3 line.long 0x00 "UART3_RSR,UART3 Receive Shift Register" hexmask.long.word 0x00 0.--9. 1. " VALUE ,Contents of RSR" group.long 0x30++0x3 line.long 0x00 "UART3_TXCNT,UART3 Transmit Counter Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value" group.long 0x34++0x3 line.long 0x00 "UART3_RXCNT,UART3 Receive Counter Register" hexmask.long.word 0x00 0.--15. 1. " VALUE ,16-bit Counter Value" tree.end tree.end tree "USBC (USB Controller)" base ad:0x310C5000 width 25. group.long 0x0++0x3 line.long 0x00 "USBC0_OTG_CTL,USBC0 OTG Control ans Status Register" bitfld.long 0x00 21. " CurMod ," "0,1" bitfld.long 0x00 20. " OTGVer ," "0,1" bitfld.long 0x00 19. " BSesVld ," "0,1" newline bitfld.long 0x00 18. " ASesVld ," "0,1" bitfld.long 0x00 17. " DbncTime ," "0,1" bitfld.long 0x00 16. " ConIDSts ," "0,1" newline bitfld.long 0x00 12. " EHEn ," "0,1" bitfld.long 0x00 11. " DevHNPEn ," "0,1" bitfld.long 0x00 10. " HstSetHNPEn ," "0,1" newline bitfld.long 0x00 9. " HNPReq ," "0,1" bitfld.long 0x00 8. " HstNegScs ," "0,1" bitfld.long 0x00 7. " BvalidOvVal ," "0,1" newline bitfld.long 0x00 6. " BvalidOvEn ," "0,1" bitfld.long 0x00 5. " AvalidOvVal ," "0,1" bitfld.long 0x00 4. " AvalidOvEn ," "0,1" newline bitfld.long 0x00 3. " VbvalidOvVal ," "0,1" bitfld.long 0x00 2. " VbvalidOvEn ," "0,1" bitfld.long 0x00 1. " SesReq ," "0,1" newline bitfld.long 0x00 0. " SesReqScs ," "0,1" group.long 0x4++0x3 line.long 0x00 "USBC0_OTG_IRQ,USBC0 OTG Interrupt Register" bitfld.long 0x00 19. " DbnceDone ," "0,1" bitfld.long 0x00 18. " ADevTOUTChg ," "0,1" bitfld.long 0x00 17. " HstNegDet ," "0,1" newline bitfld.long 0x00 9. " HstNegSucStsChng ," "0,1" bitfld.long 0x00 8. " SesReqSucStsChng ," "0,1" bitfld.long 0x00 2. " SesEndDet ," "0,1" group.long 0x8++0x3 line.long 0x00 "USBC0_AHB_CFG,USBC0 AHB Configuration Register" bitfld.long 0x00 24. " InvDescEndianess ," "0,1" bitfld.long 0x00 23. " AHBSingle ," "0,1" bitfld.long 0x00 22. " NotiAllDmaWrit ," "0,1" newline bitfld.long 0x00 21. " RemMemSupp ," "0,1" bitfld.long 0x00 7. " NPTxFEmpLvl ," "0,1" bitfld.long 0x00 5. " DMAEn ," "0,1" newline bitfld.long 0x00 1.--4. " HBstLen ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " GlblIntrMsk ," "0,1" group.long 0xC++0x3 line.long 0x00 "USBC0_CFG,USBC0 USB Configuration Register" bitfld.long 0x00 31. " CorruptTxPkt ," "0,1" bitfld.long 0x00 30. " ForceDevMode ," "0,1" bitfld.long 0x00 29. " ForceHstMode ," "0,1" newline bitfld.long 0x00 28. " TxEndDelay ," "0,1" bitfld.long 0x00 26. " IC_USBCap ," "0,1" bitfld.long 0x00 25. " ULPI ," "0,1" newline bitfld.long 0x00 24. " Indicator ," "0,1" bitfld.long 0x00 23. " Complement ," "0,1" bitfld.long 0x00 22. " TermSelDLPulse ," "0,1" newline bitfld.long 0x00 21. " ULPIExtVbusIndicator ," "0,1" bitfld.long 0x00 20. " ULPIExtVbusDrv ," "0,1" bitfld.long 0x00 19. " ULPIClkSusM ," "0,1" newline bitfld.long 0x00 18. " ULPIAutoRes ," "0,1" bitfld.long 0x00 10.--13. " USBTrdTim ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 9. " HNPCap ," "0,1" newline bitfld.long 0x00 8. " SRPCap ," "0,1" bitfld.long 0x00 7. " DDRSel ," "0,1" bitfld.long 0x00 6. " PHYSel ," "0,1" newline bitfld.long 0x00 5. " FSIntf ," "0,1" bitfld.long 0x00 4. " ULPI_UTMI_Sel ," "0,1" bitfld.long 0x00 3. " PHYIf ," "0,1" newline bitfld.long 0x00 0.--2. " TOutCal ," "0,1,2,3,4,5,6,7" group.long 0x10++0x3 line.long 0x00 "USBC0_RST_CTL,USBC0 Reset Register" bitfld.long 0x00 31. " AHBIdle ," "0,1" bitfld.long 0x00 30. " DMAReq ," "0,1" bitfld.long 0x00 6.--10. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 5. " TxFFlsh ," "0,1" bitfld.long 0x00 4. " RxFFlsh ," "0,1" bitfld.long 0x00 2. " FrmCntrRst ," "0,1" newline bitfld.long 0x00 1. " PIUFSSftRst ," "0,1" bitfld.long 0x00 0. " CSftRst ," "0,1" group.long 0x14++0x3 line.long 0x00 "USBC0_ISTAT,USBC0 Interrupt Status Register" bitfld.long 0x00 31. " WkUpInt ," "0,1" bitfld.long 0x00 30. " SessReqInt ," "0,1" bitfld.long 0x00 29. " DisconnInt ," "0,1" newline bitfld.long 0x00 28. " ConIDStsChng ," "0,1" bitfld.long 0x00 25. " HChInt ," "0,1" bitfld.long 0x00 24. " PrtInt ," "0,1" newline bitfld.long 0x00 23. " ResetDet ," "0,1" bitfld.long 0x00 22. " FetSusp ," "0,1" bitfld.long 0x00 21. " incomplP ," "0,1" newline bitfld.long 0x00 20. " incompISOIN ," "0,1" bitfld.long 0x00 19. " OEPInt ," "0,1" bitfld.long 0x00 18. " IEPInt ," "0,1" newline bitfld.long 0x00 17. " EPMis ," "0,1" bitfld.long 0x00 15. " EOPF ," "0,1" bitfld.long 0x00 14. " ISOOutDrop ," "0,1" newline bitfld.long 0x00 13. " EnumDone ," "0,1" bitfld.long 0x00 12. " USBRst ," "0,1" bitfld.long 0x00 11. " USBSusp ," "0,1" newline bitfld.long 0x00 10. " ErlySusp ," "0,1" bitfld.long 0x00 7. " GOUTNakEff ," "0,1" bitfld.long 0x00 6. " GINNakEff ," "0,1" newline bitfld.long 0x00 5. " NPTxFEmp ," "0,1" bitfld.long 0x00 4. " RxFLvl ," "0,1" bitfld.long 0x00 3. " Sof ," "0,1" newline bitfld.long 0x00 2. " OTGInt ," "0,1" bitfld.long 0x00 1. " ModeMis ," "0,1" bitfld.long 0x00 0. " CurMod ," "0,1" group.long 0x18++0x3 line.long 0x00 "USBC0_IMSK,USBC0 Interrupt Mask Register" bitfld.long 0x00 31. " WkUpIntMsk ," "0,1" bitfld.long 0x00 30. " SessReqIntMsk ," "0,1" bitfld.long 0x00 29. " DisconnIntMsk ," "0,1" newline bitfld.long 0x00 28. " ConIDStsChngMsk ," "0,1" bitfld.long 0x00 25. " HChIntMsk ," "0,1" bitfld.long 0x00 24. " PrtIntMsk ," "0,1" newline bitfld.long 0x00 23. " ResetDetMsk ," "0,1" bitfld.long 0x00 22. " FetSuspMsk ," "0,1" bitfld.long 0x00 21. " incomplPMsK ," "0,1" newline bitfld.long 0x00 19. " OEPIntMsk ," "0,1" bitfld.long 0x00 18. " IEPIntMsk ," "0,1" bitfld.long 0x00 17. " EPMisMsk ," "0,1" newline bitfld.long 0x00 15. " EOPFMsk ," "0,1" bitfld.long 0x00 14. " ISOOutDropMsk ," "0,1" bitfld.long 0x00 13. " EnumDoneMsk ," "0,1" newline bitfld.long 0x00 12. " USBRstMsk ," "0,1" bitfld.long 0x00 11. " USBSuspMsk ," "0,1" bitfld.long 0x00 10. " ErlySuspMsk ," "0,1" newline bitfld.long 0x00 7. " GOUTNakEffMsk ," "0,1" bitfld.long 0x00 6. " GINNakEffMsk ," "0,1" bitfld.long 0x00 5. " NPTxFEmpMsk ," "0,1" newline bitfld.long 0x00 4. " RxFLvlMsk ," "0,1" bitfld.long 0x00 3. " SofMsk ," "0,1" bitfld.long 0x00 2. " OTGIntMsk ," "0,1" newline bitfld.long 0x00 1. " ModeMisMsk ," "0,1" group.long 0x1C++0x3 line.long 0x00 "USBC0_RXDBG_STAT,USBC0 Receive Status Debug Read Register" bitfld.long 0x00 21.--24. " FN ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " PktSts ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15.--16. " DPID ," "0,1,2,3" newline hexmask.long.word 0x00 4.--14. 1. " BCnt ," bitfld.long 0x00 0.--3. " ChNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x3 line.long 0x00 "USBC0_RXDATA_STAT,USBC0 Receive Status Read/Pop Register" bitfld.long 0x00 21.--24. " FN ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 17.--20. " PktSts ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15.--16. " DPID ," "0,1,2,3" newline hexmask.long.word 0x00 4.--14. 1. " BCnt ," bitfld.long 0x00 0.--3. " ChNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x24++0x3 line.long 0x00 "USBC0_RXFIFOSZ,USBC0 Receive FIFO Size Register" hexmask.long.word 0x00 0.--11. 1. " RxFDep ," group.long 0x28++0x3 line.long 0x00 "USBC0_RXFIFOSZ_NP,USBC0 Non-periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--27. 1. " NPTXFDep ," hexmask.long.word 0x00 0.--11. 1. " NPTXFStAddr ," group.long 0x2C++0x3 line.long 0x00 "USBC0_TXFIFO_STAT_NP,USBC0 Non-periodic Transmit FIFO/Queue Status Register" hexmask.long.byte 0x00 24.--30. 1. " NPTxQTop ," hexmask.long.byte 0x00 16.--23. 1. " NPTxQSpcAvail ," hexmask.long.word 0x00 0.--15. 1. " NPTxFSpcAvail ," group.long 0x34++0x3 line.long 0x00 "USBC0_PHYIF_CTL,USBC0 PHY Interface Control Register" bitfld.long 0x00 27. " VStsDone ," "0,1" bitfld.long 0x00 26. " VStsBsy ," "0,1" bitfld.long 0x00 25. " NewRegReq ," "0,1" newline bitfld.long 0x00 22. " RegWr ," "0,1" bitfld.long 0x00 16.--21. " RegAddr ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x00 8.--15. 1. " VCtrl ," newline hexmask.long.byte 0x00 0.--7. 1. " RegData ," group.long 0x40++0x3 line.long 0x00 "USBC0_MODID,USBC0 Module ID Register" group.long 0x44++0x3 line.long 0x00 "USBC0_HWCFG1,USBC0 User Hardware Configuration 1 Register" group.long 0x48++0x3 line.long 0x00 "USBC0_HWCFG2,USBC0 User Hardware Configuration 2 Register" bitfld.long 0x00 26.--30. " TknQDepth ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24.--25. " PTxQDepth ," "0,1,2,3" bitfld.long 0x00 22.--23. " NPTxQDepth ," "0,1,2,3" newline bitfld.long 0x00 20. " MultiProcIntrpt ," "0,1" bitfld.long 0x00 19. " DynFifoSizing ," "0,1" bitfld.long 0x00 18. " PerioSupport ," "0,1" newline bitfld.long 0x00 14.--17. " NumHstChnl ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. " NumDevEps ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--9. " FSPhyType ," "0,1,2,3" newline bitfld.long 0x00 6.--7. " HSPhyType ," "0,1,2,3" bitfld.long 0x00 5. " SingPnt ," "0,1" bitfld.long 0x00 3.--4. " OtgArch ," "0,1,2,3" newline bitfld.long 0x00 0.--2. " OtgMode ," "0,1,2,3,4,5,6,7" group.long 0x4C++0x3 line.long 0x00 "USBC0_HWCFG3,USBC0 User Hardware Configuration 3 Register" hexmask.long.word 0x00 16.--31. 1. " DfifoDepth ," bitfld.long 0x00 15. " LPMMode ," "0,1" bitfld.long 0x00 14. " BCSupport ," "0,1" newline bitfld.long 0x00 13. " HSICMode ," "0,1" bitfld.long 0x00 12. " ADPSupport ," "0,1" bitfld.long 0x00 11. " RstType ," "0,1" newline bitfld.long 0x00 10. " OptFeature ," "0,1" bitfld.long 0x00 9. " VndctlSupt ," "0,1" bitfld.long 0x00 8. " I2CIntSel ," "0,1" newline bitfld.long 0x00 7. " OtgEn ," "0,1" bitfld.long 0x00 4.--6. " PktSizeWidth ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--3. " XferSizeWidth ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x3 line.long 0x00 "USBC0_HWCFG4,USBC0 User Hardware Configuration 4 Register" bitfld.long 0x00 31. " DescDMA ," "0,1" bitfld.long 0x00 30. " DescDMAEnabled ," "0,1" bitfld.long 0x00 26.--29. " INEps ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 25. " DedFifoMode ," "0,1" bitfld.long 0x00 24. " SessEndFltr ," "0,1" bitfld.long 0x00 23. " BValidFltr ," "0,1" newline bitfld.long 0x00 22. " AValidFltr ," "0,1" bitfld.long 0x00 21. " VBusValidFltr ," "0,1" bitfld.long 0x00 20. " IddgFltr ," "0,1" newline bitfld.long 0x00 16.--19. " NumCtlEps ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PhyDataWidth ," "0,1,2,3" bitfld.long 0x00 13. " EnhancedLPMSupt ," "0,1" newline bitfld.long 0x00 12. " ACGSupt ," "0,1" bitfld.long 0x00 7. " ExtendedHibernation ," "0,1" bitfld.long 0x00 6. " Hibernation ," "0,1" newline bitfld.long 0x00 5. " AhbFreq ," "0,1" bitfld.long 0x00 4. " PartialPwrDn ," "0,1" bitfld.long 0x00 0.--3. " NumDevPerioEps ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x5C++0x3 line.long 0x00 "USBC0_DFIFO_CFG,USBC0 DFIFO Configuration Register" hexmask.long.word 0x00 16.--31. 1. " EPInfoBaseAddr ," hexmask.long.word 0x00 0.--15. 1. " GDFIFOCfg ," group.long 0x100++0x3 line.long 0x00 "USBC0_TXFIFOSZ_PER_H,USBC0 Host Periodic Transmit FIFO Size Register" hexmask.long.word 0x00 16.--26. 1. " PTxFSize ," hexmask.long.word 0x00 0.--12. 1. " PTxFStAddr ," group.long 0x104++0x3 line.long 0x00 "USBC0_TXFIFOSZ1_IEP_H,USBC0 Device IN Endpoint 1 Transmit FIFO Size Register" hexmask.long.word 0x00 16.--24. 1. " INEPnTxFDep ," hexmask.long.word 0x00 0.--11. 1. " INEPnTxFStAddr ," group.long 0x108++0x3 line.long 0x00 "USBC0_TXFIFOSZ2_IEP_H,USBC0 Device IN Endpoint 2 Transmit FIFO Size Register" hexmask.long.word 0x00 16.--24. 1. " INEPnTxFDep ," hexmask.long.word 0x00 0.--11. 1. " INEPnTxFStAddr ," group.long 0x10C++0x3 line.long 0x00 "USBC0_TXFIFOSZ3_IEP_H,USBC0 Device IN Endpoint 3 Transmit FIFO Size Register" hexmask.long.word 0x00 16.--24. 1. " INEPnTxFDep ," hexmask.long.word 0x00 0.--11. 1. " INEPnTxFStAddr ," group.long 0x400++0x3 line.long 0x00 "USBC0_CFG_H,USBC0 Host Configuration Register" bitfld.long 0x00 31. " ModeChTimEn ," "0,1" bitfld.long 0x00 26. " PerSchedEna ," "0,1" bitfld.long 0x00 24.--25. " FrListEn ," "0,1,2,3" newline bitfld.long 0x00 23. " DescDMA ," "0,1" bitfld.long 0x00 16. " dis_tx_ipgap_dly_check ," "0,1" hexmask.long.byte 0x00 8.--15. 1. " ResValid ," newline bitfld.long 0x00 7. " Ena32KHzS ," "0,1" bitfld.long 0x00 2. " FSLSSupp ," "0,1" bitfld.long 0x00 0.--1. " FSLSPclkSel ," "0,1,2,3" group.long 0x404++0x3 line.long 0x00 "USBC0_FIR_H,USBC0 Host Frame Interval Register" bitfld.long 0x00 16. " HFIRRldCtrl ," "0,1" hexmask.long.word 0x00 0.--15. 1. " FrInt ," group.long 0x408++0x3 line.long 0x00 "USBC0_FNUM_H,USBC0 Host Frame number/Frame time remaining Register" hexmask.long.word 0x00 16.--31. 1. " FrRem ," hexmask.long.word 0x00 0.--15. 1. " FrNum ," group.long 0x414++0x3 line.long 0x00 "USBC0_ISTAT_H,USBC0 Host All Channels Interrupt Register" hexmask.long.word 0x00 0.--15. 1. " HAINT ," group.long 0x418++0x3 line.long 0x00 "USBC0_IMSK_H,USBC0 Host All Channels Interrupt Mask Register" hexmask.long.word 0x00 0.--15. 1. " HAINTMsk ," group.long 0x41C++0x3 line.long 0x00 "USBC0_FL_BADDR_H,USBC0 Host Frame List Base Address Register" group.long 0x440++0x3 line.long 0x00 "USBC0_PORT_CTL_H,USBC0 Host Port Control and Status Register" bitfld.long 0x00 17.--18. " PrtSpd ," "0,1,2,3" bitfld.long 0x00 13.--16. " PrtTstCtl ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12. " PrtPwr ," "0,1" newline bitfld.long 0x00 10.--11. " PrtLnSts ," "0,1,2,3" bitfld.long 0x00 8. " PrtRst ," "0,1" bitfld.long 0x00 7. " PrtSusp ," "0,1" newline bitfld.long 0x00 6. " PrtRes ," "0,1" bitfld.long 0x00 5. " PrtOvrCurrChng ," "0,1" bitfld.long 0x00 4. " PrtOvrCurrAct ," "0,1" newline bitfld.long 0x00 3. " PrtEnChng ," "0,1" bitfld.long 0x00 2. " PrtEna ," "0,1" bitfld.long 0x00 1. " PrtConnDet ," "0,1" newline bitfld.long 0x00 0. " PrtConnSts ," "0,1" group.long 0x500++0x3 line.long 0x00 "USBC0_CHAR0_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x504++0x3 line.long 0x00 "USBC0_SPLT_CTL0_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x508++0x3 line.long 0x00 "USBC0_ISTAT0_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x50C++0x3 line.long 0x00 "USBC0_IMSK0_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x510++0x3 line.long 0x00 "USBC0_TSIZ0_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x514++0x3 line.long 0x00 "USBC0_DMA_ADDR0_H,USBC0 Host Channel n DMA Address Register" group.long 0x51C++0x3 line.long 0x00 "USBC0_DMA_BADDR0_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x520++0x3 line.long 0x00 "USBC0_CHAR1_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x524++0x3 line.long 0x00 "USBC0_SPLT_CTL1_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x528++0x3 line.long 0x00 "USBC0_ISTAT1_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x52C++0x3 line.long 0x00 "USBC0_IMSK1_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x530++0x3 line.long 0x00 "USBC0_TSIZ1_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x534++0x3 line.long 0x00 "USBC0_DMA_ADDR1_H,USBC0 Host Channel n DMA Address Register" group.long 0x53C++0x3 line.long 0x00 "USBC0_DMA_BADDR1_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x540++0x3 line.long 0x00 "USBC0_CHAR2_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x544++0x3 line.long 0x00 "USBC0_SPLT_CTL2_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x548++0x3 line.long 0x00 "USBC0_ISTAT2_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x54C++0x3 line.long 0x00 "USBC0_IMSK2_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x550++0x3 line.long 0x00 "USBC0_TSIZ2_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x554++0x3 line.long 0x00 "USBC0_DMA_ADDR2_H,USBC0 Host Channel n DMA Address Register" group.long 0x55C++0x3 line.long 0x00 "USBC0_DMA_BADDR2_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x560++0x3 line.long 0x00 "USBC0_CHAR3_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x564++0x3 line.long 0x00 "USBC0_SPLT_CTL3_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x568++0x3 line.long 0x00 "USBC0_ISTAT3_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x56C++0x3 line.long 0x00 "USBC0_IMSK3_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x570++0x3 line.long 0x00 "USBC0_TSIZ3_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x574++0x3 line.long 0x00 "USBC0_DMA_ADDR3_H,USBC0 Host Channel n DMA Address Register" group.long 0x57C++0x3 line.long 0x00 "USBC0_DMA_BADDR3_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x580++0x3 line.long 0x00 "USBC0_CHAR4_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x584++0x3 line.long 0x00 "USBC0_SPLT_CTL4_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x588++0x3 line.long 0x00 "USBC0_ISTAT4_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x58C++0x3 line.long 0x00 "USBC0_IMSK4_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x590++0x3 line.long 0x00 "USBC0_TSIZ4_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x594++0x3 line.long 0x00 "USBC0_DMA_ADDR4_H,USBC0 Host Channel n DMA Address Register" group.long 0x59C++0x3 line.long 0x00 "USBC0_DMA_BADDR4_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x5A0++0x3 line.long 0x00 "USBC0_CHAR5_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x5A4++0x3 line.long 0x00 "USBC0_SPLT_CTL5_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x5A8++0x3 line.long 0x00 "USBC0_ISTAT5_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x5AC++0x3 line.long 0x00 "USBC0_IMSK5_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x5B0++0x3 line.long 0x00 "USBC0_TSIZ5_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x5B4++0x3 line.long 0x00 "USBC0_DMA_ADDR5_H,USBC0 Host Channel n DMA Address Register" group.long 0x5BC++0x3 line.long 0x00 "USBC0_DMA_BADDR5_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x5C0++0x3 line.long 0x00 "USBC0_CHAR6_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x5C4++0x3 line.long 0x00 "USBC0_SPLT_CTL6_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x5C8++0x3 line.long 0x00 "USBC0_ISTAT6_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x5CC++0x3 line.long 0x00 "USBC0_IMSK6_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x5D0++0x3 line.long 0x00 "USBC0_TSIZ6_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x5D4++0x3 line.long 0x00 "USBC0_DMA_ADDR6_H,USBC0 Host Channel n DMA Address Register" group.long 0x5DC++0x3 line.long 0x00 "USBC0_DMA_BADDR6_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x5E0++0x3 line.long 0x00 "USBC0_CHAR7_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x5E4++0x3 line.long 0x00 "USBC0_SPLT_CTL7_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x5E8++0x3 line.long 0x00 "USBC0_ISTAT7_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x5EC++0x3 line.long 0x00 "USBC0_IMSK7_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x5F0++0x3 line.long 0x00 "USBC0_TSIZ7_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x5F4++0x3 line.long 0x00 "USBC0_DMA_ADDR7_H,USBC0 Host Channel n DMA Address Register" group.long 0x5FC++0x3 line.long 0x00 "USBC0_DMA_BADDR7_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x600++0x3 line.long 0x00 "USBC0_CHAR8_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x604++0x3 line.long 0x00 "USBC0_SPLT_CTL8_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x608++0x3 line.long 0x00 "USBC0_ISTAT8_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x60C++0x3 line.long 0x00 "USBC0_IMSK8_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x610++0x3 line.long 0x00 "USBC0_TSIZ8_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x614++0x3 line.long 0x00 "USBC0_DMA_ADDR8_H,USBC0 Host Channel n DMA Address Register" group.long 0x61C++0x3 line.long 0x00 "USBC0_DMA_BADDR8_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x620++0x3 line.long 0x00 "USBC0_CHAR9_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x624++0x3 line.long 0x00 "USBC0_SPLT_CTL9_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x628++0x3 line.long 0x00 "USBC0_ISTAT9_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x62C++0x3 line.long 0x00 "USBC0_IMSK9_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x630++0x3 line.long 0x00 "USBC0_TSIZ9_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x634++0x3 line.long 0x00 "USBC0_DMA_ADDR9_H,USBC0 Host Channel n DMA Address Register" group.long 0x63C++0x3 line.long 0x00 "USBC0_DMA_BADDR9_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x640++0x3 line.long 0x00 "USBC0_CHAR10_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x644++0x3 line.long 0x00 "USBC0_SPLT_CTL10_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x648++0x3 line.long 0x00 "USBC0_ISTAT10_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x64C++0x3 line.long 0x00 "USBC0_IMSK10_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x650++0x3 line.long 0x00 "USBC0_TSIZ10_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x654++0x3 line.long 0x00 "USBC0_DMA_ADDR10_H,USBC0 Host Channel n DMA Address Register" group.long 0x65C++0x3 line.long 0x00 "USBC0_DMA_BADDR10_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x660++0x3 line.long 0x00 "USBC0_CHAR11_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x664++0x3 line.long 0x00 "USBC0_SPLT_CTL11_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x668++0x3 line.long 0x00 "USBC0_ISTAT11_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x66C++0x3 line.long 0x00 "USBC0_IMSK11_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x670++0x3 line.long 0x00 "USBC0_TSIZ11_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x674++0x3 line.long 0x00 "USBC0_DMA_ADDR11_H,USBC0 Host Channel n DMA Address Register" group.long 0x67C++0x3 line.long 0x00 "USBC0_DMA_BADDR11_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x680++0x3 line.long 0x00 "USBC0_CHAR12_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x684++0x3 line.long 0x00 "USBC0_SPLT_CTL12_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x688++0x3 line.long 0x00 "USBC0_ISTAT12_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x68C++0x3 line.long 0x00 "USBC0_IMSK12_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x690++0x3 line.long 0x00 "USBC0_TSIZ12_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x694++0x3 line.long 0x00 "USBC0_DMA_ADDR12_H,USBC0 Host Channel n DMA Address Register" group.long 0x69C++0x3 line.long 0x00 "USBC0_DMA_BADDR12_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x6A0++0x3 line.long 0x00 "USBC0_CHAR13_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x6A4++0x3 line.long 0x00 "USBC0_SPLT_CTL13_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x6A8++0x3 line.long 0x00 "USBC0_ISTAT13_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x6AC++0x3 line.long 0x00 "USBC0_IMSK13_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x6B0++0x3 line.long 0x00 "USBC0_TSIZ13_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x6B4++0x3 line.long 0x00 "USBC0_DMA_ADDR13_H,USBC0 Host Channel n DMA Address Register" group.long 0x6BC++0x3 line.long 0x00 "USBC0_DMA_BADDR13_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x6C0++0x3 line.long 0x00 "USBC0_CHAR14_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x6C4++0x3 line.long 0x00 "USBC0_SPLT_CTL14_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x6C8++0x3 line.long 0x00 "USBC0_ISTAT14_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x6CC++0x3 line.long 0x00 "USBC0_IMSK14_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x6D0++0x3 line.long 0x00 "USBC0_TSIZ14_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x6D4++0x3 line.long 0x00 "USBC0_DMA_ADDR14_H,USBC0 Host Channel n DMA Address Register" group.long 0x6DC++0x3 line.long 0x00 "USBC0_DMA_BADDR14_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x6E0++0x3 line.long 0x00 "USBC0_CHAR15_H,USBC0 Host Channel n Characteristics Register" bitfld.long 0x00 31. " ChEna ," "0,1" bitfld.long 0x00 30. " ChDis ," "0,1" bitfld.long 0x00 29. " OddFrm ," "0,1" newline hexmask.long.byte 0x00 22.--28. 1. " DevAddr ," bitfld.long 0x00 20.--21. " EC ," "0,1,2,3" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " LSpdDev ," "0,1" bitfld.long 0x00 15. " EPDir ," "0,1" bitfld.long 0x00 11.--14. " EPNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x6E4++0x3 line.long 0x00 "USBC0_SPLT_CTL15_H,USBC0 Host Channel n split control Register" bitfld.long 0x00 31. " SpltEna ," "0,1" bitfld.long 0x00 16. " CompSplt ," "0,1" bitfld.long 0x00 14.--15. " XactPos ," "0,1,2,3" newline hexmask.long.byte 0x00 7.--13. 1. " HubAddr ," hexmask.long.byte 0x00 0.--6. 1. " PrtAddr ," group.long 0x6E8++0x3 line.long 0x00 "USBC0_ISTAT15_H,USBC0 Host Channel n Interrupt Status Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntr ," "0,1" bitfld.long 0x00 12. " XCS_XACT_ERR ," "0,1" bitfld.long 0x00 11. " BNAIntr ," "0,1" newline bitfld.long 0x00 10. " DataTglErr ," "0,1" bitfld.long 0x00 9. " FrmOvrun ," "0,1" bitfld.long 0x00 8. " BblErr ," "0,1" newline bitfld.long 0x00 7. " XactErr ," "0,1" bitfld.long 0x00 6. " NYET ," "0,1" bitfld.long 0x00 5. " ACK ," "0,1" newline bitfld.long 0x00 4. " NAK ," "0,1" bitfld.long 0x00 3. " STALL ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " ChHltd ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x6EC++0x3 line.long 0x00 "USBC0_IMSK15_H,USBC0 Host Channel n Interrupt Mask Register" bitfld.long 0x00 13. " DESC_LST_ROLLIntrMsk ," "0,1" bitfld.long 0x00 11. " BNAIntrMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" newline bitfld.long 0x00 1. " ChHltdMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x6F0++0x3 line.long 0x00 "USBC0_TSIZ15_H,USBC0 Host Channel n Transfer Size Register" bitfld.long 0x00 31. " DoPng ," "0,1" bitfld.long 0x00 29.--30. " Pid ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," newline hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x6F4++0x3 line.long 0x00 "USBC0_DMA_ADDR15_H,USBC0 Host Channel n DMA Address Register" group.long 0x6FC++0x3 line.long 0x00 "USBC0_DMA_BADDR15_H,USBC0 Host Channel n DMA Buffer Address Register" group.long 0x800++0x3 line.long 0x00 "USBC0_CFG_D,USBC0 Device Configuration Register" bitfld.long 0x00 26.--31. " ResValid ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 24.--25. " PerSchIntvl ," "0,1,2,3" bitfld.long 0x00 23. " DescDMA ," "0,1" newline bitfld.long 0x00 15. " ErraticIntMsk ," "0,1" bitfld.long 0x00 14. " XCVRDLY ," "0,1" bitfld.long 0x00 13. " EnDevOutNak ," "0,1" newline bitfld.long 0x00 11.--12. " PerFrInt ," "0,1,2,3" hexmask.long.byte 0x00 4.--10. 1. " DevAddr ," bitfld.long 0x00 3. " Ena32KHzSusp ," "0,1" newline bitfld.long 0x00 2. " NZStsOUTHShk ," "0,1" bitfld.long 0x00 0.--1. " DevSpd ," "0,1,2,3" group.long 0x804++0x3 line.long 0x00 "USBC0_CTL_D,USBC0 Device Control Register" bitfld.long 0x00 17. " EnContOnBNA ," "0,1" bitfld.long 0x00 16. " NakOnBble ," "0,1" bitfld.long 0x00 15. " IgnrFrmNum ," "0,1" newline bitfld.long 0x00 13.--14. " GMC ," "0,1,2,3" bitfld.long 0x00 11. " PWROnPrgDone ," "0,1" bitfld.long 0x00 10. " CGOUTNak ," "0,1" newline bitfld.long 0x00 9. " SGOUTNak ," "0,1" bitfld.long 0x00 8. " CGNPInNak ," "0,1" bitfld.long 0x00 7. " SGNPInNak ," "0,1" newline bitfld.long 0x00 4.--6. " TstCtl ," "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " GOUTNakSts ," "0,1" bitfld.long 0x00 2. " GNPINNakSts ," "0,1" newline bitfld.long 0x00 1. " SftDiscon ," "0,1" bitfld.long 0x00 0. " RmtWkUpSig ," "0,1" group.long 0x808++0x3 line.long 0x00 "USBC0_STAT_D,USBC0 Device Status Register" bitfld.long 0x00 22.--23. " DevLnSts ," "0,1,2,3" hexmask.long.word 0x00 8.--21. 1. " SOFFN ," bitfld.long 0x00 3. " ErrticErr ," "0,1" newline bitfld.long 0x00 1.--2. " EnumSpd ," "0,1,2,3" bitfld.long 0x00 0. " SuspSts ," "0,1" group.long 0x810++0x3 line.long 0x00 "USBC0_IMASK_IEP_D,USBC0 Device IN Endpoint common Interrupt mask Register" bitfld.long 0x00 13. " NAKMsk ," "0,1" bitfld.long 0x00 9. " BNAInIntrMsk ," "0,1" bitfld.long 0x00 8. " TxfifoUndrnMsk ," "0,1" newline bitfld.long 0x00 6. " INEPNakEffMsk ," "0,1" bitfld.long 0x00 5. " INTknEPMisMsk ," "0,1" bitfld.long 0x00 4. " INTknTXFEmpMsk ," "0,1" newline bitfld.long 0x00 3. " TimeOUTMsk ," "0,1" bitfld.long 0x00 2. " AHBErrMsk ," "0,1" bitfld.long 0x00 1. " EPDisbldMsk ," "0,1" newline bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x814++0x3 line.long 0x00 "USBC0_IMASK_OEP_D,USBC0 Device OUT Endpoint common Interrupt mask Register" bitfld.long 0x00 14. " NYETMsk ," "0,1" bitfld.long 0x00 13. " NAKMsk ," "0,1" bitfld.long 0x00 12. " BbleErrMsk ," "0,1" newline bitfld.long 0x00 9. " BnaOutIntrMsk ," "0,1" bitfld.long 0x00 8. " OutPktErrMsk ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" newline bitfld.long 0x00 5. " StsPhseRcvdMsk ," "0,1" bitfld.long 0x00 4. " OUTTknEPdisMsk ," "0,1" bitfld.long 0x00 3. " SetUPMsk ," "0,1" newline bitfld.long 0x00 2. " AHBErrMsk ," "0,1" bitfld.long 0x00 1. " EPDisbldMsk ," "0,1" bitfld.long 0x00 0. " XferComplMsk ," "0,1" group.long 0x818++0x3 line.long 0x00 "USBC0_ISTAT_D,USBC0 Device All Endpoint Interrupt Status Register" bitfld.long 0x00 27. " OutEPInt11 ," "0,1" bitfld.long 0x00 26. " OutEPInt10 ," "0,1" bitfld.long 0x00 25. " OutEPInt9 ," "0,1" newline bitfld.long 0x00 24. " OutEPInt8 ," "0,1" bitfld.long 0x00 23. " OutEPInt7 ," "0,1" bitfld.long 0x00 22. " OutEPInt6 ," "0,1" newline bitfld.long 0x00 21. " OutEPInt5 ," "0,1" bitfld.long 0x00 20. " OutEPInt4 ," "0,1" bitfld.long 0x00 19. " OutEPInt3 ," "0,1" newline bitfld.long 0x00 18. " OutEPInt2 ," "0,1" bitfld.long 0x00 17. " OutEPInt1 ," "0,1" bitfld.long 0x00 16. " OutEPInt0 ," "0,1" newline bitfld.long 0x00 11. " InEpInt11 ," "0,1" bitfld.long 0x00 10. " InEpInt10 ," "0,1" bitfld.long 0x00 9. " InEpInt9 ," "0,1" newline bitfld.long 0x00 8. " InEpInt8 ," "0,1" bitfld.long 0x00 7. " InEpInt7 ," "0,1" bitfld.long 0x00 6. " InEpInt6 ," "0,1" newline bitfld.long 0x00 5. " InEpInt5 ," "0,1" bitfld.long 0x00 4. " InEpInt4 ," "0,1" bitfld.long 0x00 3. " InEpInt3 ," "0,1" newline bitfld.long 0x00 2. " InEpInt2 ," "0,1" bitfld.long 0x00 1. " InEpInt1 ," "0,1" bitfld.long 0x00 0. " InEpInt0 ," "0,1" group.long 0x81C++0x3 line.long 0x00 "USBC0_IMSK_D,USBC0 Device All Endpoint Interrupt Mask Register" bitfld.long 0x00 27. " OutEPMsk11 ," "0,1" bitfld.long 0x00 26. " OutEPMsk10 ," "0,1" bitfld.long 0x00 25. " OutEPMsk9 ," "0,1" newline bitfld.long 0x00 24. " OutEPMsk8 ," "0,1" bitfld.long 0x00 23. " OutEPMsk7 ," "0,1" bitfld.long 0x00 22. " OutEPMsk6 ," "0,1" newline bitfld.long 0x00 21. " OutEPMsk5 ," "0,1" bitfld.long 0x00 20. " OutEPMsk4 ," "0,1" bitfld.long 0x00 19. " OutEPMsk3 ," "0,1" newline bitfld.long 0x00 18. " OutEPMsk2 ," "0,1" bitfld.long 0x00 17. " OutEPMsk1 ," "0,1" bitfld.long 0x00 16. " OutEPMsk0 ," "0,1" newline bitfld.long 0x00 11. " InEpMsk11 ," "0,1" bitfld.long 0x00 10. " InEpMsk10 ," "0,1" bitfld.long 0x00 9. " InEpMsk9 ," "0,1" newline bitfld.long 0x00 8. " InEpMsk8 ," "0,1" bitfld.long 0x00 7. " InEpMsk7 ," "0,1" bitfld.long 0x00 6. " InEpMsk6 ," "0,1" newline bitfld.long 0x00 5. " InEpMsk5 ," "0,1" bitfld.long 0x00 4. " InEpMsk4 ," "0,1" bitfld.long 0x00 3. " InEpMsk3 ," "0,1" newline bitfld.long 0x00 2. " InEpMsk2 ," "0,1" bitfld.long 0x00 1. " InEpMsk1 ," "0,1" bitfld.long 0x00 0. " InEpMsk0 ," "0,1" group.long 0x828++0x3 line.long 0x00 "USBC0_VBUSDIS_D,USBC0 Device VBUS Discharge time Register" hexmask.long.word 0x00 0.--15. 1. " DVBUSDis ," group.long 0x82C++0x3 line.long 0x00 "USBC0_VBUSPULSE_D,USBC0 Device VBUS pulsing time Register" hexmask.long.word 0x00 0.--11. 1. " DVBUSPulse ," group.long 0x830++0x3 line.long 0x00 "USBC0_THR_CTL_D,USBC0 Device Threshold Control Register" bitfld.long 0x00 27. " ArbPrkEn ," "0,1" hexmask.long.word 0x00 17.--25. 1. " RxThrLen ," bitfld.long 0x00 16. " RxThrEn ," "0,1" newline bitfld.long 0x00 11.--12. " AHBThrRatio ," "0,1,2,3" hexmask.long.word 0x00 2.--10. 1. " TxThrLen ," bitfld.long 0x00 1. " ISOThrEn ," "0,1" newline bitfld.long 0x00 0. " NonISOThrEn ," "0,1" group.long 0x834++0x3 line.long 0x00 "USBC0_IMSK_IEP_FEMPT_D,USBC0 Device IN Endpoint FIFO Empty Interrupt Mask Register" hexmask.long.word 0x00 0.--15. 1. " InEpTxfEmpMsk ," group.long 0x920++0x3 line.long 0x00 "USBC0_CTL_IEP1_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x928++0x3 line.long 0x00 "USBC0_ISTAT_IEP1_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x930++0x3 line.long 0x00 "USBC0_TSIZ_IEP1_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x934++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP1_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0x938++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP1_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0x93C++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP1_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0x940++0x3 line.long 0x00 "USBC0_CTL_IEP2_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x948++0x3 line.long 0x00 "USBC0_ISTAT_IEP2_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x950++0x3 line.long 0x00 "USBC0_TSIZ_IEP2_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x954++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP2_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0x958++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP2_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0x95C++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP2_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0x960++0x3 line.long 0x00 "USBC0_CTL_IEP3_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x968++0x3 line.long 0x00 "USBC0_ISTAT_IEP3_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x970++0x3 line.long 0x00 "USBC0_TSIZ_IEP3_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x974++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP3_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0x978++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP3_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0x97C++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP3_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0x980++0x3 line.long 0x00 "USBC0_CTL_IEP4_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x988++0x3 line.long 0x00 "USBC0_ISTAT_IEP4_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x990++0x3 line.long 0x00 "USBC0_TSIZ_IEP4_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x994++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP4_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0x998++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP4_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0x99C++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP4_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0x9A0++0x3 line.long 0x00 "USBC0_CTL_IEP5_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x9A8++0x3 line.long 0x00 "USBC0_ISTAT_IEP5_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x9B0++0x3 line.long 0x00 "USBC0_TSIZ_IEP5_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x9B4++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP5_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0x9B8++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP5_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0x9BC++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP5_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0x9C0++0x3 line.long 0x00 "USBC0_CTL_IEP6_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x9C8++0x3 line.long 0x00 "USBC0_ISTAT_IEP6_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x9D0++0x3 line.long 0x00 "USBC0_TSIZ_IEP6_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x9D4++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP6_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0x9D8++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP6_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0x9DC++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP6_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0x9E0++0x3 line.long 0x00 "USBC0_CTL_IEP7_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0x9E8++0x3 line.long 0x00 "USBC0_ISTAT_IEP7_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0x9F0++0x3 line.long 0x00 "USBC0_TSIZ_IEP7_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0x9F4++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP7_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0x9F8++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP7_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0x9FC++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP7_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0xA00++0x3 line.long 0x00 "USBC0_CTL_IEP8_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xA08++0x3 line.long 0x00 "USBC0_ISTAT_IEP8_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xA10++0x3 line.long 0x00 "USBC0_TSIZ_IEP8_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xA14++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP8_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0xA18++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP8_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0xA1C++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP8_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0xA20++0x3 line.long 0x00 "USBC0_CTL_IEP9_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xA28++0x3 line.long 0x00 "USBC0_ISTAT_IEP9_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xA30++0x3 line.long 0x00 "USBC0_TSIZ_IEP9_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xA34++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP9_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0xA38++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP9_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0xA3C++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP9_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0xA40++0x3 line.long 0x00 "USBC0_CTL_IEP10_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xA48++0x3 line.long 0x00 "USBC0_ISTAT_IEP10_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xA50++0x3 line.long 0x00 "USBC0_TSIZ_IEP10_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xA54++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP10_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0xA58++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP10_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0xA5C++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP10_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0xA60++0x3 line.long 0x00 "USBC0_CTL_IEP11_D,USBC0 Device Control IN Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 22.--25. " TxFNum ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xA68++0x3 line.long 0x00 "USBC0_ISTAT_IEP11_D,USBC0 Device Control IN Endpoint n Interrupt Control Register" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" bitfld.long 0x00 12. " BbleErr ," "0,1" newline bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" bitfld.long 0x00 8. " TxfifoUndrn ," "0,1" newline bitfld.long 0x00 7. " TxFEmp ," "0,1" bitfld.long 0x00 6. " INEPNakEff ," "0,1" bitfld.long 0x00 5. " INTknEPMis ," "0,1" newline bitfld.long 0x00 4. " INTknTXFEmp ," "0,1" bitfld.long 0x00 3. " TimeOUT ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xA70++0x3 line.long 0x00 "USBC0_TSIZ_IEP11_D,USBC0 Device Control IN Endpoint n Transfer size Register" bitfld.long 0x00 29.--30. " MC ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xA74++0x3 line.long 0x00 "USBC0_DMA_ADDR_IEP11_D,USBC0 Device Control IN Endpoint n DMA Address Register" group.long 0xA78++0x3 line.long 0x00 "USBC0_TXFSTAT_IEP11_D,USBC0 Device Control IN Endpoint Transmit FIFO Status Register" hexmask.long.word 0x00 0.--15. 1. " INEPTxFSpcAvail ," group.long 0xA7C++0x3 line.long 0x00 "USBC0_DMA_BADDR_IEP11_D,USBC0 Device Control IN Endpoint n DMA Buffer Address Register" group.long 0xB20++0x3 line.long 0x00 "USBC0_CTL_OEP1_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xB28++0x3 line.long 0x00 "USBC0_ISTAT_OEP1_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xB30++0x3 line.long 0x00 "USBC0_TSIZ_OEP1_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xB34++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP1_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xB3C++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP1_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xB40++0x3 line.long 0x00 "USBC0_CTL_OEP2_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xB48++0x3 line.long 0x00 "USBC0_ISTAT_OEP2_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xB50++0x3 line.long 0x00 "USBC0_TSIZ_OEP2_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xB54++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP2_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xB5C++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP2_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xB60++0x3 line.long 0x00 "USBC0_CTL_OEP3_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xB68++0x3 line.long 0x00 "USBC0_ISTAT_OEP3_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xB70++0x3 line.long 0x00 "USBC0_TSIZ_OEP3_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xB74++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP3_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xB7C++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP3_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xB80++0x3 line.long 0x00 "USBC0_CTL_OEP4_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xB88++0x3 line.long 0x00 "USBC0_ISTAT_OEP4_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xB90++0x3 line.long 0x00 "USBC0_TSIZ_OEP4_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xB94++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP4_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xB9C++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP4_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xBA0++0x3 line.long 0x00 "USBC0_CTL_OEP5_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xBA8++0x3 line.long 0x00 "USBC0_ISTAT_OEP5_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xBB0++0x3 line.long 0x00 "USBC0_TSIZ_OEP5_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xBB4++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP5_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xBBC++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP5_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xBC0++0x3 line.long 0x00 "USBC0_CTL_OEP6_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xBC8++0x3 line.long 0x00 "USBC0_ISTAT_OEP6_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xBD0++0x3 line.long 0x00 "USBC0_TSIZ_OEP6_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xBD4++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP6_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xBDC++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP6_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xBE0++0x3 line.long 0x00 "USBC0_CTL_OEP7_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xBE8++0x3 line.long 0x00 "USBC0_ISTAT_OEP7_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xBF0++0x3 line.long 0x00 "USBC0_TSIZ_OEP7_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xBF4++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP7_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xBFC++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP7_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xC00++0x3 line.long 0x00 "USBC0_CTL_OEP8_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xC08++0x3 line.long 0x00 "USBC0_ISTAT_OEP8_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xC10++0x3 line.long 0x00 "USBC0_TSIZ_OEP8_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xC14++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP8_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xC1C++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP8_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xC20++0x3 line.long 0x00 "USBC0_CTL_OEP9_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xC28++0x3 line.long 0x00 "USBC0_ISTAT_OEP9_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xC30++0x3 line.long 0x00 "USBC0_TSIZ_OEP9_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xC34++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP9_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xC3C++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP9_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xC40++0x3 line.long 0x00 "USBC0_CTL_OEP10_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xC48++0x3 line.long 0x00 "USBC0_ISTAT_OEP10_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xC50++0x3 line.long 0x00 "USBC0_TSIZ_OEP10_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xC54++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP10_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xC5C++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP10_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xC60++0x3 line.long 0x00 "USBC0_CTL_OEP11_D,USBC0 Device OUT Endpoint n Control Register" bitfld.long 0x00 31. " EPEna ," "0,1" bitfld.long 0x00 30. " EPDis ," "0,1" bitfld.long 0x00 29. " SetD1PID ," "0,1" newline bitfld.long 0x00 28. " SetD0PID ," "0,1" bitfld.long 0x00 27. " SNAK ," "0,1" bitfld.long 0x00 26. " CNAK ," "0,1" newline bitfld.long 0x00 21. " Stall ," "0,1" bitfld.long 0x00 20. " Snp ," "0,1" bitfld.long 0x00 18.--19. " EPType ," "0,1,2,3" newline bitfld.long 0x00 17. " NAKSts ," "0,1" bitfld.long 0x00 16. " DPID ," "0,1" bitfld.long 0x00 15. " USBActEP ," "0,1" newline hexmask.long.word 0x00 0.--10. 1. " MPS ," group.long 0xC68++0x3 line.long 0x00 "USBC0_ISTAT_OEP11_D,USBC0 Device OUT Endpoint n Interrupt Register" bitfld.long 0x00 15. " StupPktRcvd ," "0,1" bitfld.long 0x00 14. " NYETIntrpt ," "0,1" bitfld.long 0x00 13. " NAKIntrpt ," "0,1" newline bitfld.long 0x00 12. " BbleErr ," "0,1" bitfld.long 0x00 11. " PktDrpSts ," "0,1" bitfld.long 0x00 9. " BNAIntr ," "0,1" newline bitfld.long 0x00 8. " OutPktErr ," "0,1" bitfld.long 0x00 6. " Back2BackSETup ," "0,1" bitfld.long 0x00 5. " StsPhseRcvd ," "0,1" newline bitfld.long 0x00 4. " OUTTknEPdis ," "0,1" bitfld.long 0x00 3. " SetUp ," "0,1" bitfld.long 0x00 2. " AHBErr ," "0,1" newline bitfld.long 0x00 1. " EPDisbld ," "0,1" bitfld.long 0x00 0. " XferCompl ," "0,1" group.long 0xC70++0x3 line.long 0x00 "USBC0_TSIZ_OEP11_D,USBC0 Device OUT Endpoint n Transfer Size Register" bitfld.long 0x00 29.--30. " RxDPID ," "0,1,2,3" hexmask.long.word 0x00 19.--28. 1. " PktCnt ," hexmask.long.tbyte 0x00 0.--18. 1. " XferSize ," group.long 0xC74++0x3 line.long 0x00 "USBC0_DMA_ADDR_OEP11_D,USBC0 Device OUT Endpoint n DMA Address Register" group.long 0xC7C++0x3 line.long 0x00 "USBC0_DMA_BADDR_OEP11_D,USBC0 Device OUT Endpoint n Buffer Address Register" group.long 0xE00++0x3 line.long 0x00 "USBC0_PWR_CTL,USBC0 Power and clock gating control Register" bitfld.long 0x00 7. " L1Suspended ," "0,1" bitfld.long 0x00 6. " PhySleep ," "0,1" bitfld.long 0x00 3. " RstPdwnModule ," "0,1" newline bitfld.long 0x00 0. " StopPclk ," "0,1" tree.end tree "WDOG (Watchdog Timer)" tree "WDOG0" base ad:0x31008000 width 12. group.long 0x0++0x3 line.long 0x00 "WDOG0_CTL,WDOG0 Control Register" bitfld.long 0x00 16. " WDWE ,Watchdog Window Event" "0,1" bitfld.long 0x00 15. " WDRO ,Watch Dog Rollover" "0,1" hexmask.long.byte 0x00 4.--11. 1. " WDEN ,Watch Dog Enable" group.long 0x4++0x3 line.long 0x00 "WDOG0_CNT,WDOG0 Count Register" group.long 0x8++0x3 line.long 0x00 "WDOG0_STAT,WDOG0 Watchdog Timer Status Register" group.long 0xC++0x3 line.long 0x00 "WDOG0_WIN,WDOG0 Watchdog Timer Window Register" tree.end tree "WDOG1" base ad:0x31008800 width 12. group.long 0x0++0x3 line.long 0x00 "WDOG1_CTL,WDOG1 Control Register" bitfld.long 0x00 16. " WDWE ,Watchdog Window Event" "0,1" bitfld.long 0x00 15. " WDRO ,Watch Dog Rollover" "0,1" hexmask.long.byte 0x00 4.--11. 1. " WDEN ,Watch Dog Enable" group.long 0x4++0x3 line.long 0x00 "WDOG1_CNT,WDOG1 Count Register" group.long 0x8++0x3 line.long 0x00 "WDOG1_STAT,WDOG1 Watchdog Timer Status Register" group.long 0xC++0x3 line.long 0x00 "WDOG1_WIN,WDOG1 Watchdog Timer Window Register" tree.end tree "WDOG2" base ad:0x31009000 width 12. group.long 0x0++0x3 line.long 0x00 "WDOG2_CTL,WDOG2 Control Register" bitfld.long 0x00 16. " WDWE ,Watchdog Window Event" "0,1" bitfld.long 0x00 15. " WDRO ,Watch Dog Rollover" "0,1" hexmask.long.byte 0x00 4.--11. 1. " WDEN ,Watch Dog Enable" group.long 0x4++0x3 line.long 0x00 "WDOG2_CNT,WDOG2 Count Register" group.long 0x8++0x3 line.long 0x00 "WDOG2_STAT,WDOG2 Watchdog Timer Status Register" group.long 0xC++0x3 line.long 0x00 "WDOG2_WIN,WDOG2 Watchdog Timer Window Register" tree.end tree.end newline