; --------------------------------------------------------------------------------
; @Title: RIN32M4CL2 Specific Menu
; @Props: Released
; @Author: PIW
; @Changelog: 2022-03-07 PIW
; @Manufacturer: RENESAS - Renesas Technology Corp.
; @Core: Cortex-M4F
; @Chip: R9J03G019GBG
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menrin32m4cl2.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit"                       "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "ADC"              "per , ""ADC (A/D Converter)"""
popup "CAN"
(
menuitem "CAN0"         "per , ""CAN,CAN0"""
menuitem "CAN1"         "per , ""CAN,CAN1"""
)
menuitem "CC_LINK"          "per , ""CC_LINK (CC-Link)"""
menuitem "CC_LINK_BR"       "per , ""CC_LINK_BR (CC-Link BUS Control)"""
menuitem "CC_LINK_IEF_BR"   "per , ""CC_LINK_IEF_BR (CC-Link IE Field BUS Control)"""
menuitem "CC_LINK_RMT"      "per , ""CC_LINK_RMT (CC-Link Remote Device Station)"""
popup "CSI"
(
menuitem "CSI0"         "per , ""CSI,CSI0"""
menuitem "CSI1"         "per , ""CSI,CSI1"""
)
popup "DMAC (DMA controller)"
(
menuitem "DMAC0"        "per , ""DMAC (DMA controller),DMAC0"""
menuitem "DMAC1"        "per , ""DMAC (DMA controller),DMAC1"""
menuitem "DMAC2"        "per , ""DMAC (DMA controller),DMAC2"""
menuitem "DMAC3"        "per , ""DMAC (DMA controller),DMAC3"""
menuitem "RTDMAC"       "per , ""DMAC (DMA controller),RTDMAC"""
)
popup "DMACCTL (DMA control)"
(
menuitem "DCTL"         "per , ""DMACCTL (DMA control),DCTL"""
menuitem "RTDCTL"       "per , ""DMACCTL (DMA control),RTDCTL"""
)
popup "DMACSS (DMAC space source size)"
(
menuitem "DSS0"         "per , ""DMACSS (DMAC space source size),DSS0"""
menuitem "DSS1"         "per , ""DMACSS (DMAC space source size),DSS1"""
menuitem "DSS2"         "per , ""DMACSS (DMAC space source size),DSS2"""
menuitem "DSS3"         "per , ""DMACSS (DMAC space source size),DSS3"""
menuitem "RTDSS"        "per , ""DMACSS (DMAC space source size),RTDSS"""
)
menuitem "ETH"              "per , ""ETH (Ethernet MAC)"""
menuitem "ETHSW"            "per , ""ETHSW (Ethernet Switch)"""
menuitem "EXTPORT"          "per , ""EXTPORT (Port (EXTPORT))"""
menuitem "GPIO"             "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
menuitem "HWOS"             "per , ""HWOS (Hardware Real Time OS)"""
popup "IIC"
(
menuitem "IIC0"         "per , ""IIC,IIC0"""
menuitem "IIC1"         "per , ""IIC,IIC1"""
)
menuitem "MEMC"             "per , ""MEMC (Memory controller (ROM/SRAM))"""
menuitem "PIC"              "per , ""PIC (Peripheral Inter Connection)"""
menuitem "QINT_BUFID"       "per , ""QINT_BUFID (Receive Buffer Information)"""
menuitem "RTPORT"           "per , ""RTPORT (Port (RTPORT))"""
menuitem "SMC"              "per , ""SMC (Burst memory controller)"""
menuitem "SROM"             "per , ""SROM (Serial flash ROM memory controller)"""
menuitem "SYS"              "per , ""SYS (System)"""
menuitem "TAPA"             "per , ""TAPA (Motor control unit)"""
menuitem "TAUD"             "per , ""TAUD (Timer Array Unit D)"""
menuitem "TAUJ2"            "per , ""TIMER0 (Timer array unit(TAUJ2))"""
popup "UART (Universal Asynchronous Receiver/Transmitter)"
(
menuitem "UART0"        "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART0"""
menuitem "UART1"        "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
)
menuitem "WDT"              "per , ""WDT (Watchdog Timer Unit)"""
)
)