; -------------------------------------------------------------------------------- ; @Title: QN909x Specific Menu ; @Props: Released ; @Author: KMB, DAB ; @Changelog: 2021-07-30 KMB ; 2022-01-27 DAB ; @Manufacturer: NXP - NXP Semiconductors ; @Core: Cortex-M4 ; @Chip: QN9030HN, QN9030THN, QN9090HN, QN9090THN ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menqn909x.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-M4)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4),Nested Vectored Interrupt Controller""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) separator menuitem "ADC0" "per , ""ADC""" menuitem "AES0" "per , ""AES""" menuitem "ASYNC_SYSCON" "per , ""ASYNC_SYSCON """ menuitem "BLE_DP_TOP" "per , ""BLE_DP_TOP""" menuitem "CIC_IRB" "per , ""CIC_IRB""" popup "CTIMER" ( menuitem "CTIMER0" "per , ""CTIMER,CTIMER0""" menuitem "CTIMER1" "per , ""CTIMER,CTIMER1""" ) menuitem "DMA0" "per , ""DMA (dma)""" menuitem "DMIC0" "per , ""DMIC""" menuitem "FLASH" "per , ""FLASH""" popup "FLEXCOMM (LPC5411x Flexcomm serial communication)" ( menuitem "FLEXCOMM0" "per , ""FLEXCOMM (LPC5411x Flexcomm serial communication),FLEXCOMM0""" menuitem "FLEXCOMM1" "per , ""FLEXCOMM (LPC5411x Flexcomm serial communication),FLEXCOMM1""" menuitem "FLEXCOMM2" "per , ""FLEXCOMM (LPC5411x Flexcomm serial communication),FLEXCOMM2""" menuitem "FLEXCOMM3" "per , ""FLEXCOMM (LPC5411x Flexcomm serial communication),FLEXCOMM3""" menuitem "FLEXCOMM4" "per , ""FLEXCOMM (LPC5411x Flexcomm serial communication),FLEXCOMM4""" menuitem "FLEXCOMM5" "per , ""FLEXCOMM (LPC5411x Flexcomm serial communication),FLEXCOMM5""" menuitem "FLEXCOMM6" "per , ""FLEXCOMM (LPC5411x Flexcomm serial communication),FLEXCOMM6""" ) menuitem "GINT0" "per , ""GINT""" menuitem "GPIO" "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)""" popup "I2C (Inter-Integrated Circuit)" ( menuitem "I2C0" "per , ""I2C (Inter-Integrated Circuit),I2C0""" menuitem "I2C1" "per , ""I2C (Inter-Integrated Circuit),I2C1""" menuitem "I2C2" "per , ""I2C (Inter-Integrated Circuit),I2C2""" ) menuitem "INPUTMUX" "per , ""INPUTMUX""" menuitem "IOCON" "per , ""IOCON (I/O pin configuration (IOCON))""" menuitem "ISO7816" "per , ""ISO7816""" menuitem "OTPC" "per , ""OTPC""" menuitem "PINT" "per , ""PINT""" menuitem "PMC" "per , ""PMC""" menuitem "PWM" "per , ""PWM (Pulse-Width Modulator)""" menuitem "RNG" "per , ""RNG (Random Number Generator)""" menuitem "RTC" "per , ""RTC (Real-time Counter)""" menuitem "SHA0" "per , ""SHA""" popup "SPI" ( menuitem "SPI0" "per , ""SPI,SPI0""" menuitem "SPI1" "per , ""SPI,SPI1""" ) menuitem "SPIFI" "per , ""SPIFI""" menuitem "SYSCON" "per , ""SYSCON""" popup "USART" ( menuitem "USART0" "per , ""USART,USART0""" menuitem "USART1" "per , ""USART,USART1""" ) menuitem "WWDT" "per , ""WWDT""" ) )