; --------------------------------------------------------------------------------
; @Title: PSoC 4200 Specific Menu
; @Props: Released
; @Author: KWI, DAB
; @Changelog: 2019-02-05 KWI
;             2022-01-21 DAB
; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
; @Core: Cortex-M0
; @Chip: CY8C4244AXI-443, CY8C4244AXQ-443, CY8C4244AZI-443, CY8C4244FNI-443,
;        CY8C4244LQI-443, CY8C4244LQQ-443, CY8C4244PVI-432, CY8C4244PVI-442,
;        CY8C4244PVQ-432, CY8C4244PVQ-442, CY8C4245AXI-473, CY8C4245AXI-483,
;        CY8C4245AXQ-473, CY8C4245AXQ-483, CY8C4245AZI-473, CY8C4245AZI-483,
;        CY8C4245FNI-483, CY8C4245LQI-483, CY8C4245LQQ-483, CY8C4245PVI-482,
;        CY8C4245PVQ-482
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menpsoc4200.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M0)"
(
menuitem "[:chip]System Control"                                 "per , ""Core Registers (Cortex-M0),System Control"""
menuitem "[:chip]Nested Vectored Interrupt Controller"           "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                  "per , ""Core Registers (Cortex-M0),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit"                         "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"          "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "CLK"                      "per , ""CLK (Programmable clocks)"""
menuitem "CM0"                      "per , ""CM0 (Cortex-M0 System Bus (ARM PPB Peripherals))"""
menuitem "CORESIGHTTABLE_DATA"      "per , ""CORESIGHTTABLE_DATA (No description available)"""
menuitem "CPUSS"                    "per , ""CPUSS (CPU Subsystem)"""
menuitem "CSD"                      "per , ""CSD (Capsense Controller)"""
menuitem "CTBM"                     "per , ""CTBM (Continuous Time Block Mini)"""
menuitem "HSIOM"                    "per , ""HSIOM (High-Speed IO-Matrix for PSOC4A)"""
menuitem "LCD"                      "per , ""LCD (LCD Controller Block)"""
menuitem "LPCOMP"                   "per , ""LPCOMP (Low-power Comparator)"""
popup "PRT (GPIO Port Registers)"
(
menuitem "PRT0"                 "per , ""PRT (GPIO Port Registers),PRT0"""
menuitem "PRT1"                 "per , ""PRT (GPIO Port Registers),PRT1"""
menuitem "PRT2"                 "per , ""PRT (GPIO Port Registers),PRT2"""
menuitem "PRT3"                 "per , ""PRT (GPIO Port Registers),PRT3"""
menuitem "PRT4"                 "per , ""PRT (GPIO Port Registers),PRT4"""
)
menuitem "SAR"                      "per , ""SAR (SAR ADC with Sequencer)"""
popup "SCB (Serial Communications Block (SPI/UART/I2C))"
(
menuitem "SCB0"                 "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB0"""
menuitem "SCB1"                 "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB1"""
)
menuitem "SFLASH"                   "per , ""SFLASH (Supervisory Flash Area (Cypress Trim & Wounding Info))"""
menuitem "SPCIF"                    "per , ""SPCIF (Flash Control Interface)"""
menuitem "SROM_DATA"                "per , ""SROM_DATA (No description available)"""
menuitem "SRSS"                     "per , ""SRSS (SRSSv2 Registers (Power Clock Reset))"""
menuitem "TCPWM"                    "per , ""TCPWM (Quad Timer/Counter/PWM)"""
popup "TCPWM_CNT (Timer/Counter/PWM Counter Module)"
(
menuitem "TCPWM_CNT0"           "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT0"""
menuitem "TCPWM_CNT1"           "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT1"""
menuitem "TCPWM_CNT2"           "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT2"""
menuitem "TCPWM_CNT3"           "per , ""TCPWM_CNT (Timer/Counter/PWM Counter Module),TCPWM_CNT3"""
)
menuitem "TST"                      "per , ""TST (Test Subsystem)"""
menuitem "UDB"                      "per , ""UDB (Programmable Digital Subsystem)"""
menuitem "UDB_BCTL0"                "per , ""UDB_BCTL0 (UDB Array Bank Control)"""
popup "UDB_DSI (DSI Configuration (16 DSI))"
(
menuitem "UDB_DSI0"             "per , ""UDB_DSI (DSI Configuration (16 DSI)),UDB_DSI0"""
menuitem "UDB_DSI1"             "per , ""UDB_DSI (DSI Configuration (16 DSI)),UDB_DSI1"""
menuitem "UDB_DSI2"             "per , ""UDB_DSI (DSI Configuration (16 DSI)),UDB_DSI2"""
menuitem "UDB_DSI3"             "per , ""UDB_DSI (DSI Configuration (16 DSI)),UDB_DSI3"""
)
menuitem "UDB_P0_ROUTE"             "per , ""UDB_P0_ROUTE (Routing Configuration for one UDB Pair)"""
popup "UDB_P0_U (Single UDB Configuration)"
(
menuitem "UDB_P0_U0"            "per , ""UDB_P0_U (Single UDB Configuration),UDB_P0_U0"""
menuitem "UDB_P0_U1"            "per , ""UDB_P0_U (Single UDB Configuration),UDB_P0_U1"""
)
menuitem "UDB_P1_ROUTE"             "per , ""UDB_P1_ROUTE (Routing Configuration for one UDB Pair)"""
popup "UDB_P1_U (Single UDB Configuration)"
(
menuitem "UDB_P1_U0"            "per , ""UDB_P1_U (Single UDB Configuration),UDB_P1_U0"""
menuitem "UDB_P1_U1"            "per , ""UDB_P1_U (Single UDB Configuration),UDB_P1_U1"""
)
popup "UDB_PA (Port Adapter Configuration)"
(
menuitem "UDB_PA0"              "per , ""UDB_PA (Port Adapter Configuration),UDB_PA0"""
menuitem "UDB_PA1"              "per , ""UDB_PA (Port Adapter Configuration),UDB_PA1"""
menuitem "UDB_PA2"              "per , ""UDB_PA (Port Adapter Configuration),UDB_PA2"""
menuitem "UDB_PA3"              "per , ""UDB_PA (Port Adapter Configuration),UDB_PA3"""
)
menuitem "UDB_UDBIF"                "per , ""UDB_UDBIF (UDB Subsystem Interface Configuration)"""
popup "UDB_W (UDB Working Registers 8-bit mode (1 UDB at a time))"
(
menuitem "UDB_W8"               "per , ""UDB_W (UDB Working Registers 8-bit mode (1 UDB at a time)),UDB_W8"""
menuitem "UDB_W16"              "per , ""UDB_W (UDB Working Registers 8-bit mode (1 UDB at a time)),UDB_W16"""
menuitem "UDB_W32"              "per , ""UDB_W (UDB Working Registers 8-bit mode (1 UDB at a time)),UDB_W32"""
)
)
)