; -------------------------------------------------------------------------------- ; @Title: OMAP4460 Specific Menu ; @Props: Released ; @Author: KAM, LEM, SLA, PIW ; @Changelog: ; 2011-08-31 ; 2011-12-13 ; 2012-04-18 ; 2022-05-12 PIW ; @Manufacturer: TI - Texas Instruments ; @Core: Cortex-A9, Cortex-A9MPCore ; @Chip: OMAP4460 ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menomap4460app.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( if (CORENAME()=="CORTEXA9MPCORE") ( popup "[:chip]Core Registers (Cortex-A9MPCore)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A9MPCore),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),System Control and Configuration""" menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A9MPCore),Memory Management Unit""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A9MPCore),Cache Control and Configuration""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A9MPCore),System Performance Monitor""" menuitem "[:chip]Preload Engine" "per , ""Core Registers (Cortex-A9MPCore),Preload Engine""" menuitem "[:chip]NEON" "per , ""Core Registers (Cortex-A9MPCore),NEON""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A9MPCore),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A9MPCore),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A9MPCore),Watchpoint Control Registers""" separator menuitem "[:chip]Snoop Control Unit (SCU)" "per , ""Core Registers (Cortex-A9MPCore),Snoop Control Unit (SCU)""" menuitem "[:chip]Distributed Interrupt Controller" "per , ""Core Registers (Cortex-A9MPCore),Distributed Interrupt Controller""" menuitem "[:chip]Interface Registers" "per , ""Core Registers (Cortex-A9MPCore),Interface Registers""" menuitem "[:chip]Timer and Watchdog Blocks" "per , ""Core Registers (Cortex-A9MPCore),Timer and Watchdog Blocks""" ) ) else ( popup "[:chip]Core Registers (Cortex-A9)" ( menuitem "[:chip]ID Registers" "per , ""Core Registers (Cortex-A9),ID Registers""" menuitem "[:chip]System Control and Configuration" "per , ""Core Registers (Cortex-A9),System Control and Configuration""" menuitem "[:chip]Memory Management Unit" "per , ""Core Registers (Cortex-A9),Memory Management Unit""" menuitem "[:chip]Cache Control and Configuration" "per , ""Core Registers (Cortex-A9),Cache Control and Configuration""" menuitem "[:chip]L2 Preload Engine" "per , ""Core Registers (Cortex-A9),L2 Preload Engine""" menuitem "[:chip]System Performance Monitor" "per , ""Core Registers (Cortex-A9),System Performance Monitor""" separator menuitem "[:chip]Debug Registers" "per , ""Core Registers (Cortex-A9),Debug Registers""" menuitem "[:chip]Breakpoint Registers" "per , ""Core Registers (Cortex-A9),Breakpoint Registers""" menuitem "[:chip]Watchpoint Control Registers" "per , ""Core Registers (Cortex-A9),Watchpoint Control Registers""" ) ) separator popup "_32_kHz_Synchronized_Timer" ( menuitem "_32KTimer" "per , ""_32_kHz_Synchronized_Timer,_32KTimer""" ) popup "C2C" ( menuitem "C2C" "per , ""C2C,C2C""" menuitem "ICR_MDM" "per , ""C2C,ICR_MDM""" menuitem "ICR_MPU" "per , ""C2C,ICR_MPU""" ) popup "Control_Module" ( menuitem "SYSCTRL_GENERAL_CORE" "per , ""Control_Module,SYSCTRL_GENERAL_CORE""" menuitem "SYSCTRL_GENERAL_WKUP" "per , ""Control_Module,SYSCTRL_GENERAL_WKUP""" menuitem "SYSCTRL_PADCONF_CORE" "per , ""Control_Module,SYSCTRL_PADCONF_CORE""" menuitem "SYSCTRL_PADCONF_WKUP" "per , ""Control_Module,SYSCTRL_PADCONF_WKUP""" ) popup "Digital_Microphone_Module" ( menuitem "DMIC_Cortex_A9" "per , ""Digital_Microphone_Module,DMIC_Cortex_A9""" menuitem "DMIC_L3Interconnect" "per , ""Digital_Microphone_Module,DMIC_L3Interconnect""" ) popup "Display_Controller" ( menuitem "DISPC_L3" "per , ""Display_Controller,DISPC_L3""" menuitem "DISPC_L4_PER" "per , ""Display_Controller,DISPC_L4_PER""" ) popup "Display_Subsystem" ( menuitem "DSS_L3" "per , ""Display_Subsystem,DSS_L3""" menuitem "DSS_L4_PER" "per , ""Display_Subsystem,DSS_L4_PER""" ) popup "Dual_Cortex_A9_MPU_Subsystem" ( menuitem "CORTEXA9_CPU0" "per , ""Dual_Cortex_A9_MPU_Subsystem,CORTEXA9_CPU0""" menuitem "CORTEXA9_CPU1" "per , ""Dual_Cortex_A9_MPU_Subsystem,CORTEXA9_CPU1""" menuitem "CORTEXA9_PRM" "per , ""Dual_Cortex_A9_MPU_Subsystem,CORTEXA9_PRM""" menuitem "CORTEXA9_SOCKET_PRCM" "per , ""Dual_Cortex_A9_MPU_Subsystem,CORTEXA9_SOCKET_PRCM""" menuitem "CORTEXA9_WUGEN" "per , ""Dual_Cortex_A9_MPU_Subsystem,CORTEXA9_WUGEN""" ) popup "Dual_Cortex_M3_MPU_Subsystem" ( menuitem "CM3_RW_Table" "per , ""Dual_Cortex_M3_MPU_Subsystem,CM3_RW_Table""" menuitem "CORTEXM3_WKUP" "per , ""Dual_Cortex_M3_MPU_Subsystem,CORTEXM3_WKUP""" ) popup "Dynamic_Memory_Manager" ( menuitem "DMM" "per , ""Dynamic_Memory_Manager,DMM""" ) popup "EMIF_Controller" ( menuitem "EMIF1" "per , ""EMIF_Controller,EMIF1""" menuitem "EMIF2" "per , ""EMIF_Controller,EMIF2""" ) popup "Error_Location_Module" ( menuitem "ELM" "per , ""Error_Location_Module,ELM""" ) popup "Face_Detect" ( menuitem "FDIF" "per , ""Face_Detect,FDIF""" ) popup "Full_Speed_USB_Host_Controller" ( menuitem "USBFSHOST" "per , ""Full_Speed_USB_Host_Controller,USBFSHOST""" ) popup "General_Purpose_Interface" ( menuitem "GPIO2" "per , ""General_Purpose_Interface,GPIO2""" menuitem "GPIO3" "per , ""General_Purpose_Interface,GPIO3""" menuitem "GPIO4" "per , ""General_Purpose_Interface,GPIO4""" menuitem "GPIO5" "per , ""General_Purpose_Interface,GPIO5""" menuitem "GPIO6" "per , ""General_Purpose_Interface,GPIO6""" menuitem "GPIO1" "per , ""General_Purpose_Interface,GPIO1""" ) popup "General_Purpose_Memory_Controller" ( menuitem "GPMC" "per , ""General_Purpose_Memory_Controller,GPMC""" ) popup "General_Purpose_Timers" ( menuitem "GPTIMER10_L4Interconnect" "per , ""General_Purpose_Timers,GPTIMER10_L4Interconnect""" menuitem "GPTIMER1_L4Interconnect" "per , ""General_Purpose_Timers,GPTIMER1_L4Interconnect""" menuitem "GPTIMER2_L4Interconnect" "per , ""General_Purpose_Timers,GPTIMER2_L4Interconnect""" menuitem "GPTIMER11_L4Interconnect" "per , ""General_Purpose_Timers,GPTIMER11_L4Interconnect""" menuitem "GPTIMER3_L4Interconnect" "per , ""General_Purpose_Timers,GPTIMER3_L4Interconnect""" menuitem "GPTIMER4_L4Interconnect" "per , ""General_Purpose_Timers,GPTIMER4_L4Interconnect""" menuitem "GPTIMER5_Cortex_A9" "per , ""General_Purpose_Timers,GPTIMER5_Cortex_A9""" menuitem "GPTIMER5_L3Interconnect" "per , ""General_Purpose_Timers,GPTIMER5_L3Interconnect""" menuitem "GPTIMER6_Cortex_A9" "per , ""General_Purpose_Timers,GPTIMER6_Cortex_A9""" menuitem "GPTIMER6_L3Interconnect" "per , ""General_Purpose_Timers,GPTIMER6_L3Interconnect""" menuitem "GPTIMER7_Cortex_A9" "per , ""General_Purpose_Timers,GPTIMER7_Cortex_A9""" menuitem "GPTIMER7_L3Interconnect" "per , ""General_Purpose_Timers,GPTIMER7_L3Interconnect""" menuitem "GPTIMER8_Cortex_A9" "per , ""General_Purpose_Timers,GPTIMER8_Cortex_A9""" menuitem "GPTIMER8_L3Interconnect" "per , ""General_Purpose_Timers,GPTIMER8_L3Interconnect""" menuitem "GPTIMER9_L4Interconnect" "per , ""General_Purpose_Timers,GPTIMER9_L4Interconnect""" ) popup "HDQ_1_Wire" ( menuitem "HDQ_1_Wire" "per , ""HDQ_1_Wire,HDQ_1_Wire""" ) popup "High_Speed_Multiport_USB_Host_Subsystem" ( menuitem "EHCI" "per , ""High_Speed_Multiport_USB_Host_Subsystem,EHCI""" menuitem "HSUSBHOST" "per , ""High_Speed_Multiport_USB_Host_Subsystem,HSUSBHOST""" menuitem "OHCI" "per , ""High_Speed_Multiport_USB_Host_Subsystem,OHCI""" menuitem "USBTLLHS_config" "per , ""High_Speed_Multiport_USB_Host_Subsystem,USBTLLHS_config""" ) popup "High_Speed_USB_OTG_Controller" ( menuitem "HSUSBOTG" "per , ""High_Speed_USB_OTG_Controller,HSUSBOTG""" menuitem "OCP2SCP" "per , ""High_Speed_USB_OTG_Controller,OCP2SCP""" menuitem "USBPHY" "per , ""High_Speed_USB_OTG_Controller,USBPHY""" ) popup "HSI" ( menuitem "HSI_PORTS" "per , ""HSI,HSI_PORTS""" menuitem "HSI_TOP" "per , ""HSI,HSI_TOP""" ) popup "ISS_Interfaces" ( menuitem "ISS_BTE" "per , ""ISS_Interfaces,ISS_BTE""" menuitem "ISS_CAMERARX_CORE1" "per , ""ISS_Interfaces,ISS_CAMERARX_CORE1""" menuitem "ISS_CAMERARX_CORE2" "per , ""ISS_Interfaces,ISS_CAMERARX_CORE2""" menuitem "ISS_CBUFF" "per , ""ISS_Interfaces,ISS_CBUFF""" menuitem "ISS_CCP2" "per , ""ISS_Interfaces,ISS_CCP2""" menuitem "ISS_CSI2_A_REGS1" "per , ""ISS_Interfaces,ISS_CSI2_A_REGS1""" menuitem "ISS_CSI2_B_REGS1" "per , ""ISS_Interfaces,ISS_CSI2_B_REGS1""" menuitem "ISS_TCTRL" "per , ""ISS_Interfaces,ISS_TCTRL""" ) popup "ISS_ISP" ( menuitem "ISS_H3A" "per , ""ISS_ISP,ISS_H3A""" menuitem "ISS_IPIPE" "per , ""ISS_ISP,ISS_IPIPE""" menuitem "ISS_IPIPEIF" "per , ""ISS_ISP,ISS_IPIPEIF""" menuitem "ISS_ISIF" "per , ""ISS_ISP,ISS_ISIF""" menuitem "ISS_ISP5_SYS1" "per , ""ISS_ISP,ISS_ISP5_SYS1""" menuitem "ISS_ISP5_SYS2" "per , ""ISS_ISP,ISS_ISP5_SYS2""" menuitem "ISS_RESIZER" "per , ""ISS_ISP,ISS_RESIZER""" ) popup "ISS_Overview" ( menuitem "ISS_TOP" "per , ""ISS_Overview,ISS_TOP""" ) popup "ISS_SIMCOP_Discrete_Cosine_Transform_Module" ( menuitem "DCT_Cortex_M3" "per , ""ISS_SIMCOP_Discrete_Cosine_Transform_Module,DCT_Cortex_M3""" menuitem "DCT_L3Interconnect" "per , ""ISS_SIMCOP_Discrete_Cosine_Transform_Module,DCT_L3Interconnect""" ) popup "ISS_SIMCOP_DMA_Module" ( menuitem "DMA_L3Interconnect" "per , ""ISS_SIMCOP_DMA_Module,DMA_L3Interconnect""" ) popup "ISS_SIMCOP_Hardware_Sequencer_and_Buffers" ( menuitem "HWSEQ_Cortex_M3" "per , ""ISS_SIMCOP_Hardware_Sequencer_and_Buffers,HWSEQ_Cortex_M3""" menuitem "HWSEQ_L3Interconnect" "per , ""ISS_SIMCOP_Hardware_Sequencer_and_Buffers,HWSEQ_L3Interconnect""" ) popup "ISS_SIMCOP_Overview" ( menuitem "SIMCOP_CONTROL_L3Interconnect" "per , ""ISS_SIMCOP_Overview,SIMCOP_CONTROL_L3Interconnect""" ) popup "ISS_SIMCOP_Rotation_Accelerator_Module" ( menuitem "ROT_L3Interconnect" "per , ""ISS_SIMCOP_Rotation_Accelerator_Module,ROT_L3Interconnect""" ) popup "ISS_SIMCOP_Variable_Length_Coder_Decoder_for_JPEG_Module" ( menuitem "VLCDJ_L3Interconnect" "per , ""ISS_SIMCOP_Variable_Length_Coder_Decoder_for_JPEG_Module,VLCDJ_L3Interconnect""" ) popup "IVA_HD_Overview" ( menuitem "SYSCTRL_L3Interconnect" "per , ""IVA_HD_Overview,SYSCTRL_L3Interconnect""" ) popup "Keyboard_Controller" ( menuitem "Keyboard_Controller" "per , ""Keyboard_Controller,Keyboard_Controller""" ) popup "L3_Interconnect" ( menuitem "C2C_Master_NIU_Firewall" "per , ""L3_Interconnect,C2C_Master_NIU_Firewall""" menuitem "C2C_Slave_NIU_Firewall" "per , ""L3_Interconnect,C2C_Slave_NIU_Firewall""" menuitem "CLK1_CLK1_TARG_PWR_DISC_CLK2" "per , ""L3_Interconnect,CLK1_CLK1_TARG_PWR_DISC_CLK2""" menuitem "CLK2_CLK2_TARG_PWR_DISC_CLK1" "per , ""L3_Interconnect,CLK2_CLK2_TARG_PWR_DISC_CLK1""" menuitem "CLK1_ABE_TARG" "per , ""L3_Interconnect,CLK1_ABE_TARG""" menuitem "CLK1_DMM1_TARG" "per , ""L3_Interconnect,CLK1_DMM1_TARG""" menuitem "CLK1_DMM2_TARG" "per , ""L3_Interconnect,CLK1_DMM2_TARG""" menuitem "CLK1_L4CFG_TARG" "per , ""L3_Interconnect,CLK1_L4CFG_TARG""" menuitem "CLK2_C2C_TARG" "per , ""L3_Interconnect,CLK2_C2C_TARG""" menuitem "CLK2_CORTEXM3_TARG" "per , ""L3_Interconnect,CLK2_CORTEXM3_TARG""" menuitem "CLK2_DSS_TARG" "per , ""L3_Interconnect,CLK2_DSS_TARG""" menuitem "CLK2_GPMC_TARG" "per , ""L3_Interconnect,CLK2_GPMC_TARG""" menuitem "CLK2_ISS_TARG" "per , ""L3_Interconnect,CLK2_ISS_TARG""" menuitem "CLK2_IVAHD_TARG" "per , ""L3_Interconnect,CLK2_IVAHD_TARG""" menuitem "CLK2_L4PER0_TARG" "per , ""L3_Interconnect,CLK2_L4PER0_TARG""" menuitem "CLK2_L4PER1_TARG" "per , ""L3_Interconnect,CLK2_L4PER1_TARG""" menuitem "CLK2_L4PER2_TARG" "per , ""L3_Interconnect,CLK2_L4PER2_TARG""" menuitem "CLK2_L4PER3_TARG" "per , ""L3_Interconnect,CLK2_L4PER3_TARG""" menuitem "CLK2_OCMRAM_TARG" "per , ""L3_Interconnect,CLK2_OCMRAM_TARG""" menuitem "CLK2_SGX_TARG" "per , ""L3_Interconnect,CLK2_SGX_TARG""" menuitem "CLK2_SL2_TARG" "per , ""L3_Interconnect,CLK2_SL2_TARG""" menuitem "CLK3_L4EMU_TARG" "per , ""L3_Interconnect,CLK3_L4EMU_TARG""" menuitem "CLK1_DSS_BW_REGULATOR" "per , ""L3_Interconnect,CLK1_DSS_BW_REGULATOR""" menuitem "CLK2_ISS_BW_REGULATOR" "per , ""L3_Interconnect,CLK2_ISS_BW_REGULATOR""" menuitem "CLK2_IVAHD_BW_REGULATOR" "per , ""L3_Interconnect,CLK2_IVAHD_BW_REGULATOR""" menuitem "CLK2_SGX_BW_REGULATOR" "per , ""L3_Interconnect,CLK2_SGX_BW_REGULATOR""" menuitem "CLK1_FLAGMUX_CLK1" "per , ""L3_Interconnect,CLK1_FLAGMUX_CLK1""" menuitem "CLK2_FLAGMUX_CLK2" "per , ""L3_Interconnect,CLK2_FLAGMUX_CLK2""" menuitem "CLK3_FLAGMUX_CLK3" "per , ""L3_Interconnect,CLK3_FLAGMUX_CLK3""" menuitem "CLK1_HOST_CLK1" "per , ""L3_Interconnect,CLK1_HOST_CLK1""" menuitem "CLK2_HOST_CLK2" "per , ""L3_Interconnect,CLK2_HOST_CLK2""" menuitem "CLK3_HOST_CLK3" "per , ""L3_Interconnect,CLK3_HOST_CLK3""" menuitem "CLK1_RATE_ADAPT_RESP_32TO128_CLK1" "per , ""L3_Interconnect,CLK1_RATE_ADAPT_RESP_32TO128_CLK1""" menuitem "CLK2_RATE_ADAPT_RESP_32TO128_CLK2" "per , ""L3_Interconnect,CLK2_RATE_ADAPT_RESP_32TO128_CLK2""" menuitem "CLK3_STATCOLL_LAT0" "per , ""L3_Interconnect,CLK3_STATCOLL_LAT0""" menuitem "CLK3_STATCOLL_LAT1" "per , ""L3_Interconnect,CLK3_STATCOLL_LAT1""" menuitem "CLK3_STATCOLL_SDRAM" "per , ""L3_Interconnect,CLK3_STATCOLL_SDRAM""" menuitem "Debug_Firewall" "per , ""L3_Interconnect,Debug_Firewall""" menuitem "GPMC_Firewall" "per , ""L3_Interconnect,GPMC_Firewall""" menuitem "L3_RAM_Firewall" "per , ""L3_Interconnect,L3_RAM_Firewall""" menuitem "EMIF_Firewall" "per , ""L3_Interconnect,EMIF_Firewall""" menuitem "MA_Firewall" "per , ""L3_Interconnect,MA_Firewall""" menuitem "DSS_Firewall" "per , ""L3_Interconnect,DSS_Firewall""" menuitem "Dual_Cortex_M3_Firewall" "per , ""L3_Interconnect,Dual_Cortex_M3_Firewall""" menuitem "ISS_Firewall" "per , ""L3_Interconnect,ISS_Firewall""" menuitem "IVA_HD_Firewall" "per , ""L3_Interconnect,IVA_HD_Firewall""" menuitem "L4_ABE_Firewall" "per , ""L3_Interconnect,L4_ABE_Firewall""" menuitem "SGX_Firewall" "per , ""L3_Interconnect,SGX_Firewall""" menuitem "SL2_Firewall" "per , ""L3_Interconnect,SL2_Firewall""" ) popup "L4_Interconnects" ( menuitem "CFG_AP" "per , ""L4_Interconnects,CFG_AP""" menuitem "PER_AP" "per , ""L4_Interconnects,PER_AP""" menuitem "CFG_IA_0" "per , ""L4_Interconnects,CFG_IA_0""" menuitem "PER_IA_0" "per , ""L4_Interconnects,PER_IA_0""" menuitem "WKUP_IA_0" "per , ""L4_Interconnects,WKUP_IA_0""" menuitem "CFG_LA" "per , ""L4_Interconnects,CFG_LA""" menuitem "PER_LA" "per , ""L4_Interconnects,PER_LA""" menuitem "WKUP_LA" "per , ""L4_Interconnects,WKUP_LA""" menuitem "CFG_TA_ABEFW" "per , ""L4_Interconnects,CFG_TA_ABEFW""" menuitem "CFG_TA_CM1" "per , ""L4_Interconnects,CFG_TA_CM1""" menuitem "CFG_TA_CM2" "per , ""L4_Interconnects,CFG_TA_CM2""" menuitem "CFG_TA_CORTEXM3FW" "per , ""L4_Interconnects,CFG_TA_CORTEXM3FW""" menuitem "CFG_TA_DSP" "per , ""L4_Interconnects,CFG_TA_DSP""" menuitem "CFG_TA_DSSFW" "per , ""L4_Interconnects,CFG_TA_DSSFW""" menuitem "CFG_TA_EMIFFW" "per , ""L4_Interconnects,CFG_TA_EMIFFW""" menuitem "CFG_TA_EMUSSFW" "per , ""L4_Interconnects,CFG_TA_EMUSSFW""" menuitem "CFG_TA_FACEDETECT" "per , ""L4_Interconnects,CFG_TA_FACEDETECT""" menuitem "CFG_TA_GPMCFW" "per , ""L4_Interconnects,CFG_TA_GPMCFW""" menuitem "CFG_TA_HSI" "per , ""L4_Interconnects,CFG_TA_HSI""" menuitem "CFG_TA_HSUSBTLL" "per , ""L4_Interconnects,CFG_TA_HSUSBTLL""" menuitem "CFG_TA_ISSFW" "per , ""L4_Interconnects,CFG_TA_ISSFW""" menuitem "CFG_TA_IVAHDFW" "per , ""L4_Interconnects,CFG_TA_IVAHDFW""" menuitem "CFG_TA_L4WKUP" "per , ""L4_Interconnects,CFG_TA_L4WKUP""" menuitem "CFG_TA_MAFW" "per , ""L4_Interconnects,CFG_TA_MAFW""" menuitem "CFG_TA_MAILBOX" "per , ""L4_Interconnects,CFG_TA_MAILBOX""" menuitem "CFG_TA_OCMCRAMFW" "per , ""L4_Interconnects,CFG_TA_OCMCRAMFW""" menuitem "CFG_TA_SAR_ROM" "per , ""L4_Interconnects,CFG_TA_SAR_ROM""" menuitem "CFG_TA_SDMA" "per , ""L4_Interconnects,CFG_TA_SDMA""" menuitem "CFG_TA_SGXFW" "per , ""L4_Interconnects,CFG_TA_SGXFW""" menuitem "CFG_TA_SL2FW" "per , ""L4_Interconnects,CFG_TA_SL2FW""" menuitem "CFG_TA_SPINLOCK" "per , ""L4_Interconnects,CFG_TA_SPINLOCK""" menuitem "CFG_TA_SR1" "per , ""L4_Interconnects,CFG_TA_SR1""" menuitem "CFG_TA_SR2" "per , ""L4_Interconnects,CFG_TA_SR2""" menuitem "CFG_TA_SR3" "per , ""L4_Interconnects,CFG_TA_SR3""" menuitem "CFG_TA_SYSCTRL_GENERAL_CORE" "per , ""L4_Interconnects,CFG_TA_SYSCTRL_GENERAL_CORE""" menuitem "CFG_TA_SYSCTRL_PADCONF_CORE" "per , ""L4_Interconnects,CFG_TA_SYSCTRL_PADCONF_CORE""" menuitem "CFG_TA_USBFS" "per , ""L4_Interconnects,CFG_TA_USBFS""" menuitem "CFG_TA_USBHOSTHS" "per , ""L4_Interconnects,CFG_TA_USBHOSTHS""" menuitem "CFG_TA_USBOTGHS" "per , ""L4_Interconnects,CFG_TA_USBOTGHS""" menuitem "CFG_TA_USBPHY" "per , ""L4_Interconnects,CFG_TA_USBPHY""" menuitem "PER_TA_DSS" "per , ""L4_Interconnects,PER_TA_DSS""" menuitem "PER_TA_ELM" "per , ""L4_Interconnects,PER_TA_ELM""" menuitem "PER_TA_GPIO2" "per , ""L4_Interconnects,PER_TA_GPIO2""" menuitem "PER_TA_GPIO3" "per , ""L4_Interconnects,PER_TA_GPIO3""" menuitem "PER_TA_GPIO4" "per , ""L4_Interconnects,PER_TA_GPIO4""" menuitem "PER_TA_GPIO5" "per , ""L4_Interconnects,PER_TA_GPIO5""" menuitem "PER_TA_GPIO6" "per , ""L4_Interconnects,PER_TA_GPIO6""" menuitem "PER_TA_GPTIMER2" "per , ""L4_Interconnects,PER_TA_GPTIMER2""" menuitem "PER_TA_GPTIMER3" "per , ""L4_Interconnects,PER_TA_GPTIMER3""" menuitem "PER_TA_GPTIMER4" "per , ""L4_Interconnects,PER_TA_GPTIMER4""" menuitem "PER_TA_GPTIMER9" "per , ""L4_Interconnects,PER_TA_GPTIMER9""" menuitem "PER_TA_GPTIMER10" "per , ""L4_Interconnects,PER_TA_GPTIMER10""" menuitem "PER_TA_GPTIMER11" "per , ""L4_Interconnects,PER_TA_GPTIMER11""" menuitem "PER_TA_HDQ" "per , ""L4_Interconnects,PER_TA_HDQ""" menuitem "PER_TA_HSMMC1" "per , ""L4_Interconnects,PER_TA_HSMMC1""" menuitem "PER_TA_HSMMC3" "per , ""L4_Interconnects,PER_TA_HSMMC3""" menuitem "PER_TA_HSMMC2" "per , ""L4_Interconnects,PER_TA_HSMMC2""" menuitem "PER_TA_HSMMC4" "per , ""L4_Interconnects,PER_TA_HSMMC4""" menuitem "PER_TA_HSMMC5" "per , ""L4_Interconnects,PER_TA_HSMMC5""" menuitem "PER_TA_I2C1" "per , ""L4_Interconnects,PER_TA_I2C1""" menuitem "PER_TA_I2C2" "per , ""L4_Interconnects,PER_TA_I2C2""" menuitem "PER_TA_I2C4" "per , ""L4_Interconnects,PER_TA_I2C4""" menuitem "PER_TA_I2C3" "per , ""L4_Interconnects,PER_TA_I2C3""" menuitem "PER_TA_MCBSP4" "per , ""L4_Interconnects,PER_TA_MCBSP4""" menuitem "PER_TA_MCSPI1" "per , ""L4_Interconnects,PER_TA_MCSPI1""" menuitem "PER_TA_MCSPI2" "per , ""L4_Interconnects,PER_TA_MCSPI2""" menuitem "PER_TA_MCSPI3" "per , ""L4_Interconnects,PER_TA_MCSPI3""" menuitem "PER_TA_MCSPI4" "per , ""L4_Interconnects,PER_TA_MCSPI4""" menuitem "PER_TA_SLIMBUS2" "per , ""L4_Interconnects,PER_TA_SLIMBUS2""" menuitem "PER_TA_UART1" "per , ""L4_Interconnects,PER_TA_UART1""" menuitem "PER_TA_UART2" "per , ""L4_Interconnects,PER_TA_UART2""" menuitem "PER_TA_UART4" "per , ""L4_Interconnects,PER_TA_UART4""" menuitem "PER_TA_UART3" "per , ""L4_Interconnects,PER_TA_UART3""" menuitem "WKUP_TA_32KTIMER" "per , ""L4_Interconnects,WKUP_TA_32KTIMER""" menuitem "WKUP_TA_DM_TIMER1MS_1" "per , ""L4_Interconnects,WKUP_TA_DM_TIMER1MS_1""" menuitem "WKUP_TA_GPIO1" "per , ""L4_Interconnects,WKUP_TA_GPIO1""" menuitem "WKUP_TA_KEYBOARD" "per , ""L4_Interconnects,WKUP_TA_KEYBOARD""" menuitem "WKUP_TA_PRM" "per , ""L4_Interconnects,WKUP_TA_PRM""" menuitem "WKUP_TA_SAR_RAM" "per , ""L4_Interconnects,WKUP_TA_SAR_RAM""" menuitem "WKUP_TA_SCRM" "per , ""L4_Interconnects,WKUP_TA_SCRM""" menuitem "WKUP_TA_SYSCTRL_GENERAL_WKUP" "per , ""L4_Interconnects,WKUP_TA_SYSCTRL_GENERAL_WKUP""" menuitem "WKUP_TA_SYSCTRL_PADCONF_WKUP" "per , ""L4_Interconnects,WKUP_TA_SYSCTRL_PADCONF_WKUP""" menuitem "WKUP_TA_WDTIMER2" "per , ""L4_Interconnects,WKUP_TA_WDTIMER2""" ) popup "Mailbox" ( menuitem "IVAHD_Mailbox_L3Interconnect" "per , ""Mailbox,IVAHD_Mailbox_L3Interconnect""" menuitem "System_Mailbox_L4_CFGInterconnect" "per , ""Mailbox,System_Mailbox_L4_CFGInterconnect""" ) popup "MIPI_Display_Serial_Interface" ( menuitem "DSI1_PHY_L3" "per , ""MIPI_Display_Serial_Interface,DSI1_PHY_L3""" menuitem "DSI1_PHY_L4_PER" "per , ""MIPI_Display_Serial_Interface,DSI1_PHY_L4_PER""" menuitem "DSI2_PHY_L3" "per , ""MIPI_Display_Serial_Interface,DSI2_PHY_L3""" menuitem "DSI2_PHY_L4_PER" "per , ""MIPI_Display_Serial_Interface,DSI2_PHY_L4_PER""" menuitem "DSI1_PLLCTRL_L3" "per , ""MIPI_Display_Serial_Interface,DSI1_PLLCTRL_L3""" menuitem "DSI1_PLLCTRL_L4_PER" "per , ""MIPI_Display_Serial_Interface,DSI1_PLLCTRL_L4_PER""" menuitem "DSI2_PLLCTRL_L3" "per , ""MIPI_Display_Serial_Interface,DSI2_PLLCTRL_L3""" menuitem "DSI2_PLLCTRL_L4_PER" "per , ""MIPI_Display_Serial_Interface,DSI2_PLLCTRL_L4_PER""" menuitem "DSI1_PROTOCOL_ENGINE_L3" "per , ""MIPI_Display_Serial_Interface,DSI1_PROTOCOL_ENGINE_L3""" menuitem "DSI1_PROTOCOL_ENGINE_L4_PER" "per , ""MIPI_Display_Serial_Interface,DSI1_PROTOCOL_ENGINE_L4_PER""" menuitem "DSI2_PROTOCOL_ENGINE_L3" "per , ""MIPI_Display_Serial_Interface,DSI2_PROTOCOL_ENGINE_L3""" menuitem "DSI2_PROTOCOL_ENGINE_L4_PER" "per , ""MIPI_Display_Serial_Interface,DSI2_PROTOCOL_ENGINE_L4_PER""" ) popup "MMC_SD_SDIO" ( menuitem "MMCHS1" "per , ""MMC_SD_SDIO,MMCHS1""" menuitem "MMCHS2" "per , ""MMC_SD_SDIO,MMCHS2""" menuitem "MMCHS3" "per , ""MMC_SD_SDIO,MMCHS3""" menuitem "MMCHS4" "per , ""MMC_SD_SDIO,MMCHS4""" menuitem "MMCHS5" "per , ""MMC_SD_SDIO,MMCHS5""" ) popup "MMU" ( menuitem "CORTEXM3_L2MMU" "per , ""MMU,CORTEXM3_L2MMU""" menuitem "DSP_MMU" "per , ""MMU,DSP_MMU""" ) popup "Multichannel_Audio_Serial_Port" ( menuitem "McASP_Cortex_A9" "per , ""Multichannel_Audio_Serial_Port,McASP_Cortex_A9""" menuitem "McASP_L3Interconnect" "per , ""Multichannel_Audio_Serial_Port,McASP_L3Interconnect""" ) popup "Multichannel_Buffered_Serial_Port_McBSP" ( menuitem "MCBSP1_Cortex_A9" "per , ""Multichannel_Buffered_Serial_Port_McBSP,MCBSP1_Cortex_A9""" menuitem "MCBSP1_L3Interconnect" "per , ""Multichannel_Buffered_Serial_Port_McBSP,MCBSP1_L3Interconnect""" menuitem "MCBSP2_Cortex_A9" "per , ""Multichannel_Buffered_Serial_Port_McBSP,MCBSP2_Cortex_A9""" menuitem "MCBSP2_L3Interconnect" "per , ""Multichannel_Buffered_Serial_Port_McBSP,MCBSP2_L3Interconnect""" menuitem "MCBSP3_Cortex_A9" "per , ""Multichannel_Buffered_Serial_Port_McBSP,MCBSP3_Cortex_A9""" menuitem "MCBSP3_L3Interconnect" "per , ""Multichannel_Buffered_Serial_Port_McBSP,MCBSP3_L3Interconnect""" menuitem "MCBSP4_L4_PERInterconnect" "per , ""Multichannel_Buffered_Serial_Port_McBSP,MCBSP4_L4_PERInterconnect""" ) popup "Multichannel_PDM_Controller" ( menuitem "McPDM_Cortex_A9" "per , ""Multichannel_PDM_Controller,McPDM_Cortex_A9""" menuitem "McPDM_L3Interconnect" "per , ""Multichannel_PDM_Controller,McPDM_L3Interconnect""" ) popup "Multichannel_Serial_Port_Interface" ( menuitem "MCSPI1" "per , ""Multichannel_Serial_Port_Interface,MCSPI1""" menuitem "MCSPI2" "per , ""Multichannel_Serial_Port_Interface,MCSPI2""" menuitem "MCSPI3" "per , ""Multichannel_Serial_Port_Interface,MCSPI3""" menuitem "MCSPI4" "per , ""Multichannel_Serial_Port_Interface,MCSPI4""" ) popup "Multimaster_High_Speed_I2C_Controller" ( menuitem "I2C3" "per , ""Multimaster_High_Speed_I2C_Controller,I2C3""" menuitem "I2C1" "per , ""Multimaster_High_Speed_I2C_Controller,I2C1""" menuitem "I2C2" "per , ""Multimaster_High_Speed_I2C_Controller,I2C2""" menuitem "I2C4" "per , ""Multimaster_High_Speed_I2C_Controller,I2C4""" ) popup "PRCM" ( menuitem "ABE_CM1" "per , ""PRCM,ABE_CM1""" menuitem "ABE_PRM" "per , ""PRCM,ABE_PRM""" menuitem "ALWAYS_ON_CM2" "per , ""PRCM,ALWAYS_ON_CM2""" menuitem "ALWAYS_ON_PRM" "per , ""PRCM,ALWAYS_ON_PRM""" menuitem "CAM_CM2" "per , ""PRCM,CAM_CM2""" menuitem "CAM_PRM" "per , ""PRCM,CAM_PRM""" menuitem "CKGEN_CM1" "per , ""PRCM,CKGEN_CM1""" menuitem "CKGEN_PRM" "per , ""PRCM,CKGEN_PRM""" menuitem "CORE_CM2" "per , ""PRCM,CORE_CM2""" menuitem "CORE_PRM" "per , ""PRCM,CORE_PRM""" menuitem "DEVICE_PRM" "per , ""PRCM,DEVICE_PRM""" menuitem "DSP_CM1" "per , ""PRCM,DSP_CM1""" menuitem "DSP_PRM" "per , ""PRCM,DSP_PRM""" menuitem "DSS_CM2" "per , ""PRCM,DSS_CM2""" menuitem "DSS_PRM" "per , ""PRCM,DSS_PRM""" menuitem "EMU_CM" "per , ""PRCM,EMU_CM""" menuitem "EMU_PRM" "per , ""PRCM,EMU_PRM""" menuitem "INSTR_PRM" "per , ""PRCM,INSTR_PRM""" menuitem "INTRCONN_SOCKET_CM1" "per , ""PRCM,INTRCONN_SOCKET_CM1""" menuitem "INTRCONN_SOCKET_CM2" "per , ""PRCM,INTRCONN_SOCKET_CM2""" menuitem "INTRCONN_SOCKET_PRM" "per , ""PRCM,INTRCONN_SOCKET_PRM""" menuitem "IVAHD_CM2" "per , ""PRCM,IVAHD_CM2""" menuitem "IVAHD_PRM" "per , ""PRCM,IVAHD_PRM""" menuitem "L3INIT_CM2" "per , ""PRCM,L3INIT_CM2""" menuitem "L3INIT_PRM" "per , ""PRCM,L3INIT_PRM""" menuitem "L4PER_CM2" "per , ""PRCM,L4PER_CM2""" menuitem "L4PER_PRM" "per , ""PRCM,L4PER_PRM""" menuitem "MPU_CM1" "per , ""PRCM,MPU_CM1""" menuitem "MPU_PRM" "per , ""PRCM,MPU_PRM""" menuitem "RESTORE_CM1" "per , ""PRCM,RESTORE_CM1""" menuitem "SCRM" "per , ""PRCM,SCRM""" menuitem "SGX_CM2" "per , ""PRCM,SGX_CM2""" menuitem "SGX_PRM" "per , ""PRCM,SGX_PRM""" menuitem "SR_CORE" "per , ""PRCM,SR_CORE""" menuitem "SR_IVA" "per , ""PRCM,SR_IVA""" menuitem "SR_MPU" "per , ""PRCM,SR_MPU""" menuitem "WKUP_CM" "per , ""PRCM,WKUP_CM""" menuitem "WKUP_PRM" "per , ""PRCM,WKUP_PRM""" ) popup "Remote_Frame_Buffer_Interface" ( menuitem "RFBI_L3" "per , ""Remote_Frame_Buffer_Interface,RFBI_L3""" menuitem "RFBI_L4_PER" "per , ""Remote_Frame_Buffer_Interface,RFBI_L4_PER""" ) popup "SDMA_Module_Overview" ( menuitem "SDMA" "per , ""SDMA_Module_Overview,SDMA""" ) popup "Serial_Low_Power_Inter_Chip_Media_Bus_Controller" ( menuitem "SLIMBUS1_Cortex_A9" "per , ""Serial_Low_Power_Inter_Chip_Media_Bus_Controller,SLIMBUS1_Cortex_A9""" menuitem "SLIMBUS1_L3Interconnect" "per , ""Serial_Low_Power_Inter_Chip_Media_Bus_Controller,SLIMBUS1_L3Interconnect""" menuitem "SLIMBUS2_L3Interconnect" "per , ""Serial_Low_Power_Inter_Chip_Media_Bus_Controller,SLIMBUS2_L3Interconnect""" ) popup "SGX_Overview" ( menuitem "SGX" "per , ""SGX_Overview,SGX""" ) popup "Spinlock" ( menuitem "Spinlock" "per , ""Spinlock,Spinlock""" ) popup "UART_IrDA_CIR" ( menuitem "UART3" "per , ""UART_IrDA_CIR,UART3""" menuitem "UART1" "per , ""UART_IrDA_CIR,UART1""" menuitem "UART2" "per , ""UART_IrDA_CIR,UART2""" menuitem "UART4" "per , ""UART_IrDA_CIR,UART4""" ) popup "Video_Encoder" ( menuitem "VENC_L3" "per , ""Video_Encoder,VENC_L3""" menuitem "VENC_L4_PER" "per , ""Video_Encoder,VENC_L4_PER""" ) popup "Watchdog_Timers" ( menuitem "WDTIMER2_L4Interconnect" "per , ""Watchdog_Timers,WDTIMER2_L4Interconnect""" menuitem "WDTIMER3_Cortex_A9" "per , ""Watchdog_Timers,WDTIMER3_Cortex_A9""" menuitem "WDTIMER3_L3Interconnect" "per , ""Watchdog_Timers,WDTIMER3_L3Interconnect""" ) ) )