; -------------------------------------------------------------------------------- ; @Title: iMX23 On-Chip Peripherals ; @Props: Released ; @Author: MAV, PAC ; @Changelog: 2010-03-08 ; @Manufacturer: NXP ; @Doc: IMX23RMrev1.pdf (2009-08-13) ; @Core: ARM926EJ-S ; @Chip: IMX23 ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permcimx23.per 7592 2017-02-18 13:54:14Z askoncej $ config 16. 8. tree "ARM Core Registers" AUTOINDENT.PUSH AUTOINDENT.OFF width 8. tree "ID Registers" group c15:0x0000--0x0000 line.long 0x0 "MIDR,Identity Code" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer" hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision" hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision" group c15:0x0100--0x0100 line.long 0x0 "CTR,Cache Type" bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f" bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes" textline " " bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..." bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128" bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1" bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16" textline " " bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..." bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128" bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1" bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16" group c15:0x0200--0x0200 line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register" bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes" bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes" tree.end tree "MMU Control and Configuration" width 8. group c15:0x0001--0x0001 line.long 0x0 "CR,Control Register" bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable" bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin" bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable" bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable" bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable" bitfld.long 0x0 7. " B ,Endianism" "Little,Big" textline " " bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable" bitfld.long 0x0 0. " M ,MMU" "Disable,Enable" textline " " group c15:0x0002--0x0002 line.long 0x0 "TTBR,Translation Table Base Register" hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address" textline " " group c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group c15:0x0005--0x0005 line.long 0x0 "DFSR,Data Fault Status Register" bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page" group c15:0x0105--0x0105 line.long 0x0 "IFSR,Instruction Fault Status Register" bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page" group c15:0x0006--0x0006 line.long 0x0 "DFAR,Data Fault Address Register" textline " " group c15:0x000a--0x000a line.long 0x0 "TLBR,TLB Lockdown Register" bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. " P ,P bit" "0,1" textline " " group c15:0x000d--0x000d line.long 0x0 "FCSEPID,FCSE Process ID" group c15:0x010d--0x010d line.long 0x0 "CONTEXT,Context ID" tree.end tree "Cache Control and Configuration" group c15:0x0009--0x0009 line.long 0x0 "DCACHE,Data Cache Lockdown" bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1" bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1" bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1" bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1" group c15:0x0109--0x0109 line.long 0x0 "ICACHE,Instruction Cache Lockdown" bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1" bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1" bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1" bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1" tree.end tree "TCM Control and Configuration" group c15:0x0019--0x0019 line.long 0x0 "DTCM,Data TCM Region Register" hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address" bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res" bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable" group c15:0x0119--0x0119 line.long 0x0 "ITCM,Instruction TCM Region Register" hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address" bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res" bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable" tree.end tree "Test and Debug" group c15:0x000f--0x000f line.long 0x0 "DOVRR,Debug Override Register" bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable" bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort" bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort" textline " " bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable" bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable" bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable" bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT" group c15:0x001f--0x001f line.long 0x0 "ADDRESS,Debug/Test Address" ;wgroup c15:0x402f--0x402f ; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry" ;wgroup c15:0x403f--0x403f ; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry" ;wgroup c15:0x404f--0x404f ; line.long 0x0 "RMTLBPA,Read PA in main TLB entry" ;wgroup c15:0x405f--0x405f ; line.long 0x0 "WMTLBPA,Write PA in main TLB entry" ;wgroup c15:0x407f--0x407f ; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM" ;wgroup c15:0x412f--0x412f ; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry" ;wgroup c15:0x413f--0x413f ; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry" ;wgroup c15:0x414f--0x414f ; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry" ;wgroup c15:0x415f--0x415f ; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry" ;wgroup c15:0x417f--0x417f ; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM" group c15:0x101f--0x101f line.long 0x0 "TRACE,Trace Control" bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall" bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall" group c15:0x700f--0x700f line.long 0x0 "CACHE,Cache Debug Control" bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through" bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable" bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable" group c15:0x701f--0x701f line.long 0x0 "MMU,MMU Debug Control" bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable" bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable" bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable" bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable" textline " " bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable" bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable" bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable" bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable" group c15:0x002f--0x002f line.long 0x0 "REMAP,Memory Region Remap" bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB" bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB" textline " " bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB" bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB" tree.end tree "ICEbreaker" width 8. group ice:0x0--0x5 "Debug Control" line.long 0x0 "DBGCTRL,Debug Control Register" bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled" bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled" textline " " bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled" bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled" bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x4 "DBGSTAT,Debug Status Register" bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res" bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java" bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb" bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1" bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled" bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x8 "VECTOR,Vector Catch Register" bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena" bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena" bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena" bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena" bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena" bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena" bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena" line.long 0x10 "COMCTRL,Debug Communication Control Register" bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend" bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend" line.long 0x14 "COMDATA,Debug Communication Data Register" group ice:0x8--0x0d "Watchpoint 0" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" group ice:0x10--0x15 "Watchpoint 1" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" tree.end AUTOINDENT.POP tree.end tree "CLKCTL (Clock Controller)" base asd:0x80040000 width 25. group.long 0x00++0x13 line.long 0x00 "HW_CLKCTRL_PLLCTRL0,HW_CLKCTRL PLL Control Register 0" bitfld.long 0x00 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x00 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" textline " " bitfld.long 0x00 18. " EN_USB_CLKS ,USB Clocks Enable" "Disabled,Enabled" bitfld.long 0x00 16. " POWER ,PLL Power bit" "Off,On" line.long 0x04 "HW_CLKCTRL_PLLCTRL0_SET, HW_CLKCTRL PLL Control Register 0 Set" bitfld.long 0x04 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,?..." bitfld.long 0x04 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,?..." textline " " bitfld.long 0x04 18. " EN_USB_CLKS ,USB Clock Enable" "No effect,Set" bitfld.long 0x04 16. " POWER ,Power Enable" "No effect,Set" line.long 0x08 "HW_CLKCTRL_PLLCTRL0_CLR, HW_CLKCTRL PLL Control Register 0 Clear" bitfld.long 0x08 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,?..." bitfld.long 0x08 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,?..." textline " " bitfld.long 0x08 18. " EN_USB_CLKS ,USB Clock Enable" "No effect,Cleared" bitfld.long 0x08 16. " POWER ,PLL Power bit" "No effect,Cleared" line.long 0x0c "HW_CLKCTRL_PLLCTRL0_TOG, HW_CLKCTRL PLL Control Register 0 Toggle" bitfld.long 0x0c 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,?..." bitfld.long 0x0c 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,?..." textline " " bitfld.long 0x0c 18. " EN_USB_CLKS ,USB Clock Enable" "Not toggle,Toggle" bitfld.long 0x0c 16. " POWER ,PLL Power bit" "Not toggle,Toggle" line.long 0x10 "HW_CLKCTRL_PLLCTRL1,HW_CLKCTRL PLL Control Register 1" bitfld.long 0x10 31. " LOCK ,PLL Lock bit" "Unlocked,Locked" bitfld.long 0x10 30. " FORCE_LOCK ,Force PLL Lock" "Not forced,Forced" textline " " hexmask.long.word 0x10 0.--15. 1. " LOCK_COUNT ,Status of the PLL lock count" group.long 0x20++0x0f line.long 0x00 "HW_CLKCTRL_CPU, CPU Clock Control Register" bitfld.long 0x00 29. " BUSY_REF_XTAL ,Clock Divider XTAL Busy" "Not busy,Busy" bitfld.long 0x00 28. " BUSY_REF_CPU ,Clock Divider CPU Busy" "Not busy,Busy" textline " " bitfld.long 0x00 26. " DIV_XTAL_FRAC_EN ,Fractional Divide Enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " DIV_XTAL ,XTAL Divider" textline " " bitfld.long 0x00 12. " INTERRUPT_WAIT ,Interrupt Wait" "Not gated,Gated" bitfld.long 0x00 0.--5. " DIV_CPU ,CPU Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x04 "HW_CLKCTRL_CPU_SET, CPU Clock Control Register Set" bitfld.long 0x04 29. " BUSY_REF_XTAL ,Clock Divider XTAL " "No effect,Set" bitfld.long 0x04 28. " BUSY_REF_CPU ,Clock Divider CPU " "No effect,Set" textline " " bitfld.long 0x04 26. " DIV_XTAL_FRAC_EN ,Fractional Divide " "No effect,Set" hexmask.long.word 0x04 16.--25. 1. " DIV_XTAL ,XTAL Divider" textline " " bitfld.long 0x04 12. " INTERRUPT_WAIT ,Interrupt " "No effect,Set" bitfld.long 0x04 0.--5. " DIV_CPU ,CPU Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x08 "HW_CLKCTRL_CPU_CLR, CPU Clock Control Register Clear" bitfld.long 0x08 29. " BUSY_REF_XTAL ,Clock Divider XTAL " "No effect,Cleared" bitfld.long 0x08 28. " BUSY_REF_CPU ,Clock Divider CPU " "No effect,Cleared" textline " " bitfld.long 0x08 26. " DIV_XTAL_FRAC_EN ,Fractional Divide " "No effect,Cleared" hexmask.long.word 0x08 16.--25. 1. " DIV_XTAL ,XTAL Divider" textline " " bitfld.long 0x08 12. " INTERRUPT_WAIT ,Interrupt Gate" "No effect,Cleared" bitfld.long 0x08 0.--5. " DIV_CPU ,CPU Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" line.long 0x0c "HW_CLKCTRL_CPU_TOG, CPU Clock Control Register Toggle" bitfld.long 0x0c 29. " BUSY_REF_XTAL ,Clock Divider XTAL " "Not toggle,Toggle" bitfld.long 0x0c 28. " BUSY_REF_CPU ,Clock Divider CPU " "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " DIV_XTAL_FRAC_EN ,Fractional Divide " "Not toggle,Toggle" hexmask.long.word 0x0c 16.--25. 1. " DIV_XTAL ,XTAL Divider" textline " " bitfld.long 0x0c 12. " INTERRUPT_WAIT ,Interrupt Wait" "Not toggle,Toggle" bitfld.long 0x0c 0.--5. " DIV_CPU ,CPU Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" if (((d.l(asd:(0x80040000+0xa0)))&0x40000000)==0x0) group.long 0x30++0x0f line.long 0x00 "HW_CLKCTRL_HBUS,AHB/APBH Bus Clock Control Register" bitfld.long 0x00 29. " BUSY ,HBUS Busy" "Not busy,Busy" bitfld.long 0x00 28. " DCP_AS_ENABLE ,Auto-slow mode based on DCP activity" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " PXP_AS_ENABLE ,Auto-slow mode based on PXP activity" "Disabled,Enabled" bitfld.long 0x00 26. " APBHDMA_AS_ENABLE ,Auto-slow mode based on APBH DMA activity" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " APBXDMA_AS_ENABLE ,Auto-slow mode based on APBX DMA activity" "Disabled,Enabled" bitfld.long 0x00 24. " TRAFFIC_JAM_AS_ENABLE ,Auto-slow mode when less than three masters are trying to use the AHB" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " TRAFFIC_AS_ENABLE ,Auto-slow mode based on AHB master activity" "Disabled,Enabled" bitfld.long 0x00 22. " CPU_DATA_AS_ENABLE ,Auto-slow mode based on with CPU Data access to AHB" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " CPU_INSTR_AS_ENABLE ,Auto-slow mode based on with CPU Instruction access to AHB" "Disabled,Enabled" bitfld.long 0x00 20. " AUTO_SLOW_MODE ,CLK_H auto-slow mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--18. " SLOW_DIV ,Slow mode divide ratio" "1,2,4,8,16,32,?..." bitfld.long 0x00 5. " DIV_FRAC_EN ,Fractional Divide Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--4. " DIV ,CLK_P-to-CLK_H divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x04 "HW_CLKCTRL_HBUS_SET,Clock Control HBUS Set Register" bitfld.long 0x04 29. " BUSY ,HBUS Busy " "No effect,Set" bitfld.long 0x04 28. " DCP_AS_ENABLE ,Auto-slow mode based on DCP activity" "No effect,Set" textline " " bitfld.long 0x04 27. " PXP_AS_ENABLE ,Auto-slow mode based on PXP activity" "No effect,Set" bitfld.long 0x04 26. " APBHDMA_AS_ENABLE ,Auto-slow mode based on APBH DMA activity" "No effect,Set" textline " " bitfld.long 0x04 25. " APBXDMA_AS_ENABLE ,Auto-slow mode based on APBX DMA activity" "No effect,Set" bitfld.long 0x04 24. " TRAFFIC_JAM_AS_ENABLE ,Auto-slow mode when less than three masters are trying to use the AHB" "No effect,Set" textline " " bitfld.long 0x04 23. " TRAFFIC_AS_ENABLE ,Auto-slow mode based on AHB master activity" "No effect,Set" bitfld.long 0x04 22. " CPU_DATA_AS_ENABLE ,Auto-slow mode based on with CPU Data access to AHB" "No effect,Set" textline " " bitfld.long 0x04 21. " CPU_INSTR_AS_ENABLE ,Auto-slow mode based on with CPU Instruction access to AHB" "No effect,Set" bitfld.long 0x04 20. " AUTO_SLOW_MODE ,CLK_H auto-slow mode Enable " "No effect,Set" textline " " bitfld.long 0x04 16.--18. " SLOW_DIV ,Slow mode divide ratio" "1,2,4,8,16,32,?..." bitfld.long 0x04 5. " DIV_FRAC_EN ,Fractional Divide Enable " "No effect,Set" textline " " bitfld.long 0x04 0.--4. " DIV ,CLK_P-to-CLK_H divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "HW_CLKCTRL_HBUS_CLR,Clock Control HBUS Clear Register" bitfld.long 0x08 29. " BUSY ,HBUS Busy " "No effect,Cleared" bitfld.long 0x08 28. " DCP_AS_ENABLE ,Auto-slow mode based on DCP activity" "No effect,Cleared" textline " " bitfld.long 0x08 27. " PXP_AS_ENABLE ,Auto-slow mode based on PXP activity" "No effect,Cleared" bitfld.long 0x08 26. " APBHDMA_AS_ENABLE ,Auto-slow mode based on APBH DMA activity" "No effect,Cleared" textline " " bitfld.long 0x08 25. " APBXDMA_AS_ENABLE ,Auto-slow mode based on APBX DMA activity" "No effect,Cleared" bitfld.long 0x08 24. " TRAFFIC_JAM_AS_ENABLE ,Auto-slow mode when less than three masters are trying to use the AHB" "No effect,Cleared" textline " " bitfld.long 0x08 23. " TRAFFIC_AS_ENABLE ,Auto-slow mode based on AHB master activity" "No effect,Cleared" bitfld.long 0x08 22. " CPU_DATA_AS_ENABLE ,Auto-slow mode based on with CPU Data access to AHB" "No effect,Cleared" textline " " bitfld.long 0x08 21. " CPU_INSTR_AS_ENABLE ,Auto-slow mode based on with CPU Instruction access to AHB" "No effect,Cleared" bitfld.long 0x08 20. " AUTO_SLOW_MODE ,CLK_H auto-slow mode Enable " "No effect,Cleared" textline " " bitfld.long 0x08 16.--18. " SLOW_DIV ,Slow mode divide ratio" "1,2,4,8,16,32,?..." bitfld.long 0x08 5. " DIV_FRAC_EN ,Fractional Divide Enable " "No effect,Cleared" textline " " bitfld.long 0x08 0.--4. " DIV ,CLK_P-to-CLK_H divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x0c "HW_CLKCTRL_HBUS_TOG,Clock Control HBUS Toggle Register" bitfld.long 0x0c 29. " BUSY ,HBUS Busy " "Not toggle,Toggle" bitfld.long 0x0c 28. " DCP_AS_ENABLE ,Auto-slow mode based on DCP activity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " PXP_AS_ENABLE ,Auto-slow mode based on PXP activity" "Not toggle,Toggle" bitfld.long 0x0c 26. " APBHDMA_AS_ENABLE ,Auto-slow mode based on APBH DMA activity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " APBXDMA_AS_ENABLE ,Auto-slow mode based on APBX DMA activity" "Not toggle,Toggle" bitfld.long 0x0c 24. " TRAFFIC_JAM_AS_ENABLE ,Auto-slow mode when less than three masters are trying to use the AHB" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " TRAFFIC_AS_ENABLE ,Auto-slow mode based on AHB master activity" "Not toggle,Toggle" bitfld.long 0x0c 22. " CPU_DATA_AS_ENABLE ,Auto-slow mode based on with CPU Data access to AHB" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " CPU_INSTR_AS_ENABLE ,Auto-slow mode based on with CPU Instruction access to AHB" "Not toggle,Toggle" bitfld.long 0x0c 20. " AUTO_SLOW_MODE ,CLK_H auto-slow mode Enable " "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--18. " SLOW_DIV ,Slow mode divide ratio" "1,2,4,8,16,32,?..." bitfld.long 0x0c 5. " DIV_FRAC_EN ,Fractional Divide Enable " "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--4. " DIV ,CLK_P-to-CLK_H divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else hgroup.long 0x30++0x0f hide.long 0x00 "HW_CLKCTRL_HBUS,Clock Control HBUS Register" hide.long 0x04 "HW_CLKCTRL_HBUS_SET,Clock Control HBUS Set Register" hide.long 0x08 "HW_CLKCTRL_HBUS,Clock Control HBUS Clear Register" hide.long 0x0c "HW_CLKCTRL_HBUS,Clock Control HBUS Toggle Register" endif group.long 0x40++0x03 line.long 0x00 "HW_CLKCTRL_XBUS,APBX Clock Control Register" bitfld.long 0x00 31. " BUSY ,APBX Clock Busy" "Not busy,Busy" hexmask.long.word 0x00 0.--9. 1. " DIV ,CLK_X divide ratio" group.long 0x50++0x13 line.long 0x00 "HW_CLKCTRL_XTAL,XTAL Clock Control Register" bitfld.long 0x00 31. " UART_CLK_GATE ,UART Clock Gate" "Not gated,Gated off" bitfld.long 0x00 30. " FILT_CLK24M_GATE ,Digital Filter Clock Gate" "Not gated,Gated off" textline " " bitfld.long 0x00 29. " PWM_CLK24M_GATE ,PWM Clock Gate" "Not gated,Gated off" bitfld.long 0x00 28. " DRI_CLK24M_GATE ,DRI Clock Gate" "Not gated,Gated off" textline " " bitfld.long 0x00 27. " DIGCTRL_CLK1M_GATE ,DIGCTRL Clock Gate" "Not gated,Gated off" bitfld.long 0x00 26. " TIMROT_CLK32K_GATE ,TIMROT Clock Gate" "Not gated,Gated off" line.long 0x04 "HW_CLKCTRL_XTAL_SET,XTAL Clock Control Set Register" bitfld.long 0x04 31. " UART_CLK_GATE ,UART Clock Gate " "No effect,Set" bitfld.long 0x04 30. " FILT_CLK24M_GATE ,Digital Filter Clock Gate " "No effect,Set" textline " " bitfld.long 0x04 29. " PWM_CLK24M_GATE ,PWM Clock Gate " "No effect,Set" bitfld.long 0x04 28. " DRI_CLK24M_GATE ,DRI Clock Gate " "No effect,Set" textline " " bitfld.long 0x04 27. " DIGCTRL_CLK1M_GATE ,DIGCTRL Clock Gate " "No effect,Set" bitfld.long 0x04 26. " TIMROT_CLK32K_GATE ,TIMROT Clock Gate " "No effect,Set" line.long 0x08 "HW_CLKCTRL_XTAL_CLR,XTAL Clock Control Clear Register" bitfld.long 0x08 31. " UART_CLK_GATE ,UART Clock Gate " "No effect,Cleared" bitfld.long 0x08 30. " FILT_CLK24M_GATE ,Digital Filter Clock Gate " "No effect,Cleared" textline " " bitfld.long 0x08 29. " PWM_CLK24M_GATE ,PWM Clock Gate " "No effect,Cleared" bitfld.long 0x08 28. " DRI_CLK24M_GATE ,DRI Clock Gate " "No effect,Cleared" textline " " bitfld.long 0x08 27. " DIGCTRL_CLK1M_GATE ,DIGCTRL Clock Gate " "No effect,Cleared" bitfld.long 0x08 26. " TIMROT_CLK32K_GATE ,TIMROT Clock Gate " "No effect,Cleared" line.long 0x0c "HW_CLKCTRL_XTAL_TOG,XTAL Clock Control Toggle Register" bitfld.long 0x0c 31. " UART_CLK_GATE ,UART Clock Gate " "Not toggle,Toggle" bitfld.long 0x0c 30. " FILT_CLK24M_GATE ,Digital Filter Clock Gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " PWM_CLK24M_GATE ,PWM Clock Gate " "Not toggle,Toggle" bitfld.long 0x0c 28. " DRI_CLK24M_GATE ,DRI Clock Gate " "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " DIGCTRL_CLK1M_GATE ,DIGCTRL Clock Gate " "Not toggle,Toggle" bitfld.long 0x0c 26. " TIMROT_CLK32K_GATE ,TIMROT Clock Gate " "Not toggle,Toggle" line.long 0x10 "HW_CLKCTRL_PIX,PIX (LCDIF) Clock Control Register" bitfld.long 0x10 31. " CLKGATE ,CLK_PIX Gate" "Not gated,Gated off" bitfld.long 0x10 29. " BUSY ,CLK_PIX Busy" "Not busy,Busy" textline " " hexmask.long.word 0x10 0.--11. 1. " DIV ,Pixel Clock Frequency Divider" group.long 0x70++0x03 line.long 0x00 "HW_CLKCTRL_SSP,Synchronous Serial Port Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,SSP Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,SSP Busy" "Not busy,Busy" textline " " hexmask.long.word 0x00 0.--8. 1. " DIV ,Synchronous Serial Port Divider" group.long 0x80++0x03 line.long 0x00 "HW_CLKCTRL_GPMI,General-Purpose Media Interface Clock Control Register" bitfld.long 0x00 31. " CLKGATE , GPMI Clock Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY , GPMI Busy" "Not busy,Busy" textline " " hexmask.long.word 0x00 0.--9. 1. " DIV ,GPMI clock frequency divider" group.long 0x90++0x03 line.long 0x00 "HW_CLKCTRL_SPDIF,SPDIF Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_PCMSPDIF Gate" "Not gated,Gated off" if (((d.l(asd:(0x80040000+0xa0)))&0x40000000)==0x0) group.long 0xa0++0x03 line.long 0x00 "HW_CLKCTRL_EMI,EMI Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_EMI crystal divider Gate" "Not gated,Gated off" bitfld.long 0x00 30. " SYNC_MODE_EN ,EMI_CLK Synchronization Mode " "Asynchronous,Synchronous" textline " " bitfld.long 0x00 29. " BUSY_REF_XTAL ,XTAL Busy" "Not busy,Busy" bitfld.long 0x00 28. " BUSY_REF_EMI ,EMI Busy" "Not busy,Busy" textline " " bitfld.long 0x00 26. " BUSY_SYNC_MODE ,Synchronization Mode Busy" "0,1" bitfld.long 0x00 8.--11. " DIV_XTAL ,Crystal Reference Clock Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long.byte 0x00 0.--5. 1. " DIV_EMI ,EMI Divider" else group.long 0xa0++0x03 line.long 0x00 "HW_CLKCTRL_EMI,EMI Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_EMI crystal divider Gate" "Not gated,Gated off" bitfld.long 0x00 30. " SYNC_MODE_EN ,EMI_CLK Synchronization Mode " "Asynchronous,Synchronous" textline " " bitfld.long 0x00 28. " BUSY_REF_EMI ,EMI Busy" "Not busy,Busy" bitfld.long 0x00 27. " BUSY_REF_CPU ,CPU Busy" "Not busy,Busy" textline " " bitfld.long 0x00 26. " BUSY_SYNC_MODE ,Synchronization Mode Busy" "0,1" bitfld.long 0x00 8.--11. " DIV_XTAL ,Crystal Reference Clock Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long.byte 0x00 0.--5. 1. " DIV_EMI ,EMI Divider" endif group.long 0xc0++0x03 line.long 0x00 "HW_CLKCTRL_SAIF,SAIF Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_SAIF Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,SAIF Busy" "Not Busy,Busy" textline " " hexmask.long.word 0x00 0.--15. 1. " DIV ,SAIF clock frequency divider" group.long 0xd0++0x03 line.long 0x00 "HW_CLKCTRL_TV,TV Encode Clock Control Register" bitfld.long 0x00 31. " CLK_TV108M_GATE ,108-MHz clock TV Component Video Gate" "Not gated,Gated off" bitfld.long 0x00 30. " CLK_TV_GATE ,54-MHz and 27-MHz clocks TV Encoder Gate" "Not gated,Gated off" group.long 0xe0++0x03 line.long 0x00 "HW_CLKCTRL_ETM,ETM Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_ETM Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,ETM Busy" "Not busy,Busy" textline " " bitfld.long 0x00 0.--5. " DIV ,ETM Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" group.long 0xf0++0x33 line.long 0x00 "HW_CLKCTRL_FRAC,Fractional Clock Control Register" bitfld.long 0x00 31. " CLKGATEIO ,IO Clock Gate" "Enabled,Disabled" bitfld.long 0x00 30. " IO_STABLE ,IO Stable" "Not stabled,Stabled" textline " " bitfld.long 0x00 24.--29. " IOFRAC ,IO clocks fractional divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." bitfld.long 0x00 23. " CLKGATEPIX ,PIX Clock Gate " "Enabled,Disabled" textline " " bitfld.long 0x00 22. " PIX_STABLE ,PIX Stable" "Not stabled,Stabled" bitfld.long 0x00 16.--21. " PIXFRAC ,Pixel Clock Fractional Divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." textline " " bitfld.long 0x00 15. " CLKGATEEMI ,EMI Clock Gate" "Enabled,Disabled" bitfld.long 0x00 14. " EMI_STABLE ,EMI Stable" "Not stabled,Stabled" textline " " bitfld.long 0x00 8.--13. " EMIFRAC ,EMI clock fractional divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." bitfld.long 0x00 7. " CLKGATECPU ,CPU Clock Gate" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CPU_STABLE ,fractional divide stable" "Not stabled,Stabled" hexmask.long.byte 0x00 0.--5. 1. " CPUFRAC ,CPU clock fractional divider" line.long 0x04 "HW_CLKCTRL_FRAC_SET,Fractional Clock Control Set Register" bitfld.long 0x04 31. " CLKGATEIO ,IO Clock Gate " "No effect,Set" bitfld.long 0x04 30. " IO_STABLE ,IO Stable " "No effect,Set" textline " " bitfld.long 0x04 24.--29. " IOFRAC ,IO clocks fractional divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." bitfld.long 0x04 23. " CLKGATEPIX ,PIX Clock Gate " "No effect,Set" textline " " bitfld.long 0x04 22. " PIX_STABLE ,PIX Stable " "No effect,Set" bitfld.long 0x04 16.--21. " PIXFRAC ,Pixel Clock Fractional Divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." textline " " bitfld.long 0x04 15. " CLKGATEEMI ,EMI Clock Gate " "No effect,Set" bitfld.long 0x04 14. " EMI_STABLE ,EMI Stable" "No effect,Set" textline " " bitfld.long 0x04 8.--13. " EMIFRAC ,EMI clock fractional divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." bitfld.long 0x00 7. " CLKGATECPU ,CPU Clock Gate" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CPU_STABLE ,fractional divide stable" "Not stabled,Stabled" hexmask.long.byte 0x00 0.--5. 1. " CPUFRAC ,CPU clock fractional divider" line.long 0x08 "HW_CLKCTRL_FRAC_CLR,Fractional Clock Control Clear Register" bitfld.long 0x08 31. " CLKGATEIO ,IO Clock Gate " "No effect,Cleared" bitfld.long 0x08 30. " IO_STABLE ,IO Stable " "No effect,Cleared" textline " " bitfld.long 0x08 24.--29. " IOFRAC ,IO clocks fractional divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." bitfld.long 0x08 23. " CLKGATEPIX ,PIX Clock Gate " "No effect,Cleared" textline " " bitfld.long 0x08 22. " PIX_STABLE ,PIX Stable " "No effect,Cleared" bitfld.long 0x08 16.--21. " PIXFRAC ,Pixel Clock Fractional Divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." textline " " bitfld.long 0x08 15. " CLKGATEEMI ,EMI Clock Gate " "No effect,Cleared" bitfld.long 0x08 14. " EMI_STABLE ,EMI Stable " "No effect,Cleared" textline " " bitfld.long 0x08 8.--13. " EMIFRAC ,EMI clock fractional divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." bitfld.long 0x00 7. " CLKGATECPU ,CPU Clock Gate" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CPU_STABLE ,fractional divide stable" "Not stabled,Stabled" hexmask.long.byte 0x00 0.--5. 1. " CPUFRAC ,CPU clock fractional divider" line.long 0x0c "HW_CLKCTRL_FRAC_TOG,Fractional Clock Control Toggle Register" bitfld.long 0x0c 31. " CLKGATEIO ,IO Clock Gate " "Not toggle,Toggle" bitfld.long 0x0c 30. " IO_STABLE ,IO Stable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24.--29. " IOFRAC ,IO clocks fractional divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." bitfld.long 0x0c 23. " CLKGATEPIX ,PIX Clock Gate " "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " PIX_STABLE ,PIX Stable" "Not toggle,Toggle" bitfld.long 0x0c 16.--21. " PIXFRAC ,Pixel Clock Fractional Divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." textline " " bitfld.long 0x0c 15. " CLKGATEEMI ,EMI Clock Gate " "Not toggle,Toggle" bitfld.long 0x0c 14. " EMI_STABLE ,EMI Stable " "Not toggle,Toggle" textline " " bitfld.long 0x0c 8.--13. " EMIFRAC ,EMI clock fractional divider" "Reserved,8640,4320,2880,2160,1728,1440,1234.286,1080,960,864,785.455,720,664.615,617.143,576,540,508.235,480,454.737,432,411.428,392.727,375.652,360,345.6,332.308,320,308.571,297.931,288,278.709,270,261.818,254.118,246.857,?..." bitfld.long 0x00 7. " CLKGATECPU ,CPU Clock Gate" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CPU_STABLE ,fractional divide stable" "Not stabled,Stabled" hexmask.long.byte 0x00 0.--5. 1. " CPUFRAC ,CPU clock fractional divider" line.long 0x10 "HW_CLKCTRL_FRAC1,Fractional Clock Control Register 1" bitfld.long 0x10 31. " CLKGATEVID ,432 MHz PLL Clock Gate" "Enabled,Disabled" bitfld.long 0x10 30. " VID_STABLE ,VID Stable" "Not stable,Stable" line.long 0x14 "HW_CLKCTRL_FRAC1_SET,Fractional Clock Control Set Register 1" bitfld.long 0x14 31. " CLKGATEVID ,432 MHz PLL Clock Gate" "No effect,Set" bitfld.long 0x14 30. " VID_STABLE ,VID Stable" "No effect,Set" line.long 0x18 "HW_CLKCTRL_FRAC1_CLR,Fractional Clock Control Clear Register 1" bitfld.long 0x18 31. " CLKGATEVID ,432 MHz PLL Clock Gate " "No effect,Cleared" bitfld.long 0x18 30. " VID_STABLE ,VID Stable " "No effect,Cleared" line.long 0x1c "HW_CLKCTRL_FRAC1_TOG,Fractional Clock Control Toggle Register 1" bitfld.long 0x1c 31. " CLKGATEVID ,432 MHz PLL Clock Gate " "Not toggle,Toggle" bitfld.long 0x1c 30. " VID_STABLE ,VID Stable" "Not toggle,Toggle" line.long 0x20 "HW_CLKCTRL_CLKSEQ,Clock Frequency Sequence Control Register" bitfld.long 0x20 8. " BYPASS_ETM ,ETM bypass select" "Ref_cpu,Ref_xtal" bitfld.long 0x20 7. " BYPASS_CPU ,CPU bypass select" "Ref_cpu,Ref_xtal" textline " " bitfld.long 0x20 6. " BYPASS_EMI ,EMI bypass select" "Ref_cpu,Ref_xtal" bitfld.long 0x20 5. " BYPASS_SSP ,SSP bypass select" "Ref_cpu,Ref_xtal" textline " " bitfld.long 0x20 4. " BYPASS_GPMI ,GPMI bypass select" "Ref_cpu,Ref_xtal" bitfld.long 0x20 3. " BYPASS_IR ,IR bypass select" "Ref_cpu,Ref_xtal" textline " " bitfld.long 0x20 1. " BYPASS_PIX ,PIX bypass select" "Ref_cpu,Ref_xtal" line.long 0x24 "HW_CLKCTRL_CLKSEQ_SET,Clock Frequency Sequence Control Set Register" bitfld.long 0x24 8. " BYPASS_ETM ,ETM bypass select set" "No effect,Set" bitfld.long 0x24 7. " BYPASS_CPU ,CPU bypass select set" "No effect,Set" textline " " bitfld.long 0x24 6. " BYPASS_EMI ,EMI bypass select set" "No effect,Set" bitfld.long 0x24 5. " BYPASS_SSP ,SSP bypass select set" "No effect,Set" textline " " bitfld.long 0x24 4. " BYPASS_GPMI ,GPMI bypass select set" "No effect,Set" bitfld.long 0x24 3. " BYPASS_IR ,IR bypass select set" "No effect,Set" textline " " bitfld.long 0x24 1. " BYPASS_PIX ,PIX bypass select set" "No effect,Set" line.long 0x28 "HW_CLKCTRL_CLKSEQ_CLR,Clock Frequency Sequence Control Clear Register" bitfld.long 0x28 8. " BYPASS_ETM ,ETM bypass select " "No effect,Cleared" bitfld.long 0x28 7. " BYPASS_CPU ,CPU bypass select " "No effect,Cleared" textline " " bitfld.long 0x28 6. " BYPASS_EMI ,EMI bypass select " "No effect,Cleared" bitfld.long 0x28 5. " BYPASS_SSP ,SSP bypass select " "No effect,Cleared" textline " " bitfld.long 0x28 4. " BYPASS_GPMI ,GPMI bypass select " "No effect,Cleared" bitfld.long 0x28 3. " BYPASS_IR ,IR bypass select " "No effect,Cleared" textline " " bitfld.long 0x28 1. " BYPASS_PIX ,PIX bypass select " "No effect,Cleared" line.long 0x2c "HW_CLKCTRL_CLKSEQ_TOG,Clock Frequency Sequence Control Toggle Register" bitfld.long 0x2c 8. " BYPASS_ETM ,ETM bypass select" "Not toggle,Toggle" bitfld.long 0x2c 7. " BYPASS_CPU ,CPU bypass select" "Not toggle,Toggle" textline " " bitfld.long 0x2c 6. " BYPASS_EMI ,EMI bypass select" "Not toggle,Toggle" bitfld.long 0x2c 5. " BYPASS_SSP ,SSP bypass select" "Not toggle,Toggle" textline " " bitfld.long 0x2c 4. " BYPASS_GPMI ,GPMI bypass select" "Not toggle,Toggle" bitfld.long 0x2c 3. " BYPASS_IR ,IR bypass select " "Not toggle,Toggle" textline " " bitfld.long 0x2c 1. " BYPASS_PIX ,PIX bypass select" "Not toggle,Toggle" line.long 0x30 "HW_CLKCTRL_RESET,System Software Reset Register" bitfld.long 0x30 1. " CHIP ,Entire Chip Reset" "No reset,Reset" bitfld.long 0x30 0. " DIG , Digital Sections Chip reset" "No reset,Reset" rgroup.long 0x130++0x03 line.long 0x00 "HW_CLKCTRL_STATUS,ClkCtrl Status Register" bitfld.long 0x00 30.--31. " CPU_LIMIT ,CPU Limiting Frequency" "Full frequency,Limited(411.43MHz),Limited(360MHz),Limited(320MHz)" rgroup.long 0x140++0x03 line.long 0x00 "HW_CLKCTRL_VERSION,ClkCtrl Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "INTC (Interrupt Controller)" base asd:0x80000000 width 21. group.long 0x00++0x13 line.long 0x00 "HW_ICOLL_VECTOR,Interrupt Collector Interrupt Vector Address Register" hexmask.long 0x00 2.--31. 0x4 " IRQVECTOR ,Vector address for the interrupt currently active" line.long 0x04 "HW_ICOLL_VECTOR_SET,Interrupt Collector Interrupt Vector Address Set Register" hexmask.long 0x04 2.--31. 0x4 " IRQVECTOR ,Vector address for the interrupt currently active" line.long 0x08 "HW_ICOLL_VECTOR_CLR,Interrupt Collector Interrupt Vector Address Clear Register" hexmask.long 0x08 2.--31. 0x4 " IRQVECTOR ,Vector address for the interrupt currently active" line.long 0x0c "HW_ICOLL_VECTOR_TOG,Interrupt Collector Interrupt Vector Address Toggle Register" hexmask.long 0x0c 2.--31. 0x4 " IRQVECTOR ,Vector address for the interrupt currently active" line.long 0x10 "HW_ICOLL_LEVELACK,Interrupt Collector Level Acknowledge Register" bitfld.long 0x10 0.--3. " IRQLEVELACK ,Interrupt Level Acknowledge" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level 3,?..." group.long 0x20++0x0f line.long 0x00 "HW_ICOLL_CTRL,Interrupt Collector Control Register" bitfld.long 0x00 31. " SFTRST ,Interrupt Collector Soft Reset" "Run,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock Gate Off" "Run,No clocks" textline " " bitfld.long 0x00 21.--23. " VECTOR_PITCH ,Vector Pitch Multiplier Values" "DEFAULT_BY4,BY4,BY8,BY12,BY16,BY20,BY24,BY28" bitfld.long 0x00 20. " BYPASS_FSM ,Bypass FSM Control" "Normal,Bypass" textline " " bitfld.long 0x00 19. " NO_NESTING ,Nesting Disable" "NORMAL,NO_NEST" bitfld.long 0x00 18. " ARM_RSE_MODE ,Arm RSE Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " FIQ_FINAL_ENABLE ,FIQ Final Enable" "Disabled,Enabled" bitfld.long 0x00 16. " IRQ_FINAL_ENABLE ,IRQ Final Enable" "Disabled,Enabled" line.long 0x04 "HW_ICOLL_CTRL_SET,Interrupt Collector Control Set Register" bitfld.long 0x04 31. " SFTRST ,Interrupt Collector Soft Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock Gate Off" "No effect,Set" textline " " bitfld.long 0x04 21.--23. " VECTOR_PITCH ,Vector Pitch Multiplier Values" "DEFAULT_BY4,BY4,BY8,BY12,BY16,BY20,BY24,BY28" bitfld.long 0x04 20. " BYPASS_FSM ,Bypass FSM Control" "No effect,Set" textline " " bitfld.long 0x04 19. " NO_NESTING ,Nesting Disable" "No effect,Set" bitfld.long 0x04 18. " ARM_RSE_MODE ,Arm RSE Mode" "No effect,Set" textline " " bitfld.long 0x04 17. " FIQ_FINAL_ENABLE ,FIQ Final Enable" "No effect,Set" bitfld.long 0x04 16. " IRQ_FINAL_ENABLE ,IRQ Final Enable" "No effect,Set" line.long 0x08 "HW_ICOLL_CTRL_CLR,Interrupt Collector Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Interrupt Collector Soft Reset" "No effect,Cleared" bitfld.long 0x08 30. " CLKGATE ,Clock Gate Off" "No effect,Cleared" textline " " bitfld.long 0x08 21.--23. " VECTOR_PITCH ,Vector Pitch Multiplier Values" "DEFAULT_BY4,BY4,BY8,BY12,BY16,BY20,BY24,BY28" bitfld.long 0x08 20. " BYPASS_FSM ,Bypass FSM Control" "No effect,Cleared" textline " " bitfld.long 0x08 19. " NO_NESTING ,Nesting Disable" "No effect,Cleared" bitfld.long 0x08 18. " ARM_RSE_MODE ,Arm RSE Mode" "No effect,Cleared" textline " " bitfld.long 0x08 17. " FIQ_FINAL_ENABLE ,FIQ Final Enable" "No effect,Cleared" bitfld.long 0x08 16. " IRQ_FINAL_ENABLE ,IRQ Final Enable" "No effect,Cleared" line.long 0x0c "HW_ICOLL_CTRL_TOG,Interrupt Collector Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Interrupt Collector Soft Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock Gate Off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21.--23. " VECTOR_PITCH ,Vector Pitch Multiplier Values " "DEFAULT_BY4,BY4,BY8,BY12,BY16,BY20,BY24,BY28" bitfld.long 0x0c 20. " BYPASS_FSM ,Bypass FSM Control" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " NO_NESTING ,Nesting Disable" "Not toggle,Toggle" bitfld.long 0x0c 18. " ARM_RSE_MODE ,Arm RSE Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " FIQ_FINAL_ENABLE ,FIQ Final Enable" "Not toggle,Toggle" bitfld.long 0x0c 16. " IRQ_FINAL_ENABLE ,IRQ Final Enable" "Not toggle,Toggle" group.long 0x40++0x0f line.long 0x00 "HW_ICOLL_VBASE,Interrupt Collector Interrupt Vector Base Address Register" hexmask.long 0x00 2.--31. 4. " TABBLE_ADDRESS ,Upper 30 bits of the base address of the vector table" line.long 0x04 "HW_ICOLL_VBASE_SET,Interrupt Collector Interrupt Vector Base Address Set Register" hexmask.long 0x04 2.--31. 4. " TABBLE_ADDRESS ,Upper 30 bits of the base address of the vector table" line.long 0x08 "HW_ICOLL_VBASE_CLR,Interrupt Collector Interrupt Vector Base Addressc Clear Register" hexmask.long 0x08 2.--31. 4. " TABBLE_ADDRESS ,Upper 30 bits of the base address of the vector table" line.long 0x0C "HW_ICOLL_VBASE_TOG,Interrupt Collector Interrupt Vector Base Address Toggle Register" hexmask.long 0x0C 2.--31. 4. " TABBLE_ADDRESS ,Upper 30 bits of the base address of the vector table" rgroup.long 0x70++0x03 line.long 0x00 "HW_ICOLL_STAT,Interrupt Collector Status Register" hexmask.long.byte 0x00 0.--6. 1. " VECTOR_NUMBER ,Vector number of current interrupt" width 19. tree "Interrupt RAW Registers" rgroup.long 0xa0++0x2f line.long 0x00 "HW_ICOLL_RAW0,Interrupt Collector Raw Interrupt Input Register 0" bitfld.long 0x00 31. " RAW_IRQS[31] ,TIMER3 Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 30. " RAW_IRQS[30] ,TIMER2 Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " RAW_IRQS[29] ,TIMER1 Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 28. " RAW_IRQS[28] ,TIMER0 Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " RAW_IRQS[27] ,I2C_ERROR Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 26. " RAW_IRQS[26] ,I2C_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " RAW_IRQS[25] ,UARTAPP_RX_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 24. " RAW_IRQS[24] ,UARTAPP_INTERNAL Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " RAW_IRQS[23] ,UARTAPP_TX_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 22. " RAW_IRQS[22] ,RTC_ALARM Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " RAW_IRQS[21] ,ECC8_IRQ Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 20. " RAW_IRQS[20] ,SSP2_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " RAW_IRQS[19] ,SAIF1_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 18. " RAW_IRQS[18] ,GPIO2 Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " RAW_IRQS[17] ,GPIO1 Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 16. " RAW_IRQS[16] ,GPIO0 Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " RAW_IRQS[15] ,SSP_ERROR Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 14. " RAW_IRQS[14] ,SSP1_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " RAW_IRQS[13] ,GPMI_DMA Hardware Interrupt Bit " "No interrupt,Interrupt" bitfld.long 0x00 12. " RAW_IRQS[12] ,USB_WAKEUP Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " RAW_IRQS[11] ,USB_CTRL Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 10. " RAW_IRQS[10] ,SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ Hardware Interrupt Bit " "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " RAW_IRQS[9] ,SPDIF_DMA,SAIF2_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 8. " RAW_IRQS[8] ,ADC_ERROR Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " RAW_IRQS[7] ,ADC_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 6. " RAW_IRQS[6] ,DAC_ERROR Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " RAW_IRQS[5] ,DAC_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 4. " RAW_IRQS[4] ,HEADPHONE_SHORT Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " RAW_IRQS[3] ,VDD5V Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 2. " RAW_IRQS[2] ,SSP2_ERROR Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " RAW_IRQS[1] ,COMMS_RX,COMMS_TX Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x00 0. " RAW_IRQS[0] ,DEBUG_UART Hardware Interrupt Bit" "No interrupt,Interrupt" line.long 0x04 "HW_ICOLL_RAW0_SET,Interrupt Collector Raw Interrupt Input Set Register 0" bitfld.long 0x04 31. " RAW_IRQS[31] ,TIMER3 Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 30. " RAW_IRQS[30] ,TIMER2 Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 29. " RAW_IRQS[29] ,TIMER1 Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 28. " RAW_IRQS[28] ,TIMER0 Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 27. " RAW_IRQS[27] ,I2C_ERROR Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 26. " RAW_IRQS[26] ,I2C_DMA Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 25. " RAW_IRQS[25] ,UARTAPP_RX_DMA Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 24. " RAW_IRQS[24] ,UARTAPP_INTERNAL Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 23. " RAW_IRQS[23] ,UARTAPP_TX_DMA Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 22. " RAW_IRQS[22] ,RTC_ALARM Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 21. " RAW_IRQS[21] ,ECC8_IRQ Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 20. " RAW_IRQS[20] ,SSP2_DMA Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 19. " RAW_IRQS[19] ,SAIF1_DMA Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 18. " RAW_IRQS[18] ,GPIO2 Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 17. " RAW_IRQS[17] ,GPIO1 Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 16. " RAW_IRQS[16] ,GPIO0 Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 15. " RAW_IRQS[15] ,SSP_ERROR Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 14. " RAW_IRQS[14] ,SSP1_DMA Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 13. " RAW_IRQS[13] ,GPMI_DMA Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 12. " RAW_IRQS[12] ,USB_WAKEUP Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 11. " RAW_IRQS[11] ,USB_CTRL Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 10. " RAW_IRQS[10] ,SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 9. " RAW_IRQS[9] ,SPDIF_DMA,SAIF2_DMA Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 8. " RAW_IRQS[8] ,ADC_ERROR Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 7. " RAW_IRQS[7] ,ADC_DMA Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 6. " RAW_IRQS[6] ,DAC_ERROR Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 5. " RAW_IRQS[5] ,DAC_DMA Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 4. " RAW_IRQS[4] ,HEADPHONE_SHORT Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 3. " RAW_IRQS[3] ,VDD5V Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 2. " RAW_IRQS[2] ,SSP2_ERROR Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x04 1. " RAW_IRQS[1] ,COMMS_RX,COMMS_TX Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x04 0. " RAW_IRQS[0] ,DEBUG_UART Hardware Interrupt Bit" "No effect,Set" line.long 0x08 "HW_ICOLL_RAW0_CLR,Interrupt Collector Raw Interrupt Input Clear Register 0" bitfld.long 0x08 31. " RAW_IRQS[31] ,TIMER3 Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 30. " RAW_IRQS[30] ,TIMER2 Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 29. " RAW_IRQS[29] ,TIMER1 Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 28. " RAW_IRQS[28] ,TIMER0 Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 27. " RAW_IRQS[27] ,I2C_ERROR Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 26. " RAW_IRQS[26] ,I2C_DMA Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 25. " RAW_IRQS[25] ,UARTAPP_RX_DMA Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 24. " RAW_IRQS[24] ,UARTAPP_INTERNAL Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 23. " RAW_IRQS[23] ,UARTAPP_TX_DMA Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 22. " RAW_IRQS[22] ,RTC_ALARM Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 21. " RAW_IRQS[21] ,ECC8_IRQ Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 20. " RAW_IRQS[20] ,SSP2_DMA Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 19. " RAW_IRQS[19] ,SAIF1_DMA Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 18. " RAW_IRQS[18] ,GPIO2 Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 17. " RAW_IRQS[17] ,GPIO1 Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 16. " RAW_IRQS[16] ,GPIO0 Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 15. " RAW_IRQS[15] ,SSP_ERROR Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 14. " RAW_IRQS[14] ,SSP1_DMA Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 13. " RAW_IRQS[13] ,GPMI_DMA Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 12. " RAW_IRQS[12] ,USB_WAKEUP Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 11. " RAW_IRQS[11] ,USB_CTRL Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 10. " RAW_IRQS[10] ,SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 9. " RAW_IRQS[9] ,SPDIF_DMA,SAIF2_DMA Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 8. " RAW_IRQS[8] ,ADC_ERROR Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 7. " RAW_IRQS[7] ,ADC_DMA Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 6. " RAW_IRQS[6] ,DAC_ERROR Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 5. " RAW_IRQS[5] ,DAC_DMA Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 4. " RAW_IRQS[4] ,HEADPHONE_SHORT Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 3. " RAW_IRQS[3] ,VDD5V Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 2. " RAW_IRQS[2] ,SSP2_ERROR Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x08 1. " RAW_IRQS[1] ,COMMS_RX,COMMS_TX Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x08 0. " RAW_IRQS[0] ,DEBUG_UART Hardware Interrupt Bit" "No effect,Cleared" line.long 0x0c "HW_ICOLL_RAW0_TOG,Interrupt Collector Raw Interrupt Input Toggle Register 0" bitfld.long 0x0c 31. " RAW_IRQS[31] ,TIMER3 Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 30. " RAW_IRQS[30] ,TIMER2 Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RAW_IRQS[29] ,TIMER1 Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 28. " RAW_IRQS[28] ,TIMER0 Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RAW_IRQS[27] ,I2C_ERROR Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 26. " RAW_IRQS[26] ,I2C_DMA Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " RAW_IRQS[25] ,UARTAPP_RX_DMA Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 24. " RAW_IRQS[24] ,UARTAPP_INTERNAL Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " RAW_IRQS[23] ,UARTAPP_TX_DMA Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 22. " RAW_IRQS[22] ,RTC_ALARM Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " RAW_IRQS[21] ,ECC8_IRQ Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 20. " RAW_IRQS[20] ,SSP2_DMA Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " RAW_IRQS[19] ,SAIF1_DMA Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 18. " RAW_IRQS[18] ,GPIO2 Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " RAW_IRQS[17] ,GPIO1 Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 16. " RAW_IRQS[16] ,GPIO0 Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " RAW_IRQS[15] ,SSP_ERROR Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 14. " RAW_IRQS[14] ,SSP1_DMA Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " RAW_IRQS[13] ,GPMI_DMA Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 12. " RAW_IRQS[12] ,USB_WAKEUP Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " RAW_IRQS[11] ,USB_CTRL Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 10. " RAW_IRQS[10] ,SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " RAW_IRQS[9] ,SPDIF_DMA,SAIF2_DMA Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 8. " RAW_IRQS[8] ,ADC_ERROR Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " RAW_IRQS[7] ,ADC_DMA Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 6. " RAW_IRQS[6] ,DAC_ERROR Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " RAW_IRQS[5] ,DAC_DMA Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 4. " RAW_IRQS[4] ,HEADPHONE_SHORT Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " RAW_IRQS[3] ,VDD5V Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 2. " RAW_IRQS[2] ,SSP2_ERROR Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " RAW_IRQS[1] ,COMMS_RX,COMMS_TX Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x0c 0. " RAW_IRQS[0] ,DEBUG_UART Hardware Interrupt Bit" "Not toggle,Toggle" line.long 0x10 "HW_ICOLL_RAW1,Interrupt Collector Raw Interrupt Input Register 1" bitfld.long 0x10 29. " RAW_IRQS[61] ,VDAC_DETECT Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 28. " RAW_IRQS[60] ,UARTAPP2_RX_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 27. " RAW_IRQS[59] ,UARTAPP2_INTERNAL Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 26. " RAW_IRQS[58] ,UARTAPP2_TX_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 25. " RAW_IRQS[57] ,PXP Hardware Interrupt Bit " "No interrupt,Interrupt" bitfld.long 0x10 24. " RAW_IRQS[56] ,BCH Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 22. " RAW_IRQS[54] ,DCP Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 21. " RAW_IRQS[53] ,DCP_VMI Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 19. " RAW_IRQS[51] ,GPMI Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 16. " RAW_IRQS[48] ,RTC_1MSEC Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 15. " RAW_IRQS[47] ,DIGCTL_DEBUG_TRAP Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 14. " RAW_IRQS[46] ,LCDIF_ERROR Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 13. " RAW_IRQS[45] ,LCDIF_DMA Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 12. " RAW_IRQS[44] ,LRADC_CH7 Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 11. " RAW_IRQS[43] ,LRADC_CH6 Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 10. " RAW_IRQS[42] ,LRADC_CH5 Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 9. " RAW_IRQS[41] ,LRADC_CH4 Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 8. " RAW_IRQS[40] ,LRADC_CH3 Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 7. " RAW_IRQS[39] ,LRADC_CH2 Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 6. " RAW_IRQS[38] ,LRADC_CH1 Hardware Interrupt Bit " "No interrupt,Interrupt" textline " " bitfld.long 0x10 5. " RAW_IRQS[37] ,LRADC_CH0 Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 4. " RAW_IRQS[36] ,TOUCH_DETECT Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 3. " RAW_IRQS[35] ,VDD18_BRNOUT Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 2. " RAW_IRQS[34] ,VDDIO_BRNOUT Hardware Interrupt Bit" "No interrupt,Interrupt" textline " " bitfld.long 0x10 1. " RAW_IRQS[33] ,VDDD_BRNOUT Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x10 0. " RAW_IRQS[32] ,BATT_BRNOUT Hardware Interrupt Bit" "No interrupt,Interrupt" line.long 0x14 "HW_ICOLL_RAW1_SET,Interrupt Collector Raw Interrupt Input Set Register 1" bitfld.long 0x14 29. " RAW_IRQS[61] ,VDAC_DETECT Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 28. " RAW_IRQS[60] ,UARTAPP2_RX_DMA Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 27. " RAW_IRQS[59] ,UARTAPP2_INTERNAL Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 26. " RAW_IRQS[58] ,UARTAPP2_TX_DMA Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 25. " RAW_IRQS[57] ,PXP Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 24. " RAW_IRQS[56] ,BCH Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 22. " RAW_IRQS[54] ,DCP Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 21. " RAW_IRQS[53] ,DCP_VMI Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 19. " RAW_IRQS[51] ,GPMI Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 16. " RAW_IRQS[48] ,RTC_1MSEC Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 15. " RAW_IRQS[47] ,DIGCTL_DEBUG_TRAP Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 14. " RAW_IRQS[46] ,LCDIF_ERROR Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 13. " RAW_IRQS[45] ,LCDIF_DMA Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 12. " RAW_IRQS[44] ,LRADC_CH7 Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 11. " RAW_IRQS[43] ,LRADC_CH6 Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 10. " RAW_IRQS[42] ,LRADC_CH5 Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 9. " RAW_IRQS[41] ,LRADC_CH4 Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 8. " RAW_IRQS[40] ,LRADC_CH3 Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 7. " RAW_IRQS[39] ,LRADC_CH2 Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 6. " RAW_IRQS[38] ,LRADC_CH1 Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 5. " RAW_IRQS[37] ,LRADC_CH0 Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 4. " RAW_IRQS[36] ,TOUCH_DETECT Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 3. " RAW_IRQS[35] ,VDD18_BRNOUT Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 2. " RAW_IRQS[34] ,VDDIO_BRNOUT Hardware Interrupt Bit" "No effect,Set" textline " " bitfld.long 0x14 1. " RAW_IRQS[33] ,VDDD_BRNOUT Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x14 0. " RAW_IRQS[32] ,BATT_BRNOUT Hardware Interrupt Bit" "No effect,Set" line.long 0x18 "HW_ICOLL_RAW1_CLR,Interrupt Collector Raw Interrupt Input Clear Register 1" bitfld.long 0x18 29. " RAW_IRQS[61] ,VDAC_DETECT Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 28. " RAW_IRQS[60] ,UARTAPP2_RX_DMA Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 27. " RAW_IRQS[59] ,UARTAPP2_INTERNAL Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 26. " RAW_IRQS[58] ,UARTAPP2_TX_DMA Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 25. " RAW_IRQS[57] ,PXP Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 24. " RAW_IRQS[56] ,BCH Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 22. " RAW_IRQS[54] ,DCP Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 21. " RAW_IRQS[53] ,DCP_VMI Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 19. " RAW_IRQS[51] ,GPMI Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 16. " RAW_IRQS[48] ,RTC_1MSEC Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 15. " RAW_IRQS[47] ,DIGCTL_DEBUG_TRAP Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 14. " RAW_IRQS[46] ,LCDIF_ERROR Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 13. " RAW_IRQS[45] ,LCDIF_DMA Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 12. " RAW_IRQS[44] ,LRADC_CH7 Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 11. " RAW_IRQS[43] ,LRADC_CH6 Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 10. " RAW_IRQS[42] ,LRADC_CH5 Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 9. " RAW_IRQS[41] ,LRADC_CH4 Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 8. " RAW_IRQS[40] ,LRADC_CH3 Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 7. " RAW_IRQS[39] ,LRADC_CH2 Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 6. " RAW_IRQS[38] ,LRADC_CH1 Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 5. " RAW_IRQS[37] ,LRADC_CH0 Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 4. " RAW_IRQS[36] ,TOUCH_DETECT Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 3. " RAW_IRQS[35] ,VDD18_BRNOUT Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 2. " RAW_IRQS[34] ,VDDIO_BRNOUT Hardware Interrupt Bit" "No effect,Cleared" textline " " bitfld.long 0x18 1. " RAW_IRQS[33] ,VDDD_BRNOUT Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x18 0. " RAW_IRQS[32] ,BATT_BRNOUT Hardware Interrupt Bit" "No effect,Cleared" line.long 0x1c "HW_ICOLL_RAW1,Interrupt Collector Raw Interrupt Input Toggle Register 1" bitfld.long 0x1c 29. " RAW_IRQS[61] ,VDAC_DETECT Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 28. " RAW_IRQS[60] ,UARTAPP2_RX_DMA Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 27. " RAW_IRQS[59] ,UARTAPP2_INTERNAL Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 26. " RAW_IRQS[58] ,UARTAPP2_TX_DMA Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 25. " RAW_IRQS[57] ,PXP Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 24. " RAW_IRQS[56] ,BCH Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 22. " RAW_IRQS[54] ,DCP Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 21. " RAW_IRQS[53] ,DCP_VMI Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 19. " RAW_IRQS[51] ,GPMI Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 16. " RAW_IRQS[48] ,RTC_1MSEC Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 15. " RAW_IRQS[47] ,DIGCTL_DEBUG_TRAP Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 14. " RAW_IRQS[46] ,LCDIF_ERROR Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 13. " RAW_IRQS[45] ,LCDIF_DMA Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 12. " RAW_IRQS[44] ,LRADC_CH7 Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 11. " RAW_IRQS[43] ,LRADC_CH6 Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 10. " RAW_IRQS[42] ,LRADC_CH5 Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 9. " RAW_IRQS[41] ,LRADC_CH4 Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 8. " RAW_IRQS[40] ,LRADC_CH3 Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 7. " RAW_IRQS[39] ,LRADC_CH2 Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 6. " RAW_IRQS[38] ,LRADC_CH1 Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 5. " RAW_IRQS[37] ,LRADC_CH0 Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 4. " RAW_IRQS[36] ,TOUCH_DETECT Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " RAW_IRQS[35] ,VDD18_BRNOUT Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 2. " RAW_IRQS[34] ,VDDIO_BRNOUT Hardware Interrupt Bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " RAW_IRQS[33] ,VDDD_BRNOUT Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x1c 0. " RAW_IRQS[32] ,BATT_BRNOUT Hardware Interrupt Bit" "Not toggle,Toggle" line.long 0x20 "HW_ICOLL_RAW2,Interrupt Collector Raw Interrupt Input Register 2" bitfld.long 0x20 1. " RAW_IRQS[65] ,DCDC4P2_BO Hardware Interrupt Bit" "No interrupt,Interrupt" bitfld.long 0x20 0. " RAW_IRQS[64] ,VDD5V_DROOP Hardware Interrupt Bit" "No interrupt,Interrupt" line.long 0x24 "HW_ICOLL_RAW2_SET,Interrupt Collector Raw Interrupt Input Register 2" bitfld.long 0x24 1. " RAW_IRQS[65] ,DCDC4P2_BO Hardware Interrupt Bit" "No effect,Set" bitfld.long 0x24 0. " RAW_IRQS[64] ,VDD5V_DROOP Hardware Interrupt Bit" "No effect,Set" line.long 0x28 "HW_ICOLL_RAW2_CLR,Interrupt Collector Raw Interrupt Input Register 2" bitfld.long 0x28 1. " RAW_IRQS[65] ,DCDC4P2_BO Hardware Interrupt Bit" "No effect,Cleared" bitfld.long 0x28 0. " RAW_IRQS[64] ,VDD5V_DROOP Hardware Interrupt Bit" "No effect,Cleared" line.long 0x2c "HW_ICOLL_RAW2_TOG,Interrupt Collector Raw Interrupt Input Toggle Register 2" bitfld.long 0x2c 1. " RAW_IRQS[65] ,DCDC4P2_BO Hardware Interrupt Bit" "Not toggle,Toggle" bitfld.long 0x2c 0. " RAW_IRQS[64] ,VDD5V_DROOP Hardware Interrupt Bit" "Not toggle,Toggle" tree.end width 26. tree "Interrupt Collector Registers" group.long 0x120++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT0,Interrupt Collector Interrupt Register 0" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT0_SET,Interrupt Collector Interrupt Set Register 0" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT0_CLR,Interrupt Collector Interrupt Clear Register 0" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT0_TOG,Interrupt Collector Interrupt Toggle Register 0" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x130++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT1,Interrupt Collector Interrupt Register 1" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT1_SET,Interrupt Collector Interrupt Set Register 1" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT1_CLR,Interrupt Collector Interrupt Clear Register 1" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT1_TOG,Interrupt Collector Interrupt Toggle Register 1" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x140++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT2,Interrupt Collector Interrupt Register 2" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT2_SET,Interrupt Collector Interrupt Set Register 2" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT2_CLR,Interrupt Collector Interrupt Clear Register 2" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT2_TOG,Interrupt Collector Interrupt Toggle Register 2" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x150++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT3,Interrupt Collector Interrupt Register 3" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT3_SET,Interrupt Collector Interrupt Set Register 3" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT3_CLR,Interrupt Collector Interrupt Clear Register 3" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT3_TOG,Interrupt Collector Interrupt Toggle Register 3" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x160++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT4,Interrupt Collector Interrupt Register 4" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT4_SET,Interrupt Collector Interrupt Set Register 4" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT4_CLR,Interrupt Collector Interrupt Clear Register 4" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT4_TOG,Interrupt Collector Interrupt Toggle Register 4" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x170++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT5,Interrupt Collector Interrupt Register 5" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT5_SET,Interrupt Collector Interrupt Set Register 5" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT5_CLR,Interrupt Collector Interrupt Clear Register 5" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT5_TOG,Interrupt Collector Interrupt Toggle Register 5" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x180++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT6,Interrupt Collector Interrupt Register 6" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT6_SET,Interrupt Collector Interrupt Set Register 6" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT6_CLR,Interrupt Collector Interrupt Clear Register 6" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT6_TOG,Interrupt Collector Interrupt Toggle Register 6" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x190++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT7,Interrupt Collector Interrupt Register 7" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT7_SET,Interrupt Collector Interrupt Set Register 7" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT7_CLR,Interrupt Collector Interrupt Clear Register 7" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT7_TOG,Interrupt Collector Interrupt Toggle Register 7" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x1A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT8,Interrupt Collector Interrupt Register 8" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT8_SET,Interrupt Collector Interrupt Set Register 8" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT8_CLR,Interrupt Collector Interrupt Clear Register 8" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT8_TOG,Interrupt Collector Interrupt Toggle Register 8" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x1B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT9,Interrupt Collector Interrupt Register 9" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT9_SET,Interrupt Collector Interrupt Set Register 9" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT9_CLR,Interrupt Collector Interrupt Clear Register 9" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT9_TOG,Interrupt Collector Interrupt Toggle Register 9" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x1C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT10,Interrupt Collector Interrupt Register 10" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT10_SET,Interrupt Collector Interrupt Set Register 10" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT10_CLR,Interrupt Collector Interrupt Clear Register 10" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT10_TOG,Interrupt Collector Interrupt Toggle Register 10" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x1D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT11,Interrupt Collector Interrupt Register 11" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT11_SET,Interrupt Collector Interrupt Set Register 11" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT11_CLR,Interrupt Collector Interrupt Clear Register 11" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT11_TOG,Interrupt Collector Interrupt Toggle Register 11" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x1E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT12,Interrupt Collector Interrupt Register 12" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT12_SET,Interrupt Collector Interrupt Set Register 12" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT12_CLR,Interrupt Collector Interrupt Clear Register 12" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT12_TOG,Interrupt Collector Interrupt Toggle Register 12" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x1F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT13,Interrupt Collector Interrupt Register 13" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT13_SET,Interrupt Collector Interrupt Set Register 13" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT13_CLR,Interrupt Collector Interrupt Clear Register 13" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT13_TOG,Interrupt Collector Interrupt Toggle Register 13" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x200++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT14,Interrupt Collector Interrupt Register 14" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT14_SET,Interrupt Collector Interrupt Set Register 14" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT14_CLR,Interrupt Collector Interrupt Clear Register 14" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT14_TOG,Interrupt Collector Interrupt Toggle Register 14" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x210++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT15,Interrupt Collector Interrupt Register 15" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT15_SET,Interrupt Collector Interrupt Set Register 15" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT15_CLR,Interrupt Collector Interrupt Clear Register 15" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT15_TOG,Interrupt Collector Interrupt Toggle Register 15" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x220++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT16,Interrupt Collector Interrupt Register 16" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT16_SET,Interrupt Collector Interrupt Set Register 16" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT16_CLR,Interrupt Collector Interrupt Clear Register 16" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT16_TOG,Interrupt Collector Interrupt Toggle Register 16" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x230++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT17,Interrupt Collector Interrupt Register 17" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT17_SET,Interrupt Collector Interrupt Set Register 17" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT17_CLR,Interrupt Collector Interrupt Clear Register 17" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT17_TOG,Interrupt Collector Interrupt Toggle Register 17" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x240++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT18,Interrupt Collector Interrupt Register 18" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT18_SET,Interrupt Collector Interrupt Set Register 18" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT18_CLR,Interrupt Collector Interrupt Clear Register 18" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT18_TOG,Interrupt Collector Interrupt Toggle Register 18" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x250++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT19,Interrupt Collector Interrupt Register 19" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT19_SET,Interrupt Collector Interrupt Set Register 19" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT19_CLR,Interrupt Collector Interrupt Clear Register 19" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT19_TOG,Interrupt Collector Interrupt Toggle Register 19" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x260++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT20,Interrupt Collector Interrupt Register 20" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT20_SET,Interrupt Collector Interrupt Set Register 20" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT20_CLR,Interrupt Collector Interrupt Clear Register 20" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT20_TOG,Interrupt Collector Interrupt Toggle Register 20" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x270++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT21,Interrupt Collector Interrupt Register 21" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT21_SET,Interrupt Collector Interrupt Set Register 21" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT21_CLR,Interrupt Collector Interrupt Clear Register 21" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT21_TOG,Interrupt Collector Interrupt Toggle Register 21" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x280++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT22,Interrupt Collector Interrupt Register 22" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT22_SET,Interrupt Collector Interrupt Set Register 22" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT22_CLR,Interrupt Collector Interrupt Clear Register 22" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT22_TOG,Interrupt Collector Interrupt Toggle Register 22" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x290++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT23,Interrupt Collector Interrupt Register 23" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT23_SET,Interrupt Collector Interrupt Set Register 23" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT23_CLR,Interrupt Collector Interrupt Clear Register 23" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT23_TOG,Interrupt Collector Interrupt Toggle Register 23" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x2A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT24,Interrupt Collector Interrupt Register 24" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT24_SET,Interrupt Collector Interrupt Set Register 24" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT24_CLR,Interrupt Collector Interrupt Clear Register 24" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT24_TOG,Interrupt Collector Interrupt Toggle Register 24" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x2B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT25,Interrupt Collector Interrupt Register 25" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT25_SET,Interrupt Collector Interrupt Set Register 25" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT25_CLR,Interrupt Collector Interrupt Clear Register 25" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT25_TOG,Interrupt Collector Interrupt Toggle Register 25" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x2C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT26,Interrupt Collector Interrupt Register 26" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT26_SET,Interrupt Collector Interrupt Set Register 26" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT26_CLR,Interrupt Collector Interrupt Clear Register 26" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT26_TOG,Interrupt Collector Interrupt Toggle Register 26" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x2D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT27,Interrupt Collector Interrupt Register 27" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT27_SET,Interrupt Collector Interrupt Set Register 27" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT27_CLR,Interrupt Collector Interrupt Clear Register 27" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT27_TOG,Interrupt Collector Interrupt Toggle Register 27" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x2E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT28,Interrupt Collector Interrupt Register 28" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT28_SET,Interrupt Collector Interrupt Set Register 28" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT28_CLR,Interrupt Collector Interrupt Clear Register 28" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT28_TOG,Interrupt Collector Interrupt Toggle Register 28" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x2F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT29,Interrupt Collector Interrupt Register 29" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT29_SET,Interrupt Collector Interrupt Set Register 29" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT29_CLR,Interrupt Collector Interrupt Clear Register 29" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT29_TOG,Interrupt Collector Interrupt Toggle Register 29" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x300++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT30,Interrupt Collector Interrupt Register 30" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT30_SET,Interrupt Collector Interrupt Set Register 30" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT30_CLR,Interrupt Collector Interrupt Clear Register 30" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT30_TOG,Interrupt Collector Interrupt Toggle Register 30" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x310++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT31,Interrupt Collector Interrupt Register 31" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT31_SET,Interrupt Collector Interrupt Set Register 31" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT31_CLR,Interrupt Collector Interrupt Clear Register 31" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT31_TOG,Interrupt Collector Interrupt Toggle Register 31" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x320++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT32,Interrupt Collector Interrupt Register 32" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT32_SET,Interrupt Collector Interrupt Set Register 32" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT32_CLR,Interrupt Collector Interrupt Clear Register 32" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT32_TOG,Interrupt Collector Interrupt Toggle Register 32" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x330++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT33,Interrupt Collector Interrupt Register 33" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT33_SET,Interrupt Collector Interrupt Set Register 33" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT33_CLR,Interrupt Collector Interrupt Clear Register 33" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT33_TOG,Interrupt Collector Interrupt Toggle Register 33" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x340++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT34,Interrupt Collector Interrupt Register 34" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT34_SET,Interrupt Collector Interrupt Set Register 34" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT34_CLR,Interrupt Collector Interrupt Clear Register 34" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT34_TOG,Interrupt Collector Interrupt Toggle Register 34" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x350++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT35,Interrupt Collector Interrupt Register 35" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT35_SET,Interrupt Collector Interrupt Set Register 35" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT35_CLR,Interrupt Collector Interrupt Clear Register 35" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT35_TOG,Interrupt Collector Interrupt Toggle Register 35" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x360++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT36,Interrupt Collector Interrupt Register 36" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT36_SET,Interrupt Collector Interrupt Set Register 36" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT36_CLR,Interrupt Collector Interrupt Clear Register 36" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT36_TOG,Interrupt Collector Interrupt Toggle Register 36" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x370++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT37,Interrupt Collector Interrupt Register 37" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT37_SET,Interrupt Collector Interrupt Set Register 37" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT37_CLR,Interrupt Collector Interrupt Clear Register 37" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT37_TOG,Interrupt Collector Interrupt Toggle Register 37" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x380++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT38,Interrupt Collector Interrupt Register 38" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT38_SET,Interrupt Collector Interrupt Set Register 38" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT38_CLR,Interrupt Collector Interrupt Clear Register 38" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT38_TOG,Interrupt Collector Interrupt Toggle Register 38" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x390++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT39,Interrupt Collector Interrupt Register 39" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT39_SET,Interrupt Collector Interrupt Set Register 39" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT39_CLR,Interrupt Collector Interrupt Clear Register 39" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT39_TOG,Interrupt Collector Interrupt Toggle Register 39" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x3A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT40,Interrupt Collector Interrupt Register 40" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT40_SET,Interrupt Collector Interrupt Set Register 40" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT40_CLR,Interrupt Collector Interrupt Clear Register 40" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT40_TOG,Interrupt Collector Interrupt Toggle Register 40" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x3B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT41,Interrupt Collector Interrupt Register 41" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT41_SET,Interrupt Collector Interrupt Set Register 41" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT41_CLR,Interrupt Collector Interrupt Clear Register 41" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT41_TOG,Interrupt Collector Interrupt Toggle Register 41" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x3C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT42,Interrupt Collector Interrupt Register 42" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT42_SET,Interrupt Collector Interrupt Set Register 42" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT42_CLR,Interrupt Collector Interrupt Clear Register 42" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT42_TOG,Interrupt Collector Interrupt Toggle Register 42" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x3D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT43,Interrupt Collector Interrupt Register 43" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT43_SET,Interrupt Collector Interrupt Set Register 43" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT43_CLR,Interrupt Collector Interrupt Clear Register 43" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT43_TOG,Interrupt Collector Interrupt Toggle Register 43" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x3E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT44,Interrupt Collector Interrupt Register 44" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT44_SET,Interrupt Collector Interrupt Set Register 44" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT44_CLR,Interrupt Collector Interrupt Clear Register 44" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT44_TOG,Interrupt Collector Interrupt Toggle Register 44" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x3F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT45,Interrupt Collector Interrupt Register 45" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT45_SET,Interrupt Collector Interrupt Set Register 45" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT45_CLR,Interrupt Collector Interrupt Clear Register 45" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT45_TOG,Interrupt Collector Interrupt Toggle Register 45" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x400++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT46,Interrupt Collector Interrupt Register 46" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT46_SET,Interrupt Collector Interrupt Set Register 46" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT46_CLR,Interrupt Collector Interrupt Clear Register 46" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT46_TOG,Interrupt Collector Interrupt Toggle Register 46" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x410++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT47,Interrupt Collector Interrupt Register 47" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT47_SET,Interrupt Collector Interrupt Set Register 47" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT47_CLR,Interrupt Collector Interrupt Clear Register 47" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT47_TOG,Interrupt Collector Interrupt Toggle Register 47" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x420++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT48,Interrupt Collector Interrupt Register 48" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT48_SET,Interrupt Collector Interrupt Set Register 48" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT48_CLR,Interrupt Collector Interrupt Clear Register 48" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT48_TOG,Interrupt Collector Interrupt Toggle Register 48" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x450++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT51,Interrupt Collector Interrupt Register 51" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT51_SET,Interrupt Collector Interrupt Set Register 51" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT51_CLR,Interrupt Collector Interrupt Clear Register 51" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT51_TOG,Interrupt Collector Interrupt Toggle Register 51" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x470++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT53,Interrupt Collector Interrupt Register 53" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT53_SET,Interrupt Collector Interrupt Set Register 53" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT53_CLR,Interrupt Collector Interrupt Clear Register 53" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT53_TOG,Interrupt Collector Interrupt Toggle Register 53" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x480++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT54,Interrupt Collector Interrupt Register 54" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT54_SET,Interrupt Collector Interrupt Set Register 54" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT54_CLR,Interrupt Collector Interrupt Clear Register 54" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT54_TOG,Interrupt Collector Interrupt Toggle Register 54" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x4A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT56,Interrupt Collector Interrupt Register 56" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT56_SET,Interrupt Collector Interrupt Set Register 56" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT56_CLR,Interrupt Collector Interrupt Clear Register 56" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT56_TOG,Interrupt Collector Interrupt Toggle Register 56" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x4B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT57,Interrupt Collector Interrupt Register 57" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT57_SET,Interrupt Collector Interrupt Set Register 57" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT57_CLR,Interrupt Collector Interrupt Clear Register 57" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT57_TOG,Interrupt Collector Interrupt Toggle Register 57" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x4C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT58,Interrupt Collector Interrupt Register 58" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT58_SET,Interrupt Collector Interrupt Set Register 58" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT58_CLR,Interrupt Collector Interrupt Clear Register 58" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT58_TOG,Interrupt Collector Interrupt Toggle Register 58" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x4D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT59,Interrupt Collector Interrupt Register 59" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT59_SET,Interrupt Collector Interrupt Set Register 59" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT59_CLR,Interrupt Collector Interrupt Clear Register 59" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT59_TOG,Interrupt Collector Interrupt Toggle Register 59" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x4E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT60,Interrupt Collector Interrupt Register 60" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT60_SET,Interrupt Collector Interrupt Set Register 60" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT60_CLR,Interrupt Collector Interrupt Clear Register 60" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT60_TOG,Interrupt Collector Interrupt Toggle Register 60" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x4F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT61,Interrupt Collector Interrupt Register 61" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT61_SET,Interrupt Collector Interrupt Set Register 61" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT61_CLR,Interrupt Collector Interrupt Clear Register 61" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT61_TOG,Interrupt Collector Interrupt Toggle Register 61" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x520++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT64,Interrupt Collector Interrupt Register 64" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT64_SET,Interrupt Collector Interrupt Set Register 64" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT64_CLR,Interrupt Collector Interrupt Clear Register 64" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT64_TOG,Interrupt Collector Interrupt Toggle Register 64" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" group.long 0x530++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT65,Interrupt Collector Interrupt Register 65" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" textline " " bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT65_SET,Interrupt Collector Interrupt Set Register 65" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" textline " " bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT65_CLR,Interrupt Collector Interrupt Clear Register 65" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Cleared" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Cleared" bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT65_TOG,Interrupt Collector Interrupt Toggle Register 65" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" tree.end width 26. tree "Interrupt Debug Registers" rgroup.long 0x1120++0x2f line.long 0x00 "HW_ICOLL_DEBUG,Interrupt Collector Debug Register 0" bitfld.long 0x00 28.--31. " INSERVICE ,Nesting IRQs Inservice bits" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x00 24.--27. " LEVEL_REQUESTS ,Levels of Requests" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." textline " " bitfld.long 0x00 20.--23. " REQUESTS_BY_LEVEL ,Requests by level" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x00 17. " FIQ ,FIQ output CPU" "Not Requested,Requested" textline " " bitfld.long 0x00 16. " IRQ ,IRQ output CPU " "Not Requested,Requested" hexmask.long.word 0x00 0.--9. 1. " VECTOR_FSM ,FSM Vector" line.long 0x04 "HW_ICOLL_DEBUG_SET,Interrupt Collector Debug Set Register 0" bitfld.long 0x04 28.--31. " INSERVICE ,Nesting IRQs Inservice bits" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x04 24.--27. " LEVEL_REQUESTS ,Levels of Requests" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." textline " " bitfld.long 0x04 20.--23. " REQUESTS_BY_LEVEL ,Requests by level" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x04 17. " FIQ ,FIQ output CPU" "No effect,Set" textline " " bitfld.long 0x04 16. " IRQ ,IRQ output CPU" "No effect,Set" hexmask.long.word 0x04 0.--9. 1. " VECTOR_FSM ,FSM Vector" line.long 0x08 "HW_ICOLL_DEBUG_CLR,Interrupt Collector Debug Clear Register 0" bitfld.long 0x08 28.--31. " INSERVICE ,Nesting IRQs Inservice bits" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x08 24.--27. " LEVEL_REQUESTS ,Levels of Requests" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." textline " " bitfld.long 0x08 20.--23. " REQUESTS_BY_LEVEL ,Requests by level" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x08 17. " FIQ ,FIQ output CPU" "No effect,Cleared" textline " " bitfld.long 0x08 16. " IRQ ,IRQ output CPU" "No effect,Cleared" hexmask.long.word 0x08 0.--9. 1. " VECTOR_FSM ,FSM Vector" line.long 0x0c "HW_ICOLL_DEBUG_TOG,Interrupt Collector Debug Toggle Register 0" bitfld.long 0x0c 28.--31. " INSERVICE ,Nesting IRQs Inservice bits" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x0c 24.--27. " LEVEL_REQUESTS ,Levels of Requests" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." textline " " bitfld.long 0x0c 20.--23. " REQUESTS_BY_LEVEL ,Requests by level" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x0c 17. " FIQ ,FIQ output CPU" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " IRQ ,IRQ output CPU" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--9. 1. " VECTOR_FSM ,FSM Vector" line.long 0x10 "HW_ICOLL_DBGREAD0,Interrupt Collector Debug Read Register 0" line.long 0x14 "HW_ICOLL_DBGREAD0_SET,Interrupt Collector Debug Read Set Register 0" line.long 0x18 "HW_ICOLL_DBGREAD0_CLR,Interrupt Collector Debug Read Clear Register 0" line.long 0x1c "HW_ICOLL_DBGREAD0_TOG,Interrupt Collector Debug Read Toggle Register 0" line.long 0x20 "HW_ICOLL_DBGREAD1,Interrupt Collector Debug Read Register 1" line.long 0x24 "HW_ICOLL_DBGREAD1_SET,Interrupt Collector Debug Read Set Register 1" line.long 0x28 "HW_ICOLL_DBGREAD1_CLR,Interrupt Collector Debug Read Clear Register 1" line.long 0x2c "HW_ICOLL_DBGREAD1_TOG,Interrupt Collector Debug Read Toggle Register 1" group.long 0x1150++0x0f line.long 0x00 "HW_ICOLL_DBGFLAG,Interrupt Collector Debug Flag Register" hexmask.long.word 0x00 0.--15. 1. " FLAG ,debug facility is probably temporary" line.long 0x04 "HW_ICOLL_DBGFLAG_SET,Interrupt Collector Debug Flag Set Register" hexmask.long.word 0x04 0.--15. 1. " FLAG ,debug facility is probably temporary" line.long 0x08 "HW_ICOLL_DBGFLAG_CLR,Interrupt Collector Debug Flag Clear Register" hexmask.long.word 0x08 0.--15. 1. " FLAG ,debug facility is probably temporary" line.long 0x0c "HW_ICOLL_DBGFLAG_TOG,Interrupt Collector Debug Flag Toggle Register" hexmask.long.word 0x0c 0.--15. 1. " FLAG ,debug facility is probably temporary" rgroup.long 0x1160++0x2f line.long 0x00 "HW_ICOLL_DBGREQUEST0,Interrupt Collector Debug Read Request Register 0" bitfld.long 0x00 31. " BITS[31] ,TIMER3 Holding Request" "Not requested,Requested" bitfld.long 0x00 30. " BITS[30] ,TIMER2 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 29. " BITS[29] ,TIMER1 Holding Request" "Not requested,Requested" bitfld.long 0x00 28. " BITS[28] ,TIMER0 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 27. " BITS[27] ,I2C_ERROR Holding Request" "Not requested,Requested" bitfld.long 0x00 26. " BITS[26] ,I2C_DMA Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 25. " BITS[25] ,UARTAPP_RX_DMA Holding Request" "Not requested,Requested" bitfld.long 0x00 24. " BITS[24] ,UARTAPP_INTERNAL Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 23. " BITS[23] ,UARTAPP_TX_DMA Holding Request" "Not requested,Requested" bitfld.long 0x00 22. " BITS[22] ,RTC_ALARM Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 21. " BITS[21] ,ECC8_IRQ Holding Request" "Not requested,Requested" bitfld.long 0x00 20. " BITS[20] ,SSP2_DMA Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 19. " BITS[19] ,SAIF1_DMA Holding Request" "Not requested,Requested" bitfld.long 0x00 18. " BITS[18] ,GPIO2 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 17. " BITS[17] ,GPIO1 Holding Request" "Not requested,Requested" bitfld.long 0x00 16. " BITS[16] ,GPIO0 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 15. " BITS[15] ,SSP_ERROR Holding Request" "Not requested,Requested" bitfld.long 0x00 14. " BITS[14] ,SSP1_DMA Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 13. " BITS[13] ,GPMI_DMA Holding Request " "Not requested,Requested" bitfld.long 0x00 12. " BITS[12] ,USB_WAKEUP Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 11. " BITS[11] ,USB_CTRL Holding Request" "Not requested,Requested" bitfld.long 0x00 10. " BITS[10] ,SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ Holding Request " "Not requested,Requested" textline " " bitfld.long 0x00 9. " BITS[9] ,SPDIF_DMA,SAIF2_DMA Holding Request" "Not requested,Requested" bitfld.long 0x00 8. " BITS[8] ,ADC_ERROR Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BITS[7] ,ADC_DMA Holding Request" "Not requested,Requested" bitfld.long 0x00 6. " BITS[6] ,DAC_ERROR Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 5. " BITS[5] ,DAC_DMA Holding Request" "Not requested,Requested" bitfld.long 0x00 4. " BITS[4] ,HEADPHONE_SHORT Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BITS[3] ,VDD5V Holding Request" "Not requested,Requested" bitfld.long 0x00 2. " BITS[2] ,SSP2_ERROR Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 1. " BITS[1] ,COMMS_RX,COMMS_TX Holding Request" "Not requested,Requested" bitfld.long 0x00 0. " BITS[0] ,DEBUG_UART Holding Request" "Not requested,Requested" line.long 0x04 "HW_ICOLL_DBGREQUEST0_SET,Interrupt Collector Debug Read Request Set Register 0" bitfld.long 0x04 31. " BITS[31] ,TIMER3 Holding Request" "No effect,Set" bitfld.long 0x04 30. " BITS[30] ,TIMER2 Holding Request" "No effect,Set" textline " " bitfld.long 0x04 29. " BITS[29] ,TIMER1 Holding Request" "No effect,Set" bitfld.long 0x04 28. " BITS[28] ,TIMER0 Holding Request" "No effect,Set" textline " " bitfld.long 0x04 27. " BITS[27] ,I2C_ERROR Holding Request" "No effect,Set" bitfld.long 0x04 26. " BITS[26] ,I2C_DMA Holding Request" "No effect,Set" textline " " bitfld.long 0x04 25. " BITS[25] ,UARTAPP_RX_DMA Holding Request" "No effect,Set" bitfld.long 0x04 24. " BITS[24] ,UARTAPP_INTERNAL Holding Request" "No effect,Set" textline " " bitfld.long 0x04 23. " BITS[23] ,UARTAPP_TX_DMA Holding Request" "No effect,Set" bitfld.long 0x04 22. " BITS[22] ,RTC_ALARM Holding Request" "No effect,Set" textline " " bitfld.long 0x04 21. " BITS[21] ,ECC8_IRQ Holding Request" "No effect,Set" bitfld.long 0x04 20. " BITS[20] ,SSP2_DMA Holding Request" "No effect,Set" textline " " bitfld.long 0x04 19. " BITS[19] ,SAIF1_DMA Holding Request" "No effect,Set" bitfld.long 0x04 18. " BITS[18] ,GPIO2 Holding Request" "No effect,Set" textline " " bitfld.long 0x04 17. " BITS[17] ,GPIO1 Holding Request" "No effect,Set" bitfld.long 0x04 16. " BITS[16] ,GPIO0 Holding Request" "No effect,Set" textline " " bitfld.long 0x04 15. " BITS[15] ,SSP_ERROR Holding Request" "No effect,Set" bitfld.long 0x04 14. " BITS[14] ,SSP1_DMA Holding Request" "No effect,Set" textline " " bitfld.long 0x04 13. " BITS[13] ,GPMI_DMA Holding Request" "No effect,Set" bitfld.long 0x04 12. " BITS[12] ,USB_WAKEUP Holding Request" "No effect,Set" textline " " bitfld.long 0x04 11. " BITS[11] ,USB_CTRL Holding Request" "No effect,Set" bitfld.long 0x04 10. " BITS[10] ,SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ Holding Request" "No effect,Set" textline " " bitfld.long 0x04 9. " BITS[9] ,SPDIF_DMA,SAIF2_DMA Holding Request" "No effect,Set" bitfld.long 0x04 8. " BITS[8] ,ADC_ERROR Holding Request" "No effect,Set" textline " " bitfld.long 0x04 7. " BITS[7] ,ADC_DMA Holding Request" "No effect,Set" bitfld.long 0x04 6. " BITS[6] ,DAC_ERROR Holding Request" "No effect,Set" textline " " bitfld.long 0x04 5. " BITS[5] ,DAC_DMA Holding Request" "No effect,Set" bitfld.long 0x04 4. " BITS[4] ,HEADPHONE_SHORT Holding Request" "No effect,Set" textline " " bitfld.long 0x04 3. " BITS[3] ,VDD5V Holding Request" "No effect,Set" bitfld.long 0x04 2. " BITS[2] ,SSP2_ERROR Holding Request" "No effect,Set" textline " " bitfld.long 0x04 1. " BITS[1] ,COMMS_RX,COMMS_TX Holding Request" "No effect,Set" bitfld.long 0x04 0. " BITS[0] ,DEBUG_UART Holding Request" "No effect,Set" line.long 0x08 "HW_ICOLL_DBGREQUEST0_CLR,Interrupt Collector Debug Read Request Clear Register 0" bitfld.long 0x08 31. " BITS[31] ,TIMER3 Holding Request" "No effect,Cleared" bitfld.long 0x08 30. " BITS[30] ,TIMER2 Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 29. " BITS[29] ,TIMER1 Holding Request" "No effect,Cleared" bitfld.long 0x08 28. " BITS[28] ,TIMER0 Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 27. " BITS[27] ,I2C_ERROR Holding Request" "No effect,Cleared" bitfld.long 0x08 26. " BITS[26] ,I2C_DMA Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 25. " BITS[25] ,UARTAPP_RX_DMA Holding Request" "No effect,Cleared" bitfld.long 0x08 24. " BITS[24] ,UARTAPP_INTERNAL Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 23. " BITS[23] ,UARTAPP_TX_DMA Holding Request" "No effect,Cleared" bitfld.long 0x08 22. " BITS[22] ,RTC_ALARM Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 21. " BITS[21] ,ECC8_IRQ Holding Request" "No effect,Cleared" bitfld.long 0x08 20. " BITS[20] ,SSP2_DMA Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 19. " BITS[19] ,SAIF1_DMA Holding Request" "No effect,Cleared" bitfld.long 0x08 18. " BITS[18] ,GPIO2 Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 17. " BITS[17] ,GPIO1 Holding Request" "No effect,Cleared" bitfld.long 0x08 16. " BITS[16] ,GPIO0 Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 15. " BITS[15] ,SSP_ERROR Holding Request" "No effect,Cleared" bitfld.long 0x08 14. " BITS[14] ,SSP1_DMA Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 13. " BITS[13] ,GPMI_DMA Holding Request" "No effect,Cleared" bitfld.long 0x08 12. " BITS[12] ,USB_WAKEUP Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 11. " BITS[11] ,USB_CTRL Holding Request" "No effect,Cleared" bitfld.long 0x08 10. " BITS[10] ,SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 9. " BITS[9] ,SPDIF_DMA,SAIF2_DMA Holding Request" "No effect,Cleared" bitfld.long 0x08 8. " BITS[8] ,ADC_ERROR Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 7. " BITS[7] ,ADC_DMA Holding Request" "No effect,Cleared" bitfld.long 0x08 6. " BITS[6] ,DAC_ERROR Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 5. " BITS[5] ,DAC_DMA Holding Request" "No effect,Cleared" bitfld.long 0x08 4. " BITS[4] ,HEADPHONE_SHORT Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 3. " BITS[3] ,VDD5V Holding Request" "No effect,Cleared" bitfld.long 0x08 2. " BITS[2] ,SSP2_ERROR Holding Request" "No effect,Cleared" textline " " bitfld.long 0x08 1. " BITS[1] ,COMMS_RX,COMMS_TX Holding Request" "No effect,Cleared" bitfld.long 0x08 0. " BITS[0] ,DEBUG_UART Holding Request" "No effect,Cleared" line.long 0x0c "HW_ICOLL_DBGREQUEST0_TOG,Interrupt Collector Debug Read Request Toggle Register 0" bitfld.long 0x0c 31. " BITS[31] ,TIMER3 Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 30. " BITS[30] ,TIMER2 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " BITS[29] ,TIMER1 Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 28. " BITS[28] ,TIMER0 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " BITS[27] ,I2C_ERROR Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 26. " BITS[26] ,I2C_DMA Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " BITS[25] ,UARTAPP_RX_DMA Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 24. " BITS[24] ,UARTAPP_INTERNAL Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " BITS[23] ,UARTAPP_TX_DMA Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 22. " BITS[22] ,RTC_ALARM Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " BITS[21] ,ECC8_IRQ Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 20. " BITS[20] ,SSP2_DMA Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " BITS[19] ,SAIF1_DMA Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 18. " BITS[18] ,GPIO2 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " BITS[17] ,GPIO1 Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 16. " BITS[16] ,GPIO0 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " BITS[15] ,SSP_ERROR Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 14. " BITS[14] ,SSP1_DMA Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " BITS[13] ,GPMI_DMA Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 12. " BITS[12] ,USB_WAKEUP Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " BITS[11] ,USB_CTRL Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 10. " BITS[10] ,SPDIF_ERROR, SAIF1_IRQ, SAIF2_IRQ Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " BITS[9] ,SPDIF_DMA,SAIF2_DMA Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 8. " BITS[8] ,ADC_ERROR Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " BITS[7] ,ADC_DMA Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 6. " BITS[6] ,DAC_ERROR Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " BITS[5] ,DAC_DMA Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 4. " BITS[4] ,HEADPHONE_SHORT Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " BITS[3] ,VDD5V Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 2. " BITS[2] ,SSP2_ERROR Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " BITS[1] ,COMMS_RX,COMMS_TX Holding Request" "Not toggle,Toggle" bitfld.long 0x0c 0. " BITS[0] ,DEBUG_UART Holding Request" "Not toggle,Toggle" line.long 0x10 "HW_ICOLL_DBGREQUEST1,Interrupt Collector Debug Read Request Register 1" bitfld.long 0x10 29. " BITS[61] ,VDAC_DETECT Holding Request" "Not requested,Requested" bitfld.long 0x10 28. " BITS[60] ,UARTAPP2_RX_DMA Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 27. " BITS[59] ,UARTAPP2_INTERNAL Holding Request" "Not requested,Requested" bitfld.long 0x10 26. " BITS[58] ,UARTAPP2_TX_DMA Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 25. " BITS[57] ,PXP Holding Request " "Not requested,Requested" bitfld.long 0x10 24. " BITS[56] ,BCH Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 22. " BITS[54] ,DCP Holding Request" "Not requested,Requested" bitfld.long 0x10 21. " BITS[53] ,DCP_VMI Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 19. " BITS[51] ,GPMI Holding Request" "Not requested,Requested" bitfld.long 0x10 16. " BITS[48] ,RTC_1MSEC Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 15. " BITS[47] ,DIGCTL_DEBUG_TRAP Holding Request" "Not requested,Requested" bitfld.long 0x10 14. " BITS[46] ,LCDIF_ERROR Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 13. " BITS[45] ,LCDIF_DMA Holding Request" "Not requested,Requested" bitfld.long 0x10 12. " BITS[44] ,LRADC_CH7 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 11. " BITS[43] ,LRADC_CH6 Holding Request" "Not requested,Requested" bitfld.long 0x10 10. " BITS[42] ,LRADC_CH5 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 9. " BITS[41] ,LRADC_CH4 Holding Request" "Not requested,Requested" bitfld.long 0x10 8. " BITS[40] ,LRADC_CH3 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 7. " BITS[39] ,LRADC_CH2 Holding Request" "Not requested,Requested" bitfld.long 0x10 6. " BITS[38] ,LRADC_CH1 Holding Request " "Not requested,Requested" textline " " bitfld.long 0x10 5. " BITS[37] ,LRADC_CH0 Holding Request" "Not requested,Requested" bitfld.long 0x10 4. " BITS[36] ,TOUCH_DETECT Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 3. " BITS[35] ,VDD18_BRNOUT Holding Request" "Not requested,Requested" bitfld.long 0x10 2. " BITS[34] ,VDDIO_BRNOUT Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 1. " BITS[33] ,VDDD_BRNOUT Holding Request" "Not requested,Requested" bitfld.long 0x10 0. " BITS[32] ,BATT_BRNOUT Holding Request" "Not requested,Requested" line.long 0x14 "HW_ICOLL_DBGREQUEST1_SET,Interrupt Collector Debug Read Request Set Register 1" bitfld.long 0x14 29. " BITS[61] ,VDAC_DETECT Holding Request" "No effect,Set" bitfld.long 0x14 28. " BITS[60] ,UARTAPP2_RX_DMA Holding Request" "No effect,Set" textline " " bitfld.long 0x14 27. " BITS[59] ,UARTAPP2_INTERNAL Holding Request" "No effect,Set" bitfld.long 0x14 26. " BITS[58] ,UARTAPP2_TX_DMA Holding Request" "No effect,Set" textline " " bitfld.long 0x14 25. " BITS[57] ,PXP Holding Request" "No effect,Set" bitfld.long 0x14 24. " BITS[56] ,BCH Holding Request" "No effect,Set" textline " " bitfld.long 0x14 22. " BITS[54] ,DCP Holding Request" "No effect,Set" bitfld.long 0x14 21. " BITS[53] ,DCP_VMI Holding Request" "No effect,Set" textline " " bitfld.long 0x14 19. " BITS[51] ,GPMI Holding Request" "No effect,Set" bitfld.long 0x14 16. " BITS[48] ,RTC_1MSEC Holding Request" "No effect,Set" textline " " bitfld.long 0x14 15. " BITS[47] ,DIGCTL_DEBUG_TRAP Holding Request" "No effect,Set" bitfld.long 0x14 14. " BITS[46] ,LCDIF_ERROR Holding Request" "No effect,Set" textline " " bitfld.long 0x14 13. " BITS[45] ,LCDIF_DMA Holding Request" "No effect,Set" bitfld.long 0x14 12. " BITS[44] ,LRADC_CH7 Holding Request" "No effect,Set" textline " " bitfld.long 0x14 11. " BITS[43] ,LRADC_CH6 Holding Request" "No effect,Set" bitfld.long 0x14 10. " BITS[42] ,LRADC_CH5 Holding Request" "No effect,Set" textline " " bitfld.long 0x14 9. " BITS[41] ,LRADC_CH4 Holding Request" "No effect,Set" bitfld.long 0x14 8. " BITS[40] ,LRADC_CH3 Holding Request" "No effect,Set" textline " " bitfld.long 0x14 7. " BITS[39] ,LRADC_CH2 Holding Request" "No effect,Set" bitfld.long 0x14 6. " BITS[38] ,LRADC_CH1 Holding Request" "No effect,Set" textline " " bitfld.long 0x14 5. " BITS[37] ,LRADC_CH0 Holding Request" "No effect,Set" bitfld.long 0x14 4. " BITS[36] ,TOUCH_DETECT Holding Request" "No effect,Set" textline " " bitfld.long 0x14 3. " BITS[35] ,VDD18_BRNOUT Holding Request" "No effect,Set" bitfld.long 0x14 2. " BITS[34] ,VDDIO_BRNOUT Holding Request" "No effect,Set" textline " " bitfld.long 0x14 1. " BITS[33] ,VDDD_BRNOUT Holding Request" "No effect,Set" bitfld.long 0x14 0. " BITS[32] ,BATT_BRNOUT Holding Request" "No effect,Set" line.long 0x18 "HW_ICOLL_DBGREQUEST1_CLR,Interrupt Collector Debug Read Request Clear Register 1" bitfld.long 0x18 29. " BITS[61] ,VDAC_DETECT Holding Request" "No effect,Cleared" bitfld.long 0x18 28. " BITS[60] ,UARTAPP2_RX_DMA Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 27. " BITS[59] ,UARTAPP2_INTERNAL Holding Request" "No effect,Cleared" bitfld.long 0x18 26. " BITS[58] ,UARTAPP2_TX_DMA Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 25. " BITS[57] ,PXP Holding Request" "No effect,Cleared" bitfld.long 0x18 24. " BITS[56] ,BCH Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 22. " BITS[54] ,DCP Holding Request" "No effect,Cleared" bitfld.long 0x18 21. " BITS[53] ,DCP_VMI Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 19. " BITS[51] ,GPMI Holding Request" "No effect,Cleared" bitfld.long 0x18 16. " BITS[48] ,RTC_1MSEC Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 15. " BITS[47] ,DIGCTL_DEBUG_TRAP Holding Request" "No effect,Cleared" bitfld.long 0x18 14. " BITS[46] ,LCDIF_ERROR Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 13. " BITS[45] ,LCDIF_DMA Holding Request" "No effect,Cleared" bitfld.long 0x18 12. " BITS[44] ,LRADC_CH7 Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 11. " BITS[43] ,LRADC_CH6 Holding Request" "No effect,Cleared" bitfld.long 0x18 10. " BITS[42] ,LRADC_CH5 Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 9. " BITS[41] ,LRADC_CH4 Holding Request" "No effect,Cleared" bitfld.long 0x18 8. " BITS[40] ,LRADC_CH3 Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 7. " BITS[39] ,LRADC_CH2 Holding Request" "No effect,Cleared" bitfld.long 0x18 6. " BITS[38] ,LRADC_CH1 Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 5. " BITS[37] ,LRADC_CH0 Holding Request" "No effect,Cleared" bitfld.long 0x18 4. " BITS[36] ,TOUCH_DETECT Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 3. " BITS[35] ,VDD18_BRNOUT Holding Request" "No effect,Cleared" bitfld.long 0x18 2. " BITS[34] ,VDDIO_BRNOUT Holding Request" "No effect,Cleared" textline " " bitfld.long 0x18 1. " BITS[33] ,VDDD_BRNOUT Holding Request" "No effect,Cleared" bitfld.long 0x18 0. " BITS[32] ,BATT_BRNOUT Holding Request" "No effect,Cleared" line.long 0x1c "HW_ICOLL_DBGREQUEST1_TOG,Interrupt Collector Debug Read Request Toggle Register 1" bitfld.long 0x1c 29. " BITS[61] ,VDAC_DETECT Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 28. " BITS[60] ,UARTAPP2_RX_DMA Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 27. " BITS[59] ,UARTAPP2_INTERNAL Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 26. " BITS[58] ,UARTAPP2_TX_DMA Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 25. " BITS[57] ,PXP Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 24. " BITS[56] ,BCH Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 22. " BITS[54] ,DCP Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 21. " BITS[53] ,DCP_VMI Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 19. " BITS[51] ,GPMI Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 16. " BITS[48] ,RTC_1MSEC Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 15. " BITS[47] ,DIGCTL_DEBUG_TRAP Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 14. " BITS[46] ,LCDIF_ERROR Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 13. " BITS[45] ,LCDIF_DMA Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 12. " BITS[44] ,LRADC_CH7 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 11. " BITS[43] ,LRADC_CH6 Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 10. " BITS[42] ,LRADC_CH5 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 9. " BITS[41] ,LRADC_CH4 Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 8. " BITS[40] ,LRADC_CH3 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 7. " BITS[39] ,LRADC_CH2 Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 6. " BITS[38] ,LRADC_CH1 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 5. " BITS[37] ,LRADC_CH0 Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 4. " BITS[36] ,TOUCH_DETECT Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " BITS[35] ,VDD18_BRNOUT Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 2. " BITS[34] ,VDDIO_BRNOUT Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " BITS[33] ,VDDD_BRNOUT Holding Request" "Not toggle,Toggle" bitfld.long 0x1c 0. " BITS[32] ,BATT_BRNOUT Holding Request" "Not toggle,Toggle" line.long 0x20 "HW_ICOLL_DBGREQUEST2,Interrupt Collector Debug Read Request Register 2" bitfld.long 0x20 1. " BITS[65] ,DCDC4P2_BO Holding Request" "Not requested,Requested" bitfld.long 0x20 0. " BITS[64] ,VDD5V_DROOP Holding Request" "Not requested,Requested" line.long 0x24 "HW_ICOLL_DBGREQUEST2_SET,Interrupt Collector Debug Read Request Set Register 2" bitfld.long 0x24 1. " BITS[65] ,DCDC4P2_BO Holding Request" "No effect,Set" bitfld.long 0x24 0. " BITS[64] ,VDD5V_DROOP Holding Request" "No effect,Set" line.long 0x28 "HW_ICOLL_DBGREQUEST2_CLR,Interrupt Collector Debug Read Request Clear Register 2" bitfld.long 0x28 1. " BITS[65] ,DCDC4P2_BO Holding Request" "No effect,Cleared" bitfld.long 0x28 0. " BITS[64] ,VDD5V_DROOP Holding Request" "No effect,Cleared" line.long 0x2c "HW_ICOLL_DBGREQUEST2_TOG,Interrupt Collector Debug Read Request Toggle Register 2" bitfld.long 0x2c 1. " BITS[65] ,DCDC4P2_BO Holding Request" "Not toggle,Toggle" bitfld.long 0x2c 0. " BITS[64] ,VDD5V_DROOP Holding Request" "Not toggle,Toggle" tree.end width 18. tree "Interrupt ID Registers" rgroup.long 0x11E0++0x03 line.long 0x00 "HW_ICOLL_VERSION,Interrupt Collector Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end width 0xb tree.end tree "DIGCTL (Digital Control and On-Chip RAM)" base asd:0x8001c000 width 22. group.long 0x00++0x0f line.long 0x00 "HW_DIGCTL_CTRL,DIGCTL Control Register" bitfld.long 0x00 30. " XTAL24M_GATE ,Digital Control Microseconds counter" "Enabled,Disabled" bitfld.long 0x00 29. " TRAP_IRQ ,Trap IRQ" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " CACHE_BIST_TMODE ,Cache BIST test mode enable" "Disabled,Enabled" bitfld.long 0x00 25. " LCD_BIST_CLKEN ,LCD memory BIST clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " LCD_BIST_START ,LCD memory BIST start" "Not started,Started" bitfld.long 0x00 23. " DCP_BIST_CLKEN ,DCP memory BIST clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " DCP_BIST_START ,DCP memory BIST start" "Not started,Started" bitfld.long 0x00 21. " ARM_BIST_CLKEN ,ARM BIST clock enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " USB_TESTMODE ,USB test mode" "Not entered,Entered" bitfld.long 0x00 19. " ANALOG_TESTMODE ,analog test mode" "Not entered,Entered" textline " " bitfld.long 0x00 18. " DIGITAL_TESTMODE ,digital test mode" "Not entered,Entered" bitfld.long 0x00 17. " ARM_BIST_START ,ARM cache BIST controller start" "Not started,Started" textline " " bitfld.long 0x00 16. " UART_LOOPBACK ,Uart Loopback mode" "Normal,Loopback" bitfld.long 0x00 15. " SAIF_LOOPBACK ,Saif Loopback mode" "Normal,Loopback" textline " " bitfld.long 0x00 13.--14. " SAIF_CLKMUX_SEL ,Selects the muxed pins and directions for the SAIF1 and SAIF2 master clock (MCLK), bit clock (BITCLK), and left/right sample clock (LRCLK)" "MBL_CLK_OUT,BL_CLK_OUT,UM_CLK_OT_BL_CLK_IN,BL_CLK_IN" bitfld.long 0x00 12. " SAIF_CLKMST_SEL ,Selects whether SAIF1 or SAIF2 drives MCLK/BITCLK/LRCLK" "SAIF1_MST,SAIF2_MST" textline " " bitfld.long 0x00 11. " SAIF_ALT_BITCLK_SEL ,SAIF2_SDATA2 or LCD_D16 is used to input/output BITCLK" "SAIF2_SDATA2,LCD_D16" bitfld.long 0x00 9. " SY_ENDIAN ,SY endian mode" "Little endian,Big endian" textline " " bitfld.long 0x00 8. " SY_SFTRST ,SY reset" "No reset,Reset" bitfld.long 0x00 7. " SY_CLKGATE ,SY Clock Gate" "Not gated,Gated" textline " " bitfld.long 0x00 6. " USE_SERIAL_JTAG ,JTAG interface mode" "Six-wire parallel,One-wire serial" bitfld.long 0x00 5. " TRAP_IN_RANGE ,debug trap function causes a match when the master address is inside the specified range " "Outside range,Inside range" textline " " bitfld.long 0x00 4. " TRAP_ENABLE ,AHB arbiter debug trap functions" "Not occurred,Occurred" bitfld.long 0x00 3. " DEBUG_DISABLE ,ARM core's debug logic disable" "Enabled,Disabled" textline " " bitfld.long 0x00 2. " USB_CLKGATE ,USB Clock Gate" "RUN,NO_CLKS" bitfld.long 0x00 1. " JTAG_SHIELD ,JTAG Shield debugger mode" "NORMAL,SHIELDS_UP" textline " " bitfld.long 0x00 0. " LATCH_ENTROPY ,Latch entropy" "Not latched,Latched" line.long 0x04 "HW_DIGCTL_CTRL_SET,DIGCTL Control Set Register" bitfld.long 0x04 30. " XTAL24M_GATE ,Digital Control Microseconds counter" "No effect,Set" bitfld.long 0x04 29. " TRAP_IRQ ,Trap IRQ" "No effect,Set" textline " " bitfld.long 0x04 26. " CACHE_BIST_TMODE ,Cache BIST test mode enable" "No effect,Set" bitfld.long 0x04 25. " LCD_BIST_CLKEN ,LCD memory BIST clock enable" "No effect,Set" textline " " bitfld.long 0x04 24. " LCD_BIST_START ,LCD memory BIST start" "No effect,Set" bitfld.long 0x04 23. " DCP_BIST_CLKEN ,DCP memory BIST clock enable" "No effect,Set" textline " " bitfld.long 0x04 22. " DCP_BIST_START ,DCP memory BIST start" "No effect,Set" bitfld.long 0x04 21. " ARM_BIST_CLKEN ,ARM BIST clock enable" "No effect,Set" textline " " bitfld.long 0x04 20. " USB_TESTMODE ,USB test mode" "No effect,Set" bitfld.long 0x04 19. " ANALOG_TESTMODE ,analog test mode" "No effect,Set" textline " " bitfld.long 0x04 18. " DIGITAL_TESTMODE ,digital test mode" "No effect,Set" bitfld.long 0x04 17. " ARM_BIST_START ,ARM cache BIST controller start" "No effect,Set" textline " " bitfld.long 0x04 16. " UART_LOOPBACK ,Uart Loopback mode" "No effect,Set" bitfld.long 0x04 15. " SAIF_LOOPBACK ,Saif Loopback mode" "No effect,Set" textline " " bitfld.long 0x04 13.--14. " SAIF_CLKMUX_SEL ,Selects the muxed pins and directions for the SAIF1 and SAIF2 master clock (MCLK), bit clock (BITCLK), and left/right sample clock (LRCLK)" "MBL_CLK_OUT,BL_CLK_OUT,UM_CLK_OT_BL_CLK_IN,BL_CLK_IN" bitfld.long 0x04 12. " SAIF_CLKMST_SEL ,Selects whether SAIF1 or SAIF2 drives MCLK/BITCLK/LRCLK" "No effect,Set" textline " " bitfld.long 0x04 11. " SAIF_ALT_BITCLK_SEL ,SAIF2_SDATA2 or LCD_D16 is used to input/output BITCLK" "No effect,Set" bitfld.long 0x04 9. " SY_ENDIAN ,SY endian mode" "No effect,Set" textline " " bitfld.long 0x04 8. " SY_SFTRST ,SY reset" "No effect,Set" bitfld.long 0x04 7. " SY_CLKGATE ,SY Clock Gate" "No effect,Set" textline " " bitfld.long 0x04 6. " USE_SERIAL_JTAG ,JTAG interface mode" "No effect,Set" bitfld.long 0x04 5. " TRAP_IN_RANGE ,debug trap function causes a match when the master address is inside the specified range " "No effect,Set" textline " " bitfld.long 0x04 4. " TRAP_ENABLE ,AHB arbiter debug trap functions" "No effect,Set" bitfld.long 0x04 3. " DEBUG_DISABLE ,ARM core's debug logic disable" "No effect,Set" textline " " bitfld.long 0x04 2. " USB_CLKGATE ,USB Clock Gate" "No effect,Set" bitfld.long 0x04 1. " JTAG_SHIELD ,JTAG Shield debugger mode" "No effect,Set" textline " " bitfld.long 0x04 0. " LATCH_ENTROPY ,Latch entropy" "No effect,Set" line.long 0x08 "HW_DIGCTL_CTRL_CLR,DIGCTL Control Clear Register" bitfld.long 0x08 30. " XTAL24M_GATE ,Digital Control Microseconds counter" "No effect,Cleared" bitfld.long 0x08 29. " TRAP_IRQ ,Trap IRQ" "No effect,Cleared" textline " " bitfld.long 0x08 26. " CACHE_BIST_TMODE ,Cache BIST test mode enable" "No effect,Cleared" bitfld.long 0x08 25. " LCD_BIST_CLKEN ,LCD memory BIST clock enable" "No effect,Cleared" textline " " bitfld.long 0x08 24. " LCD_BIST_START ,LCD memory BIST start" "No effect,Cleared" bitfld.long 0x08 23. " DCP_BIST_CLKEN ,DCP memory BIST clock enable" "No effect,Cleared" textline " " bitfld.long 0x08 22. " DCP_BIST_START ,DCP memory BIST start" "No effect,Cleared" bitfld.long 0x08 21. " ARM_BIST_CLKEN ,ARM BIST clock enable" "No effect,Cleared" textline " " bitfld.long 0x08 20. " USB_TESTMODE ,USB test mode" "No effect,Cleared" bitfld.long 0x08 19. " ANALOG_TESTMODE ,analog test mode" "No effect,Cleared" textline " " bitfld.long 0x08 18. " DIGITAL_TESTMODE ,digital test mode" "No effect,Cleared" bitfld.long 0x08 17. " ARM_BIST_START ,ARM cache BIST controller start" "No effect,Cleared" textline " " bitfld.long 0x08 16. " UART_LOOPBACK ,Uart Loopback mode" "No effect,Cleared" bitfld.long 0x08 15. " SAIF_LOOPBACK ,Saif Loopback mode" "No effect,Cleared" textline " " bitfld.long 0x08 13.--14. " SAIF_CLKMUX_SEL ,Selects the muxed pins and directions for the SAIF1 and SAIF2 master clock (MCLK), bit clock (BITCLK), and left/right sample clock (LRCLK)" "MBL_CLK_OUT,BL_CLK_OUT,UM_CLK_OT_BL_CLK_IN,BL_CLK_IN" bitfld.long 0x08 12. " SAIF_CLKMST_SEL ,Selects whether SAIF1 or SAIF2 drives MCLK/BITCLK/LRCLK" "No effect,Cleared" textline " " bitfld.long 0x08 11. " SAIF_ALT_BITCLK_SEL ,SAIF2_SDATA2 or LCD_D16 is used to input/output BITCLK" "No effect,Cleared" bitfld.long 0x08 9. " SY_ENDIAN ,SY endian mode" "No effect,Cleared" textline " " bitfld.long 0x08 8. " SY_SFTRST ,SY reset" "No effect,Cleared" bitfld.long 0x08 7. " SY_CLKGATE ,SY Clock Gate" "No effect,Cleared" textline " " bitfld.long 0x08 6. " USE_SERIAL_JTAG ,JTAG interface mode" "No effect,Cleared" bitfld.long 0x08 5. " TRAP_IN_RANGE ,debug trap function causes a match when the master address is inside the specified range " "No effect,Cleared" textline " " bitfld.long 0x08 4. " TRAP_ENABLE ,AHB arbiter debug trap functions" "No effect,Cleared" bitfld.long 0x08 3. " DEBUG_DISABLE ,ARM core's debug logic disable" "No effect,Cleared" textline " " bitfld.long 0x08 2. " USB_CLKGATE ,USB Clock Gate" "No effect,Cleared" bitfld.long 0x08 1. " JTAG_SHIELD ,JTAG Shield debugger mode" "No effect,Cleared" textline " " bitfld.long 0x08 0. " LATCH_ENTROPY ,Latch entropy" "No effect,Cleared" line.long 0x0c "HW_DIGCTL_CTRL_TOG,DIGCTL Control Toggle Register" bitfld.long 0x0c 30. " XTAL24M_GATE ,Digital Control Microseconds counter" "Not toggle,Toggle" bitfld.long 0x0c 29. " TRAP_IRQ ,Trap IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " CACHE_BIST_TMODE ,Cache BIST test mode enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " LCD_BIST_CLKEN ,LCD memory BIST clock enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " LCD_BIST_START ,LCD memory BIST start" "Not toggle,Toggle" bitfld.long 0x0c 23. " DCP_BIST_CLKEN ,DCP memory BIST clock enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " DCP_BIST_START ,DCP memory BIST start" "Not toggle,Toggle" bitfld.long 0x0c 21. " ARM_BIST_CLKEN ,ARM BIST clock enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " USB_TESTMODE ,USB test mode" "Not toggle,Toggle" bitfld.long 0x0c 19. " ANALOG_TESTMODE ,analog test mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " DIGITAL_TESTMODE ,digital test mode" "Not toggle,Toggle" bitfld.long 0x0c 17. " ARM_BIST_START ,ARM cache BIST controller start" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " UART_LOOPBACK ,Uart Loopback mode" "Not toggle,Toggle" bitfld.long 0x0c 15. " SAIF_LOOPBACK ,Saif Loopback mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13.--14. " SAIF_CLKMUX_SEL ,Selects the muxed pins and directions for the SAIF1 and SAIF2 master clock (MCLK), bit clock (BITCLK), and left/right sample clock (LRCLK)" "MBL_CLK_OUT,BL_CLK_OUT,UM_CLK_OT_BL_CLK_IN,BL_CLK_IN" bitfld.long 0x0c 12. " SAIF_CLKMST_SEL ,Selects whether SAIF1 or SAIF2 drives MCLK/BITCLK/LRCLK" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SAIF_ALT_BITCLK_SEL ,SAIF2_SDATA2 or LCD_D16 is used to input/output BITCLK" "Not toggle,Toggle" bitfld.long 0x0c 9. " SY_ENDIAN ,SY endian mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SY_SFTRST ,SY reset" "Not toggle,Toggle" bitfld.long 0x0c 7. " SY_CLKGATE ,SY Clock Gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " USE_SERIAL_JTAG ,JTAG interface mode" "Not toggle,Toggle" bitfld.long 0x0c 5. " TRAP_IN_RANGE ,debug trap function causes a match when the master address is inside the specified range " "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " TRAP_ENABLE ,AHB arbiter debug trap functions" "Not toggle,Toggle" bitfld.long 0x0c 3. " DEBUG_DISABLE ,ARM core's debug logic disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " USB_CLKGATE ,USB Clock Gate" "Not toggle,Toggle" bitfld.long 0x0c 1. " JTAG_SHIELD ,JTAG Shield debugger mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " LATCH_ENTROPY ,Latch entropy" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_DIGCTL_STATUS,DIGCTL Status Register" bitfld.long 0x00 31. " USB_HS_PRESENT ,USB High-Speed Present" "Not present,Present" bitfld.long 0x00 30. " USB_OTG_PRESENT ,USB On-the-Go Present" "Not present,Present" textline " " bitfld.long 0x00 29. " USB_HOST_PRESENT ,USB Host Present" "Not present,Present" bitfld.long 0x00 28. " USB_DEVICE_PRESENT ,USB Device Present" "Not present,Present" textline " " bitfld.long 0x00 10. " DCP_BIST_FAIL ,DCP memory BIST failure" "Not failed,Failed" bitfld.long 0x00 9. " DCP_BIST_PASS ,DCP memory BIST pass" "Not passed,Passed" textline " " bitfld.long 0x00 8. " DCP_BIST_DONE ,DCP memory BIST done" "Not completed,Completed" bitfld.long 0x00 7. " LCD_BIST_FAIL ,LCD memory BIST failure" "Not failed,Failed" textline " " bitfld.long 0x00 6. " LCD_BIST_PASS ,LCD memory BIST pass" "Not passed,Passed" bitfld.long 0x00 5. " LCD_BIST_DONE ,LCD memory BIST done" "Not completed,Completed" textline " " bitfld.long 0x00 4. " JTAG_IN_USE ,JTAG in use" "Not used,Used" bitfld.long 0x00 1.--3. " PACKAGE_TYPE ,Type of package" "169BGA,Reserved,Reserved,128TQFP,?..." textline " " bitfld.long 0x00 0. " WRITTEN ,Write to HW_DIGCTL_WRITEONCE register" "Not succeeded,Succeeded" group.long 0x14++0x0b line.long 0x00 "HW_DIGCTL_STATUS_SET,DIGCTL Status Set Register" bitfld.long 0x00 31. " USB_HS_PRESENT ,USB High-Speed Present" "No effect,Set" bitfld.long 0x00 30. " USB_OTG_PRESENT ,USB On-the-Go Present" "No effect,Set" textline " " bitfld.long 0x00 29. " USB_HOST_PRESENT ,USB Host Present" "No effect,Set" bitfld.long 0x00 28. " USB_DEVICE_PRESENT ,USB Device Present" "No effect,Set" textline " " bitfld.long 0x00 10. " DCP_BIST_FAIL ,DCP memory BIST failure" "No effect,Set" bitfld.long 0x00 9. " DCP_BIST_PASS ,DCP memory BIST pass" "No effect,Set" textline " " bitfld.long 0x00 8. " DCP_BIST_DONE ,DCP memory BIST done" "No effect,Set" bitfld.long 0x00 7. " LCD_BIST_FAIL ,LCD memory BIST failure" "No effect,Set" textline " " bitfld.long 0x00 6. " LCD_BIST_PASS ,LCD memory BIST pass" "No effect,Set" bitfld.long 0x00 5. " LCD_BIST_DONE ,LCD memory BIST done" "No effect,Set" textline " " bitfld.long 0x00 4. " JTAG_IN_USE ,JTAG in use" "No effect,Set" bitfld.long 0x00 1.--3. " PACKAGE_TYPE ,Type of package" "169BGA,Reserved,Reserved,128TQFP,?..." textline " " bitfld.long 0x00 0. " WRITTEN ,Write to HW_DIGCTL_WRITEONCE register" "No effect,Set" line.long 0x04 "HW_DIGCTL_STATUS_CLR,DIGCTL Status Clear Register" bitfld.long 0x04 31. " USB_HS_PRESENT ,USB High-Speed Present" "Not cleared,Cleared" bitfld.long 0x04 30. " USB_OTG_PRESENT ,USB On-the-Go Present" "Not cleared,Cleared" textline " " bitfld.long 0x04 29. " USB_HOST_PRESENT ,USB Host Present" "Not cleared,Cleared" bitfld.long 0x04 28. " USB_DEVICE_PRESENT ,USB Device Present" "Not cleared,Cleared" textline " " bitfld.long 0x04 10. " DCP_BIST_FAIL ,DCP memory BIST failure" "Not cleared,Cleared" bitfld.long 0x04 9. " DCP_BIST_PASS ,DCP memory BIST pass" "Not cleared,Cleared" textline " " bitfld.long 0x04 8. " DCP_BIST_DONE ,DCP memory BIST done" "Not cleared,Cleared" bitfld.long 0x04 7. " LCD_BIST_FAIL ,LCD memory BIST failure" "Not cleared,Cleared" textline " " bitfld.long 0x04 6. " LCD_BIST_PASS ,LCD memory BIST pass" "Not cleared,Cleared" bitfld.long 0x04 5. " LCD_BIST_DONE ,LCD memory BIST done" "Not cleared,Cleared" textline " " bitfld.long 0x04 4. " JTAG_IN_USE ,JTAG in use" "Not cleared,Cleared" bitfld.long 0x04 1.--3. " PACKAGE_TYPE ,Type of package" "169BGA,Reserved,Reserved,128TQFP,?..." textline " " bitfld.long 0x04 0. " WRITTEN ,Write to HW_DIGCTL_WRITEONCE register" "Not cleared,Cleared" line.long 0x08 "HW_DIGCTL_STATUS_TOG,DIGCTL Status Toggle Register" bitfld.long 0x08 31. " USB_HS_PRESENT ,USB High-Speed Present" "Not toggle,Toggle" bitfld.long 0x08 30. " USB_OTG_PRESENT ,USB On-the-Go Present" "Not toggle,Toggle" textline " " bitfld.long 0x08 29. " USB_HOST_PRESENT ,USB Host Present" "Not toggle,Toggle" bitfld.long 0x08 28. " USB_DEVICE_PRESENT ,USB Device Present" "Not toggle,Toggle" textline " " bitfld.long 0x08 10. " DCP_BIST_FAIL ,DCP memory BIST failure" "Not toggle,Toggle" bitfld.long 0x08 9. " DCP_BIST_PASS ,DCP memory BIST pass" "Not toggle,Toggle" textline " " bitfld.long 0x08 8. " DCP_BIST_DONE ,DCP memory BIST done" "Not toggle,Toggle" bitfld.long 0x08 7. " LCD_BIST_FAIL ,LCD memory BIST failure" "Not toggle,Toggle" textline " " bitfld.long 0x08 6. " LCD_BIST_PASS ,LCD memory BIST pass" "Not toggle,Toggle" bitfld.long 0x08 5. " LCD_BIST_DONE ,LCD memory BIST done" "Not toggle,Toggle" textline " " bitfld.long 0x08 4. " JTAG_IN_USE ,JTAG in use" "Not toggle,Toggle" bitfld.long 0x08 1.--3. " PACKAGE_TYPE ,Type of package" "169BGA,Reserved,Reserved,128TQFP,?..." textline " " bitfld.long 0x08 0. " WRITTEN ,Write to HW_DIGCTL_WRITEONCE register" "Not toggle,Toggle" width 33. rgroup.long 0x20++0x03 line.long 0x00 "HW_DIGCTL_HCLKCOUNT,Free-Running HCLK Counter Register" group.long 0x24++0x0b line.long 0x00 "HW_DIGCTL_HCLKCOUNT_SET,Free-Running HCLK Counter Set Register" line.long 0x04 "HW_DIGCTL_HCLKCOUNT_CLR,Free-Running HCLK Counter Clear Register" line.long 0x08 "HW_DIGCTL_HCLKCOUNT_TOG,Free-Running HCLK Counter Toggle Register" group.long 0x30++0x33 line.long 0x00 "HW_DIGCTL_RAMCTRL,On-Chip RAM Control Register" bitfld.long 0x00 8.--11. " SPEED_SELECT ,Speed select for 16Kx32 OCRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " RAM_REPAIR_EN ,RAM Repair Enable" "Disabled,Enabled" line.long 0x04 "HW_DIGCTL_RAMCTRL_SET,On-Chip RAM Control Set Register" bitfld.long 0x04 8.--11. " SPEED_SELECT ,Speed select for 16Kx32 OCRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0. " RAM_REPAIR_EN ,RAM Repair Enable" "Disabled,Enabled" line.long 0x08 "HW_DIGCTL_RAMCTRL_CLR,On-Chip RAM Control Clear Register" bitfld.long 0x08 8.--11. " SPEED_SELECT ,Speed select for 16Kx32 OCRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 0. " RAM_REPAIR_EN ,RAM Repair Enable" "Disabled,Enabled" line.long 0x0c "HW_DIGCTL_RAMCTRL_TOG,On-Chip RAM Control Toggle Register" bitfld.long 0x0c 8.--11. " SPEED_SELECT ,Speed select for 16Kx32 OCRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 0. " RAM_REPAIR_EN ,RAM Repair Enable" "Disabled,Enabled" line.long 0x10 "HW_DIGCTL_RAMREPAIR,On-Chip RAM Repair Address Register" hexmask.long.word 0x10 0.--15. 1. " ADDR ,Word repair address for OCRAM" line.long 0x14 "HW_DIGCTL_RAMREPAIR_SET,On-Chip RAM Repair Address Set Register" hexmask.long.word 0x14 0.--15. 1. " ADDR ,Word repair address for OCRAM" line.long 0x18 "HW_DIGCTL_RAMREPAIR_CLR,On-Chip RAM Repair Address Clear Register" hexmask.long.word 0x18 0.--15. 1. " ADDR ,Word repair address for OCRAM" line.long 0x1c "HW_DIGCTL_RAMREPAIR_TOG,On-Chip RAM Repair Address Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " ADDR ,Word repair address for OCRAM" line.long 0x20 "HW_DIGCTL_ROMCTRL,On-Chip ROM Control Register" bitfld.long 0x20 0.--3. " RD_MARGIN ,setting the read margin for the on-chip ROM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x24 "HW_DIGCTL_ROMCTRL_SET,On-Chip ROM Control Set Register" bitfld.long 0x24 0.--3. " RD_MARGIN ,setting the read margin for the on-chip ROM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x28 "HW_DIGCTL_ROMCTRL_CLR,On-Chip ROM Control Clear Register" bitfld.long 0x28 0.--3. " RD_MARGIN ,setting the read margin for the on-chip ROM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x2c "HW_DIGCTL_ROMCTRL_TOG,On-Chip ROM Control Toggle Register" bitfld.long 0x2c 0.--3. " RD_MARGIN ,setting the read margin for the on-chip ROM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x30 "HW_DIGCTL_WRITEONCE,Software Write-Once Register" rgroup.long 0x90++0x03 line.long 0x00 "HW_DIGCTL_ENTROPY,Entropy Register" rgroup.long 0xa0++0x03 line.long 0x00 "HW_DIGCTL_ENTROPY_LATCHED,Entropy Latched Register" group.long 0xb0++0x1f line.long 0x00 "HW_DIGCTL_SJTAGDBG,SJTAG Debug Register" hexmask.long.word 0x00 16.--26. 1. " SJTAG_STATE ,state of the sjtag_state flip-flops inside the SJTAG controller" bitfld.long 0x00 10. " SJTAG_TDO ,ARM JTAG TDO state" "Low,High" textline " " bitfld.long 0x00 9. " SJTAG_TDI ,JTAG TDI state" "Low,High" bitfld.long 0x00 8. " SJTAG_MODE ,JTAG mode state" "Low,High" textline " " bitfld.long 0x00 4.--7. " DELAYED_ACTIVE ,delay_onewire_active_reg FF active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " ACTIVE ,onewire_active_reg FF active" "Not active,Active" textline " " bitfld.long 0x00 2. " SJTAG_PIN_STATE ,JTAG Pin State" "Low,High" bitfld.long 0x00 1. " SJTAG_DEBUG_DATA ,JTAG Debug Data" "0,1" textline " " bitfld.long 0x00 0. " SJTAG_DEBUG_OE ,JTAG Debug Overflow" "Not overflow,Overflow" line.long 0x04 "HW_DIGCTL_SJTAGDBG_SET,SJTAG Debug Set Register" hexmask.long.word 0x04 16.--26. 1. " SJTAG_STATE ,state of the sjtag_state flip-flops inside the SJTAG controller" bitfld.long 0x04 10. " SJTAG_TDO ,ARM JTAG TDO state" "No effect,Set" textline " " bitfld.long 0x04 9. " SJTAG_TDI ,JTAG TDI state" "No effect,Set" bitfld.long 0x04 8. " SJTAG_MODE ,JTAG mode state" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " DELAYED_ACTIVE ,delay_onewire_active_reg FF active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 3. " ACTIVE ,onewire_active_reg FF active" "No effect,Set" textline " " bitfld.long 0x04 2. " SJTAG_PIN_STATE ,JTAG Pin State" "No effect,Set" bitfld.long 0x04 1. " SJTAG_DEBUG_DATA ,JTAG Debug Data" "No effect,Set" textline " " bitfld.long 0x04 0. " SJTAG_DEBUG_OE ,JTAG Debug Overflow" "No effect,Set" line.long 0x08 "HW_DIGCTL_SJTAGDBG_CLR,SJTAG Debug Clear Register" hexmask.long.word 0x08 16.--26. 1. " SJTAG_STATE ,state of the sjtag_state flip-flops inside the SJTAG controller" bitfld.long 0x08 10. " SJTAG_TDO ,ARM JTAG TDO state" "No effect,Cleared" textline " " bitfld.long 0x08 9. " SJTAG_TDI ,JTAG TDI state" "No effect,Cleared" bitfld.long 0x08 8. " SJTAG_MODE ,JTAG mode state" "No effect,Cleared" textline " " bitfld.long 0x08 4.--7. " DELAYED_ACTIVE ,delay_onewire_active_reg FF active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 3. " ACTIVE ,onewire_active_reg FF active" "No effect,Cleared" textline " " bitfld.long 0x08 2. " SJTAG_PIN_STATE ,JTAG Pin State" "No effect,Cleared" bitfld.long 0x08 1. " SJTAG_DEBUG_DATA ,JTAG Debug Data" "No effect,Cleared" textline " " bitfld.long 0x08 0. " SJTAG_DEBUG_OE ,JTAG Debug Overflow" "No effect,Cleared" line.long 0x0c "HW_DIGCTL_SJTAGDBG_TOG,SJTAG Debug Toggle Register" hexmask.long.word 0x0c 16.--26. 1. " SJTAG_STATE ,state of the sjtag_state flip-flops inside the SJTAG controller" bitfld.long 0x0c 10. " SJTAG_TDO ,ARM JTAG TDO state" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " SJTAG_TDI ,JTAG TDI state" "Not toggle,Toggle" bitfld.long 0x0c 8. " SJTAG_MODE ,JTAG mode state" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " DELAYED_ACTIVE ,delay_onewire_active_reg FF active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 3. " ACTIVE ,onewire_active_reg FF active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " SJTAG_PIN_STATE ,JTAG Pin State" "Not toggle,Toggle" bitfld.long 0x0c 1. " SJTAG_DEBUG_DATA ,JTAG Debug Data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " SJTAG_DEBUG_OE ,JTAG Debug Overflow" "Not toggle,Toggle" line.long 0x10 "HW_DIGCTL_MICROSECONDS,Digital Control Microseconds Counter Register" line.long 0x14 "HW_DIGCTL_MICROSECONDS_SET,Digital Control Microseconds Counter Set Register" line.long 0x18 "HW_DIGCTL_MICROSECONDS_CLR,Digital Control Microseconds Counter Clear Register" line.long 0x1c "HW_DIGCTL_MICROSECONDS_TOG,Digital Control Microseconds Counter Toggle Register" rgroup.long 0xd0++0x03 line.long 0x00 "HW_DIGCTL_DBGRD,Digital Control Debug Read Test Register" rgroup.long 0xe0++0x03 line.long 0x00 "HW_DIGCTL_DBG,Digital Control Debug Register" group.long 0xf0++0x0f line.long 0x00 "HW_DIGCTL_OCRAM_BIST_CSR,SRAM BIST Control and Status Register" bitfld.long 0x00 10. " BIST_DEBUG_MODE ,OCRAM BIST debug mode select" "Not selected,Selected" bitfld.long 0x00 9. " BIST_DATA_CHANGE ,OCRAM BIST data background select" "Not selected,Selected" textline " " bitfld.long 0x00 8. " BIST_CLKEN ,Enable clock gate for OCRAM BIST" "Disabled,Enabled" bitfld.long 0x00 3. " FAIL ,BIST Fail" "Not failed,Failed" textline " " bitfld.long 0x00 2. " PASS ,BIST Pass" "Not passed,Passed" bitfld.long 0x00 1. " DONE ,BIST Done" "Not completed,Completed" textline " " bitfld.long 0x00 0. " START ,BIST Initiate" "Not started,Started" line.long 0x04 "HW_DIGCTL_OCRAM_BIST_CSR_SET,SRAM BIST Control and Status Set Register" bitfld.long 0x04 10. " BIST_DEBUG_MODE ,OCRAM BIST debug mode select" "No effect,Set" bitfld.long 0x04 9. " BIST_DATA_CHANGE ,OCRAM BIST data background select" "No effect,Set" textline " " bitfld.long 0x04 8. " BIST_CLKEN ,Enable clock gate for OCRAM BIST" "No effect,Set" bitfld.long 0x04 3. " FAIL ,BIST Fail" "No effect,Set" textline " " bitfld.long 0x04 2. " PASS ,BIST Pass" "No effect,Set" bitfld.long 0x04 1. " DONE ,BIST Done" "No effect,Set" textline " " bitfld.long 0x04 0. " START ,BIST Initiate" "No effect,Set" line.long 0x08 "HW_DIGCTL_OCRAM_BIST_CSR_CLR,SRAM BIST Control and Status Clear Register" bitfld.long 0x08 10. " BIST_DEBUG_MODE ,OCRAM BIST debug mode select" "No effect,Cleared" bitfld.long 0x08 9. " BIST_DATA_CHANGE ,OCRAM BIST data background select" "No effect,Cleared" textline " " bitfld.long 0x08 8. " BIST_CLKEN ,Enable clock gate for OCRAM BIST" "No effect,Cleared" bitfld.long 0x08 3. " FAIL ,BIST Fail" "No effect,Cleared" textline " " bitfld.long 0x08 2. " PASS ,BIST Pass" "No effect,Cleared" bitfld.long 0x08 1. " DONE ,BIST Done" "No effect,Cleared" textline " " bitfld.long 0x08 0. " START ,BIST Initiate" "No effect,Cleared" line.long 0x0c "HW_DIGCTL_OCRAM_BIST_CSR_TOG,SRAM BIST Control and Status Toggle Register" bitfld.long 0x0c 10. " BIST_DEBUG_MODE ,OCRAM BIST debug mode select" "Not toggle,Toggle" bitfld.long 0x0c 9. " BIST_DATA_CHANGE ,OCRAM BIST data background select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BIST_CLKEN ,Enable clock gate for OCRAM BIST" "Not toggle,Toggle" bitfld.long 0x0c 3. " FAIL ,BIST Fail" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " PASS ,BIST Pass" "Not toggle,Toggle" bitfld.long 0x0c 1. " DONE ,BIST Done" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " START ,BIST Initiate" "Not toggle,Toggle" rgroup.long 0x110++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS0,SRAM Status Register 0" group.long (0x110+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS0_SET,SRAM Status Set Register 0" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS0_CLR,SRAM Status Clear Register 0" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS0_TOG,SRAM Status Toggle Register 0" rgroup.long 0x120++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS1,SRAM Status Register 1" group.long (0x120+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS1_SET,SRAM Status Set Register 1" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS1_CLR,SRAM Status Clear Register 1" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS1_TOG,SRAM Status Toggle Register 1" rgroup.long 0x130++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS2,SRAM Status Register 2" group.long (0x130+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS2_SET,SRAM Status Set Register 2" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS2_CLR,SRAM Status Clear Register 2" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS2_TOG,SRAM Status Toggle Register 2" rgroup.long 0x140++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS3,SRAM Status Register 3" group.long (0x140+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS3_SET,SRAM Status Set Register 3" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS3_CLR,SRAM Status Clear Register 3" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS3_TOG,SRAM Status Toggle Register 3" rgroup.long 0x150++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS4,SRAM Status Register 4" group.long (0x150+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS4_SET,SRAM Status Set Register 4" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS4_CLR,SRAM Status Clear Register 4" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS4_TOG,SRAM Status Toggle Register 4" rgroup.long 0x160++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS5,SRAM Status Register 5" group.long (0x160+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS5_SET,SRAM Status Set Register 5" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS5_CLR,SRAM Status Clear Register 5" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS5_TOG,SRAM Status Toggle Register 5" rgroup.long 0x170++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS6,SRAM Status Register 6" group.long (0x170+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS6_SET,SRAM Status Set Register 6" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS6_CLR,SRAM Status Clear Register 6" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS6_TOG,SRAM Status Toggle Register 6" rgroup.long 0x180++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS7,SRAM Status Register 7" group.long (0x180+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS7_SET,SRAM Status Set Register 7" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS7_CLR,SRAM Status Clear Register 7" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS7_TOG,SRAM Status Toggle Register 7" rgroup.long 0x190++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS8,SRAM Status Register 8" hexmask.long.word 0x00 16.--28. 1. " FAILADDR01 ,failing address for the second fail in block 0" hexmask.long.word 0x00 0.--12. 1. " FAILADDR00 ,failing address for the first fail in block 0" group.long (0x190+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS8_SET,SRAM Status Set Register 8" hexmask.long.word 0x00 16.--28. 1. " FAILADDR01 ,failing address for the second fail in block 0" hexmask.long.word 0x00 0.--12. 1. " FAILADDR00 ,failing address for the first fail in block 0" line.long 0x00 "HW_DIGCTL_OCRAM_STATUS8_CLR,SRAM Status Clear Register 8" hexmask.long.word 0x00 16.--28. 1. " FAILADDR01 ,failing address for the second fail in block 0" hexmask.long.word 0x00 0.--12. 1. " FAILADDR00 ,failing address for the first fail in block 0" line.long 0x00 "HW_DIGCTL_OCRAM_STATUS8_TOG,SRAM Status Toggle Register 8" hexmask.long.word 0x00 16.--28. 1. " FAILADDR01 ,failing address for the second fail in block 0" hexmask.long.word 0x00 0.--12. 1. " FAILADDR00 ,failing address for the first fail in block 0" rgroup.long 0x1A0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS9,SRAM Status Register 9" hexmask.long.word 0x00 16.--28. 1. " FAILADDR11 ,failing address for the second fail in block 1" hexmask.long.word 0x00 0.--12. 1. " FAILADDR10 ,failing address for the first fail in block 1" group.long (0x1A0+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS9_SET,SRAM Status Set Register 9" hexmask.long.word 0x00 16.--28. 1. " FAILADDR11 ,failing address for the second fail in block 1" hexmask.long.word 0x00 0.--12. 1. " FAILADDR10 ,failing address for the first fail in block 1" line.long 0x00 "HW_DIGCTL_OCRAM_STATUS9_CLR,SRAM Status Clear Register 9" hexmask.long.word 0x00 16.--28. 1. " FAILADDR11 ,failing address for the second fail in block 1" hexmask.long.word 0x00 0.--12. 1. " FAILADDR10 ,failing address for the first fail in block 1" line.long 0x00 "HW_DIGCTL_OCRAM_STATUS9_TOG,SRAM Status Toggle Register 9" hexmask.long.word 0x00 16.--28. 1. " FAILADDR11 ,failing address for the second fail in block 1" hexmask.long.word 0x00 0.--12. 1. " FAILADDR10 ,failing address for the first fail in block 1" rgroup.long 0x1B0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS10,SRAM Status Register 10" hexmask.long.word 0x00 16.--28. 1. " FAILADDR21 ,failing address for the second fail in block 2" hexmask.long.word 0x00 0.--12. 1. " FAILADDR20 ,failing address for the first fail in block 2" group.long (0x1B0+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS10_SET,SRAM Status Set Register 10" hexmask.long.word 0x00 16.--28. 1. " FAILADDR21 ,failing address for the second fail in block 2" hexmask.long.word 0x00 0.--12. 1. " FAILADDR20 ,failing address for the first fail in block 2" line.long 0x00 "HW_DIGCTL_OCRAM_STATUS10_CLR,SRAM Status Clear Register 10" hexmask.long.word 0x00 16.--28. 1. " FAILADDR21 ,failing address for the second fail in block 2" hexmask.long.word 0x00 0.--12. 1. " FAILADDR20 ,failing address for the first fail in block 2" line.long 0x00 "HW_DIGCTL_OCRAM_STATUS10_TOG,SRAM Status Toggle Register 10" hexmask.long.word 0x00 16.--28. 1. " FAILADDR21 ,failing address for the second fail in block 2" hexmask.long.word 0x00 0.--12. 1. " FAILADDR20 ,failing address for the first fail in block 2" rgroup.long 0x1C0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS11,SRAM Status Register 11" hexmask.long.word 0x00 16.--28. 1. " FAILADDR31 ,failing address for the second fail in block 3" hexmask.long.word 0x00 0.--12. 1. " FAILADDR30 ,failing address for the first fail in block 3" group.long (0x1C0+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS11_SET,SRAM Status Set Register 11" hexmask.long.word 0x00 16.--28. 1. " FAILADDR31 ,failing address for the second fail in block 3" hexmask.long.word 0x00 0.--12. 1. " FAILADDR30 ,failing address for the first fail in block 3" line.long 0x00 "HW_DIGCTL_OCRAM_STATUS11_CLR,SRAM Status Clear Register 11" hexmask.long.word 0x00 16.--28. 1. " FAILADDR31 ,failing address for the second fail in block 3" hexmask.long.word 0x00 0.--12. 1. " FAILADDR30 ,failing address for the first fail in block 3" line.long 0x00 "HW_DIGCTL_OCRAM_STATUS11_TOG,SRAM Status Toggle Register 11" hexmask.long.word 0x00 16.--28. 1. " FAILADDR31 ,failing address for the second fail in block 3" hexmask.long.word 0x00 0.--12. 1. " FAILADDR30 ,failing address for the first fail in block 3" rgroup.long 0x1d0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS12,SRAM Status Register 12" hexmask.long.byte 0x00 24.--27. 1. " FAILSTATE11 ,Failing state for the second fail in block 1" hexmask.long.byte 0x00 16.--19. 1. " FAILSTATE10 ,Failing state for the first fail in block 1" textline " " hexmask.long.byte 0x00 8.--11. 1. " FAILSTATE01 ,Failing state for the second fail in block 0" hexmask.long.byte 0x00 0.--3. 1. " FAILSTATE00 ,Failing state for the first fail in block 0" group.long 0x1d4++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS12_SET,SRAM Status Set Register 12" hexmask.long.byte 0x00 24.--27. 1. " FAILSTATE11 ,Failing state for the second fail in block 1" hexmask.long.byte 0x00 16.--19. 1. " FAILSTATE10 ,Failing state for the first fail in block 1" textline " " hexmask.long.byte 0x00 8.--11. 1. " FAILSTATE01 ,Failing state for the second fail in block 0" hexmask.long.byte 0x00 0.--3. 1. " FAILSTATE00 ,Failing state for the first fail in block 0" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS12_CLR,SRAM Status Clear Register 12" hexmask.long.byte 0x04 24.--27. 1. " FAILSTATE11 ,Failing state for the second fail in block 1" hexmask.long.byte 0x04 16.--19. 1. " FAILSTATE10 ,Failing state for the first fail in block 1" textline " " hexmask.long.byte 0x04 8.--11. 1. " FAILSTATE01 ,Failing state for the second fail in block 0" hexmask.long.byte 0x04 0.--3. 1. " FAILSTATE00 ,Failing state for the first fail in block 0" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS12_TOG,SRAM Status Toggle Register 12" hexmask.long.byte 0x08 24.--27. 1. " FAILSTATE11 ,Failing state for the second fail in block 1" hexmask.long.byte 0x08 16.--19. 1. " FAILSTATE10 ,Failing state for the first fail in block 1" textline " " hexmask.long.byte 0x08 8.--11. 1. " FAILSTATE01 ,Failing state for the second fail in block 0" hexmask.long.byte 0x08 0.--3. 1. " FAILSTATE00 ,Failing state for the first fail in block 0" rgroup.long 0x1e0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS13,SRAM Status Register 13" hexmask.long.byte 0x00 24.--27. 1. " FAILSTATE31 ,Failing state for the second fail in block 3" hexmask.long.byte 0x00 16.--19. 1. " FAILSTATE30 ,Failing state for the first fail in block 3" textline " " hexmask.long.byte 0x00 8.--11. 1. " FAILSTATE21 ,Failing state for the second fail in block 2" hexmask.long.byte 0x00 0.--3. 1. " FAILSTATE20 ,Failing state for the first fail in block 2" group.long 0x1e4++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS13_SET,SRAM Status Set Register 13" hexmask.long.byte 0x00 24.--27. 1. " FAILSTATE31 ,Failing state for the second fail in block 3" hexmask.long.byte 0x00 16.--19. 1. " FAILSTATE30 ,Failing state for the first fail in block 3" textline " " hexmask.long.byte 0x00 8.--11. 1. " FAILSTATE21 ,Failing state for the second fail in block 2" hexmask.long.byte 0x00 0.--3. 1. " FAILSTATE20 ,Failing state for the first fail in block 2" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS13_CLR,SRAM Status Clear Register 13" hexmask.long.byte 0x04 24.--27. 1. " FAILSTATE31 ,Failing state for the second fail in block 3" hexmask.long.byte 0x04 16.--19. 1. " FAILSTATE30 ,Failing state for the first fail in block 3" textline " " hexmask.long.byte 0x04 8.--11. 1. " FAILSTATE21 ,Failing state for the second fail in block 2" hexmask.long.byte 0x04 0.--3. 1. " FAILSTATE20 ,Failing state for the first fail in block 2" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS13_TOG,SRAM Status Toggle Register 13" hexmask.long.byte 0x08 24.--27. 1. " FAILSTATE31 ,Failing state for the second fail in block 3" hexmask.long.byte 0x08 16.--19. 1. " FAILSTATE30 ,Failing state for the first fail in block 3" textline " " hexmask.long.byte 0x08 8.--11. 1. " FAILSTATE21 ,Failing state for the second fail in block 2" hexmask.long.byte 0x08 0.--3. 1. " FAILSTATE20 ,Failing state for the first fail in block 2" group.long 0x290++0x03 line.long 0x00 "HW_DIGCTL_SCRATCH0,Digital Control Scratch Register 0" group.long 0x2a0++0x03 line.long 0x00 "HW_DIGCTL_SCRATCH1,Digital Control Scratch Register 1" group.long 0x2b0++0x03 line.long 0x00 "HW_DIGCTL_ARMCACHE,Digital Control ARM Cache Register" bitfld.long 0x00 16.--17. " VALID_SS ,Timing Control for 64x24x1 RAMs" "0,1,2,3" bitfld.long 0x00 12.--13. " DRTY_SS ,Timing Control for 128x8x1 RAM (DDRTY)" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " CACHE_SS ,Timing Control for 1024x32x4 RAMs" "0,1,2,3" bitfld.long 0x00 4.--5. " DTAG_SS ,Timing Control for 256x22x4 RAM (DTAG)" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " ITAG_SS ,Timing Control for 128x22x4 RAM (ITAG)" "0,1,2,3" group.long 0x2c0++0x03 line.long 0x00 "HW_DIGCTL_DEBUG_TRAP_ADDR_LOW,Debug Trap Range Low Address Register" group.long 0x2d0++0x03 line.long 0x00 "HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH,Debug Trap Range High Address Register" rgroup.long 0x300++0x03 line.long 0x00 "HW_DIGCTL_SGTL,Freescale Copyright Identifier Register Description" rgroup.long 0x310++0x03 line.long 0x00 "HW_DIGCTL_CHIPID,Digital Control Chip Revision Register" hexmask.long.word 0x00 16.--31. 1. " PRODUCT_CODE ,generation from which the part is derived" hexmask.long.byte 0x00 0.--7. 1. " REVISION ,revision level of the chip" group.long 0x330++0x03 line.long 0x00 "HW_DIGCTL_AHB_STATS_SELECT,AHB Statistics Control Register" bitfld.long 0x00 24.--27. " L3_MASTER_SELECT ,AHB Layer 3 arbiter monitoring select" "Reserved,APBH,APBX,Reserved,USB,?..." bitfld.long 0x00 16.--19. " L2_MASTER_SELECT ,AHB Layer 2 arbiter monitoring select" "Reserved,ARM_D,?..." textline " " bitfld.long 0x00 8.--11. " L1_MASTER_SELECT ,AHB Layer 1 arbiter monitoring select" "Reserved,ARM_I,?..." bitfld.long 0x00 0.--3. " L0_MASTER_SELECT ,AHB Layer 0 arbiter monitoring select" "Reserved,ECC8,CRYPTO,?..." group.long 0x340++0x03 line.long 0x00 "HW_DIGCTL_L0_AHB_ACTIVE_CYCLES,AHB Layer 0 Transfer Count Register" group.long (0x340+0x10)++0x03 line.long 0x00 "HW_DIGCTL_L0_AHB_DATA_STALLED,AHB Layer 0 Performance Metric for Stalled Bus Cycles Register" group.long (0x340+0x20)++0x03 line.long 0x00 "HW_DIGCTL_L0_AHB_DATA_CYCLES,AHB Layer 0 Performance Metric for Valid Bus Cycles Register" group.long 0x370++0x03 line.long 0x00 "HW_DIGCTL_L1_AHB_ACTIVE_CYCLES,AHB Layer 1 Transfer Count Register" group.long (0x370+0x10)++0x03 line.long 0x00 "HW_DIGCTL_L1_AHB_DATA_STALLED,AHB Layer 1 Performance Metric for Stalled Bus Cycles Register" group.long (0x370+0x20)++0x03 line.long 0x00 "HW_DIGCTL_L1_AHB_DATA_CYCLES,AHB Layer 1 Performance Metric for Valid Bus Cycles Register" group.long 0x3A0++0x03 line.long 0x00 "HW_DIGCTL_L2_AHB_ACTIVE_CYCLES,AHB Layer 2 Transfer Count Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "HW_DIGCTL_L2_AHB_DATA_STALLED,AHB Layer 2 Performance Metric for Stalled Bus Cycles Register" group.long (0x3A0+0x20)++0x03 line.long 0x00 "HW_DIGCTL_L2_AHB_DATA_CYCLES,AHB Layer 2 Performance Metric for Valid Bus Cycles Register" group.long 0x3D0++0x03 line.long 0x00 "HW_DIGCTL_L3_AHB_ACTIVE_CYCLES,AHB Layer 3 Transfer Count Register" group.long (0x3D0+0x10)++0x03 line.long 0x00 "HW_DIGCTL_L3_AHB_DATA_STALLED,AHB Layer 3 Performance Metric for Stalled Bus Cycles Register" group.long (0x3D0+0x20)++0x03 line.long 0x00 "HW_DIGCTL_L3_AHB_DATA_CYCLES,AHB Layer 3 Performance Metric for Valid Bus Cycles Register" group.long 0x500++0x03 line.long 0x00 "HW_DIGCTL_EMICLK_DELAY,EMI CLK/CLKN Delay Adjustment Register" bitfld.long 0x00 0.--4. " NUM_TAPS ,Select one of 32 delay line taps" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0xb tree.end tree "OCOTP (On-Chip OTP Controller)" base asd:0x8002c000 width 19. group.long 0x00++0x13 line.long 0x00 "HW_OCOTP_CTRL,OTP Controller Control Register" hexmask.long.word 0x00 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write accesses" bitfld.long 0x00 13. " RELOAD_SHADOWS ,re-loading the shadow registers" "Not forced,Forced" textline " " bitfld.long 0x00 12. " RD_BANK_OPEN ,OTP banks open for reading" "Not opened,Opened" bitfld.long 0x00 9. " ERROR ,OTP Error " "No error,Error" textline " " bitfld.long 0x00 8. " BUSY ,OTP controller status bit" "Not busy,Busy" hexmask.long.byte 0x00 0.--4. 1. " ADDR ,OTP write access address register" line.long 0x04 "HW_OCOTP_CTRL_SET,OTP Controller Control Set Register" hexmask.long.word 0x04 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write accesses" bitfld.long 0x04 13. " RELOAD_SHADOWS ,re-loading the shadow registers" "No effect,Set" textline " " bitfld.long 0x04 12. " RD_BANK_OPEN ,OTP banks open for reading" "No effect,Set" bitfld.long 0x04 9. " ERROR ,OTP Error " "No effect,Set" textline " " bitfld.long 0x04 8. " BUSY ,OTP controller status bit" "No effect,Set" hexmask.long.byte 0x04 0.--4. 1. " ADDR ,OTP write access address register" line.long 0x08 "HW_OCOTP_CTRL_CLR,OTP Controller Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write accesses" bitfld.long 0x08 13. " RELOAD_SHADOWS ,re-loading the shadow registers" "No effect,Cleared" textline " " bitfld.long 0x08 12. " RD_BANK_OPEN ,OTP banks open for reading" "No effect,Cleared" bitfld.long 0x08 9. " ERROR ,OTP Error " "No effect,Cleared" textline " " bitfld.long 0x08 8. " BUSY ,OTP controller status bit" "No effect,Cleared" hexmask.long.byte 0x08 0.--4. 1. " ADDR ,OTP write access address register" line.long 0x0c "HW_OCOTP_CTRL_TOG,OTP Controller Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write accesses" bitfld.long 0x0c 13. " RELOAD_SHADOWS ,re-loading the shadow registers" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " RD_BANK_OPEN ,OTP banks open for reading" "Not toggle,Toggle" bitfld.long 0x0c 9. " ERROR ,OTP Error " "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BUSY ,OTP controller status bit" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--4. 1. " ADDR ,OTP write access address register" line.long 0x10 "HW_OCOTP_DATA,OTP Controller Write Data Register" rgroup.long 0x20++0x03 line.long 0x00 "HW_OCOTP_CUST0,Value of OTP Bank0 Word0(Customer) Register" rgroup.long (0x20+0x40)++0x03 line.long 0x00 "HW_OCOTP_CRYPTO0,Value of OTP Bank0 Word4(Crypto Key) Register" rgroup.long 0x30++0x03 line.long 0x00 "HW_OCOTP_CUST1,Value of OTP Bank0 Word1(Customer) Register" rgroup.long (0x30+0x40)++0x03 line.long 0x00 "HW_OCOTP_CRYPTO1,Value of OTP Bank0 Word5(Crypto Key) Register" rgroup.long 0x40++0x03 line.long 0x00 "HW_OCOTP_CUST2,Value of OTP Bank0 Word2(Customer) Register" rgroup.long (0x40+0x40)++0x03 line.long 0x00 "HW_OCOTP_CRYPTO2,Value of OTP Bank0 Word6(Crypto Key) Register" rgroup.long 0x50++0x03 line.long 0x00 "HW_OCOTP_CUST3,Value of OTP Bank0 Word3(Customer) Register" rgroup.long (0x50+0x40)++0x03 line.long 0x00 "HW_OCOTP_CRYPTO3,Value of OTP Bank0 Word7(Crypto Key) Register" group.long 0xA0++0x03 line.long 0x00 "HW_OCOTP_HWCAP0,HW Capability Shadow Register 0" group.long 0xB0++0x03 line.long 0x00 "HW_OCOTP_HWCAP1,HW Capability Shadow Register 1" group.long 0xC0++0x03 line.long 0x00 "HW_OCOTP_HWCAP2,HW Capability Shadow Register 2" group.long 0xD0++0x03 line.long 0x00 "HW_OCOTP_HWCAP3,HW Capability Shadow Register 3" group.long 0xE0++0x03 line.long 0x00 "HW_OCOTP_HWCAP4,HW Capability Shadow Register 4" group.long 0xF0++0x03 line.long 0x00 "HW_OCOTP_HWCAP5,HW Capability Shadow Register 5" group.long 0x100++0x03 line.long 0x00 "HW_OCOTP_SWCAP,SW Capability Shadow Register" group.long 0x110++0x03 line.long 0x00 "HW_OCOTP_CUSTCAP,Customer Capability Shadow Register" bitfld.long 0x00 31. " CUST_DISABLE_WMADRM9 ,WMA DRM9 Disable" "Enabled,Disabled" bitfld.long 0x00 30. " CUST_DISABLE_JANUSDRM10 ,WMA Janus DRM 10 Disable" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " ENABLE_SJTAG_12MA_DRIVE ,SJTAG 12mA Enable" "Disabled,Enabled" bitfld.long 0x00 3. " USE_PARALLEL_JTAG ,Parallel JTAG Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " RTC_XTAL_32768_PRESENT ,32.768KHz crystal off-chip Present" "Not present,Present" bitfld.long 0x00 1. " RTC_XTAL_32000_PRESENT ,32.000KHz crystal off-chip Present" "Not present,Present" rgroup.long 0x120++0x03 line.long 0x00 "HW_OCOTP_LOCK,LOCK Shadow Register OTP Bank 2 Word 0" bitfld.long 0x00 31. " ROM7 ,ROM region lock bit" "Unlocked,Locked" bitfld.long 0x00 30. " ROM6 ,ROM region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 29. " ROM5 ,ROM region lock bit" "Unlocked,Locked" bitfld.long 0x00 28. " ROM4 ,ROM region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 27. " ROM3 ,ROM region lock bit" "Unlocked,Locked" bitfld.long 0x00 26. " ROM2 ,ROM region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 25. " ROM1 ,ROM region lock bit" "Unlocked,Locked" bitfld.long 0x00 24. " ROM0 ,ROM region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 23. " HWSW_SHADOW_ALT ,HWSW_SHADOW lock bit" "Unlocked,Locked" bitfld.long 0x00 22. " CRYPTODCP_ALT ,CRYPTODCP lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 21. " CRYPTOKEY_ALT ,CRYPTOKEY lock bit" "Unlocked,Locked" bitfld.long 0x00 20. " PIN ,Pin access lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 19. " OPS ,SGTL-OPS region lock bit" "Unlocked,Locked" bitfld.long 0x00 18. " UN2 ,Un-assigned lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 17. " UN1 ,Un-assigned lock bit" "Unlocked,Locked" bitfld.long 0x00 16. " UN0 ,Un-assigned lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 11.--15. " UNALLOCATED ,Value of un-used portion of LOCK word" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " ROM_SHADOW ,ROM region shadow register lock" "Unlocked,Locked" textline " " bitfld.long 0x00 9. " CUSTCAP ,Customer Capability region lock bit" "Unlocked,Locked" bitfld.long 0x00 8. " HWSW ,HW/SW region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 7. " CUSTCAP_SHADOW ,Customer Capability shadow register lock" "Unlocked,Locked" bitfld.long 0x00 6. " HWSW_SHADOW ,HW/SW Capability shadow register lock" "Unlocked,Locked" textline " " bitfld.long 0x00 5. " CRYPTODCP ,DCP APB crypto access lock bit" "Unlocked,Locked" bitfld.long 0x00 4. " CRYPTOKEY ,Crypto key region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 3. " CUST3 ,Customer region word lock bit" "Unlocked,Locked" bitfld.long 0x00 2. " CUST2 ,Customer region word lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 1. " CUST1 ,Customer region word lock bit" "Unlocked,Locked" bitfld.long 0x00 0. " CUST0 ,Customer region word lock bit" "Unlocked,Locked" rgroup.long 0x130++0x03 line.long 0x00 "HW_OCOTP_OPS0,OTP Bank2 Word1 (Freescale OPS0) Register" rgroup.long 0x140++0x03 line.long 0x00 "HW_OCOTP_OPS1,OTP Bank2 Word2 (Freescale OPS1) Register" rgroup.long 0x150++0x03 line.long 0x00 "HW_OCOTP_OPS2,OTP Bank2 Word3 (Freescale OPS2) Register" rgroup.long 0x160++0x03 line.long 0x00 "HW_OCOTP_OPS3,OTP Bank2 Word4 (Freescale OPS3) Register" rgroup.long 0x170++0x03 line.long 0x00 "HW_OCOTP_UN0,OTP Bank2 Word5 (Unassigned0) Register" rgroup.long 0x180++0x03 line.long 0x00 "HW_OCOTP_UN0,OTP Bank2 Word6 (Unassigned1) Register" rgroup.long 0x190++0x03 line.long 0x00 "HW_OCOTP_UN0,OTP Bank2 Word7 (Unassigned2) Register" group.long 0x1a0++0x03 ;14.--19. doc describtion p.326 line.long 0x00 "HW_OCOTP_ROM0,Shadow Register for OTP Bank3 Word0 (ROM Use 0)" hexmask.long.byte 0x00 24.--31. 1. " BOOT_MODE ,Encoded boot mode" bitfld.long 0x00 23. " ENABLE_PJTAG_12MA_DRIVE ,PJTAG 12mA enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " USE_PARALLEL_JTAG ,Parallel JTAG enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " SD_POWER_GATE_GPIO ,SD card power gate GPIO pin select" "PWM0,LCD_DOTCLK,PWM3,NO_GATE" textline " " bitfld.long 0x00 14.--19. " SD_POWER_UP_DELAY ,SD card power up delay required after enabling GPIO power gate" "0 ms,10 ms,20 ms,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,630 ms" bitfld.long 0x00 12.--13. " SD_BUS_WIDTH ,SD card bus width" "4-bit,1-bit,8-bit,?..." textline " " bitfld.long 0x00 8.--11. " SSP_SCK_INDEX ,SSP clock speed index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6. " DISABLE_SPI_NOR_FAST_READ ,SPI NOR fast read disable" "Enabled,Disabled" textline " " bitfld.long 0x00 5. " ENABLE_USB_BOOT_SERIAL_NUM ,USB boot serial number enable" "Disabled,Enabled" bitfld.long 0x00 4. " ENABLE_UNENCRYPTED_BOOT ,Unecrypted boot modes enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SD_MBR_BOOT ,master boot record (MBR) enable" "Disabled,Enabled" group.long 0x1b0++0x03 line.long 0x00 "HW_OCOTP_ROM1,Shadow Register for OTP Bank3 Word1 (ROM Use 1)" bitfld.long 0x00 28.--29. " USE_ALT_GPMI_RDY3 ,GPMI_RDY3 alternate pin enable" "GPMI_RDY3,PWM2,LCD_DOTCK,?..." bitfld.long 0x00 26.--27. " USE_ALT_GPMI_CE3 ,GPMI_CE3 alternate pin enable" "GPMI_D15,LCD_RESET,SSP_DETECT,ROTARYB" textline " " bitfld.long 0x00 25. " USE_ALT_GPMI_RDY2 ,GPMI_RDY2 alternate pins enable" "Disabled,Enabled" bitfld.long 0x00 24. " USE_ALT_GPMI_CE2 ,GPMI_CE2 alternate pins enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " ENABLE_NAND3_CE_RDY_PULLUP ,Enable ROM NAND3_CE RDY internal pullup" "Disabled,Enabled" bitfld.long 0x00 22. " ENABLE_NAND2_CE_RDY_PULLUP ,Enable ROM NAND2_CE RDY internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " ENABLE_NAND1_CE_RDY_PULLUP ,Enable ROM NAND1_CE RDY internal pullup" "Disabled,Enabled" bitfld.long 0x00 20. " ENABLE_NAND0_CE_RDY_PULLUP ,Enable ROM NAND0_CE RDY internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " UNTOUCH_INTERNAL_SSP_PULLUP ,Untouch internal pullup for SSP" "Disabled,Enabled" bitfld.long 0x00 18. " SSP2_EXT_PULLUP ,External pull-ups for SSP2" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " SSP1_EXT_PULLUP ,External pull-ups for SSP1" "Disabled,Enabled" bitfld.long 0x00 16. " SD_INCREASE_INIT_SEQ_TIME ,Initialization sequence time" "1ms,4ms" textline " " bitfld.long 0x00 15. " SD_INIT_SEQ_2_ENABLE ,Second initialization sequence for SD enable" "Disabled,Enabled" bitfld.long 0x00 14. " SD_CMD0_DISABLE ,Startup SD Card Cmd0 disable" "Enabled,Disabled" textline " " bitfld.long 0x00 13. " SD_INIT_SEQ_1_DISABLE ,First initialization sequence for SD disable" "Disabled,Enabled" bitfld.long 0x00 12. " 12_USE_ALT_SSP1_DATA4-7 ,Alternate pin use for SSP1 data lines 4-7" "Enabled,Disabled" textline " " bitfld.long 0x00 8.--11. " BOOT_SEARCH_COUNT ,Number of 64 page blocks that should be read by the boot loader" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " NUMBER_OF_NANDS ,Number of external NAND devices" "0,1,2,3,4,5,6,7" group.long 0x1c0++0x03 line.long 0x00 "HW_OCOTP_ROM2,Shadow Register for OTP Bank3 Word2 (ROM Use 2)" hexmask.long.word 0x00 16.--31. 1. " USB_VID ,USB Vendor ID" hexmask.long.word 0x00 0.--15. 1. " USB_PID ,USB Product ID" hgroup.long 0x1d0++0x03 hide.long 0x00 "HW_OCOTP_ROM3,Shadow Register for OTP Bank3 Word3 (ROM Use 3)" group.long 0x1E0++0x03 line.long 0x00 "HW_OCOTP_ROM4,Shadow Register for OTP Bank3 Word4 (ROM Use 4)" group.long 0x1F0++0x03 line.long 0x00 "HW_OCOTP_ROM5,Shadow Register for OTP Bank3 Word5 (ROM Use 5)" group.long 0x200++0x03 line.long 0x00 "HW_OCOTP_ROM6,Shadow Register for OTP Bank3 Word6 (ROM Use 6)" group.long 0x210++0x03 line.long 0x00 "HW_OCOTP_ROM7,Shadow Register for OTP Bank3 Word7 (ROM Use 7)" bitfld.long 0x00 8. " ENABLE_SSP_12MA_DRIVE ,SSP 12mA Enable" "Disabled,Enabled" bitfld.long 0x00 3. " I2C_USE_400KHZ ,I2C boot loader run mode" "100kHz,400kHz" textline " " bitfld.long 0x00 2. " ENABLE_ARM_ICACHE ,ARM 926 ICache boot enable" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE_PIN_BOOT_CHECK ,Enable Pin Boot " "Disabled,Enabled" rgroup.long 0x220++0x03 line.long 0x00 "HW_OCOTP_VERSION,OTP Controller Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version." hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree.open "USB (USB High-Speed Host/Device Controller)" tree "USB Control Registers" base asd:0x80080000 width 29. rgroup.long 0x00++0x1b line.long 0x00 "HW_USBCTRL_ID,Identification Register" bitfld.long 0x00 29.--31. " CIVERSION ,Identifies the Chip Idea product version of the USB-HS USB 2.0 core" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--28. " VERSION ,Identifies the version of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--24. " REVISION ,Identifies the revision of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " TAG ,Identifies the revision of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--13. " NID ,One's complement version of ID[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " ID ,Configuration number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HW_USBCTRL_HWGENERAL,General Hardware Parameters Register" bitfld.long 0x04 9.--10. " SM ,PHY Serial Engine Type" "Not present,?..." bitfld.long 0x04 6.--8. " PHYM ,PHY Type" "Reserved,UTMI,?..." textline " " bitfld.long 0x04 4.--5. " PHYW ,Data Interface Width to PHY" "Reserved,16 bits,?..." bitfld.long 0x04 1.--2. " CLKC ,USB Controller Clocking Method" "Reserved,Reserved,Mixed clocked,?..." textline " " bitfld.long 0x04 0. " RT ,Reset Type" "Reserved,Synchronous" line.long 0x08 "HW_USBCTRL_HWHOST,Host Hardware Parameters Register" hexmask.long.byte 0x08 24.--31. 1. " TTPER ,Periodic contexts for hub TT" hexmask.long.byte 0x08 16.--23. 1. " TTASY ,Asynch contexts for hub TT" textline " " bitfld.long 0x08 1.--3. " NPORT ,Maximum downstream ports minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " HC ,Host Capable" "Reserved,1" line.long 0x0c "HW_USBCTRL_HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x0C 1.--5. " DEVEP ,Maximum number of endpoints" "0,1,2,3,4,5,?..." bitfld.long 0x0C 0. " DC ,Device Capable" "Reserved,1" line.long 0x10 "HW_USBCTRL_HWTXBUF,TX Buffer Hardware Parameters Register" bitfld.long 0x10 31. " TXLCR ,Transmit LCR" "0,1" hexmask.long.byte 0x10 16.--23. 1. " TXCHANADD ,Number of address bits for the TX buffer" textline " " hexmask.long.byte 0x10 8.--15. 1. " TXADD ,Transmit Add" hexmask.long.byte 0x10 0.--7. 1. " TXBURST ,Burst size for memory-to-TX-buffer transfers" line.long 0x14 "HW_USBCTRL_HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x14 8.--15. 1. " RXADD ,Receive Add" hexmask.long.byte 0x14 0.--7. 1. " RXBURST ,Burst size for RX buffer-to-memory transfers" group.long 0x80++0x07 line.long 0x00 "HW_USBCTRL_GPTIMER0LD,General-Purpose Timer 0 Load (Non-EHCI-Compliant) Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General-Purpose Timer Load Value" line.long 0x04 "HW_USBCTRL_GPTIMER0CTRL,General-Purpose Timer 0 Control (Non-EHCI-Compliant) Register" bitfld.long 0x04 31. " GPTRUN ,General-Purpose Timer Run" "Stop,Run" bitfld.long 0x04 30. " GPTRST ,General-Purpose Timer Reset" "No effect,1 load" textline " " bitfld.long 0x04 24. " GPTMODE ,General-Purpose Timer Mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General-Purpose Timer Counter" group.long 0x88++0x07 line.long 0x00 "HW_USBCTRL_GPTIMER1LD,General-Purpose Timer 1 Load (Non-EHCI-Compliant) Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General-Purpose Timer Load Value" line.long 0x04 "HW_USBCTRL_GPTIMER1CTRL,General-Purpose Timer 1 Control (Non-EHCI-Compliant) Register" bitfld.long 0x04 31. " GPTRUN ,General-Purpose Timer Run" "Stop,Run" bitfld.long 0x04 30. " GPTRST ,General-Purpose Timer Reset" "No effect,1 load" textline " " bitfld.long 0x04 24. " GPTMODE ,General-Purpose Timer Mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General-Purpose Timer Counter" group.long 0x90++0x03 line.long 0x00 "HW_USBCTRL_SBUSCFG,System Bus Configuration (Non-EHCI-Compliant) Register" bitfld.long 0x00 0.--2. " AHBBRST ,AMBA AHB BURST" "U_INCR,S_INCR4,S_INCR8,S_INCR16,Reserved,U_INCR4,U_INCR8,U_INCR16" rgroup.long 0x100++0x07 line.long 0x00 "HW_USBCTRL_CAPLENGTH,Capability Length and HCI Version (EHCI-Compliant) Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,BCD encoding of the EHCI revision number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Offset to add to register base address at beginning of the Operational Register" line.long 0x04 "HW_USBCTRL_HCSPARAMS,Host Control Structural Parameters (EHCI-Compliant with Extensions) Register" bitfld.long 0x04 24.--27. " N_TT ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " N_PTT ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 16. " PI ,Port Indicators" "Not supported,Supported" bitfld.long 0x04 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. " PPC ,Port Power Control" "Disabled,Enabled" textline " " bitfld.long 0x04 0.--3. " N_PORTS ,Number of downstream ports" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.l(asd:(0x80080000+0x108)))&0x80)==0x0) group.long 0x108++0x03 line.long 0x00 "HW_USBCTRL_HCCPARAMS,Host Control Capability Parameters (EHCI-Compliant) Register" hexmask.long.byte 0x00 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x00 7. " IST[7] ,Isochronous Scheduling Threshold 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IST[6] ,Isochronous Scheduling Threshold 6" "Disabled,Enabled" bitfld.long 0x00 5. " IST[5] ,Isochronous Scheduling Threshold 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IST[4] ,Isochronous Scheduling Threshold 4" "Disabled,Enabled" bitfld.long 0x00 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" textline " " bitfld.long 0x00 1. " PFL ,Programmable Frame List Flag" "Not set,Set" bitfld.long 0x00 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" else group.long 0x108++0x03 line.long 0x00 "HW_USBCTRL_HCCPARAMS,Host Control Capability Parameters (EHCI-Compliant) Register" hexmask.long.byte 0x00 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x00 7. " IST[7] ,Isochronous data structure for an entire frame" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" bitfld.long 0x00 1. " PFL ,Programmable Frame List Flag" "Not set,Set" textline " " bitfld.long 0x00 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" endif group.long 0x120++0x03 line.long 0x00 "HW_USBCTRL_DCIVERSION,Device Interface Version Number (Non-EHCI-Compliant) Register" hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Two-byte BCD encoding of the interface version number" rgroup.long 0x124++0x03 line.long 0x00 "HW_USBCTRL_DCCPARAMS,Device Control Capability Parameters (Non-EHCI-Compliant) Register" bitfld.long 0x00 8. " HC ,Host Capable(EHCI-compatible USB 2.0 host controller)" "Not capable,Capable" bitfld.long 0x00 7. " DC ,Device Capable(USB 2.0 device)" "Not capable,Capable" textline " " bitfld.long 0x00 0.--4. " DEN ,Device Endpoint Number" "0,1,2,3,4,5,?..." if (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x3) group.long 0x140++0x0f line.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS ,Frame List Size Field" "4096 bytes,2048 bytes,1024 bytes,512 bytes,256 bytes,128 bytes,64 bytes,32 bytes" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Reserved,1,2,3" textline " " bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General-Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General-Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 19. " UPI ,USB Host Periodic Interrupt" "Not occurred,Occurred" bitfld.long 0x04 18. " UAI ,USB Host Asynchronous Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt Bit" "Not occurred,Occurred" bitfld.long 0x04 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" bitfld.long 0x04 13. " RCL ,Reclamation (empty asynchronous schedule)" "Not empty,Empty" textline " " bitfld.long 0x04 12. " HCH ,HC Halted" "Not halted,Halted" eventfld.long 0x04 7. " SRI ,SOF Received" "Not received,Received" textline " " bitfld.long 0x04 5. " AAI ,Interrupt on Async Advance" "Not occurred,Occurred" bitfld.long 0x04 3. " FRI ,Frame List Rollover" "Not occurred,Occurred" textline " " bitfld.long 0x04 2. " PCI ,Port Change Detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,USB Error Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 0. " UI ,USB Interrupt" "Not occurred,Occurred" line.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" bitfld.long 0x08 25. " TIE1 ,General-Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General-Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " UPIE ,USB Host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " UAIE ,USB Host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x0c "HW_USBCTRL_FRINDEX,USB Frame Index Register" hexmask.long.word 0x0c 3.--13. 1. " FRINDEX ,Frame List Current Index" bitfld.long 0x0c 0.--2. " UINDEX ,Current Microframe" "0,1,2,3,4,5,6,7" group.long 0x154++0x07 line.long 0x00 "HW_USBCTRL_PERIODICLISTBASE,Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " PERBASE ,HW_USBCTRL_PERIODICLISTBASE" line.long 0x04 "HW_USBCTRL_ASYNCLISTADDR,Next Asynchronous Address Register" hexmask.long 0x04 5.--31. 0x10 " ASYBASE ,Link Pointer Low (LPL)" group.long 0x15c++0x03 line.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" hexmask.long.byte 0x00 24.--30. 1. " TTHA ,Internal TT Hub Address Representation" elif (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x2) ;8--9. Doc Describtion 0x0 in device mode - undefined behavior - mistake? group.long 0x140++0x0b line.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not active,Active" textline " " bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not set,Set" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Reserved,1,2,3" bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General-Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General-Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt Bit" "Not occurred,Occurred" bitfld.long 0x04 8. " SLI ,DC Suspend" "Not suspended,Suspended" textline " " eventfld.long 0x04 7. " SRI ,SOF Received" "Not received,Received" bitfld.long 0x04 6. " URI ,USB Reset Received" "Not received,Received" textline " " bitfld.long 0x04 2. " PCI ,Port Change Detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,USB Error Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 0. " UI ,USB Interrupt" "Not occurred,Occurred" line.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" bitfld.long 0x08 25. " TIE1 ,General-Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General-Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 8. " SLE ,Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" bitfld.long 0x08 6. " URE ,USB Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" rgroup.long 0x14c++0x03 line.long 0x00 "HW_USBCTRL_FRINDEX,USB Frame Index Register" hexmask.long.word 0x00 3.--13. 1. " FRINDEX ,Frame List Current Index" bitfld.long 0x00 0.--2. " UINDEX ,Current Microframe" "0,1,2,3,4,5,6,7" group.long 0x154++0x07 line.long 0x00 "HW_USBCTRL_DEVICEADDR,USB Device Address Register" hexmask.long.byte 0x00 25.--31. 2. " USBADR ,Device Address" bitfld.long 0x00 24. " USBADRA ,Device Address Advance" "Disabled,Enabled" line.long 0x04 "HW_USBCTRL_ENDPOINTLISTADDR,Endpoint List Address Register" hexmask.long.tbyte 0x04 11.--31. 8. " EPBASE ,Endpoint List Pointer(Low)" hgroup.long 0x15c++0x03 hide.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" else hgroup.long 0x140++0x0b hide.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hide.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" hide.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" hide.long 0x0c "HW_USBCTRL_FRINDEX,USB Frame Index Register" hgroup.long 0x154++0x07 hide.long 0x00 "HW_USBCTRL_DEVICEADDR,USB Device Address Register" hide.long 0x04 "HW_USBCTRL_ENDPOINTLISTADDR,Endpoint List Address Register" hgroup.long 0x15c++0x03 hide.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" endif group.long 0x160++0x07 line.long 0x00 "HW_USBCTRL_BURSTSIZE,Programmable Burst Size Register" hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" line.long 0x04 "HW_USBCTRL_TXFILLTUNING,Host Transmit Pre-Buffer Packet Timing Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler Health Counter" textline " " hexmask.long.byte 0x04 0.--6. 1. " TXSCHOH ,Scheduler Overhead" group.long 0x16c++0x03 line.long 0x00 "HW_USBCTRL_IC_USB,Inter-Chip Control Register" bitfld.long 0x00 3. " IC_ENABLE ,Inter-Chip Transceiver Enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " IC_VDD ,Inter-Chip Transceiver Voltage" "None,1.0V,1.2V,1.5V,1.8V,3.0V,?..." hgroup.long 0x170++0x03 hide.long 0x00 "HW_USBCTRL_ULPI,ULPI Viewport Register" if (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x3) group.long 0x184++0x03 line.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL" bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,?..." bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Reserved,High speed,?..." textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "No,Yes" textline " " bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable (WKOC_E)" "Disabled,Enabled" bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable (WKDSCNNT_E)" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable (WKCNNT_E)" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "TEST_DISABLE,TEST_J_STATE,TEST_K_STATE,TEST_J_SE0_NAK,TEST_PACKET,TEST_FORCE_ENABLE_HS,TEST_FORCE_ENABLE_FS,TEST_FORCE_ENABLE_LS,?..." textline " " bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "OFF,AMBER,GREEN,UNDEF" bitfld.long 0x00 13. " PO ,Port Owner" "0,1" textline " " bitfld.long 0x00 12. " PP ,Port Power (PP)" "Off,On" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,K_STATE,J_STATE,J_STATE" textline " " bitfld.long 0x00 9. " HSP ,High-Speed Port" "No,Yes" bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not occurred,Occurred" bitfld.long 0x00 6. " FPR ,Force Port Resume" "No resume,Resume" textline " " bitfld.long 0x00 5. " OCC ,Over-Current Change" "Not changed,Changed" bitfld.long 0x00 4. " OCA ,Over-Current Active" "Not active,Active" textline " " bitfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "No changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CSC ,Connect Status Change" "No changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not present,Present" group.long 0x1a4++0x03 line.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " ONEMSE ,1 Millisecond Timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " ONEMSS ,1 Millisecond Timer Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not occurred,Occurred" bitfld.long 0x00 13. " ONEMST ,1 Millisecond Timer Toggle" "Not toggle,Toggle" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended" bitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Not started,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not pulsed,Pulsed" bitfld.long 0x00 3. " OT ,OTG Termination" "Not terminated,Terminated" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "No effect,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS_Discharge" "No effect,Discharged" elif (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x2) group.long 0x184++0x03 line.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL" bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,?..." bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Reserved,High speed,?..." textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "No,Yes" textline " " bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable (WKOC_E)" "Disabled,Enabled" bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable (WKDSCNNT_E)" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable (WKCNNT_E)" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "TEST_DISABLE,TEST_J_STATE,TEST_K_STATE,TEST_J_SE0_NAK,TEST_PACKET,TEST_FORCE_ENABLE_HS,TEST_FORCE_ENABLE_FS,TEST_FORCE_ENABLE_LS,?..." textline " " bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "OFF,AMBER,GREEN,UNDEF" bitfld.long 0x00 13. " PO ,Port Owner" "0,1" textline " " bitfld.long 0x00 12. " PP ,Port Power (PP)" "Off,On" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,K_STATE,J_STATE,J_STATE" textline " " bitfld.long 0x00 9. " HSP ,High-Speed Port" "No,Yes" bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not occurred,Occurred" bitfld.long 0x00 6. " FPR ,Force Port Resume" "No resume,Resume" textline " " bitfld.long 0x00 5. " OCC ,Over-Current Change" "Not changed,Changed" bitfld.long 0x00 4. " OCA ,Over-Current Active" "Not active,Active" textline " " bitfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "No changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not Attached,Attached" hgroup.long 0x1a4++0x03 hide.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" else hgroup.long 0x184++0x03 hide.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" hgroup.long 0x1a4++0x03 hide.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" endif group.long 0x1a8++0x03 line.long 0x00 "HW_USBCTRL_USBMODE,USB Device Mode Register" bitfld.long 0x00 5. " VBPS ,Vbus Power Select" "0,1" bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active" textline " " bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" textline " " bitfld.long 0x00 0.--1. " CM ,Controller Mode" "Idle,Reserved,Device,Host" width 0xb tree.end tree "USB Endpoint Registers" base asd:0x80080000 width 27. group.long 0x178++0x07 line.long 0x00 "HW_USBCTRL_ENDPTNAK,Endpoint NAK Register" bitfld.long 0x00 20. " EPTN[4] ,TX Endpoint 4 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 19. " EPTN[3] ,TX Endpoint 3 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 18. " EPTN[2] ,TX Endpoint 2 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 17. " EPTN[1] ,TX Endpoint 1 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 16. " EPTN[0] ,TX Endpoint 0 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 4. " EPRN[4] ,RX Endpoint 4 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX Endpoint 3 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 2. " EPRN[2] ,RX Endpoint 2 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 1. " EPRN[1] ,RX Endpoint 1 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 0. " EPRN[0] ,RX Endpoint 0 NAK" "Acknowledged,No acknowledged" line.long 0x04 "HW_USBCTRL_ENDPTNAKEN,Endpoint NAK Enable Register" bitfld.long 0x04 20. " EPTNE[4] ,TX Endpoint NAK 4 Enable" "Disabled,Enabled" bitfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" bitfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" bitfld.long 0x04 4. " EPRNE[4] ,RX Endpoint NAK 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" bitfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" if (((d.l(asd:(0x80080000+0x1ac)))&0x3)==0x1) group.long 0x1ac++0x03 line.long 0x00 "HW_USBCTRL_ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 4. " ENDPTSETUPSTAT[4] ,Setup Endpoint 4 Status" "Not occurred,Occurred" bitfld.long 0x00 3. " ENDPTSETUPSTAT[3] ,Setup Endpoint 3 Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " ENDPTSETUPSTAT[2] ,Setup Endpoint 2 Status" "Not occurred,Occurred" bitfld.long 0x00 1. " ENDPTSETUPSTAT[1] ,Setup Endpoint 1 Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " ENDPTSETUPSTAT[0] ,Setup Endpoint 0 Status" "Not occurred,Occurred" else hgroup.long 0x1ac++0x03 hide.long 0x00 "HW_USBCTRL_ENDPTSETUPSTAT,Endpoint Setup Status Register" endif if (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x1) group.long 0x1b0++0x00f line.long 0x00 "HW_USBCTRL_ENDPTPRIME,Endpoint Prime Register" bitfld.long 0x00 20. " PETB[4] ,Prime Endpoint 4 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 19. " PETB[3] ,Prime Endpoint 3 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 18. " PETB[2] ,Prime Endpoint 2 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 17. " PETB[1] ,Prime Endpoint 1 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 16. " PETB[0] ,Prime Endpoint 0 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 4. " PERB[4] ,Prime Endpoint 4 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PERB[3] ,Prime Endpoint 3 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 2. " PERB[2] ,Prime Endpoint 2 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 1. " PERB[1] ,Prime Endpoint 1 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 0. " PERB[0] ,Prime Endpoint 0 Receive Buffer" "Not requested,Requested" line.long 0x04 "HW_USBCTRL_ENDPTFLUSH,Endpoint Flush Register" bitfld.long 0x04 20. " FETB[4] ,Flush Endpoint 4 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 19. " FETB[3] ,Flush Endpoint 3 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 18. " FETB[2] ,Flush Endpoint 2 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 17. " FETB[1] ,Flush Endpoint 1 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 16. " FETB[0] ,Flush Endpoint 0 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 4. " FERB[4] ,Flush Endpoint 4 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 3. " FERB[3] ,Flush Endpoint 3 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 2. " FERB[2] ,Flush Endpoint 2 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 1. " FERB[1] ,Flush Endpoint 1 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 0. " FERB[0] ,Flush Endpoint 0 Receive Buffer" "Not requested,Requested" line.long 0x08 "HW_USBCTRL_ENDPTSTAT,Endpoint Status Register" bitfld.long 0x08 20. " ETBR[4] ,Endpoint 4 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 19. " ETBR[3] ,Endpoint 3 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 18. " ETBR[2] ,Endpoint 2 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 17. " ETBR[1] ,Endpoint 1 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 16. " ETBR[0] ,Endpoint 0 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 4. " ERBR[4] ,Endpoint 4 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 3. " ERBR[3] ,Endpoint 3 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 2. " ERBR[2] ,Endpoint 2 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 1. " ERBR[1] ,Endpoint 1 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 0. " ERBR[0] ,Endpoint 0 Receive Buffer Ready" "Not ready,Ready" line.long 0x0c "HW_USBCTRL_ENDPTCOMPLETE,Endpoint Complete Register" bitfld.long 0x0c 20. " ETCE[4] ,Endpoint 4 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 19. " ETCE[3] ,Endpoint 3 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 18. " ETCE[2] ,Endpoint 2 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 17. " ETCE[1] ,Endpoint 1 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 16. " ETCE[0] ,Endpoint 0 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 4. " ERCE[4] ,Endpoint 4 Receive Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 3. " ERCE[3] ,Endpoint 3 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 2. " ERCE[2] ,Endpoint 2 Receive Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 1. " ERCE[1] ,Endpoint 1 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 0. " ERCE[0] ,Endpoint 0 Receive Complete Event" "Not completed,Completed" else hgroup.long 0x1b0++0x00f hide.long 0x00 "HW_USBCTRL_ENDPTPRIME,Endpoint Prime Register" hide.long 0x04 "HW_USBCTRL_ENDPTFLUSH,Endpoint Flush Register" hide.long 0x08 "HW_USBCTRL_ENDPTSTAT,Endpoint Status Register" hide.long 0x0c "HW_USBCTRL_ENDPTCOMPLETE,Endpoint Complete Register" endif group.long 0x1c0++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "Control,?..." textline " " bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Ok,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "No effect,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Ok,Stalled" group.long 0x1C4++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL1,Endpoint Control 1" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1C8++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL2,Endpoint Control 2" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1CC++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL3,Endpoint Control 3" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1D0++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL4,Endpoint Control 4" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" width 0xb tree.end tree.end tree "USBPHY (USB Physical Interface)" base asd:0x8007c000 width 25. group.long 0x00++0x43 line.long 0x00 "HW_USBPHY_PWD,USB PHY Power-Down Register" bitfld.long 0x00 20. " RXPWDRX ,Receiver block power down except for the full speed differential receiver" "Disabled,Enabled" bitfld.long 0x00 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "Disabled,Enabled" bitfld.long 0x00 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "Disabled,Enabled" bitfld.long 0x00 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " TXPWDFS ,USB full-speed drivers power down" "Disabled,Enabled" line.long 0x04 "HW_USBPHY_PWD_SET,USB PHY Power-Down Set Register" bitfld.long 0x04 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "No effect,Set" bitfld.long 0x04 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "No effect,Set" textline " " bitfld.long 0x04 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "No effect,Set" bitfld.long 0x04 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "No effect,Set" textline " " bitfld.long 0x04 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "No effect,Set" bitfld.long 0x04 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "No effect,Set" textline " " bitfld.long 0x04 10. " TXPWDFS ,USB full-speed drivers power down" "No effect,Set" line.long 0x08 "HW_USBPHY_PWD_CLR,USB PHY Power-Down Clear Register" bitfld.long 0x08 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "No effect,Cleared" bitfld.long 0x08 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "No effect,Cleared" textline " " bitfld.long 0x08 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "No effect,Cleared" bitfld.long 0x08 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "No effect,Cleared" textline " " bitfld.long 0x08 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "No effect,Cleared" bitfld.long 0x08 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "No effect,Cleared" textline " " bitfld.long 0x08 10. " TXPWDFS ,USB full-speed drivers power down" "No effect,Cleared" line.long 0x0c "HW_USBPHY_PWD_TOG,USB PHY Power-Down Toggle Register" bitfld.long 0x0c 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "Not toggle,Toggle" bitfld.long 0x0c 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "Not toggle,Toggle" bitfld.long 0x0c 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "Not toggle,Toggle" bitfld.long 0x0c 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " TXPWDFS ,USB full-speed drivers power down" "Not toggle,Toggle" line.long 0x10 "HW_USBPHY_TX,USB PHY Transmitter Control Register" bitfld.long 0x10 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x10 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No sync,Sync" textline " " bitfld.long 0x10 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No sync,Sync" bitfld.long 0x10 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x14 "HW_USBPHY_TX_SET,USB PHY Transmitter Control Set Register" bitfld.long 0x14 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x14 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No effect,Set" textline " " bitfld.long 0x14 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No effect,Set" bitfld.long 0x14 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x18 "HW_USBPHY_TX_CLR,USB PHY Transmitter Control Clear Register" bitfld.long 0x18 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x18 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No effect,Cleared" textline " " bitfld.long 0x18 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No effect,Cleared" bitfld.long 0x18 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x1c "HW_USBPHY_TX_TOG,USB PHY Transmitter Control Toggle Register" bitfld.long 0x1c 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x1c 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "Not toggle,Toggle" bitfld.long 0x1c 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x1c 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1c 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x20 "HW_USBPHY_RX,USB PHY Receiver Control Register" bitfld.long 0x20 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "Disabled,Enabled" bitfld.long 0x20 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x20 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x24 "HW_USBPHY_RX_SET,USB PHY Receiver Control Set Register" bitfld.long 0x24 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "No effect,Set" bitfld.long 0x24 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x24 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x28 "HW_USBPHY_RX_CLR,USB PHY Receiver Control Clear Register" bitfld.long 0x28 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "No effect,Cleared" bitfld.long 0x28 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x28 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x2c "HW_USBPHY_RX_TOG,USB PHY Receiver Control Toggle Register" bitfld.long 0x2c 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "Not toggle,Toggle" bitfld.long 0x2c 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x2c 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x30 "HW_USBPHY_CTRL,USB PHY General Control Register" bitfld.long 0x30 31. " SFTRST ,USBPHY Soft reset bit" "Not reset,Reset" bitfld.long 0x30 30. " CLKGATE ,Gate UTMI clocks" "Not gated,Gated" textline " " bitfld.long 0x30 29. " UTMI_SUSPENDM ,Power down state" "Occurred,Not occurred" bitfld.long 0x30 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "Not forced,Forced" textline " " bitfld.long 0x30 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "Disabled,Enabled" bitfld.long 0x30 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "Disconnected,Connected" textline " " bitfld.long 0x30 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "Disabled,Enabled" bitfld.long 0x30 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "Not suspended,Suspended" textline " " bitfld.long 0x30 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Disabled,Enabled" bitfld.long 0x30 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" textline " " bitfld.long 0x30 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "Plugged,Unplugged" bitfld.long 0x30 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "Disabled,Enabled" textline " " bitfld.long 0x30 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "Connected,Disconnected" bitfld.long 0x30 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "Disabled,Enabled" line.long 0x34 "HW_USBPHY_CTRL_SET,USB PHY General Control Set Register" bitfld.long 0x34 31. " SFTRST ,USBPHY Soft reset bit" "No effect,Set" bitfld.long 0x34 30. " CLKGATE ,Gate UTMI clocks" "No effect,Set" textline " " bitfld.long 0x34 29. " UTMI_SUSPENDM ,Power down state" "No effect,Set" bitfld.long 0x34 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "No effect,Set" textline " " bitfld.long 0x34 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "No effect,Set" bitfld.long 0x34 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "No effect,Set" textline " " bitfld.long 0x34 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "No effect,Set" bitfld.long 0x34 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "No effect,Set" textline " " bitfld.long 0x34 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Set" bitfld.long 0x34 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "No effect,Set" textline " " bitfld.long 0x34 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Set" textline " " bitfld.long 0x34 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "No effect,Set" bitfld.long 0x34 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "No effect,Set" textline " " bitfld.long 0x34 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "No effect,Set" bitfld.long 0x34 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No effect,Set" textline " " bitfld.long 0x34 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "No effect,Set" line.long 0x38 "HW_USBPHY_CTRL_CLR,USB PHY General Control Clear Register" bitfld.long 0x38 31. " SFTRST ,USBPHY Soft reset bit" "No effect,Cleared" bitfld.long 0x38 30. " CLKGATE ,Gate UTMI clocks" "No effect,Cleared" textline " " bitfld.long 0x38 29. " UTMI_SUSPENDM ,Power down state" "No effect,Cleared" bitfld.long 0x38 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "No effect,Cleared" textline " " bitfld.long 0x38 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "No effect,Cleared" bitfld.long 0x38 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "No effect,Cleared" textline " " bitfld.long 0x38 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "No effect,Cleared" bitfld.long 0x38 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "No effect,Cleared" textline " " bitfld.long 0x38 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Cleared" bitfld.long 0x38 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Cleared" textline " " bitfld.long 0x38 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "No effect,Cleared" bitfld.long 0x38 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "No effect,Cleared" textline " " bitfld.long 0x38 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "No effect,Cleared" bitfld.long 0x38 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No effect,Cleared" textline " " bitfld.long 0x38 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "No effect,Cleared" line.long 0x3c "HW_USBPHY_CTRL_TOG,USB PHY General Control Toggle Register" bitfld.long 0x3c 31. " SFTRST ,USBPHY Soft reset bit" "Not toggle,Toggle" bitfld.long 0x3c 30. " CLKGATE ,Gate UTMI clocks" "Not toggle,Toggle" textline " " bitfld.long 0x3c 29. " UTMI_SUSPENDM ,Power down state" "Not toggle,Toggle" bitfld.long 0x3c 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "Not toggle,Toggle" textline " " bitfld.long 0x3c 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "Not toggle,Toggle" bitfld.long 0x3c 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "Not toggle,Toggle" textline " " bitfld.long 0x3c 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "Not toggle,Toggle" bitfld.long 0x3c 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "Not toggle,Toggle" textline " " bitfld.long 0x3c 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Not toggle,Toggle" bitfld.long 0x3c 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Not toggle,Toggle" textline " " bitfld.long 0x3c 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "Not toggle,Toggle" bitfld.long 0x3c 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "Not toggle,Toggle" textline " " bitfld.long 0x3c 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "Not toggle,Toggle" bitfld.long 0x3c 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "Not toggle,Toggle" textline " " bitfld.long 0x3c 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "Not toggle,Toggle" line.long 0x40 "HW_USBPHY_STATUS,USB PHY Status Register" bitfld.long 0x40 10. " RESUME_STATUS ,Indicates that the host is sending a wake-up after suspend and has triggered an interrupt" "Not occurred,Occurred" bitfld.long 0x40 8. " OTGID_STATUS ,Indicates the results of ID pin on MiniAB plug" "host(A),device(B)" textline " " bitfld.long 0x40 6. " DEVPLUGIN_STATUS ,Indicates that the device has been connected on the USB_DP and USB_DM lines" "Not connected,Connected" bitfld.long 0x40 3. " HOSTDISCONDETECT_STATUS ,Indicates that the device has disconnected while in high-speed host mode" "Connected,Disconnected" group.long 0x50++0x0f line.long 0x00 "HW_USBPHY_DEBUG,USB PHY Debug Register" bitfld.long 0x00 30. " CLKGATE ,Gate Test Clocks" "Not gated,Gated" bitfld.long 0x00 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" textline " " bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No reset,Reset" textline " " bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "Not allowed,Allowed" textline " " bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x00 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "Not override,Override" textline " " bitfld.long 0x00 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "Not override,Override" bitfld.long 0x00 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "Disabled,Enabled" bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "Not hold,Hold" textline " " bitfld.long 0x00 0. " OTGIDPIOLOCK ,OTG ID hold value" "Not locked,Locked" line.long 0x04 "HW_USBPHY_DEBUG_SET,USB PHY Debug Set Register" bitfld.long 0x04 30. " CLKGATE ,Gate Test Clocks" "No effect,Set" bitfld.long 0x04 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "No effect,Set" textline " " bitfld.long 0x04 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "No effect,Set" textline " " bitfld.long 0x04 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x04 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "No effect,Set" textline " " bitfld.long 0x04 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "No effect,Set" bitfld.long 0x04 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "No effect,Set" textline " " bitfld.long 0x04 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "No effect,Set" bitfld.long 0x04 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "No effect,Set" textline " " bitfld.long 0x04 0. " OTGIDPIOLOCK ,OTG ID hold value" "No effect,Set" line.long 0x08 "HW_USBPHY_DEBUG_CLR,USB PHY Debug Clear Register" bitfld.long 0x08 30. " CLKGATE ,Gate Test Clocks" "No effect,Cleared" bitfld.long 0x08 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "No effect,Cleared" textline " " bitfld.long 0x08 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No effect,Cleared" textline " " bitfld.long 0x08 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "No effect,Cleared" textline " " bitfld.long 0x08 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x08 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "No effect,Cleared" textline " " bitfld.long 0x08 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "No effect,Cleared" bitfld.long 0x08 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "No effect,Cleared" textline " " bitfld.long 0x08 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "No effect,Cleared" bitfld.long 0x08 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "No effect,Cleared" textline " " bitfld.long 0x08 0. " OTGIDPIOLOCK ,OTG ID hold value" "No effect,Cleared" line.long 0x0c "HW_USBPHY_DEBUG_TOG,USB PHY Debug Toggle Register" bitfld.long 0x0c 30. " CLKGATE ,Gate Test Clocks" "Not toggle,Toggle" bitfld.long 0x0c 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x0c 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "Not toggle,Toggle" bitfld.long 0x0c 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "Not toggle,Toggle" bitfld.long 0x0c 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " OTGIDPIOLOCK ,OTG ID hold value" "Not toggle,Toggle" rgroup.long 0x60++0x03 line.long 0x00 "HW_USBPHY_DEBUG0_STATUS,UTMI Debug Status Register 0" hexmask.long.byte 0x00 26.--31. 1. " SQUELCH_COUNT ,Running count of the squelch reset instead of normal end for HS RX" hexmask.long.word 0x00 16.--25. 1. " UTMI_RXERROR_FAIL_COUNT ,Running count of the UTMI_RXERROR" textline " " hexmask.long.word 0x00 0.--15. 1. " LOOP_BACK_FAIL_COUNT ,Running count of the failed pseudo-random generator loopback" group.long 0x70++0x0f line.long 0x00 "HW_USBPHY_DEBUG1,UTMI Debug Status Register 1" bitfld.long 0x00 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x00 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HW_USBPHY_DEBUG1_SET,UTMI Debug Status Set Register 1" bitfld.long 0x04 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x04 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "HW_USBPHY_DEBUG1_CLR,UTMI Debug Status Clear Register 1" bitfld.long 0x08 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x08 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0c "HW_USBPHY_DEBUG1_TOG,UTMI Debug Status Toggle Register 1" bitfld.long 0x0c 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x0c 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x80++0x03 line.long 0x00 "HW_USBPHY_VERSION,UTMI RTL Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0x90++0x0f line.long 0x00 "HW_USBPHY_IP,USB PHY IP Block Register" bitfld.long 0x00 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." textline " " bitfld.long 0x00 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x00 18. " TSTI_TX_DP ,DP Analog testmode bit" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " TSTI_TX_DM ,DM Analog testmode bit" "Disabled,Enabled" bitfld.long 0x00 16. " ANALOG_TESTMODE ,Analog testmode bit" "Normal,Debug" textline " " bitfld.long 0x00 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "Off,On" bitfld.long 0x00 1. " PLL_LOCKED ,USB PLL lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 0. " PLL_POWER ,USB PLL power bit" "Off,On" line.long 0x04 "HW_USBPHY_IP_SET,USB PHY IP Block Set Register" bitfld.long 0x04 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." textline " " bitfld.long 0x04 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x04 18. " TSTI_TX_DP ,DP Analog testmode bit" "No effect,Set" textline " " bitfld.long 0x04 17. " TSTI_TX_DM ,DM Analog testmode bit" "No effect,Set" bitfld.long 0x04 16. " ANALOG_TESTMODE ,Analog testmode bit" "No effect,Set" textline " " bitfld.long 0x04 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "No effect,Set" bitfld.long 0x04 1. " PLL_LOCKED ,USB PLL lock bit" "No effect,Set" textline " " bitfld.long 0x04 0. " PLL_POWER ,USB PLL power bit" "No effect,Set" line.long 0x08 "HW_USBPHY_IP_CLR,USB PHY IP Block Clear Register" bitfld.long 0x08 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." textline " " bitfld.long 0x08 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x08 18. " TSTI_TX_DP ,DP Analog testmode bit" "No effect,Cleared" textline " " bitfld.long 0x08 17. " TSTI_TX_DM ,DM Analog testmode bit" "No effect,Cleared" bitfld.long 0x08 16. " ANALOG_TESTMODE ,Analog testmode bit" "No effect,Cleared" textline " " bitfld.long 0x08 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "No effect,Cleared" bitfld.long 0x08 1. " PLL_LOCKED ,USB PLL lock bit" "No effect,Cleared" textline " " bitfld.long 0x08 0. " PLL_POWER ,USB PLL power bit" "No effect,Cleared" line.long 0x0c "HW_USBPHY_IP_TOG,USB PHY IP Block Toggle Register" bitfld.long 0x0c 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." textline " " bitfld.long 0x0c 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x0c 18. " TSTI_TX_DP ,DP Analog testmode bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " TSTI_TX_DM ,DM Analog testmode bit" "Not toggle,Toggle" bitfld.long 0x0c 16. " ANALOG_TESTMODE ,Analog testmode bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "Not toggle,Toggle" bitfld.long 0x0c 1. " PLL_LOCKED ,USB PLL lock bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " PLL_POWER ,USB PLL power bit" "Not toggle,Toggle" width 0xb tree.end tree "APBHDMA (AHB-to-APBH Bridge with DMA)" base asd:0x80004000 width 19. group.long 0x00++0x2f line.long 0x00 "HW_APBH_CTRL0,AHB to APBH Bridge Control and Status Register 0" bitfld.long 0x00 31. " SFTRST ,Normal APBH DMA operation" "Disabled,Enabled" bitfld.long 0x00 30. " CLKGATE ,Clock Gate" "Normal,Gated off" textline " " bitfld.long 0x00 29. " AHB_BURST8_EN ,AHB 8-beat burst" "Disabled,Enabled" bitfld.long 0x00 28. " APB_BURST4_EN ,APB 4-beat burst" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 16.--23. 1. " RESET_CHANNEL ,Causes the DMA controller to take the corresponding channel through its reset state" hexmask.long.byte 0x00 8.--15. 1. " CLKGATE_CHANNEL ,When set to one they gate off the individual clocks to the channels" textline " " hexmask.long.byte 0x00 0.--7. 1. " FREEZE_CHANNEL ,direct input to the DMA channel arbiter" line.long 0x04 "HW_APBH_CTRL0_SET,AHB to APBH Bridge Control and Status Set Register 0" bitfld.long 0x04 31. " SFTRST ,Normal APBH DMA operation" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock Gate" "No effect,Set" textline " " bitfld.long 0x04 29. " AHB_BURST8_EN ,AHB 8-beat burst" "No effect,Set" bitfld.long 0x04 28. " APB_BURST4_EN ,APB 4-beat burst" "No effect,Set" textline " " hexmask.long.byte 0x04 16.--23. 1. " RESET_CHANNEL ,the DMA controller to take the corresponding channel through its reset state" hexmask.long.byte 0x04 8.--15. 1. " CLKGATE_CHANNEL ,When set to one they gate off the individual clocks to the channels" textline " " hexmask.long.byte 0x04 0.--7. 1. " FREEZE_CHANNEL ,direct input to the DMA channel arbiter" line.long 0x08 "HW_APBH_CTRL0_CLR,AHB to APBH Bridge Control and Status Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Normal APBH DMA operation" "No effect,Cleared" bitfld.long 0x08 30. " CLKGATE ,Clock Gate" "No effect,Cleared" textline " " bitfld.long 0x08 29. " AHB_BURST8_EN ,AHB 8-beat burst" "No effect,Cleared" bitfld.long 0x08 28. " APB_BURST4_EN ,APB 4-beat burst" "No effect,Cleared" textline " " hexmask.long.byte 0x08 16.--23. 1. " RESET_CHANNEL ,the DMA controller to take the corresponding channel through its reset state" hexmask.long.byte 0x08 8.--15. 1. " CLKGATE_CHANNEL ,When set to one they gate off the individual clocks to the channels" textline " " hexmask.long.byte 0x08 0.--7. 1. " FREEZE_CHANNEL ,direct input to the DMA channel arbiter" line.long 0x0c "HW_APBH_CTRL0_TOG,AHB to APBH Bridge Control and Status Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Normal APBH DMA operation" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock Gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " AHB_BURST8_EN ,AHB 8-beat burst" "Not toggle,Toggle" bitfld.long 0x0c 28. " APB_BURST4_EN ,APB 4-beat burst" "Not toggle,Toggle" textline " " hexmask.long.byte 0x0c 16.--23. 1. " RESET_CHANNEL ,the DMA controller to take the corresponding channel through its reset state" hexmask.long.byte 0x0c 8.--15. 1. " CLKGATE_CHANNEL ,When set to one they gate off the individual clocks to the channels" textline " " hexmask.long.byte 0x0c 0.--7. 1. " FREEZE_CHANNEL ,direct input to the DMA channel arbiter" line.long 0x10 "HW_APBH_CTRL1,AHB to APBH Bridge Control and Status Register 1" bitfld.long 0x10 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "Disabled,Enabled" bitfld.long 0x10 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "Not requested,Requested" bitfld.long 0x10 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "Not requested,Requested" textline " " bitfld.long 0x10 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "Not requested,Requested" bitfld.long 0x10 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "Not requested,Requested" textline " " bitfld.long 0x10 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "Not requested,Requested" bitfld.long 0x10 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not requested,Requested" textline " " bitfld.long 0x10 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "Not requested,Requested" bitfld.long 0x10 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "Not requested,Requested" line.long 0x14 "HW_APBH_CTRL1_SET,AHB to APBH Bridge Control and Status Set Register 1" bitfld.long 0x14 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "No effect,Set" bitfld.long 0x14 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "No effect,Set" bitfld.long 0x14 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "No effect,Set" bitfld.long 0x14 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "No effect,Set" bitfld.long 0x14 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Set" bitfld.long 0x14 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Set" textline " " bitfld.long 0x14 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Set" bitfld.long 0x14 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Set" textline " " bitfld.long 0x14 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Set" bitfld.long 0x14 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Set" textline " " bitfld.long 0x14 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Set" bitfld.long 0x14 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Set" line.long 0x18 "HW_APBH_CTRL1_CLR,AHB to APBH Bridge Control and Status Clear Register 1" bitfld.long 0x18 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "No effect,Cleared" bitfld.long 0x18 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "No effect,Cleared" textline " " bitfld.long 0x18 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "No effect,Cleared" bitfld.long 0x18 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "No effect,Cleared" textline " " bitfld.long 0x18 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "No effect,Cleared" bitfld.long 0x18 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Cleared" textline " " bitfld.long 0x18 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "No effect,Cleared" bitfld.long 0x18 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "No effect,Cleared" textline " " bitfld.long 0x18 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Cleared" bitfld.long 0x18 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Cleared" textline " " bitfld.long 0x18 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Cleared" bitfld.long 0x18 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Cleared" textline " " bitfld.long 0x18 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Cleared" bitfld.long 0x18 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Cleared" textline " " bitfld.long 0x18 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Cleared" bitfld.long 0x18 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Cleared" line.long 0x1c "HW_APBH_CTRL1_TOG,AHB to APBH Bridge Control and Status Toggle Register 1" bitfld.long 0x1c 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1c 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1c 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1c 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1c 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1c 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1c 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "Not toggle,Toggle" bitfld.long 0x1c 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1c 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "Not toggle,Toggle" bitfld.long 0x1c 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x1c 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "Not toggle,Toggle" bitfld.long 0x1c 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "Not toggle,Toggle" bitfld.long 0x1c 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "Not toggle,Toggle" bitfld.long 0x1c 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "Not toggle,Toggle" line.long 0x20 "HW_APBH_CTRL2,AHB to APBH Bridge Control and Status Register 2" bitfld.long 0x20 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "Terminated,Bus error" bitfld.long 0x20 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "Terminated,Bus error" textline " " bitfld.long 0x20 21. " CH5_ERROR_STATUS ,Error status bit for APBX DMA Channel 5" "Terminated,Bus error" bitfld.long 0x20 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "Terminated,Bus error" textline " " bitfld.long 0x20 19. " CH3_ERROR_STATUS ,Error status bit for APBX DMA Channel 3" "Terminated,Bus error" bitfld.long 0x20 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "Terminated,Bus error" textline " " bitfld.long 0x20 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "Terminated,Bus error" bitfld.long 0x20 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "Terminated,Bus error" textline " " bitfld.long 0x20 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "Disabled,Enabled" bitfld.long 0x20 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "Disabled,Enabled" textline " " bitfld.long 0x20 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 5" "Disabled,Enabled" bitfld.long 0x20 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "Disabled,Enabled" textline " " bitfld.long 0x20 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 3" "Disabled,Enabled" bitfld.long 0x20 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "Disabled,Enabled" bitfld.long 0x20 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "Disabled,Enabled" line.long 0x24 "HW_APBH_CTRL2_SET,AHB to APBH Bridge Control and Status Set Register 2" bitfld.long 0x24 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "No effect,Set" bitfld.long 0x24 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "No effect,Set" textline " " bitfld.long 0x24 21. " CH5_ERROR_STATUS ,Error status bit for APBX DMA Channel 5" "No effect,Set" bitfld.long 0x24 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "No effect,Set" textline " " bitfld.long 0x24 19. " CH3_ERROR_STATUS ,Error status bit for APBX DMA Channel 3" "No effect,Set" bitfld.long 0x24 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "No effect,Set" textline " " bitfld.long 0x24 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "No effect,Set" bitfld.long 0x24 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "No effect,Set" textline " " bitfld.long 0x24 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "No effect,Set" bitfld.long 0x24 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "No effect,Set" textline " " bitfld.long 0x24 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 5" "No effect,Set" bitfld.long 0x24 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "No effect,Set" textline " " bitfld.long 0x24 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 3" "No effect,Set" bitfld.long 0x24 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "No effect,Set" textline " " bitfld.long 0x24 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "No effect,Set" bitfld.long 0x24 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "No effect,Set" line.long 0x28 "HW_APBH_CTRL2_CLR,AHB to APBH Bridge Control and Status Clear Register 2" bitfld.long 0x28 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "No effect,Cleared" bitfld.long 0x28 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "No effect,Cleared" textline " " bitfld.long 0x28 21. " CH5_ERROR_STATUS ,Error status bit for APBX DMA Channel 5" "No effect,Cleared" bitfld.long 0x28 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "No effect,Cleared" textline " " bitfld.long 0x28 19. " CH3_ERROR_STATUS ,Error status bit for APBX DMA Channel 3" "No effect,Cleared" bitfld.long 0x28 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "No effect,Cleared" textline " " bitfld.long 0x28 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "No effect,Cleared" bitfld.long 0x28 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "No effect,Cleared" textline " " bitfld.long 0x28 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "No effect,Cleared" bitfld.long 0x28 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "No effect,Cleared" textline " " bitfld.long 0x28 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 5" "No effect,Cleared" bitfld.long 0x28 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "No effect,Cleared" textline " " bitfld.long 0x28 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 3" "No effect,Cleared" bitfld.long 0x28 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "No effect,Cleared" textline " " bitfld.long 0x28 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "No effect,Cleared" bitfld.long 0x28 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "No effect,Cleared" line.long 0x2c "HW_APBH_CTRL2_TOG,AHB to APBH Bridge Control and Status Toggle Register 2" bitfld.long 0x2c 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "Not toggle,Toggle" bitfld.long 0x2c 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x2c 21. " CH5_ERROR_STATUS ,Error status bit for APBX DMA Channel 5" "Not toggle,Toggle" bitfld.long 0x2c 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x2c 19. " CH3_ERROR_STATUS ,Error status bit for APBX DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x2c 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x2c 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x2c 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "Not toggle,Toggle" textline " " bitfld.long 0x2c 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "Not toggle,Toggle" bitfld.long 0x2c 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x2c 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 5" "Not toggle,Toggle" bitfld.long 0x2c 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x2c 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x2c 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x2c 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x2c 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "Not toggle,Toggle" hgroup.long 0x30++0x03 hide.long 0x00 "HW_APBH_DEVSEL,AHB to APBH DMA Device Assignment Register" rgroup.long 0x3f0++0x03 line.long 0x00 "HW_APBH_VERSION,APBH Bridge Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 23. tree "DMA Channel Registers" tree "Channel 0" rgroup.long 0x40++0x03 line.long 0x00 "HW_APBH_CH0_CURCMDAR,APBH DMA Channel 0 Current Command Address Register" rgroup.long (0x40+0x10)++0x03 line.long 0x00 "HW_APBH_CH0_NXTCMDAR,APBH DMA Channel 0 Next Command Address Register" rgroup.long (0x40+0x20)++0x03 line.long 0x00 "HW_APBH_CH0_CMD,APBH DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,ATA/NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,ATA/NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x40+0x30)++0x03 line.long 0x00 "HW_APBH_CH0_BAR,APBH DMA Channel 0 Buffer Address Register" group.long (0x40+0x40)++0x03 line.long 0x00 "HW_APBH_CH0_SEMA,APBH DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x40+0x50)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG1,AHB to APBH DMA Channel 0 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,?..." rgroup.long (0x40+0x60)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG2,AHB to APBH DMA Channel 0 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end tree "Channel 1" rgroup.long 0xB0++0x03 line.long 0x00 "HW_APBH_CH1_CURCMDAR,APBH DMA Channel 1 Current Command Address Register" rgroup.long (0xB0+0x10)++0x03 line.long 0x00 "HW_APBH_CH1_NXTCMDAR,APBH DMA Channel 1 Next Command Address Register" rgroup.long (0xB0+0x20)++0x03 line.long 0x00 "HW_APBH_CH1_CMD,APBH DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,ATA/NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,ATA/NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0xB0+0x30)++0x03 line.long 0x00 "HW_APBH_CH1_BAR,APBH DMA Channel 1 Buffer Address Register" group.long (0xB0+0x40)++0x03 line.long 0x00 "HW_APBH_CH1_SEMA,APBH DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0xB0+0x50)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG1,AHB to APBH DMA Channel 1 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,?..." rgroup.long (0xB0+0x60)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG2,AHB to APBH DMA Channel 1 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end tree "Channel 2" rgroup.long 0x120++0x03 line.long 0x00 "HW_APBH_CH2_CURCMDAR,APBH DMA Channel 2 Current Command Address Register" rgroup.long (0x120+0x10)++0x03 line.long 0x00 "HW_APBH_CH2_NXTCMDAR,APBH DMA Channel 2 Next Command Address Register" rgroup.long (0x120+0x20)++0x03 line.long 0x00 "HW_APBH_CH2_CMD,APBH DMA Channel 2 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,ATA/NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,ATA/NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x120+0x30)++0x03 line.long 0x00 "HW_APBH_CH2_BAR,APBH DMA Channel 2 Buffer Address Register" group.long (0x120+0x40)++0x03 line.long 0x00 "HW_APBH_CH2_SEMA,APBH DMA Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x120+0x50)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG1,AHB to APBH DMA Channel 2 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,?..." rgroup.long (0x120+0x60)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG2,AHB to APBH DMA Channel 2 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end tree "Channel 3" rgroup.long 0x190++0x03 line.long 0x00 "HW_APBH_CH3_CURCMDAR,APBH DMA Channel 3 Current Command Address Register" rgroup.long (0x190+0x10)++0x03 line.long 0x00 "HW_APBH_CH3_NXTCMDAR,APBH DMA Channel 3 Next Command Address Register" rgroup.long (0x190+0x20)++0x03 line.long 0x00 "HW_APBH_CH3_CMD,APBH DMA Channel 3 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,ATA/NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,ATA/NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x190+0x30)++0x03 line.long 0x00 "HW_APBH_CH3_BAR,APBH DMA Channel 3 Buffer Address Register" group.long (0x190+0x40)++0x03 line.long 0x00 "HW_APBH_CH3_SEMA,APBH DMA Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x190+0x50)++0x03 line.long 0x00 "HW_APBH_CH3_DEBUG1,AHB to APBH DMA Channel 3 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,?..." rgroup.long (0x190+0x60)++0x03 line.long 0x00 "HW_APBH_CH3_DEBUG2,AHB to APBH DMA Channel 3 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end tree "Channel 4" rgroup.long 0x200++0x03 line.long 0x00 "HW_APBH_CH4_CURCMDAR,APBH DMA Channel 4 Current Command Address Register" rgroup.long (0x200+0x10)++0x03 line.long 0x00 "HW_APBH_CH4_NXTCMDAR,APBH DMA Channel 4 Next Command Address Register" rgroup.long (0x200+0x20)++0x03 line.long 0x00 "HW_APBH_CH4_CMD,APBH DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,ATA/NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,ATA/NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x200+0x30)++0x03 line.long 0x00 "HW_APBH_CH4_BAR,APBH DMA Channel 4 Buffer Address Register" group.long (0x200+0x40)++0x03 line.long 0x00 "HW_APBH_CH4_SEMA,APBH DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x200+0x50)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG1,AHB to APBH DMA Channel 4 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,?..." rgroup.long (0x200+0x60)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG2,AHB to APBH DMA Channel 4 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end tree "Channel 5" rgroup.long 0x270++0x03 line.long 0x00 "HW_APBH_CH5_CURCMDAR,APBH DMA Channel 5 Current Command Address Register" rgroup.long (0x270+0x10)++0x03 line.long 0x00 "HW_APBH_CH5_NXTCMDAR,APBH DMA Channel 5 Next Command Address Register" rgroup.long (0x270+0x20)++0x03 line.long 0x00 "HW_APBH_CH5_CMD,APBH DMA Channel 5 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,ATA/NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,ATA/NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x270+0x30)++0x03 line.long 0x00 "HW_APBH_CH5_BAR,APBH DMA Channel 5 Buffer Address Register" group.long (0x270+0x40)++0x03 line.long 0x00 "HW_APBH_CH5_SEMA,APBH DMA Channel 5 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x270+0x50)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG1,AHB to APBH DMA Channel 5 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,?..." rgroup.long (0x270+0x60)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG2,AHB to APBH DMA Channel 5 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end tree "Channel 6" rgroup.long 0x2E0++0x03 line.long 0x00 "HW_APBH_CH6_CURCMDAR,APBH DMA Channel 6 Current Command Address Register" rgroup.long (0x2E0+0x10)++0x03 line.long 0x00 "HW_APBH_CH6_NXTCMDAR,APBH DMA Channel 6 Next Command Address Register" rgroup.long (0x2E0+0x20)++0x03 line.long 0x00 "HW_APBH_CH6_CMD,APBH DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,ATA/NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,ATA/NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x2E0+0x30)++0x03 line.long 0x00 "HW_APBH_CH6_BAR,APBH DMA Channel 6 Buffer Address Register" group.long (0x2E0+0x40)++0x03 line.long 0x00 "HW_APBH_CH6_SEMA,APBH DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x2E0+0x50)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG1,AHB to APBH DMA Channel 6 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,?..." rgroup.long (0x2E0+0x60)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG2,AHB to APBH DMA Channel 6 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end tree "Channel 7" rgroup.long 0x350++0x03 line.long 0x00 "HW_APBH_CH7_CURCMDAR,APBH DMA Channel 7 Current Command Address Register" rgroup.long (0x350+0x10)++0x03 line.long 0x00 "HW_APBH_CH7_NXTCMDAR,APBH DMA Channel 7 Next Command Address Register" rgroup.long (0x350+0x20)++0x03 line.long 0x00 "HW_APBH_CH7_CMD,APBH DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,ATA/NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,ATA/NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x350+0x30)++0x03 line.long 0x00 "HW_APBH_CH7_BAR,APBH DMA Channel 7 Buffer Address Register" group.long (0x350+0x40)++0x03 line.long 0x00 "HW_APBH_CH7_SEMA,APBH DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x350+0x50)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG1,AHB to APBH DMA Channel 7 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,?..." rgroup.long (0x350+0x60)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG2,AHB to APBH DMA Channel 7 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end tree.end width 0xb tree.end tree "APBXDMA (AHB-to-APBX Bridge with DMA)" base asd:0x80024000 width 26. group.long 0x00++0x1f line.long 0x00 "HW_APBX_CTRL0,AHB to APBX Bridge Control Register 0" bitfld.long 0x00 31. " SFTRST ,Set this bit to zero to enable normal APBX DMA operation" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock Gate bit" "Normal,Gated off" line.long 0x04 "HW_APBX_CTRL0_SET,AHB_TOG to APBX Bridge Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Set this bit to zero to enable normal APBX DMA operation" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock Gate bit" "No effect,Set" line.long 0x08 "HW_APBX_CTRL0_CLR,AHB to APBX Bridge Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Set this bit to zero to enable normal APBX DMA operation" "No effect,Cleared" bitfld.long 0x08 30. " CLKGATE ,Clock Gate bit" "No effect,Cleared" line.long 0x0c "HW_APBX_CTRL0_TOG,AHB to APBX Bridge Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Set this bit to zero to enable normal APBX DMA operation" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock Gate bit" "Not toggle,Toggle" line.long 0x10 "HW_APBX_CTRL1,AHB to APBX Bridge Control Register 1" bitfld.long 0x10 26. " CH10_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10" "Disabled,Enabled" bitfld.long 0x10 25. " CH9_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9" "Disabled,Enabled" textline " " bitfld.long 0x10 24. " CH8_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8" "Disabled,Enabled" bitfld.long 0x10 23. " CH7_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " CH6_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6" "Disabled,Enabled" bitfld.long 0x10 20. " CH4_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " CH3_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 3" "Disabled,Enabled" bitfld.long 0x10 18. " CH2_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2" "Disabled,Enabled" textline " " bitfld.long 0x10 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "Disabled,Enabled" bitfld.long 0x10 16. " CH0_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 10" "Not completed,Completed" bitfld.long 0x10 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 9" "Not completed,Completed" textline " " bitfld.long 0x10 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 8" "Not completed,Completed" bitfld.long 0x10 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 7" "Not completed,Completed" textline " " bitfld.long 0x10 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 6" "Not completed,Completed" bitfld.long 0x10 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 4" "Not completed,Completed" textline " " bitfld.long 0x10 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 3" "Not completed,Completed" bitfld.long 0x10 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 2" "Not completed,Completed" textline " " bitfld.long 0x10 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 1" "Not completed,Completed" bitfld.long 0x10 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 0" "Not completed,Completed" line.long 0x14 "HW_APBX_CTRL1_SET,AHB to APBX Bridge Control Set Register 1" bitfld.long 0x14 26. " CH10_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10" "No effect,Set" bitfld.long 0x14 25. " CH9_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9" "No effect,Set" textline " " bitfld.long 0x14 24. " CH8_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8" "No effect,Set" bitfld.long 0x14 23. " CH7_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7" "No effect,Set" textline " " bitfld.long 0x14 22. " CH6_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6" "No effect,Set" bitfld.long 0x14 20. " CH4_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4" "No effect,Set" textline " " bitfld.long 0x14 19. " CH3_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 3" "No effect,Set" bitfld.long 0x14 18. " CH2_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2" "No effect,Set" textline " " bitfld.long 0x14 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "No effect,Set" bitfld.long 0x14 16. " CH0_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0" "No effect,Set" textline " " bitfld.long 0x14 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 10" "No effect,Set" bitfld.long 0x14 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 9" "No effect,Set" textline " " bitfld.long 0x14 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 8" "No effect,Set" bitfld.long 0x14 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 7" "No effect,Set" textline " " bitfld.long 0x14 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 6" "No effect,Set" bitfld.long 0x14 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 4" "No effect,Set" textline " " bitfld.long 0x14 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 3" "No effect,Set" bitfld.long 0x14 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 2" "No effect,Set" textline " " bitfld.long 0x14 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 1" "No effect,Set" bitfld.long 0x14 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 0" "No effect,Set" line.long 0x18 "HW_APBX_CTRL1_CLR,AHB to APBX Bridge Control Clear Register 1" bitfld.long 0x18 26. " CH10_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10" "No effect,Cleared" bitfld.long 0x18 25. " CH9_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9" "No effect,Cleared" textline " " bitfld.long 0x18 24. " CH8_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8" "No effect,Cleared" bitfld.long 0x18 23. " CH7_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7" "No effect,Cleared" textline " " bitfld.long 0x18 22. " CH6_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6" "No effect,Cleared" bitfld.long 0x18 20. " CH4_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4" "No effect,Cleared" textline " " bitfld.long 0x18 19. " CH3_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 3" "No effect,Cleared" bitfld.long 0x18 18. " CH2_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2" "No effect,Cleared" textline " " bitfld.long 0x18 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "No effect,Cleared" bitfld.long 0x18 16. " CH0_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0" "No effect,Cleared" textline " " bitfld.long 0x18 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 10" "No effect,Cleared" bitfld.long 0x18 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 9" "No effect,Cleared" textline " " bitfld.long 0x18 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 8" "No effect,Cleared" bitfld.long 0x18 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 7" "No effect,Cleared" textline " " bitfld.long 0x18 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 6" "No effect,Cleared" bitfld.long 0x18 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 4" "No effect,Cleared" textline " " bitfld.long 0x18 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 3" "No effect,Cleared" bitfld.long 0x18 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 2" "No effect,Cleared" textline " " bitfld.long 0x18 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 1" "No effect,Cleared" bitfld.long 0x18 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 0" "No effect,Cleared" line.long 0x1c "HW_APBX_CTRL1_TOG,AHB to APBX Bridge Control Toggle Register 1" bitfld.long 0x1c 26. " CH10_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10" "Not toggle,Toggle" bitfld.long 0x1c 25. " CH9_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " CH8_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8" "Not toggle,Toggle" bitfld.long 0x1c 23. " CH7_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7" "Not toggle,Toggle" textline " " bitfld.long 0x1c 22. " CH6_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6" "Not toggle,Toggle" bitfld.long 0x1c 20. " CH4_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x1c 19. " CH3_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x1c 18. " CH2_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x1c 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x1c 16. " CH0_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0" "Not toggle,Toggle" textline " " bitfld.long 0x1c 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 10" "Not toggle,Toggle" bitfld.long 0x1c 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 9" "Not toggle,Toggle" textline " " bitfld.long 0x1c 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 8" "Not toggle,Toggle" bitfld.long 0x1c 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 7" "Not toggle,Toggle" textline " " bitfld.long 0x1c 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 6" "Not toggle,Toggle" bitfld.long 0x1c 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x1c 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x1c 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 0" "Not toggle,Toggle" rgroup.long 0x20++0x0f line.long 0x00 "HW_APBX_CTRL2,AHB to APBX Bridge Control and Status Register 2" bitfld.long 0x00 26. " CH10_ERROR_STATUS ,Error status bit for APBX DMA Channel 10" "Terminated,Bus error" bitfld.long 0x00 25. " CH9_ERROR_STATUS ,Error status bit for APBX DMA Channel 9" "Terminated,Bus error" textline " " bitfld.long 0x00 24. " CH8_ERROR_STATUS ,Error status bit for APBX DMA Channel 8" "Terminated,Bus error" bitfld.long 0x00 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "Terminated,Bus error" textline " " bitfld.long 0x00 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "Terminated,Bus error" bitfld.long 0x00 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "Terminated,Bus error" textline " " bitfld.long 0x00 19. " CH3_ERROR_STATUS ,Error status bit for APBX DMA Channel 3" "Terminated,Bus error" bitfld.long 0x00 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "Terminated,Bus error" textline " " bitfld.long 0x00 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "Terminated,Bus error" bitfld.long 0x00 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "Terminated,Bus error" textline " " bitfld.long 0x00 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 10" "No interrupt,Interrupt" bitfld.long 0x00 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 9" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 8" "No interrupt,Interrupt" bitfld.long 0x00 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "No interrupt,Interrupt" bitfld.long 0x00 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 3" "No interrupt,Interrupt" bitfld.long 0x00 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "No interrupt,Interrupt" bitfld.long 0x00 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "No interrupt,Interrupt" line.long 0x04 "HW_APBX_CTRL2,AHB to APBX Bridge Control and Status Register 2" bitfld.long 0x04 26. " CH10_ERROR_STATUS ,Error status bit for APBX DMA Channel 10" "No effect,Set" bitfld.long 0x04 25. " CH9_ERROR_STATUS ,Error status bit for APBX DMA Channel 9" "No effect,Set" textline " " bitfld.long 0x04 24. " CH8_ERROR_STATUS ,Error status bit for APBX DMA Channel 8" "No effect,Set" bitfld.long 0x04 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "No effect,Set" textline " " bitfld.long 0x04 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "No effect,Set" bitfld.long 0x04 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "No effect,Set" textline " " bitfld.long 0x04 19. " CH3_ERROR_STATUS ,Error status bit for APBX DMA Channel 3" "No effect,Set" bitfld.long 0x04 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "No effect,Set" textline " " bitfld.long 0x04 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "No effect,Set" bitfld.long 0x04 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "No effect,Set" textline " " bitfld.long 0x04 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 10" "No effect,Set" bitfld.long 0x04 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 9" "No effect,Set" textline " " bitfld.long 0x04 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 8" "No effect,Set" bitfld.long 0x04 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "No effect,Set" textline " " bitfld.long 0x04 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "No effect,Set" bitfld.long 0x04 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "No effect,Set" textline " " bitfld.long 0x04 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 3" "No effect,Set" bitfld.long 0x04 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "No effect,Set" textline " " bitfld.long 0x04 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "No effect,Set" bitfld.long 0x04 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "No effect,Set" line.long 0x08 "HW_APBX_CTRL2,AHB to APBX Bridge Control and Status Register 2" bitfld.long 0x08 26. " CH10_ERROR_STATUS ,Error status bit for APBX DMA Channel 10" "No effect,Cleared" bitfld.long 0x08 25. " CH9_ERROR_STATUS ,Error status bit for APBX DMA Channel 9" "No effect,Cleared" textline " " bitfld.long 0x08 24. " CH8_ERROR_STATUS ,Error status bit for APBX DMA Channel 8" "No effect,Cleared" bitfld.long 0x08 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "No effect,Cleared" textline " " bitfld.long 0x08 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "No effect,Cleared" bitfld.long 0x08 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "No effect,Cleared" textline " " bitfld.long 0x08 19. " CH3_ERROR_STATUS ,Error status bit for APBX DMA Channel 3" "No effect,Cleared" bitfld.long 0x08 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "No effect,Cleared" textline " " bitfld.long 0x08 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "No effect,Cleared" bitfld.long 0x08 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "No effect,Cleared" textline " " bitfld.long 0x08 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 10" "No effect,Cleared" bitfld.long 0x08 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 9" "No effect,Cleared" textline " " bitfld.long 0x08 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 8" "No effect,Cleared" bitfld.long 0x08 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "No effect,Cleared" textline " " bitfld.long 0x08 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "No effect,Cleared" bitfld.long 0x08 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "No effect,Cleared" textline " " bitfld.long 0x08 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 3" "No effect,Cleared" bitfld.long 0x08 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "No effect,Cleared" textline " " bitfld.long 0x08 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "No effect,Cleared" bitfld.long 0x08 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "No effect,Cleared" line.long 0x0c "HW_APBX_CTRL2,AHB to APBX Bridge Control and Status Register 2" bitfld.long 0x0c 26. " CH10_ERROR_STATUS ,Error status bit for APBX DMA Channel 10" "Not toggle,Toggle" bitfld.long 0x0c 25. " CH9_ERROR_STATUS ,Error status bit for APBX DMA Channel 9" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " CH8_ERROR_STATUS ,Error status bit for APBX DMA Channel 8" "Not toggle,Toggle" bitfld.long 0x0c 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "Not toggle,Toggle" bitfld.long 0x0c 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " CH3_ERROR_STATUS ,Error status bit for APBX DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x0c 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x0c 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 10" "Not toggle,Toggle" bitfld.long 0x0c 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 9" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 8" "Not toggle,Toggle" bitfld.long 0x0c 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "Not toggle,Toggle" bitfld.long 0x0c 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x0c 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x0c 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "Not toggle,Toggle" group.long 0x30++0x0f line.long 0x00 "HW_APBX_CHANNEL_CTRL,AHB to APBX Bridge Channel Register" bitfld.long 0x00 31. " RESET_CHANNEL[15] ,Channel 15 Reset State" "No reset,Reset" bitfld.long 0x00 30. " RESET_CHANNEL[14] ,Channel 14 Reset State" "No reset,Reset" textline " " bitfld.long 0x00 29. " RESET_CHANNEL[13] ,Channel 13 Reset State" "No reset,Reset" bitfld.long 0x00 28. " RESET_CHANNEL[12] ,Channel 12 Reset State" "No reset,Reset" textline " " bitfld.long 0x00 27. " RESET_CHANNEL[11] ,Channel 11 Reset State" "No reset,Reset" bitfld.long 0x00 26. " RESET_CHANNEL[10] ,Channel 10 Reset State" "No reset,Reset" textline " " bitfld.long 0x00 25. " RESET_CHANNEL[9] ,Channel 9 Reset State" "No reset,Reset" bitfld.long 0x00 24. " RESET_CHANNEL[8] ,Channel 8 Reset State" "No reset,Reset" textline " " bitfld.long 0x00 23. " RESET_CHANNEL[7] ,Channel 7 Reset State" "No reset,Reset" bitfld.long 0x00 22. " RESET_CHANNEL[6] ,Channel 6 Reset State" "No reset,Reset" textline " " bitfld.long 0x00 21. " RESET_CHANNEL[5] ,Channel 5 Reset State" "No reset,Reset" bitfld.long 0x00 20. " RESET_CHANNEL[4] ,Channel 4 Reset State" "No reset,Reset" textline " " bitfld.long 0x00 19. " RESET_CHANNEL[3] ,Channel 3 Reset State" "No reset,Reset" bitfld.long 0x00 18. " RESET_CHANNEL[2] ,Channel 2 Reset State" "No reset,Reset" textline " " bitfld.long 0x00 17. " RESET_CHANNEL[1] ,Channel 1 Reset State" "No reset,Reset" bitfld.long 0x00 16. " RESET_CHANNEL[0] ,Channel 0 Reset State" "No reset,Reset" textline " " bitfld.long 0x00 15. " FREEZE_CHANNEL[15] ,Channel 15 Freeze State" "Not frozen,Frozen" bitfld.long 0x00 14. " FREEZE_CHANNEL[14] ,Channel 14 Freeze State" "Not frozen,Frozen" textline " " bitfld.long 0x00 13. " FREEZE_CHANNEL[13] ,Channel 13 Freeze State" "Not frozen,Frozen" bitfld.long 0x00 12. " FREEZE_CHANNEL[12] ,Channel 12 Freeze State" "Not frozen,Frozen" textline " " bitfld.long 0x00 11. " FREEZE_CHANNEL[11] ,Channel 11 Freeze State" "Not frozen,Frozen" bitfld.long 0x00 10. " FREEZE_CHANNEL[10] ,Channel 10 Freeze State" "Not frozen,Frozen" textline " " bitfld.long 0x00 9. " FREEZE_CHANNEL[9] ,Channel 9 Freeze State" "Not frozen,Frozen" bitfld.long 0x00 8. " FREEZE_CHANNEL[8] ,Channel 8 Freeze State" "Not frozen,Frozen" textline " " bitfld.long 0x00 7. " FREEZE_CHANNEL[7] ,Channel 7 Freeze State" "Not frozen,Frozen" bitfld.long 0x00 6. " FREEZE_CHANNEL[6] ,Channel 6 Freeze State" "Not frozen,Frozen" textline " " bitfld.long 0x00 5. " FREEZE_CHANNEL[5] ,Channel 5 Freeze State" "Not frozen,Frozen" bitfld.long 0x00 4. " FREEZE_CHANNEL[4] ,Channel 4 Freeze State" "Not frozen,Frozen" textline " " bitfld.long 0x00 3. " FREEZE_CHANNEL[3] ,Channel 3 Freeze State" "Not frozen,Frozen" bitfld.long 0x00 2. " FREEZE_CHANNEL[2] ,Channel 2 Freeze State" "Not frozen,Frozen" textline " " bitfld.long 0x00 1. " FREEZE_CHANNEL[1] ,Channel 1 Freeze State" "Not frozen,Frozen" bitfld.long 0x00 0. " FREEZE_CHANNEL[0] ,Channel 0 Freeze State" "Not frozen,Frozen" line.long 0x04 "HW_APBX_CHANNEL_CTRL_SET,AHB to APBX Bridge Channel Set Register" bitfld.long 0x04 31. " RESET_CHANNEL[15] ,Channel 15 Reset State" "No effect,Set" bitfld.long 0x04 30. " RESET_CHANNEL[14] ,Channel 14 Reset State" "No effect,Set" textline " " bitfld.long 0x04 29. " RESET_CHANNEL[13] ,Channel 13 Reset State" "No effect,Set" bitfld.long 0x04 28. " RESET_CHANNEL[12] ,Channel 12 Reset State" "No effect,Set" textline " " bitfld.long 0x04 27. " RESET_CHANNEL[11] ,Channel 11 Reset State" "No effect,Set" bitfld.long 0x04 26. " RESET_CHANNEL[10] ,Channel 10 Reset State" "No effect,Set" textline " " bitfld.long 0x04 25. " RESET_CHANNEL[9] ,Channel 9 Reset State" "No effect,Set" bitfld.long 0x04 24. " RESET_CHANNEL[8] ,Channel 8 Reset State" "No effect,Set" textline " " bitfld.long 0x04 23. " RESET_CHANNEL[7] ,Channel 7 Reset State" "No effect,Set" bitfld.long 0x04 22. " RESET_CHANNEL[6] ,Channel 6 Reset State" "No effect,Set" textline " " bitfld.long 0x04 21. " RESET_CHANNEL[5] ,Channel 5 Reset State" "No effect,Set" bitfld.long 0x04 20. " RESET_CHANNEL[4] ,Channel 4 Reset State" "No effect,Set" textline " " bitfld.long 0x04 19. " RESET_CHANNEL[3] ,Channel 3 Reset State" "No effect,Set" bitfld.long 0x04 18. " RESET_CHANNEL[2] ,Channel 2 Reset State" "No effect,Set" textline " " bitfld.long 0x04 17. " RESET_CHANNEL[1] ,Channel 1 Reset State" "No effect,Set" bitfld.long 0x04 16. " RESET_CHANNEL[0] ,Channel 0 Reset State" "No effect,Set" textline " " bitfld.long 0x04 15. " FREEZE_CHANNEL[15] ,Channel 15 Freeze State" "No effect,Set" bitfld.long 0x04 14. " FREEZE_CHANNEL[14] ,Channel 14 Freeze State" "No effect,Set" textline " " bitfld.long 0x04 13. " FREEZE_CHANNEL[13] ,Channel 13 Freeze State" "No effect,Set" bitfld.long 0x04 12. " FREEZE_CHANNEL[12] ,Channel 12 Freeze State" "No effect,Set" textline " " bitfld.long 0x04 11. " FREEZE_CHANNEL[11] ,Channel 11 Freeze State" "No effect,Set" bitfld.long 0x04 10. " FREEZE_CHANNEL[10] ,Channel 10 Freeze State" "No effect,Set" textline " " bitfld.long 0x04 9. " FREEZE_CHANNEL[9] ,Channel 9 Freeze State" "No effect,Set" bitfld.long 0x04 8. " FREEZE_CHANNEL[8] ,Channel 8 Freeze State" "No effect,Set" textline " " bitfld.long 0x04 7. " FREEZE_CHANNEL[7] ,Channel 7 Freeze State" "No effect,Set" bitfld.long 0x04 6. " FREEZE_CHANNEL[6] ,Channel 6 Freeze State" "No effect,Set" textline " " bitfld.long 0x04 5. " FREEZE_CHANNEL[5] ,Channel 5 Freeze State" "No effect,Set" bitfld.long 0x04 4. " FREEZE_CHANNEL[4] ,Channel 4 Freeze State" "No effect,Set" textline " " bitfld.long 0x04 3. " FREEZE_CHANNEL[3] ,Channel 3 Freeze State" "No effect,Set" bitfld.long 0x04 2. " FREEZE_CHANNEL[2] ,Channel 2 Freeze State" "No effect,Set" textline " " bitfld.long 0x04 1. " FREEZE_CHANNEL[1] ,Channel 1 Freeze State" "No effect,Set" bitfld.long 0x04 0. " FREEZE_CHANNEL[0] ,Channel 0 Freeze State" "No effect,Set" line.long 0x08 "HW_APBX_CHANNEL_CTRL_CLR,AHB to APBX Bridge Channel Clear Register" bitfld.long 0x08 31. " RESET_CHANNEL[15] ,Channel 15 Reset State" "No effect,Cleared" bitfld.long 0x08 30. " RESET_CHANNEL[14] ,Channel 14 Reset State" "No effect,Cleared" textline " " bitfld.long 0x08 29. " RESET_CHANNEL[13] ,Channel 13 Reset State" "No effect,Cleared" bitfld.long 0x08 28. " RESET_CHANNEL[12] ,Channel 12 Reset State" "No effect,Cleared" textline " " bitfld.long 0x08 27. " RESET_CHANNEL[11] ,Channel 11 Reset State" "No effect,Cleared" bitfld.long 0x08 26. " RESET_CHANNEL[10] ,Channel 10 Reset State" "No effect,Cleared" textline " " bitfld.long 0x08 25. " RESET_CHANNEL[9] ,Channel 9 Reset State" "No effect,Cleared" bitfld.long 0x08 24. " RESET_CHANNEL[8] ,Channel 8 Reset State" "No effect,Cleared" textline " " bitfld.long 0x08 23. " RESET_CHANNEL[7] ,Channel 7 Reset State" "No effect,Cleared" bitfld.long 0x08 22. " RESET_CHANNEL[6] ,Channel 6 Reset State" "No effect,Cleared" textline " " bitfld.long 0x08 21. " RESET_CHANNEL[5] ,Channel 5 Reset State" "No effect,Cleared" bitfld.long 0x08 20. " RESET_CHANNEL[4] ,Channel 4 Reset State" "No effect,Cleared" textline " " bitfld.long 0x08 19. " RESET_CHANNEL[3] ,Channel 3 Reset State" "No effect,Cleared" bitfld.long 0x08 18. " RESET_CHANNEL[2] ,Channel 2 Reset State" "No effect,Cleared" textline " " bitfld.long 0x08 17. " RESET_CHANNEL[1] ,Channel 1 Reset State" "No effect,Cleared" bitfld.long 0x08 16. " RESET_CHANNEL[0] ,Channel 0 Reset State" "No effect,Cleared" textline " " bitfld.long 0x08 15. " FREEZE_CHANNEL[15] ,Channel 15 Freeze State" "No effect,Cleared" bitfld.long 0x08 14. " FREEZE_CHANNEL[14] ,Channel 14 Freeze State" "No effect,Cleared" textline " " bitfld.long 0x08 13. " FREEZE_CHANNEL[13] ,Channel 13 Freeze State" "No effect,Cleared" bitfld.long 0x08 12. " FREEZE_CHANNEL[12] ,Channel 12 Freeze State" "No effect,Cleared" textline " " bitfld.long 0x08 11. " FREEZE_CHANNEL[11] ,Channel 11 Freeze State" "No effect,Cleared" bitfld.long 0x08 10. " FREEZE_CHANNEL[10] ,Channel 10 Freeze State" "No effect,Cleared" textline " " bitfld.long 0x08 9. " FREEZE_CHANNEL[9] ,Channel 9 Freeze State" "No effect,Cleared" bitfld.long 0x08 8. " FREEZE_CHANNEL[8] ,Channel 8 Freeze State" "No effect,Cleared" textline " " bitfld.long 0x08 7. " FREEZE_CHANNEL[7] ,Channel 7 Freeze State" "No effect,Cleared" bitfld.long 0x08 6. " FREEZE_CHANNEL[6] ,Channel 6 Freeze State" "No effect,Cleared" textline " " bitfld.long 0x08 5. " FREEZE_CHANNEL[5] ,Channel 5 Freeze State" "No effect,Cleared" bitfld.long 0x08 4. " FREEZE_CHANNEL[4] ,Channel 4 Freeze State" "No effect,Cleared" textline " " bitfld.long 0x08 3. " FREEZE_CHANNEL[3] ,Channel 3 Freeze State" "No effect,Cleared" bitfld.long 0x08 2. " FREEZE_CHANNEL[2] ,Channel 2 Freeze State" "No effect,Cleared" textline " " bitfld.long 0x08 1. " FREEZE_CHANNEL[1] ,Channel 1 Freeze State" "No effect,Cleared" bitfld.long 0x08 0. " FREEZE_CHANNEL[0] ,Channel 0 Freeze State" "No effect,Cleared" line.long 0x0c "HW_APBX_CHANNEL_CTRL_TOG,AHB to APBX Bridge Channel Toggle Register" bitfld.long 0x0c 31. " RESET_CHANNEL[15] ,Channel 15 Reset State" "Not toggle,Toggle" bitfld.long 0x0c 30. " RESET_CHANNEL[14] ,Channel 14 Reset State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESET_CHANNEL[13] ,Channel 13 Reset State" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESET_CHANNEL[12] ,Channel 12 Reset State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESET_CHANNEL[11] ,Channel 11 Reset State" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESET_CHANNEL[10] ,Channel 10 Reset State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " RESET_CHANNEL[9] ,Channel 9 Reset State" "Not toggle,Toggle" bitfld.long 0x0c 24. " RESET_CHANNEL[8] ,Channel 8 Reset State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " RESET_CHANNEL[7] ,Channel 7 Reset State" "Not toggle,Toggle" bitfld.long 0x0c 22. " RESET_CHANNEL[6] ,Channel 6 Reset State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " RESET_CHANNEL[5] ,Channel 5 Reset State" "Not toggle,Toggle" bitfld.long 0x0c 20. " RESET_CHANNEL[4] ,Channel 4 Reset State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " RESET_CHANNEL[3] ,Channel 3 Reset State" "Not toggle,Toggle" bitfld.long 0x0c 18. " RESET_CHANNEL[2] ,Channel 2 Reset State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " RESET_CHANNEL[1] ,Channel 1 Reset State" "Not toggle,Toggle" bitfld.long 0x0c 16. " RESET_CHANNEL[0] ,Channel 0 Reset State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FREEZE_CHANNEL[15] ,Channel 15 Freeze State" "Not toggle,Toggle" bitfld.long 0x0c 14. " FREEZE_CHANNEL[14] ,Channel 14 Freeze State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " FREEZE_CHANNEL[13] ,Channel 13 Freeze State" "Not toggle,Toggle" bitfld.long 0x0c 12. " FREEZE_CHANNEL[12] ,Channel 12 Freeze State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " FREEZE_CHANNEL[11] ,Channel 11 Freeze State" "Not toggle,Toggle" bitfld.long 0x0c 10. " FREEZE_CHANNEL[10] ,Channel 10 Freeze State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " FREEZE_CHANNEL[9] ,Channel 9 Freeze State" "Not toggle,Toggle" bitfld.long 0x0c 8. " FREEZE_CHANNEL[8] ,Channel 8 Freeze State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " FREEZE_CHANNEL[7] ,Channel 7 Freeze State" "Not toggle,Toggle" bitfld.long 0x0c 6. " FREEZE_CHANNEL[6] ,Channel 6 Freeze State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " FREEZE_CHANNEL[5] ,Channel 5 Freeze State" "Not toggle,Toggle" bitfld.long 0x0c 4. " FREEZE_CHANNEL[4] ,Channel 4 Freeze State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " FREEZE_CHANNEL[3] ,Channel 3 Freeze State" "Not toggle,Toggle" bitfld.long 0x0c 2. " FREEZE_CHANNEL[2] ,Channel 2 Freeze State" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " FREEZE_CHANNEL[1] ,Channel 1 Freeze State" "Not toggle,Toggle" bitfld.long 0x0c 0. " FREEZE_CHANNEL[0] ,Channel 0 Freeze State" "Not toggle,Toggle" hgroup.long 0x40++0x03 hide.long 0x00 "HW_APBX_DEVSEL,AHB to APBX DMA Device Assignment Register" rgroup.long 0x100++0x03 line.long 0x00 "HW_APBX_CH0_CURCMDAR,APBX DMA Channel 0 Current Command Address Register" group.long (0x100+0x10)++0x03 line.long 0x00 "HW_APBX_CH0_NXTCMDAR,APBX DMA Channel 0 Next Command Address Register" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "HW_APBX_CH0_CMD,APBX DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "HW_APBX_CH0_BAR,APBX DMA Channel 0 Buffer Address Register" in group.long (0x100+0x40)++0x03 line.long 0x00 "HW_APBX_CH0_SEMA,APBX DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "HW_APBX_CH0_DEBUG1,AHB to APBX DMA Channel 0 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x100+0x60)++0x03 line.long 0x00 "HW_APBX_CH0_DEBUG2,AHB to APBX DMA Channel 0 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x170++0x03 line.long 0x00 "HW_APBX_CH1_CURCMDAR,APBX DMA Channel 1 Current Command Address Register" group.long (0x170+0x10)++0x03 line.long 0x00 "HW_APBX_CH1_NXTCMDAR,APBX DMA Channel 1 Next Command Address Register" rgroup.long (0x170+0x20)++0x03 line.long 0x00 "HW_APBX_CH1_CMD,APBX DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x170+0x30)++0x03 hide.long 0x00 "HW_APBX_CH1_BAR,APBX DMA Channel 1 Buffer Address Register" in group.long (0x170+0x40)++0x03 line.long 0x00 "HW_APBX_CH1_SEMA,APBX DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "HW_APBX_CH1_DEBUG1,AHB to APBX DMA Channel 1 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x170+0x60)++0x03 line.long 0x00 "HW_APBX_CH1_DEBUG2,AHB to APBX DMA Channel 1 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x1E0++0x03 line.long 0x00 "HW_APBX_CH2_CURCMDAR,APBX DMA Channel 2 Current Command Address Register" group.long (0x1E0+0x10)++0x03 line.long 0x00 "HW_APBX_CH2_NXTCMDAR,APBX DMA Channel 2 Next Command Address Register" rgroup.long (0x1E0+0x20)++0x03 line.long 0x00 "HW_APBX_CH2_CMD,APBX DMA Channel 2 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x1E0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH2_BAR,APBX DMA Channel 2 Buffer Address Register" in group.long (0x1E0+0x40)++0x03 line.long 0x00 "HW_APBX_CH2_SEMA,APBX DMA Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "HW_APBX_CH2_DEBUG1,AHB to APBX DMA Channel 2 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "HW_APBX_CH2_DEBUG2,AHB to APBX DMA Channel 2 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x250++0x03 line.long 0x00 "HW_APBX_CH3_CURCMDAR,APBX DMA Channel 3 Current Command Address Register" group.long (0x250+0x10)++0x03 line.long 0x00 "HW_APBX_CH3_NXTCMDAR,APBX DMA Channel 3 Next Command Address Register" rgroup.long (0x250+0x20)++0x03 line.long 0x00 "HW_APBX_CH3_CMD,APBX DMA Channel 3 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x250+0x30)++0x03 hide.long 0x00 "HW_APBX_CH3_BAR,APBX DMA Channel 3 Buffer Address Register" in group.long (0x250+0x40)++0x03 line.long 0x00 "HW_APBX_CH3_SEMA,APBX DMA Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x250+0x50)++0x03 line.long 0x00 "HW_APBX_CH3_DEBUG1,AHB to APBX DMA Channel 3 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x250+0x60)++0x03 line.long 0x00 "HW_APBX_CH3_DEBUG2,AHB to APBX DMA Channel 3 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x2C0++0x03 line.long 0x00 "HW_APBX_CH4_CURCMDAR,APBX DMA Channel 4 Current Command Address Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "HW_APBX_CH4_NXTCMDAR,APBX DMA Channel 4 Next Command Address Register" rgroup.long (0x2C0+0x20)++0x03 line.long 0x00 "HW_APBX_CH4_CMD,APBX DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x2C0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH4_BAR,APBX DMA Channel 4 Buffer Address Register" in group.long (0x2C0+0x40)++0x03 line.long 0x00 "HW_APBX_CH4_SEMA,APBX DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "HW_APBX_CH4_DEBUG1,AHB to APBX DMA Channel 4 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "HW_APBX_CH4_DEBUG2,AHB to APBX DMA Channel 4 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x3A0++0x03 line.long 0x00 "HW_APBX_CH6_CURCMDAR,APBX DMA Channel 6 Current Command Address Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "HW_APBX_CH6_NXTCMDAR,APBX DMA Channel 6 Next Command Address Register" rgroup.long (0x3A0+0x20)++0x03 line.long 0x00 "HW_APBX_CH6_CMD,APBX DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x3A0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH6_BAR,APBX DMA Channel 6 Buffer Address Register" in group.long (0x3A0+0x40)++0x03 line.long 0x00 "HW_APBX_CH6_SEMA,APBX DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "HW_APBX_CH6_DEBUG1,AHB to APBX DMA Channel 6 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "HW_APBX_CH6_DEBUG2,AHB to APBX DMA Channel 6 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x410++0x03 line.long 0x00 "HW_APBX_CH7_CURCMDAR,APBX DMA Channel 7 Current Command Address Register" group.long (0x410+0x10)++0x03 line.long 0x00 "HW_APBX_CH7_NXTCMDAR,APBX DMA Channel 7 Next Command Address Register" rgroup.long (0x410+0x20)++0x03 line.long 0x00 "HW_APBX_CH7_CMD,APBX DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x410+0x30)++0x03 hide.long 0x00 "HW_APBX_CH7_BAR,APBX DMA Channel 7 Buffer Address Register" in group.long (0x410+0x40)++0x03 line.long 0x00 "HW_APBX_CH7_SEMA,APBX DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "HW_APBX_CH7_DEBUG1,AHB to APBX DMA Channel 7 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x410+0x60)++0x03 line.long 0x00 "HW_APBX_CH7_DEBUG2,AHB to APBX DMA Channel 7 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x480++0x03 line.long 0x00 "HW_APBX_CH8_CURCMDAR,APBX DMA Channel 8 Current Command Address Register" group.long (0x480+0x10)++0x03 line.long 0x00 "HW_APBX_CH8_NXTCMDAR,APBX DMA Channel 8 Next Command Address Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "HW_APBX_CH8_CMD,APBX DMA Channel 8 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x480+0x30)++0x03 hide.long 0x00 "HW_APBX_CH8_BAR,APBX DMA Channel 8 Buffer Address Register" in group.long (0x480+0x40)++0x03 line.long 0x00 "HW_APBX_CH8_SEMA,APBX DMA Channel 8 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "HW_APBX_CH8_DEBUG1,AHB to APBX DMA Channel 8 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x480+0x60)++0x03 line.long 0x00 "HW_APBX_CH8_DEBUG2,AHB to APBX DMA Channel 8 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x4F0++0x03 line.long 0x00 "HW_APBX_CH9_CURCMDAR,APBX DMA Channel 9 Current Command Address Register" group.long (0x4F0+0x10)++0x03 line.long 0x00 "HW_APBX_CH9_NXTCMDAR,APBX DMA Channel 9 Next Command Address Register" rgroup.long (0x4F0+0x20)++0x03 line.long 0x00 "HW_APBX_CH9_CMD,APBX DMA Channel 9 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x4F0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH9_BAR,APBX DMA Channel 9 Buffer Address Register" in group.long (0x4F0+0x40)++0x03 line.long 0x00 "HW_APBX_CH9_SEMA,APBX DMA Channel 9 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "HW_APBX_CH9_DEBUG1,AHB to APBX DMA Channel 9 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "HW_APBX_CH9_DEBUG2,AHB to APBX DMA Channel 9 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" rgroup.long 0x560++0x03 line.long 0x00 "HW_APBX_CH10_CURCMDAR,APBX DMA Channel 10 Current Command Address Register" group.long (0x560+0x10)++0x03 line.long 0x00 "HW_APBX_CH10_NXTCMDAR,APBX DMA Channel 10 Next Command Address Register" rgroup.long (0x560+0x20)++0x03 line.long 0x00 "HW_APBX_CH10_CMD,APBX DMA Channel 10 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,number of bytes to transfer to or from the appropriate PIO register in the ADC device HW_AUDIOIN_DATA" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x560+0x30)++0x03 hide.long 0x00 "HW_APBX_CH10_BAR,APBX DMA Channel 10 Buffer Address Register" in group.long (0x560+0x40)++0x03 line.long 0x00 "HW_APBX_CH10_SEMA,APBX DMA Channel 10 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "HW_APBX_CH10_DEBUG1,AHB to APBX DMA Channel 10 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x560+0x60)++0x03 line.long 0x00 "HW_APBX_CH10_DEBUG2,AHB to APBX DMA Channel 10 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" group.long 0x800++0x03 line.long 0x00 "HW_APBX_VERSION,APBX Bridge Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree.open "EMI (External Memory Interface)" tree "EMI Control Registers" base asd:0x80020000 width 17. group.long 0x00++0x0f line.long 0x00 "HW_EMI_CTRL,EMI Control Register" bitfld.long 0x00 31. " SFTRST ,Reset EMI register block" "No reset,Reset" bitfld.long 0x00 29. " TRAP_SR ,Self-Refresh mode" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " TRAP_INIT ,DRAM controller Initialization " "Not init,Init" bitfld.long 0x00 26.--27. " AXI_DEPTH ,Number of commands allowed in the AXI port queue" "1,2,3,4" textline " " bitfld.long 0x00 25. " DLL_SHIFT_RESET ,When set, forces the DRAM controller DLL startpoint shift logic into a reset state" "Not forced,Forced" bitfld.long 0x00 24. " DLL_RESET ,When set, forces the DRAM controller into a reset state" "Not forced,Forced" textline " " bitfld.long 0x00 22.--23. " ARB_MODE ,arbitration mode for the DRAM port controller" "TIMESTAMP,WRITE_HYBRID,PORT_PRIORITY,?..." bitfld.long 0x00 16.--20. " PORT_PRIORITY_ORDER ,priority order of the 4 arbitrated ports" "PORT0123(highest),PORT0312,PORT0231,PORT0321,PORT0213,PORT0132,PORT1023,PORT1302,PORT1230,PORT1320,PORT1203,PORT1032,PORT2013,PORT2301,PORT2130,PORT2310,PORT2103,PORT2031,PORT3012,PORT3201,PORT3120,PORT3210,PORT3102,PORT3021,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230(lowest)" textline " " bitfld.long 0x00 12.--14. " PRIORITY_WRITE_ITER ,specifies how many times to iterate through the high-priority write phase" "1,2,3,4,5,?..." bitfld.long 0x00 10. " HIGH_PRIORITY_WRITE[2] ,EMI AXI0 high write priority" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " HIGH_PRIORITY_WRITE[1] ,EMI AHB2 high write priority" "Disabled,Enabled" bitfld.long 0x00 8. " HIGH_PRIORITY_WRITE[0] ,EMI AHB3 high write priority" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " MEM_WIDTH ,Memory width" "8 bit,16 bit" bitfld.long 0x00 4. " RESET_OUT ,Reset output state" "Low,High" line.long 0x04 "HW_EMI_CTRL_SET,EMI Control Set Register" bitfld.long 0x04 31. " SFTRST ,Reset EMI register block" "No effect,Set" bitfld.long 0x04 29. " TRAP_SR ,Self-Refresh mode" "No effect,Set" textline " " bitfld.long 0x04 28. " TRAP_INIT ,DRAM controller Initialization " "No effect,Set" bitfld.long 0x04 26.--27. " AXI_DEPTH ,Number of commands allowed in the AXI port queue" "1,2,3,4" textline " " bitfld.long 0x04 25. " DLL_SHIFT_RESET ,When set, forces the DRAM controller DLL startpoint shift logic into a reset state" "No effect,Set" bitfld.long 0x04 24. " DLL_RESET ,When set, forces the DRAM controller into a reset state" "No effect,Set" textline " " bitfld.long 0x04 22.--23. " ARB_MODE ,arbitration mode for the DRAM port controller" "TIMESTAMP,WRITE_HYBRID,PORT_PRIORITY,?..." bitfld.long 0x04 16.--20. " PORT_PRIORITY_ORDER ,priority order of the 4 arbitrated ports" "PORT0123(highest),PORT0312,PORT0231,PORT0321,PORT0213,PORT0132,PORT1023,PORT1302,PORT1230,PORT1320,PORT1203,PORT1032,PORT2013,PORT2301,PORT2130,PORT2310,PORT2103,PORT2031,PORT3012,PORT3201,PORT3120,PORT3210,PORT3102,PORT3021,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230(lowest)" textline " " bitfld.long 0x04 12.--14. " PRIORITY_WRITE_ITER ,specifies how many times to iterate through the high-priority write phase" "1,2,3,4,5,?..." bitfld.long 0x04 10. " HIGH_PRIORITY_WRITE[2] ,EMI AXI0 high write priority" "No effect,Set" textline " " bitfld.long 0x04 9. " HIGH_PRIORITY_WRITE[1] ,EMI AHB2 high write priority" "No effect,Set" bitfld.long 0x04 8. " HIGH_PRIORITY_WRITE[0] ,EMI AHB3 high write priority" "No effect,Set" textline " " bitfld.long 0x04 6. " MEM_WIDTH ,Memory width" "No effect,Set" bitfld.long 0x04 4. " RESET_OUT ,Reset output state" "No effect,Set" line.long 0x08 "HW_EMI_CTRL_CLR,EMI Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Reset EMI register block" "No effect,Cleared" bitfld.long 0x08 29. " TRAP_SR ,Self-Refresh mode" "No effect,Cleared" textline " " bitfld.long 0x08 28. " TRAP_INIT ,DRAM controller Initialization " "No effect,Cleared" bitfld.long 0x08 26.--27. " AXI_DEPTH ,Number of commands allowed in the AXI port queue" "1,2,3,4" textline " " bitfld.long 0x08 25. " DLL_SHIFT_RESET ,When set, forces the DRAM controller DLL startpoint shift logic into a reset state" "No effect,Cleared" bitfld.long 0x08 24. " DLL_RESET ,When set, forces the DRAM controller into a reset state" "No effect,Cleared" textline " " bitfld.long 0x08 22.--23. " ARB_MODE ,arbitration mode for the DRAM port controller" "TIMESTAMP,WRITE_HYBRID,PORT_PRIORITY,?..." bitfld.long 0x08 16.--20. " PORT_PRIORITY_ORDER ,priority order of the 4 arbitrated ports" "PORT0123(highest),PORT0312,PORT0231,PORT0321,PORT0213,PORT0132,PORT1023,PORT1302,PORT1230,PORT1320,PORT1203,PORT1032,PORT2013,PORT2301,PORT2130,PORT2310,PORT2103,PORT2031,PORT3012,PORT3201,PORT3120,PORT3210,PORT3102,PORT3021,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230(lowest)" textline " " bitfld.long 0x08 12.--14. " PRIORITY_WRITE_ITER ,specifies how many times to iterate through the high-priority write phase" "1,2,3,4,5,?..." bitfld.long 0x08 10. " HIGH_PRIORITY_WRITE[2] ,EMI AXI0 high write priority" "No effect,Cleared" textline " " bitfld.long 0x08 9. " HIGH_PRIORITY_WRITE[1] ,EMI AHB2 high write priority" "No effect,Cleared" bitfld.long 0x08 8. " HIGH_PRIORITY_WRITE[0] ,EMI AHB3 high write priority" "No effect,Cleared" textline " " bitfld.long 0x08 6. " MEM_WIDTH ,Memory width" "No effect,Cleared" bitfld.long 0x08 4. " RESET_OUT ,Reset output state" "No effect,Cleared" line.long 0x0c "HW_EMI_CTRL_TOG,EMI Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Reset EMI register block" "Not toggle,Toggle" bitfld.long 0x0c 29. " TRAP_SR ,Self-Refresh mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 28. " TRAP_INIT ,DRAM controller Initialization " "Not toggle,Toggle" bitfld.long 0x0c 26.--27. " AXI_DEPTH ,Number of commands allowed in the AXI port queue" "1,2,3,4" textline " " bitfld.long 0x0c 25. " DLL_SHIFT_RESET ,When set, forces the DRAM controller DLL startpoint shift logic into a reset state" "Not toggle,Toggle" bitfld.long 0x0c 24. " DLL_RESET ,When set, forces the DRAM controller into a reset state" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22.--23. " ARB_MODE ,arbitration mode for the DRAM port controller" "TIMESTAMP,WRITE_HYBRID,PORT_PRIORITY,?..." bitfld.long 0x0c 16.--20. " PORT_PRIORITY_ORDER ,priority order of the 4 arbitrated ports" "PORT0123(highest),PORT0312,PORT0231,PORT0321,PORT0213,PORT0132,PORT1023,PORT1302,PORT1230,PORT1320,PORT1203,PORT1032,PORT2013,PORT2301,PORT2130,PORT2310,PORT2103,PORT2031,PORT3012,PORT3201,PORT3120,PORT3210,PORT3102,PORT3021,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230,PORT1230(lowest)" textline " " bitfld.long 0x0c 12.--14. " PRIORITY_WRITE_ITER ,specifies how many times to iterate through the high-priority write phase" "1,2,3,4,5,?..." bitfld.long 0x0c 10. " HIGH_PRIORITY_WRITE[2] ,EMI AXI0 high write priority" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " HIGH_PRIORITY_WRITE[1] ,EMI AHB2 high write priority" "Not toggle,Toggle" bitfld.long 0x0c 8. " HIGH_PRIORITY_WRITE[0] ,EMI AHB3 high write priority" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " MEM_WIDTH ,Memory width" "Not toggle,Toggle" bitfld.long 0x0c 4. " RESET_OUT ,Reset output state" "Not toggle,Toggle" group.long 0xf0++0x03 line.long 0x00 "HW_EMI_VERSION,EMI Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--21. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "DRAM Control Registers" base asd:0x800E0000 width 15. group.long 0x00++0x57 line.long 0x00 "HW_DRAM_CTL00,DRAM Control Register 00" bitfld.long 0x00 24. " AHB0_W_PRIORITY ,Priority of write commands from port 0" "Highest,Lowest" bitfld.long 0x00 16. " AHB0_R_PRIORITY ,Priority of read commands from port 0" "Highest,Lowest" textline " " bitfld.long 0x00 8. " AHB0_FIFO_TYPE_REG ,Clock domain relativity between port 0 and memory controller core" "Asynchronous,Synchronous" bitfld.long 0x00 0. " ADDR_CMP_EN ,Address collision detection for command queue placement logic" "Disabled,Enabled" line.long 0x04 "HW_DRAM_CTL01,DRAM Control Register 01" bitfld.long 0x04 24. " AHB2_FIFO_TYPE_REG ,Clock domain relativity between port 2 and memory controller core" "Asynchronous,Synchronous" bitfld.long 0x04 16. " AHB1_W_PRIORITY ,Priority of write commands from port 1" "Highest,Lowest" textline " " bitfld.long 0x04 8. " AHB1_R_PRIORITY ,Priority of read commands from port 1" "Highest,Lowest" bitfld.long 0x04 0. " AHB1_FIFO_TYPE_REG ,Clock domain relativity between port 1 and memory controller core" "Asynchronous,Synchronous" line.long 0x08 "HW_DRAM_CTL02,DRAM Control Register 02" bitfld.long 0x08 24. " AHB3_R_PRIORITY ,Priority of read commands from port 3" "Highest,Lowest" bitfld.long 0x08 16. " AHB3_FIFO_TYPE_REG ,Clock domain relativity between port 3 and memory controller core" "Asynchronous,Synchronous" textline " " bitfld.long 0x08 8. " AHB2_W_PRIORITY ,Priority of write commands from port 2" "Highest,Lowest" bitfld.long 0x08 0. " AHB2_R_PRIORITY ,Priority of read commands from port 2" "Highest,Lowest" line.long 0x0c "HW_DRAM_CTL03,DRAM Control Register 03" bitfld.long 0x0C 24. " AUTO_REFRESH_MODE ,Auto-refresh next burst or next command boundary" "DRAM burst boundary,Command boundary" bitfld.long 0x0C 16. " AREFRESH ,Initiate auto-refresh" "No action,Refresh" textline " " bitfld.long 0x0C 8. " AP ,Auto pre-charge mode of controller" "Disabled,Enabled" bitfld.long 0x0C 0. " AHB3_W_PRIORITY ,Priority of write commands from port 3" "Highest,Lowest" line.long 0x10 "HW_DRAM_CTL04,DRAM Control Register 04" bitfld.long 0x10 24. " DLL_BYPASS_MODE ,DLL bypass mode" "Normal,Bypass" bitfld.long 0x10 16. " DLLLOCKREG ,Status of DLL lock coming out of master delay" "Locked,Unlocked" textline " " bitfld.long 0x10 8. " CONCURRENTAP ,Concurrent auto pre-charge enable" "Disabled,Enabled" bitfld.long 0x10 0. " BANK_SPLIT_EN ,Enable bank splitting for command queue placement logic" "Disabled,Enabled" line.long 0x14 "HW_DRAM_CTL05,DRAM Control Register 05" bitfld.long 0x14 24. " INTRPTREADA ,Enables interrupting of a combined read with auto pre-charge command with another read command" "Disabled,Enabled" bitfld.long 0x14 16. " INTRPTAPBURST ,Interrupt an auto pre-charge command with another command" "Disabled,Enabled" textline " " bitfld.long 0x14 8. " FAST_WRITE ,DRAM fast write enable " "Disabled,Enabled" bitfld.long 0x14 0. " EN_LOWPOWER_MODE ,Enable low-power mode in controller" "Disabled,Enabled" line.long 0x18 "HW_DRAM_CTL06,DRAM Control Register 06" bitfld.long 0x18 24. " POWER_DOWN ,Disable clock enable and set DRAMs in power-down state" "Disabled,Enabled" bitfld.long 0x18 16. " PLACEMENT_EN ,Enable placement logic for command queue" "Disabled,Enabled" textline " " bitfld.long 0x18 8. " NO_CMD_INIT ,Disable DRAM commands until TDLL has expired during initialization" "Issue REF/PREF,Not issue" bitfld.long 0x18 0. " INTRPTWRITEA ,Interrupting of a combined write with auto pre-charge command with another read or write command" "Disabled,Enabled" line.long 0x1c "HW_DRAM_CTL07,DRAM Control Register 07" bitfld.long 0x1C 24. " RW_SAME_EN ,Enable read/write grouping for command queue placement logic" "Disabled,Enabled" bitfld.long 0x1C 16. " REG_DIMM_ENABLE ,Enable registered DIMM operation of the controller" "Disabled,Enabled" textline " " bitfld.long 0x1C 8. " RD2RD_TURN ,Enable insertion of addition turn around clock for back to back reads to different css" "Disabled,Enabled" bitfld.long 0x1C 0. " PRIORITY_EN ,Enable priority for command queue placement logic" "Disabled,Enabled" line.long 0x20 "HW_DRAM_CTL08,DRAM Control Register 08" bitfld.long 0x20 24. " TRAS_LOCKOUT ,Allow the controller to execute auto pre-charge commands before TRAS_MIN expires" "Not supported,Supported" bitfld.long 0x20 16. " START ,Initiate command processing in the controller" "Not active,Init active" textline " " bitfld.long 0x20 8. " SREFRESH ,Place DRAMs in self-refresh mode" "Disabled,Enabled" bitfld.long 0x20 0. " SDR_MODE ,Select SDR or DDR mode of the controller" "DDR,SDR" line.long 0x24 "HW_DRAM_CTL09,DRAM Control Register 09" bitfld.long 0x24 24.--25. " OUT_OF_RANGE_TYPE ,Type of command that caused an Out-of-Range interrupt" "0,1,2,3" bitfld.long 0x24 16.--17. " OUT_OF_RANGE_SOURCE_ID ,Source ID out of range interrupt" "0,1,2,3" textline " " bitfld.long 0x24 8. " WRITE_MODEREG ,Write EMRS data to the DRAMs" "Not allowed,Allowed" bitfld.long 0x24 0. " WRITEINTERP ,Allow controller to interrupt a write bursts to the DRAMs with a read command" "Not supported,Supported" line.long 0x28 "HW_DRAM_CTL10,DRAM Control Register 10" bitfld.long 0x28 24.--26. " AGE_COUNT ,Initial value of master aging-rate counter for command aging" "0,1,2,3,4,5,6,7" bitfld.long 0x28 16.--18. " ADDR_PINS ,Difference between number of address pins available and number being used" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x28 8.--9. " TEMRS ,DRAM TEMRS parameter in cycles" "0,1,2,3" bitfld.long 0x28 0.--1. " Q_FULLNESS ,Quantity that determines command queue full" "0,1,2,3" line.long 0x2c "HW_DRAM_CTL11,DRAM Control Register 11" bitfld.long 0x2C 24.--26. " MAX_CS_REG ,Maximum number of chip selects available" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 16.--18. " COMMAND_AGE_COUNT ,Initial value of individual command aging counters for command aging" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x2C 8.--10. " COLUMN_SIZE ,Difference between number of column pins available and number being used" "0,1,2,3,4,5,6,7" bitfld.long 0x2C 0.--2. " CASLAT ,Encoded CAS latency sent to DRAMs during initialization" "0,1,2,3,4,5,6,7" line.long 0x30 "HW_DRAM_CTL12,DRAM Control Register 12" bitfld.long 0x30 24.--26. " TWR_INT ,DRAM TWR parameter in cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x30 16.--18. " TRRD ,DRAM TRRD parameter in cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x30 0.--2. " TCKE ,Minimum CKE pulse width in cycles" "0,1,2,3,4,5,6,7" line.long 0x34 "HW_DRAM_CTL13,DRAM Control Register 13" bitfld.long 0x34 24.--27. " CASLAT_LIN_GATE ,Adjusts data capture gate open by half cycles" "Reserved,Reserved,Reserved,1.5 cycles,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,Reserved,5 cycles,?..." bitfld.long 0x34 16.--19. " CASLAT_LIN ,Sets latency from read command send to data receive from/to controller" "Reserved,Reserved,Reserved,1.5 cycles,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,Reserved,5 cycles,?..." textline " " bitfld.long 0x34 8.--11. " APREBIT ,Location of the auto pre-charge bit in the DRAM address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x34 0.--2. " TWTR ,DRAM TWTR parameter in cycles" "0,1,2,3,4,5,6,7" line.long 0x38 "HW_DRAM_CTL14,DRAM Control Register 14" bitfld.long 0x38 24.--27. " MAX_COL_REG ,Maximum width of column address in DRAMs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x38 19. " LOWPOWER_REFRESH_ENABLE[3] ,Enable refreshes during power down" "Disabled,Enabled" textline " " bitfld.long 0x38 18. " LOWPOWER_REFRESH_ENABLE[2] ,Enable refreshes during power down" "Disabled,Enabled" bitfld.long 0x38 17. " LOWPOWER_REFRESH_ENABLE[1] ,Enable refreshes during power down" "Disabled,Enabled" textline " " bitfld.long 0x38 16. " LOWPOWER_REFRESH_ENABLE[0] ,Enable refreshes during power down" "Disabled,Enabled" bitfld.long 0x38 8.--11. " INITAREF ,Number of auto-refresh commands to execute during DRAM initialization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x38 0.--3. " CS_MAP ,Sets the mask that determines which chip select pins are active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x3c "HW_DRAM_CTL15,DRAM Control Register 15" bitfld.long 0x3C 24.--27. " TRP ,DRAM TRP parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 16.--19. " TDAL ,DRAM TDAL parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x3C 11. " PORT_BUSY[3] ,Per-port indicator that the controller is processing a command" "Not busy,Busy" bitfld.long 0x3C 10. " PORT_BUSY[2] ,Per-port indicator that the controller is processing a command" "Not busy,Busy" textline " " bitfld.long 0x3C 9. " PORT_BUSY[1] ,Per-port indicator that the controller is processing a command" "Not busy,Busy" bitfld.long 0x3C 8. " PORT_BUSY[0] ,Per-port indicator that the controller is processing a command" "Not busy,Busy" textline " " bitfld.long 0x3C 0.--3. " MAX_ROW_REG ,Maximum width of memory address bus ,Maximum width of memory address bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "HW_DRAM_CTL16,DRAM Control Register 16" bitfld.long 0x40 24.--28. " TMRD ,DRAM TMRD parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x40 20. " LOWPOWER_CONTROL[4] ,Controls memory power-down mode" "Disabled,Enabled" textline " " bitfld.long 0x40 19. " LOWPOWER_CONTROL[3] ,Controls memory power-down with memory clock gating mode" "Disabled,Enabled" bitfld.long 0x40 18. " LOWPOWER_CONTROL[2] ,Controls memory self-refresh mode" "Disabled,Enabled" textline " " bitfld.long 0x40 17. " LOWPOWER_CONTROL[1] ,Controls memory self-refresh with memory clock gating mode" "Disabled,Enabled" bitfld.long 0x40 12. " LOWPOWER_AUTO_ENABLE[4] ,Controls memory power-down mode" "Disabled,Enabled" textline " " bitfld.long 0x40 11. " LOWPOWER_AUTO_ENABLE[3] ,Controls memory power-down with memory clock gating mode" "Disabled,Enabled" bitfld.long 0x40 3. " INT_ACK[3] ,Clear mask of the INT_STATUS bit field" "No acknowledge,Acknowledge" textline " " bitfld.long 0x40 2. " INT_ACK[2] ,Clear mask of the INT_STATUS bit field" "No acknowledge,Acknowledge" bitfld.long 0x40 1. " INT_ACK[1] ,Clear mask of the INT_STATUS bit field" "No acknowledge,Acknowledge" textline " " bitfld.long 0x40 0. " INT_ACK[0] ,Clear mask of the INT_STATUS bit field" "No acknowledge,Acknowledge" line.long 0x44 "HW_DRAM_CTL17,DRAM Control Register 17" hexmask.long.byte 0x44 24.--31. 1. " DLL_START_POINT ,Initial delay count when searching for lock in master DLL" hexmask.long.byte 0x44 16.--23. 1. " DLL_LOCK ,Number of delay elements in master DLL lock" textline " " hexmask.long.byte 0x44 8.--15. 1. " DLL_INCREMENT ,Number of elements to add to DLL_START_POINT when searching for lock" bitfld.long 0x44 0.--4. " TRC ,DRAM TRC parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x48 "HW_DRAM_CTL18,DRAM Control Register 18" hexmask.long.byte 0x48 24.--30. 1. " DLL_DQS_DELAY_1 ,Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 1 during reads" hexmask.long.byte 0x48 16.--22. 1. " DLL_DQS_DELAY_0 ,Fraction of a cycle to delay the dqs signal from the DRAMs for dll_rd_dqs_slice 0 during reads" textline " " bitfld.long 0x48 12. " INTSTATUS[4] ,Logical OR of all lower bits" "Not occurred,Occurred" bitfld.long 0x48 11. " INTSTATUS[3] ,DLL unlock condition detected" "Not detected,Detected" textline " " bitfld.long 0x48 10. " INTSTATUS[2] ,DRAM initialization complete" "Not completed,Completed" bitfld.long 0x48 9. " INTSTATUS[1] ,Multiple accesses outside the defined PHYSICAL memory space detected" "Not detected,Detected" textline " " bitfld.long 0x48 8. " INTSTATUS[0] ,A single access outside the defined PHYSICAL memory space detected" "Not detected,Detected" bitfld.long 0x48 4. " INT_MASK[4] ,Mask for controller_int signals from the INT_STATUS bit field" "Not masked,Masked" textline " " bitfld.long 0x48 3. " INT_MASK[3] ,Mask for controller_int signals from the INT_STATUS bit field" "Not masked,Masked" bitfld.long 0x48 2. " INT_MASK[2] ,Mask for controller_int signals from the INT_STATUS bit field" "Not masked,Masked" textline " " bitfld.long 0x48 1. " INT_MASK[1] ,Mask for controller_int signals from the INT_STATUS bit field" "Not masked,Masked" bitfld.long 0x48 0. " INT_MASK[0] ,Mask for controller_int signals from the INT_STATUS bit field" "Not masked,Masked" line.long 0x4c "HW_DRAM_CTL19,DRAM Control Register 19" hexmask.long.byte 0x4c 24.--31. 1. " DQS_OUT_SHIFT_BYPASS ,Sets the delay for the clk_dqs_out signal of the dll_wr_dqs_slice when the DLL is being bypassed" hexmask.long.byte 0x4c 16.--22. 1. " DQS_OUT_SHIFT ,Sets the delay for the clk_dqs_out signal of the dll_wr_dqs_slice to ensure correct data capture in the I/O logic" textline " " hexmask.long.byte 0x4c 8.--15. 1. " DLL_DQS_DELAY_BYPASS_1 ,Sets the delay for the read_dqs signal from the DDR SDRAM devices for dll_rd_dqs_slice 1 for reads when the DLL is being bypassed" hexmask.long.byte 0x4c 0.--7. 1. " DLL_DQS_DELAY_BYPASS_0 ,Sets the delay for the read_dqs signal from the DDR SDRAM devices for dll_rd_dqs_slice 0 for reads when the DLL is being bypassed" line.long 0x50 "HW_DRAM_CTL20,DRAM Control Register 20" hexmask.long.byte 0x50 24.--31. 1. " TRCD_INT ,DRAM TRCD parameter in cycles" hexmask.long.byte 0x50 16.--23. 1. " TRAS_MIN ,DRAM TRAS_MIN parameter in cycles" textline " " hexmask.long.byte 0x50 8.--15. 1. " WR_DQS_SHIFT_BYPASS ,Sets the delay for the clk_wr signal when the DLL is being bypassed" hexmask.long.byte 0x50 0.--6. 1. " WR_DQS_SHIFT ,Sets the delay for the clk_wr signal to ensure correct data capture in the I/O logic" line.long 0x54 "HW_DRAM_CTL21,DRAM Control Register 21" hexmask.long.word 0x54 8.--17. 1. " OUT_OF_RANGE_LENGTH ,Length of command that caused an Out-of-Range interrupt" hexmask.long.byte 0x54 0.--7. 1. " TRFC ,DRAM TRFC parameter in cycles" group.long 0x58++0x03 line.long 0x00 "HW_DRAM_CTL22,DRAM Control Register 22" hexmask.long.word 0x00 16.--26. 1. " AHB0_WRCNT ,Number of bytes for an INCR WRITE command on port 0" hexmask.long.word 0x00 0.--10. 1. " AHB0_RDCNT ,Number of bytes for an INCR READ command on port 0" group.long 0x5C++0x03 line.long 0x00 "HW_DRAM_CTL23,DRAM Control Register 23" hexmask.long.word 0x00 16.--26. 1. " AHB1_WRCNT ,Number of bytes for an INCR WRITE command on port 1" hexmask.long.word 0x00 0.--10. 1. " AHB1_RDCNT ,Number of bytes for an INCR READ command on port 1" group.long 0x60++0x03 line.long 0x00 "HW_DRAM_CTL24,DRAM Control Register 24" hexmask.long.word 0x00 16.--26. 1. " AHB2_WRCNT ,Number of bytes for an INCR WRITE command on port 2" hexmask.long.word 0x00 0.--10. 1. " AHB2_RDCNT ,Number of bytes for an INCR READ command on port 2" group.long 0x64++0x03 line.long 0x00 "HW_DRAM_CTL25,DRAM Control Register 25" hexmask.long.word 0x00 16.--26. 1. " AHB3_WRCNT ,Number of bytes for an INCR WRITE command on port 3" hexmask.long.word 0x00 0.--10. 1. " AHB3_RDCNT ,Number of bytes for an INCR READ command on port 3" group.long 0x68++0x03 line.long 0x00 "HW_DRAM_CTL26,DRAM Control Register 26" hexmask.long.word 0x00 0.--11. 1. " TREF ,DRAM TREF parameter in cycles" hgroup.long 0x6c++0x07 hide.long 0x00 "HW_DRAM_CTL27,DRAM Control Register 27" hide.long 0x04 "HW_DRAM_CTL28,DRAM Control Register 28" group.long 0x74++0x2f line.long 0x00 "HW_DRAM_CTL29,DRAM Control Register 29" hexmask.long.word 0x00 16.--31. 1. " LOWPOWER_INTERNAL_CNT ,Counts idle cycles to self-refresh with memory and controller clk gating" hexmask.long.word 0x00 0.--15. 1. " LOWPOWER_EXTERNAL_CNT ,Counts idle cycles to self-refresh with memory clock gating" line.long 0x04 "HW_DRAM_CTL30,DRAM Control Register 30" hexmask.long.word 0x04 16.--31. 1. " LOWPOWER_REFRESH_HOLD ,Re-Sync counter for DLL in Clock Gate Mode" hexmask.long.word 0x04 0.--15. 1. " LOWPOWER_POWER_DOWN_CNT ,Counts idle cycles to memory power-down" line.long 0x08 "HW_DRAM_CTL31,DRAM Control Register 31" hexmask.long.word 0x08 16.--31. 1. " TDLL ,DRAM TDLL parameter in cycles" hexmask.long.word 0x08 0.--15. 1. " LOWPOWER_SELF_REFRESH_CNT ,Counts idle cycles to memory self-refresh" line.long 0x0c "HW_DRAM_CTL32,DRAM Control Register 32" hexmask.long.word 0x0c 16.--31. 1. " TXSNR ,DRAM TXSNR parameter in cycles" hexmask.long.word 0x0c 0.--15. 1. " TRAS_MAX ,DRAM TRAS_MAX parameter in cycles" line.long 0x10 "HW_DRAM_CTL33,DRAM Control Register 33" hexmask.long.word 0x10 16.--31. 1. " VERSION ,Controller version number" hexmask.long.word 0x10 0.--15. 1. " TXSR ,DRAM TXSR parameter in cycles" line.long 0x14 "HW_DRAM_CTL34,DRAM Control Register 34" hexmask.long.tbyte 0x14 0.--23. 1. " TINIT ,DRAM TINIT parameter in cycles" line.long 0x18 "HW_DRAM_CTL35,DRAM Control Register 35" hexmask.long 0x18 0.--30. 1. "OUT_OF_RANGE_ADDR,Address of command that caused an Out-of-Range interrupt" line.long 0x1c "HW_DRAM_CTL36,DRAM Control Register 36" bitfld.long 0x1C 24. " PWRUP_SREFRESH_EXIT ,Powerup via self-refresh instead of full memory initialization" "Disabled,Enabled" bitfld.long 0x1C 16. " ENABLE_QUICK_SREFRESH ,Interrupts memory initialization to enter self-refresh mode" "Not entered,Entered" textline " " bitfld.long 0x1C 0. " ACTIVE_AGING ,Enable aging of the active command" "Disabled,Enabled" line.long 0x20 "HW_DRAM_CTL37,DRAM Control Register 37" hexmask.long.word 0x20 8.--17. 1. " BUS_SHARE_TIMEOUT ,Wait time from when the memory controller needs the bus to asserting bus_timeout signal" bitfld.long 0x20 0. " TREF_ENABLE ,Internal refresh commands" "Disabled,Enabled" line.long 0x24 "HW_DRAM_CTL38,DRAM Control Register 38" hexmask.long.word 0x24 16.--28. 1. " EMRS2_DATA_0 ,EMRS2 data for chip select 0" hexmask.long.word 0x24 0.--12. 1. " EMRS1_DATA ,EMRS1 data" line.long 0x28 "HW_DRAM_CTL39,DRAM Control Register 39" hexmask.long.word 0x28 16.--28. 1. " EMRS2_DATA_2 ,EMRS2 data for chip select 2" hexmask.long.word 0x28 0.--12. 1. " EMRS2_DATA_1 ,EMRS2 data for chip select 1" line.long 0x2c "HW_DRAM_CTL40,DRAM Control Register 40" hexmask.long.word 0x2c 16.--31. 1. " TPDEX ,DRAM TPDEX parameter in cycles" hexmask.long.word 0x2c 0.--12. 1. " EMRS2_DATA_3 ,EMRS2 data for chip select 3" width 0xb tree.end tree.end tree "GPMI (General-Purpose Media Interface)" base asd:0x8000C000 width 21. group.long 0x00++0x13 line.long 0x00 "HW_GPMI_CTRL0,GPMI Control Register 0" bitfld.long 0x00 31. " SFTRST ,Soft reset" "Run,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gate" "Run,No_clks" textline " " bitfld.long 0x00 29. " RUN ,GPMI busy running" "Idle,Busy" bitfld.long 0x00 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x00 23. " WORD_LENGTH ,Data bus mode" "16 bit,8 bit" textline " " bitfld.long 0x00 22. " LOCK_CS ,Chip select lock bit" "Disabled,Enabled" bitfld.long 0x00 20.--21. " CS ,Chip select bit" "0,1,2,3" textline " " bitfld.long 0x00 16. " ADDRESS_INCREMENT ,Adress increment" "Not incremented,Incremented" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x04 "HW_GPMI_CTRL0_SET,GPMI Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,GPMI busy running" "No effect,Set" bitfld.long 0x04 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "No effect,Set" textline " " bitfld.long 0x04 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x04 23. " WORD_LENGTH ,Data bus mode" "No effect,Set" textline " " bitfld.long 0x04 22. " LOCK_CS ,Chip select lock bit" "No effect,Set" bitfld.long 0x04 20.--21. " CS ,Chip select bit" "0,1,2,3" textline " " bitfld.long 0x04 16. " ADDRESS_INCREMENT ,Adress increment" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x08 "HW_GPMI_CTRL0_CLR,GPMI Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Cleared" bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Cleared" textline " " bitfld.long 0x08 29. " RUN ,GPMI busy running" "No effect,Cleared" bitfld.long 0x08 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "No effect,Cleared" textline " " bitfld.long 0x08 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x08 23. " WORD_LENGTH ,Data bus mode" "No effect,Cleared" textline " " bitfld.long 0x08 22. " LOCK_CS ,Chip select lock bit" "No effect,Cleared" bitfld.long 0x08 20.--21. " CS ,Chip select bit" "0,1,2,3" textline " " bitfld.long 0x08 16. " ADDRESS_INCREMENT ,Adress increment" "No effect,Cleared" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x0c "HW_GPMI_CTRL0_TOG,GPMI Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Soft reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,GPMI busy running" "Not toggle,Toggle" bitfld.long 0x0c 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x0c 23. " WORD_LENGTH ,Data bus mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " LOCK_CS ,Chip select lock bit" "Not toggle,Toggle" bitfld.long 0x0c 20.--21. " CS ,Chip select bit" "0,1,2,3" textline " " bitfld.long 0x0c 16. " ADDRESS_INCREMENT ,Adress increment" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x10 "HW_GPMI_COMPARE,GPMI Compare Register Description" hexmask.long.word 0x10 16.--31. 1. " MASK ,16-bit mask which is applied after the read data is XORed with the REFERENCE bit field" hexmask.long.word 0x10 0.--15. 1. " REFERENCE ,16-bit value which is XORed with data read from the NAND device" group.long 0x20++0x13 line.long 0x00 "HW_GPMI_ECCCTRL,GPMI Integrated ECC Control Register" hexmask.long.word 0x00 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x00 13.--14. " ECC_CMD ,ECC Command information" "DECODE_4_BIT,ENCODE_4_BIT,DECODE_8_BIT,ENCODE_8_BIT" textline " " bitfld.long 0x00 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Disabled,Enabled" bitfld.long 0x00 8. " AUXILIARY ,Request transfer to/from the auxiliary buffer" "Not requested,Requested" textline " " bitfld.long 0x00 7. " BUFFER_MASK[7] ,Request transfer to/from data buffer 7" "Not requested,Requested" bitfld.long 0x00 6. " BUFFER_MASK[6] ,Request transfer to/from data buffer 6" "Not requested,Requested" textline " " bitfld.long 0x00 5. " BUFFER_MASK[5] ,Request transfer to/from data buffer 5" "Not requested,Requested" bitfld.long 0x00 4. " BUFFER_MASK[4] ,Request transfer to/from data buffer 4" "Not requested,Requested" textline " " bitfld.long 0x00 3. " BUFFER_MASK[3] ,Request transfer to/from data buffer 3" "Not requested,Requested" bitfld.long 0x00 2. " BUFFER_MASK[2] ,Request transfer to/from data buffer 2" "Not requested,Requested" textline " " bitfld.long 0x00 1. " BUFFER_MASK[1] ,Request transfer to/from data buffer 1" "Not requested,Requested" bitfld.long 0x00 0. " BUFFER_MASK[0] ,Request transfer to/from data buffer 0" "Not requested,Requested" line.long 0x04 "HW_GPMI_ECCCTRL_SET,GPMI Integrated ECC Control Set Register" hexmask.long.word 0x04 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x04 13.--14. " ECC_CMD ,ECC Command information" "DECODE_4_BIT,ENCODE_4_BIT,DECODE_8_BIT,ENCODE_8_BIT" textline " " bitfld.long 0x04 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Set" bitfld.long 0x04 8. " AUXILIARY ,Request transfer to/from the auxiliary buffer" "No effect,Set" textline " " bitfld.long 0x04 7. " BUFFER_MASK[7] ,Request transfer to/from data buffer 7" "No effect,Set" bitfld.long 0x04 6. " BUFFER_MASK[6] ,Request transfer to/from data buffer 6" "No effect,Set" textline " " bitfld.long 0x04 5. " BUFFER_MASK[5] ,Request transfer to/from data buffer 5" "No effect,Set" bitfld.long 0x04 4. " BUFFER_MASK[4] ,Request transfer to/from data buffer 4" "No effect,Set" textline " " bitfld.long 0x04 3. " BUFFER_MASK[3] ,Request transfer to/from data buffer 3" "No effect,Set" bitfld.long 0x04 2. " BUFFER_MASK[2] ,Request transfer to/from data buffer 2" "No effect,Set" textline " " bitfld.long 0x04 1. " BUFFER_MASK[1] ,Request transfer to/from data buffer 1" "No effect,Set" bitfld.long 0x04 0. " BUFFER_MASK[0] ,Request transfer to/from data buffer 0" "No effect,Set" line.long 0x08 "HW_GPMI_ECCCTRL_CLR,GPMI Integrated ECC Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x08 13.--14. " ECC_CMD ,ECC Command information" "DECODE_4_BIT,ENCODE_4_BIT,DECODE_8_BIT,ENCODE_8_BIT" textline " " bitfld.long 0x08 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Cleared" bitfld.long 0x08 8. " AUXILIARY ,Request transfer to/from the auxiliary buffer" "No effect,Cleared" textline " " bitfld.long 0x08 7. " BUFFER_MASK[7] ,Request transfer to/from data buffer 7" "No effect,Cleared" bitfld.long 0x08 6. " BUFFER_MASK[6] ,Request transfer to/from data buffer 6" "No effect,Cleared" textline " " bitfld.long 0x08 5. " BUFFER_MASK[5] ,Request transfer to/from data buffer 5" "No effect,Cleared" bitfld.long 0x08 4. " BUFFER_MASK[4] ,Request transfer to/from data buffer 4" "No effect,Cleared" textline " " bitfld.long 0x08 3. " BUFFER_MASK[3] ,Request transfer to/from data buffer 3" "No effect,Cleared" bitfld.long 0x08 2. " BUFFER_MASK[2] ,Request transfer to/from data buffer 2" "No effect,Cleared" textline " " bitfld.long 0x08 1. " BUFFER_MASK[1] ,Request transfer to/from data buffer 1" "No effect,Cleared" bitfld.long 0x08 0. " BUFFER_MASK[0] ,Request transfer to/from data buffer 0" "No effect,Cleared" line.long 0x0c "HW_GPMI_ECCCTRL_TOG,GPMI Integrated ECC Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x0c 13.--14. " ECC_CMD ,ECC Command information" "DECODE_4_BIT,ENCODE_4_BIT,DECODE_8_BIT,ENCODE_8_BIT" textline " " bitfld.long 0x0c 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Not toggle,Toggle" bitfld.long 0x0c 8. " AUXILIARY ,Request transfer to/from the auxiliary buffer" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " BUFFER_MASK[7] ,Request transfer to/from data buffer 7" "Not toggle,Toggle" bitfld.long 0x0c 6. " BUFFER_MASK[6] ,Request transfer to/from data buffer 6" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " BUFFER_MASK[5] ,Request transfer to/from data buffer 5" "Not toggle,Toggle" bitfld.long 0x0c 4. " BUFFER_MASK[4] ,Request transfer to/from data buffer 4" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " BUFFER_MASK[3] ,Request transfer to/from data buffer 3" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUFFER_MASK[2] ,Request transfer to/from data buffer 2" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " BUFFER_MASK[1] ,Request transfer to/from data buffer 1" "Not toggle,Toggle" bitfld.long 0x0c 0. " BUFFER_MASK[0] ,Request transfer to/from data buffer 0" "Not toggle,Toggle" line.long 0x10 "HW_GPMI_ECCCOUNT,GPMI Integrated ECC Transfer Count Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of bytes to pass through ECC" group.long 0x40++0x03 line.long 0x00 "HW_GPMI_PAYLOAD,GPMI Payload Address" hexmask.long 0x00 2.--31. 4. " ADDRESS ,Pointer to an array of one or more 512 byte payload buffers" group.long 0x50++0x03 line.long 0x00 "HW_GPMI_AUXILIARY,GPMI Auxiliary Address Register" hexmask.long 0x00 2.--31. 4. " ADDRESS ,Pointer to ECC control structure and meta-data storage" group.long 0x60++0x13 line.long 0x00 "HW_GPMI_CTRL1,GPMI Control Register 1" bitfld.long 0x00 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not forced,Forced" bitfld.long 0x00 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "ECC8,BCH" textline " " bitfld.long 0x00 17. " DLL_ENABLE ,GPMI DLL enable bit" "Disabled,Enabled" bitfld.long 0x00 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Disabled,Enabled" textline " " bitfld.long 0x00 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " DMA2ECC_MODE ,DMA ECC mode" "0,1" textline " " bitfld.long 0x00 9. " TIMEOUT_IRQ ,Interrupt timeout" "Not occurred,Occurred" bitfld.long 0x00 8. " BURST_EN ,4-transfer burst on APB bus enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ABORT_WAIT_FOR_READY3 ,Abort a wait for ready command on channel 3" "Not aborted,Aborted" bitfld.long 0x00 6. " ABORT_WAIT_FOR_READY2 ,Abort a wait for ready command on channel 2" "Not aborted,Aborted" textline " " bitfld.long 0x00 5. " ABORT_WAIT_FOR_READY1 ,Abort a wait for ready command on NAND channel 1" "Not aborted,Aborted" bitfld.long 0x00 4. " ABORT_WAIT_FOR_READY0 ,Abort a wait for ready command on channel 0" "Not aborted,Aborted" textline " " bitfld.long 0x00 3. " DEV_RESET ,Device reset" "No reset,Reset" bitfld.long 0x00 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Activelow,Activehigh" textline " " bitfld.long 0x00 0. " GPMI_MODE ,GPMI Mode" "NAND,?..." line.long 0x04 "HW_GPMI_CTRL1_SET,GPMI Control Set Register 1" bitfld.long 0x04 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Set" bitfld.long 0x04 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Set" textline " " bitfld.long 0x04 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Set" bitfld.long 0x04 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Set" textline " " bitfld.long 0x04 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 11. " DMA2ECC_MODE ,DMA ECC mode" "No effect,Set" textline " " bitfld.long 0x04 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Set" bitfld.long 0x04 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Set" textline " " bitfld.long 0x04 7. " ABORT_WAIT_FOR_READY3 ,Abort a wait for ready command on channel 3" "No effect,Set" bitfld.long 0x04 6. " ABORT_WAIT_FOR_READY2 ,Abort a wait for ready command on channel 3" "No effect,Set" textline " " bitfld.long 0x04 5. " ABORT_WAIT_FOR_READY1 ,Abort a wait for ready command on NAND channel 1" "No effect,Set" bitfld.long 0x04 4. " ABORT_WAIT_FOR_READY0 ,Abort a wait for ready command on channel 0" "No effect,Set" textline " " bitfld.long 0x04 3. " DEV_RESET ,Device reset" "No effect,Set" bitfld.long 0x04 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Set" textline " " bitfld.long 0x04 0. " GPMI_MODE ,GPMI Mode" "No effect,Set" line.long 0x08 "HW_GPMI_CTRL1_CLR,GPMI Control Clear Register 1" bitfld.long 0x08 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Cleared" bitfld.long 0x08 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Cleared" textline " " bitfld.long 0x08 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Cleared" bitfld.long 0x08 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Cleared" textline " " bitfld.long 0x08 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 11. " DMA2ECC_MODE ,DMA ECC mode" "No effect,Cleared" textline " " bitfld.long 0x08 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Cleared" bitfld.long 0x08 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Cleared" textline " " bitfld.long 0x08 7. " ABORT_WAIT_FOR_READY3 ,Abort a wait for ready command on channel 3" "No effect,Cleared" bitfld.long 0x08 6. " ABORT_WAIT_FOR_READY2 ,Abort a wait for ready command on channel 3" "No effect,Cleared" textline " " bitfld.long 0x08 5. " ABORT_WAIT_FOR_READY1 ,Abort a wait for ready command on NAND channel 1" "No effect,Cleared" bitfld.long 0x08 4. " ABORT_WAIT_FOR_READY0 ,Abort a wait for ready command on channel 0" "No effect,Cleared" textline " " bitfld.long 0x08 3. " DEV_RESET ,Device reset" "No effect,Cleared" bitfld.long 0x08 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Cleared" textline " " bitfld.long 0x08 0. " GPMI_MODE ,GPMI Mode" "No effect,Cleared" line.long 0x0c "HW_GPMI_CTRL1_TOG,GPMI Control Toggle Register 1" bitfld.long 0x0c 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not toggle,Toggle" bitfld.long 0x0c 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " DLL_ENABLE ,GPMI DLL enable bit" "Not toggle,Toggle" bitfld.long 0x0c 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 11. " DMA2ECC_MODE ,DMA ECC mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " TIMEOUT_IRQ ,Interrupt timeout" "Not toggle,Toggle" bitfld.long 0x0c 8. " BURST_EN ,4-transfer burst on APB bus enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " ABORT_WAIT_FOR_READY3 ,Abort a wait for ready command on channel 3" "Not toggle,Toggle" bitfld.long 0x0c 6. " ABORT_WAIT_FOR_READY2 ,Abort a wait for ready command on channel 3" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " ABORT_WAIT_FOR_READY1 ,Abort a wait for ready command on NAND channel 1" "Not toggle,Toggle" bitfld.long 0x0c 4. " ABORT_WAIT_FOR_READY0 ,Abort a wait for ready command on channel 0" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " DEV_RESET ,Device reset" "Not toggle,Toggle" bitfld.long 0x0c 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " GPMI_MODE ,GPMI Mode" "Not toggle,Toggle" line.long 0x10 "HW_GPMI_TIMING0,GPMI Timing Register 0" hexmask.long.byte 0x10 16.--23. 1. " ADDRESS_SETUP ,Number of GPMICLK cycles that the CE signals are active before a strobe is asserted" hexmask.long.byte 0x10 8.--15. 1. " DATA_HOLD ,Data bus hold time in GPMICLK cycles" textline " " hexmask.long.byte 0x10 0.--7. 1. " DATA_SETUP ,Data bus setup time in GPMICLK cycles" group.long 0x80++0x03 line.long 0x00 "HW_GPMI_TIMING1,GPMI Timing Register 1" hexmask.long.word 0x00 16.--31. 1. " DEVICE_BUSY_TIMEOUT ,Timeout waiting for NAND Ready/Busy" group.long 0xa0++0x03 line.long 0x00 "HW_GPMI_DATA,GPMI DMA Data Transfer Register" rgroup.long 0xb0++0x03 line.long 0x00 "HW_GPMI_STAT,GPMI Status Register" bitfld.long 0x00 31. " PRESENT ,GPMI product present" "Not present,Present" bitfld.long 0x00 11. " RDY_TIMEOUT[3] ,Status of the RDY/BUSY Timeout Flag" "Not timeout,Timeout" textline " " bitfld.long 0x00 10. " RDY_TIMEOUT[2] ,Status of the RDY/BUSY Timeout Flag" "Not timeout,Timeout" bitfld.long 0x00 9. " RDY_TIMEOUT[1] ,Status of the RDY/BUSY Timeout Flag" "Not timeout,Timeout" textline " " bitfld.long 0x00 8. " RDY_TIMEOUT[0] ,Status of the RDY/BUSY Timeout Flag" "Not timeout,Timeout" bitfld.long 0x00 6. " INVALID_BUFFER_MASK ,ECC Buffer Mask Invalid" "Not valid,Invalid" textline " " bitfld.long 0x00 5. " FIFO_EMPTY ,FIFO empty bit" "Not empty,Empty" bitfld.long 0x00 4. " FIFO_FULL ,FIFO full bit" "Not full,Full" textline " " bitfld.long 0x00 3. " DEV3_ERROR ,NAND Device 3 error bit" "No error,Error" bitfld.long 0x00 2. " DEV2_ERROR ,NAND Device 2 error bit" "No error,Error" textline " " bitfld.long 0x00 1. " DEV1_ERROR ,NAND Device 1 error bit" "No error,Error" bitfld.long 0x00 0. " DEV0_ERROR ,NAND Device 0 error bit" "No error,Error" rgroup.long 0xc0++0x03 line.long 0x00 "HW_GPMI_DEBUG,GPMI Debug Information Register" bitfld.long 0x00 31. " READY3 ,Ready Line 3" "Not ready,Ready" bitfld.long 0x00 30. " READY2 ,Ready Line 2" "Not ready,Ready" textline " " bitfld.long 0x00 29. " READY1 ,Ready Line 1" "Not ready,Ready" bitfld.long 0x00 28. " READY0 ,Ready Line 0" "Not ready,Ready" textline " " bitfld.long 0x00 27. " WAIT_FOR_READY_END3 ,WAIT_FOR_READY command end of channel 3" "Not occurred,Occurred" bitfld.long 0x00 26. " WAIT_FOR_READY_END2 ,WAIT_FOR_READY command end of channel 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " WAIT_FOR_READY_END1 ,WAIT_FOR_READY command end of channel 1" "Not occurred,Occurred" bitfld.long 0x00 24. " WAIT_FOR_READY_END0 ,WAIT_FOR_READY command end of channel 0" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " SENSE3 ,sense state of channel 3" "No effect,Failed/Timeouted" bitfld.long 0x00 22. " SENSE2 ,sense state of channel 2" "No effect,Failed/Timeouted" textline " " bitfld.long 0x00 21. " SENSE1 ,sense state of channel 1" "No effect,Failed/Timeouted" bitfld.long 0x00 20. " SENSE0 ,sense state of channel 0" "No effect,Failed/Timeouted" textline " " bitfld.long 0x00 19. " DMAREQ3 ,DMA request line for channel 3" "Not requested,Requested" bitfld.long 0x00 18. " DMAREQ2 ,DMA request line for channel 2" "Not requested,Requested" textline " " bitfld.long 0x00 17. " DMAREQ1 ,DMA request line for channel 1" "Not requested,Requested" bitfld.long 0x00 16. " DMAREQ0 ,DMA request line for channel 0" "Not requested,Requested" textline " " bitfld.long 0x00 15. " CMD_END[3] ,Command End toggle to DMA Channel 3" "Not finished,Finished" bitfld.long 0x00 14. " CMD_END[2] ,Command End toggle to DMA Channel 2" "Not finished,Finished" textline " " bitfld.long 0x00 13. " CMD_END[1] ,Command End toggle to DMA Channel 1" "Not finished,Finished" bitfld.long 0x00 12. " CMD_END[0] ,Command End toggle to DMA Channel 0" "Not finished,Finished" textline " " bitfld.long 0x00 8.--11. " UDMA_STATE ,UDMA State mode" "IDLE,DMARQ,ACK,FIFO_E,WPAUSE,TSTRB,CAPTUR,DATAOUT,CRC,WAIT_R,END,WAIT_S,RPAUSE,RSTOP,WTERM,RTERM" bitfld.long 0x00 7. " BUSY ,GPMI Busy bit" "Not busy,Busy" textline " " bitfld.long 0x00 4.--6. " PIN_STATE ,Pin State mode" "IDLE,BYTCNT,ADDR,STALL,STROBE,ATARDY,DHOLD,DONE" bitfld.long 0x00 0.--3. " MAIN_STATE ,Main State mode" "IDLE,BYTCNT,WAITFE,WAITFR,DMAREQ,DMAACK,WAITFF,LDFIFO,LDDMAR,RDCMP,DONE,?..." rgroup.long 0xd0++0x03 line.long 0x00 "HW_GPMI_VERSION,GPMI Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0xe0++0x03 line.long 0x00 "HW_GPMI_DEBUG2,GPMI Debug2 Information Register" bitfld.long 0x00 12.--15. " SYND2GPMI_BE ,Data byte enable Input from ECC8 or BCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 11. " GPMI2SYND_VALID ,Data handshake output to ECC8 or BCH valid" "Not valid,Valid" textline " " bitfld.long 0x00 10. " GPMI2SYND_READY ,Data handshake output to ECC8 or BCH ready" "Not ready,Ready" bitfld.long 0x00 9. " SYND2GPMI_VALID ,Data handshake Input from ECC8 or BCH valid" "Not valid,Valid" textline " " bitfld.long 0x00 8. " SYND2GPMI_READY ,Data handshake Input from ECC8 or BCH ready" "Not ready,Ready" bitfld.long 0x00 7. " VIEW_DELAYED_RDN ,View delayed RDN" "Not selected,Selected" textline " " bitfld.long 0x00 6. " UPDATE_WINDOW ,DLL is busy generating the required delay" "Not updated,Updated" bitfld.long 0x00 0.--5. " RDN_TAP ,This is the DLL tap calculated by the DLL controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xf0++0x03 line.long 0x00 "HW_GPMI_DEBUG3,GPMI Debug3 Information Register" hexmask.long.word 0x00 16.--31. 1. " APB_WORD_CNTR ,Reflects the number of words (16 or 8-bit) remains to be transferred on the APB bus" hexmask.long.word 0x00 0.--15. 1. " DEV_WORD_CNTR ,Reflects the number of words (16 or 8-bit) remains to be transferred on the Nand bus" width 0xb tree.end tree "ECC8 (8-Symbol Correcting ECC Accelerator)" base asd:0x80008000 width 24. group.long 0x00++0x0f line.long 0x00 "HW_ECC8_CTRL,Hardware ECC Accelerator Control Register" bitfld.long 0x00 31. " SFTRST ,Soft reset" "Run,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gate" "Run,No_Clks" textline " " bitfld.long 0x00 29. " AHBM_SFTRST ,AHB state machine reset" "Run,Reset" bitfld.long 0x00 24.--27. " THROTTLE ,Non-zero values will hold off that number of HCLKs between success burst requests on the AHB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode" "Disabled,Enabled" bitfld.long 0x00 9. " DEBUG_WRITE_IRQ_EN ,Interrupt on debug write mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " COMPLETE_IRQ_EN ,Interrupt on complection of correction" "Disabled,Enabled" bitfld.long 0x00 3. " BM_ERROR_IRQ ,AHB Bus Interface Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " DEBUG_WRITE_IRQ ,Debug Write Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " COMPLETE_IRQ ,External Interrupt Line Status" "Not occurred,Occurred" line.long 0x04 "HW_ECC8_CTRL_SET,Hardware ECC Accelerator Control Set Register" bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set" textline " " bitfld.long 0x04 29. " AHBM_SFTRST ,AHB state machine reset" "No effect,Set" bitfld.long 0x04 24.--27. " THROTTLE ,Non-zero values will hold off that number of HCLKs between success burst requests on the AHB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode" "No effect,Set" bitfld.long 0x04 9. " DEBUG_WRITE_IRQ_EN ,Interrupt on debug write mode" "No effect,Set" textline " " bitfld.long 0x04 8. " COMPLETE_IRQ_EN ,Interrupt on complection of correction" "No effect,Set" bitfld.long 0x04 3. " BM_ERROR_IRQ ,AHB Bus Interface Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " DEBUG_WRITE_IRQ ,Debug Write Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 0. " COMPLETE_IRQ ,External Interrupt Line Status" "No effect,Set" line.long 0x08 "HW_ECC8_CTRL_CLR,Hardware ECC Accelerator Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Cleared" bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Cleared" textline " " bitfld.long 0x08 29. " AHBM_SFTRST ,AHB state machine reset" "No effect,Cleared" bitfld.long 0x08 24.--27. " THROTTLE ,Non-zero values will hold off that number of HCLKs between success burst requests on the AHB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode" "No effect,Cleared" bitfld.long 0x08 9. " DEBUG_WRITE_IRQ_EN ,Interrupt on debug write mode" "No effect,Cleared" textline " " bitfld.long 0x08 8. " COMPLETE_IRQ_EN ,Interrupt on complection of correction" "No effect,Cleared" bitfld.long 0x08 3. " BM_ERROR_IRQ ,AHB Bus Interface Error Interrupt Status" "No effect,Cleared" textline " " bitfld.long 0x08 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "No effect,Cleared" bitfld.long 0x08 1. " DEBUG_WRITE_IRQ ,Debug Write Interrupt Status" "No effect,Cleared" textline " " bitfld.long 0x08 0. " COMPLETE_IRQ ,External Interrupt Line Status" "No effect,Cleared" line.long 0x0c "HW_ECC8_CTRL_TOG,Hardware ECC Accelerator Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Soft reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " AHBM_SFTRST ,AHB state machine reset" "Not toggle,Toggle" bitfld.long 0x0c 24.--27. " THROTTLE ,Non-zero values will hold off that number of HCLKs between success burst requests on the AHB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0c 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode" "Not toggle,Toggle" bitfld.long 0x0c 9. " DEBUG_WRITE_IRQ_EN ,Interrupt on debug write mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " COMPLETE_IRQ_EN ,Interrupt on complection of correction" "Not toggle,Toggle" bitfld.long 0x0c 3. " BM_ERROR_IRQ ,AHB Bus Interface Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " DEBUG_WRITE_IRQ ,Debug Write Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " COMPLETE_IRQ ,External Interrupt Line Status" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_ECC8_STATUS0,Hardware ECC Accelerator Status Register 0" hexmask.long.word 0x00 20.--31. 1. " HANDLE ,12-bit handle supplies" bitfld.long 0x00 16.--19. " COMPLETED_CE ,Chip enable number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8.--11. " STATUS_AUX ,Count of symbols in error during processing of auxiliary data area" "No Errors,1 correctable,2 correctable,3 correctable,4 correctable,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" bitfld.long 0x00 4. " ALLONES ,All data bits of this transaction are 1" "Not set,Set" textline " " bitfld.long 0x00 3. " CORRECTED ,At least one correctable error encountered during last processing cycle" "Not set,Set" bitfld.long 0x00 2. " UNCORRECTABLE ,Uncorrectable error encountered during last processing cycle" "Not set,Set" rgroup.long 0x20++0x03 line.long 0x00 "HW_ECC8_STATUS1,Hardware ECC Accelerator Status Register 1" bitfld.long 0x00 28.--31. " STATUS_PAYLOAD7 ,Count of symbols in error during processing of payload area 7" "No errors,1 correctable,2 correctable,3 correctable,4 correctable,5 correctable,6 correctable,7 correctable,8 correctable,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" bitfld.long 0x00 24.--27. " STATUS_PAYLOAD6 ,Count of symbols in error during processing of payload area 6" "No errors,1 correctable,2 correctable,3 correctable,4 correctable,5 correctable,6 correctable,7 correctable,8 correctable,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" textline " " bitfld.long 0x00 20.--23. " STATUS_PAYLOAD5 ,Count of symbols in error during processing of payload area 5" "No errors,1 correctable,2 correctable,3 correctable,4 correctable,5 correctable,6 correctable,7 correctable,8 correctable,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" bitfld.long 0x00 16.--19. " STATUS_PAYLOAD4 ,Count of symbols in error during processing of payload area 4" "No errors,1 correctable,2 correctable,3 correctable,4 correctable,5 correctable,6 correctable,7 correctable,8 correctable,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" textline " " bitfld.long 0x00 12.--15. " STATUS_PAYLOAD3 ,Count of symbols in error during processing of payload area 3" "No errors,1 correctable,2 correctable,3 correctable,4 correctable,5 correctable,6 correctable,7 correctable,8 correctable,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" bitfld.long 0x00 8.--11. " STATUS_PAYLOAD2 ,Count of symbols in error during processing of payload area 2" "No errors,1 correctable,2 correctable,3 correctable,4 correctable,5 correctable,6 correctable,7 correctable,8 correctable,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" textline " " bitfld.long 0x00 4.--7. " STATUS_PAYLOAD1 ,Count of symbols in error during processing of payload area 1" "No errors,1 correctable,2 correctable,3 correctable,4 correctable,5 correctable,6 correctable,7 correctable,8 correctable,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" bitfld.long 0x00 0.--3. " STATUS_PAYLOAD0 ,Count of symbols in error during processing of payload area 0" "No errors,1 correctable,2 correctable,3 correctable,4 correctable,5 correctable,6 correctable,7 correctable,8 correctable,Reserved,Reserved,Reserved,Not checked,Reserved,Uncorrectable,All ones" group.long 0x30++0x0f line.long 0x00 "HW_ECC8_DEBUG0,Hardware ECC Accelerator Debug Register 0" hexmask.long.word 0x00 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Input of the KES engine" bitfld.long 0x00 15. " KES_DEBUG_SHIFT_SYND ,KES_DEBUG shift syndrome" "Not toggle,Toggle" textline " " bitfld.long 0x00 14. " KES_DEBUG_PAYLOAD_FLAG ,KES engine as the input payload flag" "DATA,AUX" bitfld.long 0x00 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "4k,2k" textline " " bitfld.long 0x00 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the bus master" "Not toggle,Toggle" bitfld.long 0x00 11. " KES_STANDALONE ,Standalone mode" "Normal,Test Mode" textline " " bitfld.long 0x00 10. " KES_DEBUG_STEP ,Debug step bit" "Not toggle,Toggle" bitfld.long 0x00 9. " KES_DEBUG_STALL ,Debug stall bit" "Normal,Wait" textline " " bitfld.long 0x00 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "Normal,Test Mode" bitfld.long 0x00 0.--5. " DEBUG_REG_SELECT ,The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HW_ECC8_DEBUG0_SET,Hardware ECC Accelerator Debug Set Register 0" hexmask.long.word 0x04 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Input of the KES engine" bitfld.long 0x04 15. " KES_DEBUG_SHIFT_SYND ,KES_DEBUG shift syndrome" "No effect,Set" textline " " bitfld.long 0x04 14. " KES_DEBUG_PAYLOAD_FLAG ,KES engine as the input payload flag" "No effect,Set" bitfld.long 0x04 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "No effect,Set" textline " " bitfld.long 0x04 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the bus master" "No effect,Set" bitfld.long 0x04 11. " KES_STANDALONE ,Standalone mode" "No effect,Set" textline " " bitfld.long 0x04 10. " KES_DEBUG_STEP ,Debug step bit" "No effect,Set" bitfld.long 0x04 9. " KES_DEBUG_STALL ,Debug stall bit" "No effect,Set" textline " " bitfld.long 0x04 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "No effect,Set" bitfld.long 0x04 0.--5. " DEBUG_REG_SELECT ,The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "HW_ECC8_DEBUG0_CLR,Hardware ECC Accelerator Debug Clear Register 0" hexmask.long.word 0x08 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Input of the KES engine" bitfld.long 0x08 15. " KES_DEBUG_SHIFT_SYND ,KES_DEBUG shift syndrome" "No effect,Cleared" textline " " bitfld.long 0x08 14. " KES_DEBUG_PAYLOAD_FLAG ,KES engine as the input payload flag" "No effect,Cleared" bitfld.long 0x08 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "No effect,Cleared" textline " " bitfld.long 0x08 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the bus master" "No effect,Cleared" bitfld.long 0x08 11. " KES_STANDALONE ,Standalone mode" "No effect,Cleared" textline " " bitfld.long 0x08 10. " KES_DEBUG_STEP ,Debug step bit" "No effect,Cleared" bitfld.long 0x08 9. " KES_DEBUG_STALL ,Debug stall bit" "No effect,Cleared" textline " " bitfld.long 0x08 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "No effect,Cleared" bitfld.long 0x08 0.--5. " DEBUG_REG_SELECT ,The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0c "HW_ECC8_DEBUG0_TOG,Hardware ECC Accelerator Debug Toggle Register 0" hexmask.long.word 0x0c 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,Input of the KES engine" bitfld.long 0x0c 15. " KES_DEBUG_SHIFT_SYND ,KES_DEBUG shift syndrome" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " KES_DEBUG_PAYLOAD_FLAG ,KES engine as the input payload flag" "Not toggle,Toggle" bitfld.long 0x0c 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the bus master" "Not toggle,Toggle" bitfld.long 0x0c 11. " KES_STANDALONE ,Standalone mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " KES_DEBUG_STEP ,Debug step bit" "Not toggle,Toggle" bitfld.long 0x0c 9. " KES_DEBUG_STALL ,Debug stall bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "Not toggle,Toggle" bitfld.long 0x0c 0.--5. " DEBUG_REG_SELECT ,The value loaded in this bit field is used to select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x40++0x03 line.long 0x00 "HW_ECC8_DBGKESREAD,KES Debug Read Register" rgroup.long 0x50++0x03 line.long 0x00 "HW_ECC8_DBGCSFEREAD,Chien Search Forney Evaluator Debug Read Register" rgroup.long 0x60++0x03 line.long 0x00 "HW_ECC8_DBGSYNDGENREAD,Syndrome Generator Debug Read Register" rgroup.long 0x70++0x03 line.long 0x00 "HW_ECC8_DBGAHBMREAD,AHB Master and ECC8 Controller Debug Read Register" rgroup.long 0x80++0x03 line.long 0x00 "HW_ECC8_BLOCKNAME,ECC8 Block Name Register" rgroup.long 0xa0++0x03 line.long 0x00 "HW_ECC8_VERSION,ECC8 Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "BCH (20-Bit Correcting ECC Accelerator)" base asd:0x8000A000 width 23. group.long 0x00++0x0f line.long 0x00 "HW_BCH_CTRL,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x00 31. " SFTRST ,Soft reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gate" "Run,No_clks" textline " " bitfld.long 0x00 22. " DEBUGSYNDROME ,Enable write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" bitfld.long 0x00 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x00 17. " M2M_ENCODE ,Encode or decode for memory-to-memory operations" "Encode,Decode" bitfld.long 0x00 16. " M2M_ENABLE ,Memory-to-memory operations enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x00 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt Status" "No error,Error" bitfld.long 0x00 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " COMPLETE_IRQ ,State of the external interrupt line" "Not completed,Completed" line.long 0x04 "HW_BCH_CTRL_SET,Hardware BCH ECC Accelerator Set Control Register" bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set" textline " " bitfld.long 0x04 22. " DEBUGSYNDROME ,Enable write of computed syndromes to memory on BCH decode operations" "No effect,Set" bitfld.long 0x04 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x04 17. " M2M_ENCODE ,Encode or decode for memory-to-memory operations" "No effect,Set" bitfld.long 0x04 16. " M2M_ENABLE ,Memory-to-memory operations enable" "No effect,Set" textline " " bitfld.long 0x04 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "No effect,Set" bitfld.long 0x04 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "No effect,Set" textline " " bitfld.long 0x04 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt Status" "No effect,Set" bitfld.long 0x04 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 0. " COMPLETE_IRQ ,State of the external interrupt line" "No effect,Set" line.long 0x08 "HW_BCH_CTRL_CLR,Hardware BCH ECC Accelerator Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Cleared" bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Cleared" textline " " bitfld.long 0x08 22. " DEBUGSYNDROME ,Enable write of computed syndromes to memory on BCH decode operations" "No effect,Cleared" bitfld.long 0x08 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x08 17. " M2M_ENCODE ,Encode or decode for memory-to-memory operations" "No effect,Cleared" bitfld.long 0x08 16. " M2M_ENABLE ,Memory-to-memory operations enable" "No effect,Cleared" textline " " bitfld.long 0x08 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "No effect,Cleared" bitfld.long 0x08 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "No effect,Cleared" textline " " bitfld.long 0x08 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt Status" "No effect,Cleared" bitfld.long 0x08 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "No effect,Cleared" textline " " bitfld.long 0x08 0. " COMPLETE_IRQ ,State of the external interrupt line" "No effect,Cleared" line.long 0x0c "HW_BCH_CTRL_TOG,Hardware BCH ECC Accelerator Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Soft reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " DEBUGSYNDROME ,Enable write of computed syndromes to memory on BCH decode operations" "Not toggle,Toggle" bitfld.long 0x0c 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x0c 17. " M2M_ENCODE ,Encode or decode for memory-to-memory operations" "Not toggle,Toggle" bitfld.long 0x0c 16. " M2M_ENABLE ,Memory-to-memory operations enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Not toggle,Toggle" bitfld.long 0x0c 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " COMPLETE_IRQ ,State of the external interrupt line" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_BCH_STATUS0,Hardware BCH ECC Accelerator Status Register 0" hexmask.long.word 0x00 20.--31. 1. " HANDLE ,Supplies 12 bit handle transaction started" bitfld.long 0x00 16.--19. " COMPLETED_CE ,Number corresponding to the NAND device from which data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash (metadata block)" bitfld.long 0x00 4. " ALLONES ,All data bits ONE" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORRECTED ,Correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x00 2. " UNCORRECTABLE ,Uncorrectable error encountered during last processing cycle" "No,Yes" group.long 0x20++0x03 line.long 0x00 "HW_BCH_MODE,Hardware BCH ECC Accelerator Mode" hexmask.long.byte 0x00 0.--7. 1. " ERASE_THRESHOLD ,Treshold erase" hgroup.long 0x30++0x03 hide.long 0x00 "HW_BCH_ENCODEPTR,Hardware BCH ECC Loopback Encode Buffer Register" hgroup.long 0x40++0x03 hide.long 0x00 "HW_BCH_DATAPTR,Hardware BCH ECC Loopback Data Buffer Register" hgroup.long 0x50++0x03 hide.long 0x00 "HW_BCH_METAPTR,Hardware BCH ECC Loopback Metadata Buffer Register" group.long 0x70++0x03 line.long 0x00 "HW_BCH_LAYOUTSELECT,Hardware BCH ECC Accelerator Layout Select Register" bitfld.long 0x00 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x00 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" textline " " bitfld.long 0x00 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x00 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" textline " " bitfld.long 0x00 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x00 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" textline " " bitfld.long 0x00 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x00 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" textline " " bitfld.long 0x00 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x00 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" textline " " bitfld.long 0x00 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x00 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x00 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x00 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" tree "Flash Layout Registers" group.long 0x80++0x03 line.long 0x00 "HW_BCH_FLASH0LAYOUT0,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page(excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (in bytes) to be stored on a flash page" textline " " bitfld.long 0x00 12.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." hexmask.long.word 0x00 0.--11. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (in bytes) to be stored on the flash page" group.long (0x80+0x10)++0x03 line.long 0x00 "HW_BCH_FLASH0LAYOUT1,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (in bytes)" bitfld.long 0x00 12.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." textline " " hexmask.long.word 0x00 0.--11. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page" group.long 0xA0++0x03 line.long 0x00 "HW_BCH_FLASH1LAYOUT0,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page(excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (in bytes) to be stored on a flash page" textline " " bitfld.long 0x00 12.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." hexmask.long.word 0x00 0.--11. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (in bytes) to be stored on the flash page" group.long (0xA0+0x10)++0x03 line.long 0x00 "HW_BCH_FLASH1LAYOUT1,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (in bytes)" bitfld.long 0x00 12.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." textline " " hexmask.long.word 0x00 0.--11. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page" group.long 0xC0++0x03 line.long 0x00 "HW_BCH_FLASH2LAYOUT0,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page(excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (in bytes) to be stored on a flash page" textline " " bitfld.long 0x00 12.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." hexmask.long.word 0x00 0.--11. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (in bytes) to be stored on the flash page" group.long (0xC0+0x10)++0x03 line.long 0x00 "HW_BCH_FLASH2LAYOUT1,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (in bytes)" bitfld.long 0x00 12.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." textline " " hexmask.long.word 0x00 0.--11. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page" group.long 0xE0++0x03 line.long 0x00 "HW_BCH_FLASH3LAYOUT0,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page(excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (in bytes) to be stored on a flash page" textline " " bitfld.long 0x00 12.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." hexmask.long.word 0x00 0.--11. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (in bytes) to be stored on the flash page" group.long (0xE0+0x10)++0x03 line.long 0x00 "HW_BCH_FLASH3LAYOUT1,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (in bytes)" bitfld.long 0x00 12.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." textline " " hexmask.long.word 0x00 0.--11. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page" tree.end tree "Debug Registers" group.long 0x100++0x0f line.long 0x00 "HW_BCH_DEBUG0,Hardware BCH ECC Debug Register0" bitfld.long 0x00 26. " ROM_BIST_ENABLE ,ROM BIST enable" "Disabled,Enabled" bitfld.long 0x00 25. " ROM_BIST_COMPLETE ,BIST operation complete" "Not completed,Completed" textline " " hexmask.long.word 0x00 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x00 15. " KES_DEBUG_SHIFT_SYND ,Debug shift syndrome" "Not caused,Caused" textline " " bitfld.long 0x00 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "DATA,AUX" bitfld.long 0x00 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "4k,2k" textline " " bitfld.long 0x00 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the Bus Master" "Not caused,Caused" bitfld.long 0x00 11. " KES_STANDALONE ,KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine" "Normal,Test mode" textline " " bitfld.long 0x00 10. " KES_DEBUG_STEP ,KES FSM to skip past the stall state" "Not caused,Caused" bitfld.long 0x00 9. " KES_DEBUG_STALL ,Debug stall bit" "Normal,Wait" textline " " bitfld.long 0x00 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "Normal,Test mode" bitfld.long 0x00 0.--5. " DEBUG_REG_SELECT ,Select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HW_BCH_DEBUG0_SET,Hardware BCH ECC Debug Set Register0" bitfld.long 0x04 26. " ROM_BIST_ENABLE ,ROM BIST enable" "No effect,Set" bitfld.long 0x04 25. " ROM_BIST_COMPLETE ,BIST operation complete" "No effect,Set" textline " " hexmask.long.word 0x04 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x04 15. " KES_DEBUG_SHIFT_SYND ,Debug shift syndrome" "No effect,Set" textline " " bitfld.long 0x04 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "No effect,Set" bitfld.long 0x04 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "No effect,Set" textline " " bitfld.long 0x04 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the Bus Master" "No effect,Set" bitfld.long 0x04 11. " KES_STANDALONE ,KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine" "No effect,Set" textline " " bitfld.long 0x04 10. " KES_DEBUG_STEP ,KES FSM to skip past the stall state" "No effect,Set" bitfld.long 0x04 9. " KES_DEBUG_STALL ,Debug stall bit" "No effect,Set" textline " " bitfld.long 0x04 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "No effect,Set" bitfld.long 0x04 0.--5. " DEBUG_REG_SELECT ,Select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "HW_BCH_DEBUG0_CLR,Hardware BCH ECC Debug Clear Register0" bitfld.long 0x08 26. " ROM_BIST_ENABLE ,ROM BIST enable" "No effect,Cleared" bitfld.long 0x08 25. " ROM_BIST_COMPLETE ,BIST operation complete" "No effect,Cleared" textline " " hexmask.long.word 0x08 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x08 15. " KES_DEBUG_SHIFT_SYND ,Debug shift syndrome" "No effect,Cleared" textline " " bitfld.long 0x08 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "No effect,Cleared" bitfld.long 0x08 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "No effect,Cleared" textline " " bitfld.long 0x08 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the Bus Master" "No effect,Cleared" bitfld.long 0x08 11. " KES_STANDALONE ,KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine" "No effect,Cleared" textline " " bitfld.long 0x08 10. " KES_DEBUG_STEP ,KES FSM to skip past the stall state" "No effect,Cleared" bitfld.long 0x08 9. " KES_DEBUG_STALL ,Debug stall bit" "No effect,Cleared" textline " " bitfld.long 0x08 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "No effect,Cleared" bitfld.long 0x08 0.--5. " DEBUG_REG_SELECT ,Select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0c "HW_BCH_DEBUG0_TOG,Hardware BCH ECC Debug Toggle Register0" bitfld.long 0x0c 26. " ROM_BIST_ENABLE ,ROM BIST enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " ROM_BIST_COMPLETE ,BIST operation complete" "Not toggle,Toggle" textline " " hexmask.long.word 0x0c 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x0c 15. " KES_DEBUG_SHIFT_SYND ,Debug shift syndrome" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Not toggle,Toggle" bitfld.long 0x0c 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the Bus Master" "Not toggle,Toggle" bitfld.long 0x0c 11. " KES_STANDALONE ,KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " KES_DEBUG_STEP ,KES FSM to skip past the stall state" "Not toggle,Toggle" bitfld.long 0x0c 9. " KES_DEBUG_STALL ,Debug stall bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "Not toggle,Toggle" bitfld.long 0x0c 0.--5. " DEBUG_REG_SELECT ,Select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x110++0x03 line.long 0x00 "HW_BCH_DBGKESREAD,Hardware BCH ECC KES Debug Read Register" rgroup.long 0x120++0x03 line.long 0x00 "HW_BCH_DBGCSFEREAD,Hardware BCH ECC Chien Search Debug Read Register" rgroup.long 0x130++0x03 line.long 0x00 "HW_BCH_DBGSYNDGENREAD,Hardware BCH ECC Chien Search Debug Read Register" rgroup.long 0x140++0x03 line.long 0x00 "HW_BCH_DBGAHBMREAD,Hardware BCH ECC AXI Master Debug Read Register" tree.end tree "ID Registers" rgroup.long 0x150++0x03 line.long 0x00 "HW_BCH_BLOCKNAME,Hardware BCH ECC Block Name Register" rgroup.long 0x160++0x03 line.long 0x00 "HW_BCH_VERSION,Hardware BCH ECC Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end width 0xb tree.end tree "DCP (Data Co-Processor)" base asd:0x80028000 width 24. group.long 0x00++0x2f line.long 0x00 "HW_DCP_CTRL,DCP Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset DCP block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "Not present,Present" bitfld.long 0x00 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " ENABLE_CONTEXT_CACHING ,Enable caching of contexts between operations" "Disabled,Enabled" bitfld.long 0x00 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CHANNEL_INTERRUPT_ENABLE3 ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " CHANNEL_INTERRUPT_ENABLE2 ,Channel 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CHANNEL_INTERRUPT_ENABLE1 ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHANNEL_INTERRUPT_ENABLE0 ,Channel 0 interrupt enable" "Disabled,Enabled" line.long 0x04 "HW_DCP_CTRL_SET,DCP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset DCP block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "No effect,Set" bitfld.long 0x04 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "No effect,Set" textline " " bitfld.long 0x04 22. " ENABLE_CONTEXT_CACHING ,Enable caching of contexts between operations" "No effect,Set" bitfld.long 0x04 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "No effect,Set" textline " " bitfld.long 0x04 3. " CHANNEL_INTERRUPT_ENABLE3 ,Channel 3 interrupt enable" "No effect,Set" bitfld.long 0x04 2. " CHANNEL_INTERRUPT_ENABLE2 ,Channel 2 interrupt enable" "No effect,Set" textline " " bitfld.long 0x04 1. " CHANNEL_INTERRUPT_ENABLE1 ,Channel 1 interrupt enable" "No effect,Set" bitfld.long 0x04 0. " CHANNEL_INTERRUPT_ENABLE0 ,Channel 0 interrupt enable" "No effect,Set" line.long 0x08 "HW_DCP_CTRL_CLR,DCP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset DCP block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "No effect,Clear" bitfld.long 0x08 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "No effect,Clear" textline " " bitfld.long 0x08 22. " ENABLE_CONTEXT_CACHING ,Enable caching of contexts between operations" "No effect,Clear" bitfld.long 0x08 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "No effect,Clear" textline " " bitfld.long 0x08 3. " CHANNEL_INTERRUPT_ENABLE3 ,Channel 3 interrupt enable" "No effect,Clear" bitfld.long 0x08 2. " CHANNEL_INTERRUPT_ENABLE2 ,Channel 2 interrupt enable" "No effect,Clear" textline " " bitfld.long 0x08 1. " CHANNEL_INTERRUPT_ENABLE1 ,Channel 1 interrupt enable" "No effect,Clear" bitfld.long 0x08 0. " CHANNEL_INTERRUPT_ENABLE0 ,Channel 0 interrupt enable" "No effect,Clear" line.long 0x0c "HW_DCP_CTRL_TOG,DCP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset DCP block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "Not toggle,Toggle" bitfld.long 0x0c 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " ENABLE_CONTEXT_CACHING ,Enable caching of contexts between operations" "Not toggle,Toggle" bitfld.long 0x0c 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " CHANNEL_INTERRUPT_ENABLE3 ,Channel 3 interrupt enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " CHANNEL_INTERRUPT_ENABLE2 ,Channel 2 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " CHANNEL_INTERRUPT_ENABLE1 ,Channel 1 interrupt enable" "Not toggle,Toggle" bitfld.long 0x0c 0. " CHANNEL_INTERRUPT_ENABLE0 ,Channel 0 interrupt enable" "Not toggle,Toggle" line.long 0x10 "HW_DCP_STAT,DCP Status Register" bitfld.long 0x10 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "Not ready,Ready" bitfld.long 0x10 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,Reserved,Reserved,Reserved,CSC,?..." textline " " bitfld.long 0x10 19. " READY_CHANNEL3 ,Channel 3 is ready to proceed with a transfer" "Not ready,Ready" bitfld.long 0x10 18. " READY_CHANNEL2 ,Channel 2 is ready to proceed with a transfer" "Not ready,Ready" textline " " bitfld.long 0x10 17. " READY_CHANNEL1 ,Channel 1 is ready to proceed with a transfer" "Not ready,Ready" bitfld.long 0x10 16. " READY_CHANNEL0 ,Channel 0 is ready to proceed with a transfer" "Not ready,Ready" textline " " bitfld.long 0x10 3. " IRQ3 ,Channel 3 have pending interrupt request" "Not pending,Pending" bitfld.long 0x10 2. " IRQ2 ,Channel 2 have pending interrupt request" "Not pending,Pending" textline " " bitfld.long 0x10 1. " IRQ1 ,Channel 1 have pending interrupt request" "Not pending,Pending" bitfld.long 0x10 0. " IRQ0 ,Channel 0 have pending interrupt request" "Not pending,Pending" line.long 0x14 "HW_DCP_STAT_SET,DCP Status Set Register" bitfld.long 0x14 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "No effect,Set" bitfld.long 0x14 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,Reserved,Reserved,Reserved,CSC,?..." textline " " bitfld.long 0x14 19. " READY_CHANNEL3 ,Channel 3 is ready to proceed with a transfer" "No effect,Set" bitfld.long 0x14 18. " READY_CHANNEL2 ,Channel 2 is ready to proceed with a transfer" "No effect,Set" textline " " bitfld.long 0x14 17. " READY_CHANNEL1 ,Channel 1 is ready to proceed with a transfer" "No effect,Set" bitfld.long 0x14 16. " READY_CHANNEL0 ,Channel 0 is ready to proceed with a transfer" "No effect,Set" textline " " bitfld.long 0x14 3. " IRQ3 ,Channel 3 have pending interrupt request" "No effect,Set" bitfld.long 0x14 2. " IRQ2 ,Channel 2 have pending interrupt request" "No effect,Set" textline " " bitfld.long 0x14 1. " IRQ1 ,Channel 1 have pending interrupt request" "No effect,Set" bitfld.long 0x14 0. " IRQ0 ,Channel 0 have pending interrupt request" "No effect,Set" line.long 0x18 "HW_DCP_STAT_CLR,DCP Status Clear Register" bitfld.long 0x18 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "No effect,Clear" bitfld.long 0x18 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,Reserved,Reserved,Reserved,CSC,?..." textline " " bitfld.long 0x18 19. " READY_CHANNEL3 ,Channel 3 is ready to proceed with a transfer" "No effect,Clear" bitfld.long 0x18 18. " READY_CHANNEL2 ,Channel 2 is ready to proceed with a transfer" "No effect,Clear" textline " " bitfld.long 0x18 17. " READY_CHANNEL1 ,Channel 1 is ready to proceed with a transfer" "No effect,Clear" bitfld.long 0x18 16. " READY_CHANNEL0 ,Channel 0 is ready to proceed with a transfer" "No effect,Clear" textline " " bitfld.long 0x18 3. " IRQ3 ,Channel 3 have pending interrupt request" "No effect,Clear" bitfld.long 0x18 2. " IRQ2 ,Channel 2 have pending interrupt request" "No effect,Clear" textline " " bitfld.long 0x18 1. " IRQ1 ,Channel 1 have pending interrupt request" "No effect,Clear" bitfld.long 0x18 0. " IRQ0 ,Channel 0 have pending interrupt request" "No effect,Clear" line.long 0x1c "HW_DCP_STAT_TOG,DCP Status Toggle Register" bitfld.long 0x1c 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "Not toggle,Toggle" bitfld.long 0x1C 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,Reserved,Reserved,Reserved,CSC,?..." textline " " bitfld.long 0x1c 19. " READY_CHANNEL3 ,Channel 3 is ready to proceed with a transfer" "Not toggle,Toggle" bitfld.long 0x1c 18. " READY_CHANNEL2 ,Channel 2 is ready to proceed with a transfer" "Not toggle,Toggle" textline " " bitfld.long 0x1c 17. " READY_CHANNEL1 ,Channel 1 is ready to proceed with a transfer" "Not toggle,Toggle" bitfld.long 0x1c 16. " READY_CHANNEL0 ,Channel 0 is ready to proceed with a transfer" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " IRQ3 ,Channel 3 have pending interrupt request" "Not toggle,Toggle" bitfld.long 0x1c 2. " IRQ2 ,Channel 2 have pending interrupt request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " IRQ1 ,Channel 1 have pending interrupt request" "Not toggle,Toggle" bitfld.long 0x1c 0. " IRQ0 ,Channel 0 have pending interrupt request" "Not toggle,Toggle" line.long 0x20 "HW_DCP_CHANNELCTRL,DCP Channel Control Register" bitfld.long 0x20 16. " CH0_IRQ_MERGED ,Interrupt for channel 0 is merged with the other interrupts on the shared dcp_irq interrupt" "Not merged,Merged" bitfld.long 0x20 11. " HIGH_PRIORITY_CHANNEL3 ,Mark Channel 3 as high-priority" "Not marked,Marked" textline " " bitfld.long 0x20 10. " HIGH_PRIORITY_CHANNEL2 ,Mark Channel 2 as high-priority" "Not marked,Marked" bitfld.long 0x20 9. " HIGH_PRIORITY_CHANNEL1 ,Mark Channel 1 as high-priority" "Not marked,Marked" textline " " bitfld.long 0x20 8. " HIGH_PRIORITY_CHANNEL0 ,Mark Channel 0 as high-priority" "Not marked,Marked" bitfld.long 0x20 3. " ENABLE_CHANNEL3 ,Enable the DMA channel 3" "Disabled,Enabled" textline " " bitfld.long 0x20 2. " ENABLE_CHANNEL2 ,Enable the DMA channel 2" "Disabled,Enabled" bitfld.long 0x20 1. " ENABLE_CHANNEL1 ,Enable the DMA channel 1" "Disabled,Enabled" textline " " bitfld.long 0x20 0. " ENABLE_CHANNEL0 ,Enable the DMA channel 0" "Disabled,Enabled" line.long 0x24 "HW_DCP_CHANNELCTRL_SET,DCP Channel Control Set Register" bitfld.long 0x24 16. " CH0_IRQ_MERGED ,Interrupt for channel 0 is merged with the other interrupts on the shared dcp_irq interrupt" "No effect,Set" bitfld.long 0x24 11. " HIGH_PRIORITY_CHANNEL3 ,Mark Channel 3 as high-priority" "No effect,Set" textline " " bitfld.long 0x24 10. " HIGH_PRIORITY_CHANNEL2 ,Mark Channel 2 as high-priority" "No effect,Set" bitfld.long 0x24 9. " HIGH_PRIORITY_CHANNEL1 ,Mark Channel 1 as high-priority" "No effect,Set" textline " " bitfld.long 0x24 8. " HIGH_PRIORITY_CHANNEL0 ,Mark Channel 0 as high-priority" "No effect,Set" bitfld.long 0x24 3. " ENABLE_CHANNEL3 ,Enable the DMA channel 3" "No effect,Set" textline " " bitfld.long 0x24 2. " ENABLE_CHANNEL2 ,Enable the DMA channel 2" "No effect,Set" bitfld.long 0x24 1. " ENABLE_CHANNEL1 ,Enable the DMA channel 1" "No effect,Set" textline " " bitfld.long 0x24 0. " ENABLE_CHANNEL0 ,Enable the DMA channel 0" "No effect,Set" line.long 0x28 "HW_DCP_CHANNELCTRL_CLR,DCP Channel Control Clear Register" bitfld.long 0x28 16. " CH0_IRQ_MERGED ,Interrupt for channel 0 is merged with the other interrupts on the shared dcp_irq interrupt" "No effect,Clear" bitfld.long 0x28 11. " HIGH_PRIORITY_CHANNEL3 ,Mark Channel 3 as high-priority" "No effect,Clear" textline " " bitfld.long 0x28 10. " HIGH_PRIORITY_CHANNEL2 ,Mark Channel 2 as high-priority" "No effect,Clear" bitfld.long 0x28 9. " HIGH_PRIORITY_CHANNEL1 ,Mark Channel 1 as high-priority" "No effect,Clear" textline " " bitfld.long 0x28 8. " HIGH_PRIORITY_CHANNEL0 ,Mark Channel 0 as high-priority" "No effect,Clear" bitfld.long 0x28 3. " ENABLE_CHANNEL3 ,Enable the DMA channel 3" "No effect,Clear" textline " " bitfld.long 0x28 2. " ENABLE_CHANNEL2 ,Enable the DMA channel 2" "No effect,Clear" bitfld.long 0x28 1. " ENABLE_CHANNEL1 ,Enable the DMA channel 1" "No effect,Clear" textline " " bitfld.long 0x28 0. " ENABLE_CHANNEL0 ,Enable the DMA channel 0" "No effect,Clear" line.long 0x2c "HW_DCP_CHANNELCTRL_TOG,DCP Channel Control Toggle Register" bitfld.long 0x2c 16. " CH0_IRQ_MERGED ,Interrupt for channel 0 is merged with the other interrupts on the shared dcp_irq interrupt" "Not toggle,Toggle" bitfld.long 0x2c 11. " HIGH_PRIORITY_CHANNEL3 ,Mark Channel 3 as high-priority" "Not toggle,Toggle" textline " " bitfld.long 0x2c 10. " HIGH_PRIORITY_CHANNEL2 ,Mark Channel 2 as high-priority" "Not toggle,Toggle" bitfld.long 0x2c 9. " HIGH_PRIORITY_CHANNEL1 ,Mark Channel 1 as high-priority" "Not toggle,Toggle" textline " " bitfld.long 0x2c 8. " HIGH_PRIORITY_CHANNEL0 ,Mark Channel 0 as high-priority" "Not toggle,Toggle" bitfld.long 0x2c 3. " ENABLE_CHANNEL3 ,Enable the DMA channel 3" "Not toggle,Toggle" textline " " bitfld.long 0x2c 2. " ENABLE_CHANNEL2 ,Enable the DMA channel 2" "Not toggle,Toggle" bitfld.long 0x2c 1. " ENABLE_CHANNEL1 ,Enable the DMA channel 1" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " ENABLE_CHANNEL0 ,Enable the DMA channel 0" "Not toggle,Toggle" group.long 0x30++0x03 line.long 0x00 "HW_DCP_CAPABILITY0,DCP Capability 0 Register" bitfld.long 0x00 31. " DISABLE_DECRYPT ,Disable decryption" "No,Yes" bitfld.long 0x00 30. " ENABLE_TZONE ,Enable trustzone support" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--11. " NUM_CHANNELS ,Encoded value indicating the number of channels implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " NUM_KEYS ,Encoded value indicating the number of key storage locations implemented in the design" rgroup.long 0x40++0x03 line.long 0x00 "HW_DCP_CAPABILITY1,DCP Capability 1 Register" hexmask.long.word 0x00 16.--31. 1. " HASH_ALGORITHMS ,One-hot field indicating which hashing algorithms are available" hexmask.long.word 0x00 0.--15. 1. " CIPHER_ALGORITHMS ,One-hot field indicating which cipher algorithms are available" group.long 0x50++0x03 line.long 0x00 "HW_DCP_CONTEXT,DCP Context Buffer Pointer" group.long 0x60++0x03 line.long 0x00 "HW_DCP_KEY,DCP Key Index" bitfld.long 0x00 4.--5. " INDEX ,Key index pointer" "0,1,2,3" bitfld.long 0x00 0.--1. " SUBWORD ,Key subword pointer" "0,1,2,3" group.long 0x70++0x03 line.long 0x00 "HW_DCP_KEYDATA,DCP Key Data" rgroup.long 0x80++0x03 line.long 0x00 "HW_DCP_PACKET0,DCP Work Packet 0 Status Register" rgroup.long 0x90++0x03 line.long 0x00 "HW_DCP_PACKET1,DCP Work Packet 1 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Packet Tag" bitfld.long 0x00 23. " OUTPUT_WORDSWAP ,DCP engine wordswap output data" "Not swapped,Swapped" textline " " bitfld.long 0x00 22. " OUTPUT_BYTESWAP ,DCP engine byteswap output data" "Not swapped,Swapped" bitfld.long 0x00 21. " INPUT_WORDSWAP ,DCP engine wordswap input data" "Not swapped,Swapped" textline " " bitfld.long 0x00 20. " INPUT_BYTESWAP ,DCP engine byteswap input data" "Not swapped,Swapped" bitfld.long 0x00 19. " KEY_WORDSWAP ,DCP engine swap key words" "Not swapped,Swapped" textline " " bitfld.long 0x00 18. " KEY_BYTESWAP ,DCP engine swap key bytes" "Not swapped,Swapped" bitfld.long 0x00 17. " TEST_SEMA_IRQ ,Test the channel semaphore transition to 0" "Not tested,Tested" textline " " bitfld.long 0x00 16. " CONSTANT_FILL ,DCP will simply fill the destination" "No effect,Fill" bitfld.long 0x00 15. " HASH_OUTPUT ,Input or output data is hashed" "Input,Output" textline " " bitfld.long 0x00 14. " CHECK_HASH ,Calculated hash value is compared against the hash provided in the payload" "Not compared,Compared" bitfld.long 0x00 13. " HASH_TERM ,Current hashing block is the final block in the hashing operation" "Not final,Final" textline " " bitfld.long 0x00 12. " HASH_INIT ,Current hashing block is the initial block in the hashing operation" "Not initial,Initial" bitfld.long 0x00 11. " PAYLOAD_KEY ,Payload contains the key" "Not contained,Contained" textline " " bitfld.long 0x00 10. " OTP_KEY ,Use Hardware-based key" "Not used,Used" bitfld.long 0x00 9. " CIPHER_INIT ,Cipher block load the initialization vector from the payload for this operation" "Not loaded,Loaded" textline " " bitfld.long 0x00 8. " CIPHER_ENCRYPT ,Operation type" "Decrypt,Encrypt" bitfld.long 0x00 7. " ENABLE_BLIT ,Blit operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " ENABLE_HASH ,Enable selected hashing function" "Disabled,Enabled" bitfld.long 0x00 5. " ENABLE_CIPHER ,Enable slected cipher function" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " ENABLE_MEMCOPY ,Enable selected hashing function" "Disabled,Enabled" bitfld.long 0x00 3. " CHAIN_CONTIGUOUS ,Next packet address is located following this packet payload" "Not located,Located" textline " " bitfld.long 0x00 2. " CHAIN ,Next command pointer register is loaded into the channel current descriptor pointer" "Not loaded,Loaded" bitfld.long 0x00 1. " DECR_SEMAPHORE ,Channel semaphore is decremented at the end of the current operation" "Not decremented,Decremented" textline " " bitfld.long 0x00 0. " INTERRUPT ,Channel issue an interrupt upon completion of the packet" "Not issuead,Issued" rgroup.long 0xa0++0x03 line.long 0x00 "HW_DCP_PACKET2,DCP Work Packet 2 Status Register" hexmask.long.byte 0x00 24.--31. 1. " CIPHER_CFG ,Cipher configuration bits" bitfld.long 0x00 16.--19. " HASH_SELECT ,Hash Selection Field" "SHA1,CRC32,?..." textline " " hexmask.long.byte 0x00 8.--15. 1. " KEY_SELECT ,Key Selection Field" bitfld.long 0x00 4.--7. " CIPHER_MODE ,Cipher Mode Selection Field" "ECB,CBC,?..." textline " " bitfld.long 0x00 0.--3. " CIPHER_SELECT ,Cipher Selection Field" "AES128,?..." rgroup.long 0xb0++0x03 line.long 0x00 "HW_DCP_PACKET3,DCP Work Packet 3 Status Register" rgroup.long 0xc0++0x03 line.long 0x00 "HW_DCP_PACKET4,DCP Work Packet 4 Status Register" rgroup.long 0xd0++0x03 line.long 0x00 "HW_DCP_PACKET5,DCP Work Packet 5 Status Register" rgroup.long 0xe0++0x03 line.long 0x00 "HW_DCP_PACKET6,DCP Work Packet 6 Status Register" width 20. group.long 0x100++0x03 "Channel 0 Registers" line.long 0x00 "HW_DCP_CH0CMDPTR,DCP Channel 0 Command Pointer Address Register" group.long 0x110++0x03 line.long 0x00 "HW_DCP_CH0SEMA,DCP Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,The value in this field is added to the semaphore count in an atomic way" group.long 0x120++0x1f line.long 0x00 "HW_DCP_CH0STAT,DCP Channel 0 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " bitfld.long 0x00 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error" bitfld.long 0x00 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No error,Error" textline " " bitfld.long 0x00 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No error,Error" line.long 0x04 "HW_DCP_CH0STAT_SET,DCP Channel 0 Status Set Register" hexmask.long.byte 0x04 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " bitfld.long 0x04 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set" bitfld.long 0x04 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Set" textline " " bitfld.long 0x04 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Set" line.long 0x08 "HW_DCP_CH0STAT_CLR,DCP Channel 0 Status Clear Register" hexmask.long.byte 0x08 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " bitfld.long 0x08 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear" bitfld.long 0x08 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Clear" textline " " bitfld.long 0x08 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Clear" line.long 0x0c "HW_DCP_CH0STAT_TOG,DCP Channel 0 Status Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x0c 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggle,Toggle" bitfld.long 0x0c 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "Not toggle,Toggle" line.long 0x10 "HW_DCP_CH0OPTS,DCP Channel 0 Options Register" hexmask.long.word 0x10 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x14 "HW_DCP_CH0OPTS_SET,DCP Channel 0 Options Set Register" hexmask.long.word 0x14 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x18 "HW_DCP_CH0OPTS_CLR,DCP Channel 0 Options Clear Register" hexmask.long.word 0x18 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x1c "HW_DCP_CH0OPTS_TOG,DCP Channel 0 Options Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" group.long 0x140++0x03 "Channel 1 Registers" line.long 0x00 "HW_DCP_CH1CMDPTR,DCP Channel 1 Command Pointer Address Register" group.long 0x150++0x03 line.long 0x00 "HW_DCP_CH1SEMA,DCP Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,The value in this field is added to the semaphore count in an atomic way" group.long 0x160++0x1f line.long 0x00 "HW_DCP_CH1STAT,DCP Channel 1 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " bitfld.long 0x00 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error" bitfld.long 0x00 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No error,Error" textline " " bitfld.long 0x00 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No error,Error" line.long 0x04 "HW_DCP_CH1STAT_SET,DCP Channel 1 Status Set Register" hexmask.long.byte 0x04 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " bitfld.long 0x04 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set" bitfld.long 0x04 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Set" textline " " bitfld.long 0x04 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Set" line.long 0x08 "HW_DCP_CH1STAT_CLR,DCP Channel 1 Status Clear Register" hexmask.long.byte 0x08 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " bitfld.long 0x08 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear" bitfld.long 0x08 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Clear" textline " " bitfld.long 0x08 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Clear" line.long 0x0c "HW_DCP_CH1STAT_TOG,DCP Channel 1 Status Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x0c 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggle,Toggle" bitfld.long 0x0c 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "Not toggle,Toggle" line.long 0x10 "HW_DCP_CH1OPTS,DCP Channel 1 Options Register" hexmask.long.word 0x10 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x14 "HW_DCP_CH1OPTS_SET,DCP Channel 1 Options Set Register" hexmask.long.word 0x14 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x18 "HW_DCP_CH1OPTS_CLR,DCP Channel 1 Options Clear Register" hexmask.long.word 0x18 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x1c "HW_DCP_CH1OPTS_TOG,DCP Channel 1 Options Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" group.long 0x180++0x03 "Channel 2 Registers" line.long 0x00 "HW_DCP_CH2CMDPTR,DCP Channel 2 Command Pointer Address Register" group.long 0x190++0x03 line.long 0x00 "HW_DCP_CH2SEMA,DCP Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,The value in this field is added to the semaphore count in an atomic way" group.long 0x1A0++0x1f line.long 0x00 "HW_DCP_CH2STAT,DCP Channel 2 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " bitfld.long 0x00 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error" bitfld.long 0x00 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No error,Error" textline " " bitfld.long 0x00 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No error,Error" line.long 0x04 "HW_DCP_CH2STAT_SET,DCP Channel 2 Status Set Register" hexmask.long.byte 0x04 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " bitfld.long 0x04 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set" bitfld.long 0x04 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Set" textline " " bitfld.long 0x04 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Set" line.long 0x08 "HW_DCP_CH2STAT_CLR,DCP Channel 2 Status Clear Register" hexmask.long.byte 0x08 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " bitfld.long 0x08 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear" bitfld.long 0x08 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Clear" textline " " bitfld.long 0x08 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Clear" line.long 0x0c "HW_DCP_CH2STAT_TOG,DCP Channel 2 Status Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x0c 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggle,Toggle" bitfld.long 0x0c 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "Not toggle,Toggle" line.long 0x10 "HW_DCP_CH2OPTS,DCP Channel 2 Options Register" hexmask.long.word 0x10 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x14 "HW_DCP_CH2OPTS_SET,DCP Channel 2 Options Set Register" hexmask.long.word 0x14 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x18 "HW_DCP_CH2OPTS_CLR,DCP Channel 2 Options Clear Register" hexmask.long.word 0x18 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x1c "HW_DCP_CH2OPTS_TOG,DCP Channel 2 Options Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" group.long 0x1C0++0x03 "Channel 3 Registers" line.long 0x00 "HW_DCP_CH3CMDPTR,DCP Channel 3 Command Pointer Address Register" group.long 0x1D0++0x03 line.long 0x00 "HW_DCP_CH3SEMA,DCP Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,The value in this field is added to the semaphore count in an atomic way" group.long 0x1E0++0x1f line.long 0x00 "HW_DCP_CH3STAT,DCP Channel 3 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " bitfld.long 0x00 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error" bitfld.long 0x00 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No error,Error" textline " " bitfld.long 0x00 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No error,Error" line.long 0x04 "HW_DCP_CH3STAT_SET,DCP Channel 3 Status Set Register" hexmask.long.byte 0x04 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " bitfld.long 0x04 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set" bitfld.long 0x04 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Set" textline " " bitfld.long 0x04 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Set" line.long 0x08 "HW_DCP_CH3STAT_CLR,DCP Channel 3 Status Clear Register" hexmask.long.byte 0x08 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " bitfld.long 0x08 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear" bitfld.long 0x08 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Clear" textline " " bitfld.long 0x08 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Clear" line.long 0x0c "HW_DCP_CH3STAT_TOG,DCP Channel 3 Status Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x0c 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggle,Toggle" bitfld.long 0x0c 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "Not toggle,Toggle" line.long 0x10 "HW_DCP_CH3OPTS,DCP Channel 3 Options Register" hexmask.long.word 0x10 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x14 "HW_DCP_CH3OPTS_SET,DCP Channel 3 Options Set Register" hexmask.long.word 0x14 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x18 "HW_DCP_CH3OPTS_CLR,DCP Channel 3 Options Clear Register" hexmask.long.word 0x18 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x1c "HW_DCP_CH3OPTS_TOG,DCP Channel 3 Options Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" width 18. group.long 0x400++0x03 "Debug Registers" line.long 0x00 "HW_DCP_DBGSELECT,DCP Debug Select Register" hexmask.long.byte 0x00 0.--7. 1. " INDEX ,Selects a value to read via the debug data register" rgroup.long 0x410++0x03 line.long 0x00 "HW_DCP_DBGDATA,DCP Debug Data Register" rgroup.long 0x430++0x03 line.long 0x00 "HW_DCP_VERSION,DCP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-onlyl value reflecting the MAJOR version of the design implementation" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-onlyl value reflecting the MINOR version of the design implementation" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-onlyl value reflecting the stepping of version of the design implementation" width 0x0b tree.end tree "PXP (Pixel Pipeline)" base asd:0x8002a000 width 23. group.long 0x00++0x1f line.long 0x00 "HW_PXP_CTRL,PXP Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 26.--27. " INTERLACED_OUTPUT ,Determines how the PXP writes it output RGB data" "Progressive,Field 0,Field 1,Interlaced" bitfld.long 0x00 24.--25. " INTERLACED_INPUT ,Causes the fetch side of the PXP to fetch every other line from the source buffers" "Progressive,Reserved,Field 0,Field 1" textline " " bitfld.long 0x00 22. " ALPHA_OUTPUT ,Output buffer pixels should retain their alpha value from the computed alpha for that pixel" "Retain,ALPHA field" bitfld.long 0x00 21. " IN_PLACE ,Enable the PXP to perform an alpha blend operation on an existing buffer" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " CROP ,S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping" "S0 WIDTH and HEIGHT,Cropping register" bitfld.long 0x00 18. " SCALE ,Output image should be scaled" "Not scaled,Scaled" textline " " bitfld.long 0x00 12.--15. " S0_FORMAT ,Source 0 buffer format" "Reserved,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,?..." bitfld.long 0x00 11. " VFLIP ,Output buffer should be flipped vertically" "Not flipped,Flipped" textline " " bitfld.long 0x00 10. " HFLIP ,Output buffer should be flipped horizontally" "Not flipped,Flipped" bitfld.long 0x00 8.--9. " ROTATE ,Indicates the clockwise rotation to be applied at the output buffer" "0,90,180,270" textline " " bitfld.long 0x00 4.--7. " OUTPUT_RGB_FORMAT ,Target RGB framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 1. " IRQ_ENABLE ,Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLE ,Enable PXP operation with specified parameters" "Disabled,Enabled" line.long 0x04 "HW_PXP_CTRL_SET,PXP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 26.--27. " INTERLACED_OUTPUT ,Determines how the PXP writes it output RGB data" "Progressive,Field 0,Field 1,Interlaced" bitfld.long 0x04 24.--25. " INTERLACED_INPUT ,Causes the fetch side of the PXP to fetch every other line from the source buffers" "Progressive,Reserved,Field 0,Field 1" textline " " bitfld.long 0x04 22. " ALPHA_OUTPUT ,Output buffer pixels should retain their alpha value from the computed alpha for that pixel" "No effect,Set" bitfld.long 0x04 21. " IN_PLACE ,Enable the PXP to perform an alpha blend operation on an existing buffer" "No effect,Set" textline " " bitfld.long 0x04 19. " CROP ,S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping" "No effect,Set" bitfld.long 0x04 18. " SCALE ,Output image should be scaled" "No effect,Set" textline " " bitfld.long 0x04 12.--15. " S0_FORMAT ,Source 0 buffer format" "Reserved,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,?..." bitfld.long 0x04 11. " VFLIP ,Output buffer should be flipped vertically" "No effect,Set" textline " " bitfld.long 0x04 10. " HFLIP ,Output buffer should be flipped horizontally" "No effect,Set" bitfld.long 0x04 8.--9. " ROTATE ,Indicates the clockwise rotation to be applied at the output buffer" "0,90,180,270" textline " " bitfld.long 0x04 4.--7. " OUTPUT_RGB_FORMAT ,Target RGB framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x04 1. " IRQ_ENABLE ,Interrupt enable" "No effect,Set" textline " " bitfld.long 0x04 0. " ENABLE ,Enable PXP operation with specified parameters" "No effect,Set" line.long 0x08 "HW_PXP_CTRL_CLR,PXP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 26.--27. " INTERLACED_OUTPUT ,Determines how the PXP writes it output RGB data" "Progressive,Field 0,Field 1,Interlaced" bitfld.long 0x08 24.--25. " INTERLACED_INPUT ,Causes the fetch side of the PXP to fetch every other line from the source buffers" "Progressive,Reserved,Field 0,Field 1" textline " " bitfld.long 0x08 22. " ALPHA_OUTPUT ,Output buffer pixels should retain their alpha value from the computed alpha for that pixel" "No effect,Clear" bitfld.long 0x08 21. " IN_PLACE ,Enable the PXP to perform an alpha blend operation on an existing buffer" "No effect,Clear" textline " " bitfld.long 0x08 19. " CROP ,S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping" "No effect,Clear" bitfld.long 0x08 18. " SCALE ,Output image should be scaled" "No effect,Clear" textline " " bitfld.long 0x08 12.--15. " S0_FORMAT ,Source 0 buffer format" "Reserved,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,?..." bitfld.long 0x08 11. " VFLIP ,Output buffer should be flipped vertically" "No effect,Clear" textline " " bitfld.long 0x08 10. " HFLIP ,Output buffer should be flipped horizontally" "No effect,Clear" bitfld.long 0x08 8.--9. " ROTATE ,Indicates the clockwise rotation to be applied at the output buffer" "0,90,180,270" textline " " bitfld.long 0x08 4.--7. " OUTPUT_RGB_FORMAT ,Target RGB framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x08 1. " IRQ_ENABLE ,Interrupt enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " ENABLE ,Enable PXP operation with specified parameters" "No effect,Clear" line.long 0x0c "HW_PXP_CTRL_TOG,PXP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26.--27. " INTERLACED_OUTPUT ,Determines how the PXP writes it output RGB data" "Progressive,Field 0,Field 1,Interlaced" bitfld.long 0x0c 24.--25. " INTERLACED_INPUT ,Causes the fetch side of the PXP to fetch every other line from the source buffers" "Progressive,Reserved,Field 0,Field 1" textline " " bitfld.long 0x0c 22. " ALPHA_OUTPUT ,Output buffer pixels should retain their alpha value from the computed alpha for that pixel" "Not toggle,Toggle" bitfld.long 0x0c 21. " IN_PLACE ,Enable the PXP to perform an alpha blend operation on an existing buffer" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " CROP ,S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping" "Not toggle,Toggle" bitfld.long 0x0c 18. " SCALE ,Output image should be scaled" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12.--15. " S0_FORMAT ,Source 0 buffer format" "Reserved,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,?..." bitfld.long 0x0c 11. " VFLIP ,Output buffer should be flipped vertically" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " HFLIP ,Output buffer should be flipped horizontally" "Not toggle,Toggle" bitfld.long 0x0c 8.--9. " ROTATE ,Indicates the clockwise rotation to be applied at the output buffer" "0,90,180,270" textline " " bitfld.long 0x0c 4.--7. " OUTPUT_RGB_FORMAT ,Target RGB framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x0c 1. " IRQ_ENABLE ,Interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " ENABLE ,Enable PXP operation with specified parameters" "Not toggle,Toggle" line.long 0x10 "HW_PXP_STAT,PXP Status Register" hexmask.long.byte 0x10 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x10 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x10 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 2. " AXI_READ_ERROR ,PXP encountered an AXI read error and processing has been terminated" "No error,Error" textline " " bitfld.long 0x10 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error and processing has been terminated" "No error,Error" bitfld.long 0x10 0. " IRQ ,Indicates current PXP interrupt status" "Not occurred,Occurred" line.long 0x14 "HW_PXP_STAT_SET,PXP Status Set Register" hexmask.long.byte 0x14 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x14 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x14 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 2. " AXI_READ_ERROR ,PXP encountered an AXI read error and processing has been terminated" "No effect,Set" textline " " bitfld.long 0x14 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error and processing has been terminated" "No effect,Set" bitfld.long 0x14 0. " IRQ ,Indicates current PXP interrupt status" "No effect,Set" line.long 0x18 "HW_PXP_STAT_CLR,PXP Status Clear Register" hexmask.long.byte 0x18 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x18 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x18 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 2. " AXI_READ_ERROR ,PXP encountered an AXI read error and processing has been terminated" "No effect,Clear" textline " " bitfld.long 0x18 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error and processing has been terminated" "No effect,Clear" bitfld.long 0x18 0. " IRQ ,Indicates current PXP interrupt status" "No effect,Clear" line.long 0x1c "HW_PXP_STAT_TOG,PXP Status Toggle Register" hexmask.long.byte 0x1c 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x1c 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x1c 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1c 2. " AXI_READ_ERROR ,PXP encountered an AXI read error and processing has been terminated" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error and processing has been terminated" "Not toggle,Toggle" bitfld.long 0x1c 0. " IRQ ,Indicates current PXP interrupt status" "Not toggle,Toggle" group.long 0x20++0x03 line.long 0x00 "HW_PXP_RGBBUF,RGB Output Frame Buffer Pointer" group.long 0x30++0x03 line.long 0x00 "HW_PXP_RGBBUF2,RGB Output Frame Buffer Pointer #2" group.long 0x40++0x03 line.long 0x00 "HW_PXP_RGBSIZE,PXP Output Buffer Size" hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,When generating an output RGB buffer with an alpha component, the value in this field will be used" hexmask.long.word 0x00 12.--23. 1. " WIDTH ,Number of horizontal PIXELS in the image" textline " " hexmask.long.word 0x00 0.--11. 1. " HEIGHT ,Number of vertical PIXELS in the image" group.long 0x50++0x03 line.long 0x00 "HW_PXP_S0BUF,PXP Source 0 (video) Input Buffer Pointer" group.long 0x60++0x03 line.long 0x00 "HW_PXP_S0UBUF,Source 0 U/Cb Input Buffer Pointer" group.long 0x70++0x03 line.long 0x00 "HW_PXP_S0VBUF,Source 0 V/Cr Input Buffer Pointer" group.long 0x80++0x03 line.long 0x00 "HW_PXP_S0PARAM,PXP Source 0 (video) Buffer Parameters" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,Horizontal offset location (in 8x8 block) of the S0 buffer within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Vertical offset location (in 8x8 block) of the S0 buffer within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x90++0x03 line.long 0x00 "HW_PXP_S0BACKGROUND,Source 0 Background Color" group.long 0xa0++0x03 line.long 0x00 "HW_PXP_S0CROP,Source 0 Cropping Register" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,Horizontal offset (in terms of 8-pixel blocks) into the S0 buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Vertical offset (in terms of 8-pixel blocks) into the S0 buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Ouput buffer cropped video width" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Input buffer cropped video height" group.long 0xb0++0x03 line.long 0x00 "HW_PXP_S0SCALE,Source 0 Scale Factor Register" hexmask.long.word 0x00 16.--29. 1. " YSCALE ,Y scaling factor for the S0 source buffer" hexmask.long.word 0x00 0.--13. 1. " XSCALE ,X scaling factor for the S0 source buffer" group.long 0xc0++0x03 line.long 0x00 "HW_PXP_S0OFFSET,Source 0 Scale Offset Register" hexmask.long.word 0x00 16.--27. 1. " YOFFSET ,Y scaling offset" hexmask.long.word 0x00 0.--15. 1. " XOFFSET ,X scaling offset" group.long 0xd0++0x03 line.long 0x00 "HW_PXP_CSCCOEFF0,Color Space Conversion Coefficient Register 0" bitfld.long 0x00 31. " YCBCR_MODE ,Conversion type" "YUV to RGB,YCbCR to RGB" hexmask.long.word 0x00 18.--28. 1. " C0 ,Y multiplier coefficient" textline " " hexmask.long.word 0x00 9.--17. 1. " UV_OFFSET ,Phase offset implicit for UV data" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Amplitude offset implicit in the Y data" group.long 0xe0++0x03 line.long 0x00 "HW_PXP_CSCCOEFF1,Color Space Conversion Coefficient Register 1" hexmask.long.word 0x00 16.--26. 1. " C1 ,Red V/Cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C4 ,Blue U/Cb multiplier coefficient" group.long 0xf0++0x03 line.long 0x00 "HW_PXP_CSCCOEFF2,Color Space Conversion Coefficient Register 2" hexmask.long.word 0x00 16.--26. 1. " C2 ,Green V/Cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C3 ,Green U/Cb multiplier coefficient" group.long 0x100++0x0f line.long 0x00 "HW_PXP_NEXT,PXP Next Frame Pointer" hexmask.long 0x00 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" bitfld.long 0x00 0. " ENABLED ,Next frame functionality has been enabled" "Disabled,Enabled" line.long 0x04 "HW_PXP_NEXT_SET,PXP Next Frame Pointer Set" hexmask.long 0x04 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" bitfld.long 0x04 0. " ENABLED ,Next frame functionality has been enabled" "No effect,Set" line.long 0x08 "HW_PXP_NEXT_CLR,PXP Next Frame Pointer Clear" hexmask.long 0x08 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" bitfld.long 0x08 0. " ENABLED ,Next frame functionality has been enabled" "No effect,Clear" line.long 0x0c "HW_PXP_NEXT_TOG,PXP Next Frame Pointer Toggle" hexmask.long 0x0c 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" bitfld.long 0x0c 0. " ENABLED ,Next frame functionality has been enabled" "Not toggle,Toggle" group.long 0x180++0x03 line.long 0x00 "HW_PXP_S0COLORKEYLOW,PXP S0 Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to S0 buffer" group.long 0x190++0x03 line.long 0x00 "HW_PXP_S0COLORKEYHIGH,PXP S0 Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to S0 buffer" group.long 0x1a0++0x03 line.long 0x00 "HW_PXP_OLCOLORKEYLOW,PXP Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to OL buffer" group.long 0x1b0++0x03 line.long 0x00 "HW_PXP_OLCOLORKEYHIGH,PXP Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to OL buffer" group.long 0x1d0++0x03 line.long 0x00 "HW_PXP_DEBUGCTRL,PXP Debug Control Register" hexmask.long.byte 0x00 0.--7. 1. " SELECT ,Index into one of the PXP debug registers" rgroup.long 0x1e0++0x03 line.long 0x00 "HW_PXP_DEBUG,PXP Debug Register" rgroup.long 0x1f0++0x03 line.long 0x00 "HW_PXP_VERSION,PXP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0x200++0x03 "PXP Overlay 0" line.long 0x00 "HW_PXP_OL0,PXP Overlay 0 Buffer Pointer" group.long 0x210++0x03 line.long 0x00 "HW_PXP_OL0SIZE,PXP Overlay 0 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x220++0x03 line.long 0x00 "HW_PXP_OL0PARAM,PXP Overlay 0 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x240++0x03 hide.long 0x00 "HW_PXP_OL0PARAM2,PXP Overlay 0 Parameters 2" group.long 0x240++0x03 "PXP Overlay 1" line.long 0x00 "HW_PXP_OL1,PXP Overlay 1 Buffer Pointer" group.long 0x250++0x03 line.long 0x00 "HW_PXP_OL1SIZE,PXP Overlay 1 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x260++0x03 line.long 0x00 "HW_PXP_OL1PARAM,PXP Overlay 1 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x280++0x03 hide.long 0x00 "HW_PXP_OL1PARAM2,PXP Overlay 1 Parameters 2" group.long 0x280++0x03 "PXP Overlay 2" line.long 0x00 "HW_PXP_OL2,PXP Overlay 2 Buffer Pointer" group.long 0x290++0x03 line.long 0x00 "HW_PXP_OL2SIZE,PXP Overlay 2 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x2A0++0x03 line.long 0x00 "HW_PXP_OL2PARAM,PXP Overlay 2 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x2C0++0x03 hide.long 0x00 "HW_PXP_OL2PARAM2,PXP Overlay 2 Parameters 2" group.long 0x2C0++0x03 "PXP Overlay 3" line.long 0x00 "HW_PXP_OL3,PXP Overlay 3 Buffer Pointer" group.long 0x2D0++0x03 line.long 0x00 "HW_PXP_OL3SIZE,PXP Overlay 3 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x2E0++0x03 line.long 0x00 "HW_PXP_OL3PARAM,PXP Overlay 3 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x300++0x03 hide.long 0x00 "HW_PXP_OL3PARAM2,PXP Overlay 3 Parameters 2" group.long 0x300++0x03 "PXP Overlay 4" line.long 0x00 "HW_PXP_OL4,PXP Overlay 4 Buffer Pointer" group.long 0x310++0x03 line.long 0x00 "HW_PXP_OL4SIZE,PXP Overlay 4 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x320++0x03 line.long 0x00 "HW_PXP_OL4PARAM,PXP Overlay 4 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x340++0x03 hide.long 0x00 "HW_PXP_OL4PARAM2,PXP Overlay 4 Parameters 2" group.long 0x340++0x03 "PXP Overlay 5" line.long 0x00 "HW_PXP_OL5,PXP Overlay 5 Buffer Pointer" group.long 0x350++0x03 line.long 0x00 "HW_PXP_OL5SIZE,PXP Overlay 5 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x360++0x03 line.long 0x00 "HW_PXP_OL5PARAM,PXP Overlay 5 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x380++0x03 hide.long 0x00 "HW_PXP_OL5PARAM2,PXP Overlay 5 Parameters 2" group.long 0x380++0x03 "PXP Overlay 6" line.long 0x00 "HW_PXP_OL6,PXP Overlay 6 Buffer Pointer" group.long 0x390++0x03 line.long 0x00 "HW_PXP_OL6SIZE,PXP Overlay 6 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x3A0++0x03 line.long 0x00 "HW_PXP_OL6PARAM,PXP Overlay 6 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x3C0++0x03 hide.long 0x00 "HW_PXP_OL6PARAM2,PXP Overlay 6 Parameters 2" group.long 0x3C0++0x03 "PXP Overlay 7" line.long 0x00 "HW_PXP_OL7,PXP Overlay 7 Buffer Pointer" group.long 0x3D0++0x03 line.long 0x00 "HW_PXP_OL7SIZE,PXP Overlay 7 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x3E0++0x03 line.long 0x00 "HW_PXP_OL7PARAM,PXP Overlay 7 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x400++0x03 hide.long 0x00 "HW_PXP_OL7PARAM2,PXP Overlay 7 Parameters 2" width 0xb tree.end tree "LCDIF (LCD Interface)" base asd:0x80030000 width 25. group.long 0x00++0x0f line.long 0x00 "HW_LCDIF_CTRL,LCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "0,1" bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "Not wait,Wait" textline " " bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "Left,Right" bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "Disabled,Enabled" bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass Count" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 18. " VSYNC_MODE ,Enable VSYNC mode" "Disabled,Enabled" bitfld.long 0x00 17. " DOTCLK_MODE ,Enable DOTCLK mode" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " DATA_SELECT ,Command Mode polarity bit" "Command mode,Data mode" bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" textline " " bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" textline " " bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "PIO mode,Master" bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "RGB565,ARGB555" textline " " bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "Lower 18 bits valid,Upper 18 bits valid" bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "All 24 bits valid,Drop upper 2 bits per byte" textline " " bitfld.long 0x00 0. " RUN ,Start LCDIF" "No effect,Start" line.long 0x04 "HW_LCDIF_CTRL_SET,LCDIF General Control Set Register" bitfld.long 0x04 31. " SFTRST ,Block level reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "No effect,Set" bitfld.long 0x04 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "No effect,Set" textline " " bitfld.long 0x04 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "No effect,Set" bitfld.long 0x04 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "No effect,Set" bitfld.long 0x04 19. " BYPASS_COUNT ,Bypass Count" "No effect,Set" textline " " bitfld.long 0x04 18. " VSYNC_MODE ,Enable VSYNC mode" "No effect,Set" bitfld.long 0x04 17. " DOTCLK_MODE ,Enable DOTCLK mode" "No effect,Set" textline " " bitfld.long 0x04 16. " DATA_SELECT ,Command Mode polarity bit" "No effect,Set" bitfld.long 0x04 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" textline " " bitfld.long 0x04 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" bitfld.long 0x04 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" textline " " bitfld.long 0x04 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x04 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "No effect,Set" textline " " bitfld.long 0x04 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "No effect,Set" bitfld.long 0x04 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "No effect,Set" textline " " bitfld.long 0x04 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "No effect,Set" bitfld.long 0x04 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "No effect,Set" textline " " bitfld.long 0x04 0. " RUN ,Start LCDIF" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL_CLR,LCDIF General Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Block level reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "No effect,Clear" bitfld.long 0x08 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "No effect,Clear" textline " " bitfld.long 0x08 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "No effect,Clear" bitfld.long 0x08 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x08 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "No effect,Clear" bitfld.long 0x08 19. " BYPASS_COUNT ,Bypass Count" "No effect,Clear" textline " " bitfld.long 0x08 18. " VSYNC_MODE ,Enable VSYNC mode" "No effect,Clear" bitfld.long 0x08 17. " DOTCLK_MODE ,Enable DOTCLK mode" "No effect,Clear" textline " " bitfld.long 0x08 16. " DATA_SELECT ,Command Mode polarity bit" "No effect,Clear" bitfld.long 0x08 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" textline " " bitfld.long 0x08 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" bitfld.long 0x08 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" textline " " bitfld.long 0x08 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x08 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "No effect,Clear" textline " " bitfld.long 0x08 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "No effect,Clear" bitfld.long 0x08 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "No effect,Clear" textline " " bitfld.long 0x08 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "No effect,Clear" bitfld.long 0x08 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "No effect,Clear" textline " " bitfld.long 0x08 0. " RUN ,Start LCDIF" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL_TOG,LCDIF General Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Block level reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "Not toggle,Toggle" bitfld.long 0x0c 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "Not toggle,Toggle" bitfld.long 0x0c 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0c 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "Not toggle,Toggle" bitfld.long 0x0c 19. " BYPASS_COUNT ,Bypass Count" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " VSYNC_MODE ,Enable VSYNC mode" "Not toggle,Toggle" bitfld.long 0x0c 17. " DOTCLK_MODE ,Enable DOTCLK mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " DATA_SELECT ,Command Mode polarity bit" "Not toggle,Toggle" bitfld.long 0x0c 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" textline " " bitfld.long 0x0c 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" bitfld.long 0x0c 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" textline " " bitfld.long 0x0c 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x0c 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "Not toggle,Toggle" bitfld.long 0x0c 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "Not toggle,Toggle" bitfld.long 0x0c 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " RUN ,Start LCDIF" "Not toggle,Toggle" if (((d.l(asd:(0x80030000+0x00)))&0x300)==0x100) ;8-bit group.long 0x10++0x0f line.long 0x00 "HW_LCDIF_CTRL1,LCDIF General Control1 Register" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched" textline " " bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst" bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" textline " " bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field" bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid" textline " " bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Toggle/High,Low" bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode" bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High" line.long 0x04 "HW_LCDIF_CTRL1_SET,LCDIF General Control1 Set Register" bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set" bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set" bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set" textline " " bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set" bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set" textline " " bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set" bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid" textline " " bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set" bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set" textline " " bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set" bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set" textline " " bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Set" bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set" textline " " bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set" bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL1_CLR,LCDIF General Control1 Clear Register" bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear" bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear" bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear" textline " " bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear" bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear" bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid" textline " " bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear" bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear" bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear" textline " " bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Clear" bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear" textline " " bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear" bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL1_TOG,LCDIF General Control1 Toggle Register" bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle" bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle" bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle" bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid" textline " " bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle" bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle" bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle" elif (((d.l(asd:(0x80030000+0x00)))&0x300)==0x00) ;16-bit group.long 0x10++0x0f line.long 0x00 "HW_LCDIF_CTRL1,LCDIF General Control1 Register" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched" textline " " bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst" bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" textline " " bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field" bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid" textline " " bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Toggle/High,Low" bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode" bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High" line.long 0x04 "HW_LCDIF_CTRL1_SET,LCDIF General Control1 Set Register" bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set" bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set" bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set" textline " " bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set" bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set" textline " " bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set" bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid" textline " " bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set" bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set" textline " " bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set" bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set" textline " " bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Set" bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set" textline " " bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set" bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL1_CLR,LCDIF General Control1 Clear Register" bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear" bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear" bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear" textline " " bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear" bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear" bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid" textline " " bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear" bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear" bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear" textline " " bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Clear" bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear" textline " " bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear" bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL1_TOG,LCDIF General Control1 Toggle Register" bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle" bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle" bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle" bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid" textline " " bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle" bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle" bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle" elif (((d.l(asd:(0x80030000+0x00)))&0x300)==0x200) ;18-bit group.long 0x10++0x0f line.long 0x00 "HW_LCDIF_CTRL1,LCDIF General Control1 Register" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched" textline " " bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst" bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" textline " " bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field" bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" textline " " bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Toggle/High,Low" bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode" bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High" line.long 0x04 "HW_LCDIF_CTRL1_SET,LCDIF General Control1 Set Register" bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set" bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set" bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set" textline " " bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set" bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set" textline " " bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set" bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" textline " " bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set" bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set" textline " " bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set" bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set" textline " " bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Set" bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set" textline " " bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set" bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL1_CLR,LCDIF General Control1 Clear Register" bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear" bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear" bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear" textline " " bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear" bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear" bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" textline " " bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear" bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear" bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear" textline " " bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Clear" bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear" textline " " bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear" bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL1_TOG,LCDIF General Control1 Toggle Register" bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle" bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle" bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle" bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" textline " " bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle" bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle" bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle" else ;24-bit group.long 0x10++0x0f line.long 0x00 "HW_LCDIF_CTRL1,LCDIF General Control1 Register" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled" bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled" bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched" textline " " bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst" bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" textline " " bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field" bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" textline " " bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled" bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled" bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Toggle/High,Low" bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode" bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High" line.long 0x04 "HW_LCDIF_CTRL1_SET,LCDIF General Control1 Set Register" bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set" bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set" bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set" textline " " bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set" bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set" textline " " bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set" bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" textline " " bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set" bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set" textline " " bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set" bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set" textline " " bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Set" bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set" textline " " bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set" bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL1_CLR,LCDIF General Control1 Clear Register" bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear" bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear" bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear" textline " " bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear" bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear" bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" textline " " bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear" bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear" bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear" textline " " bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "No effect,Clear" bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear" textline " " bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear" bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL1_TOG,LCDIF General Control1 Toggle Register" bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle" bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle" bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle" bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" textline " " bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle" bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " LCD_CS_CTRL ,LCD CS Control (VSYNC/DOTCLK)" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle" bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle" endif group.long 0x20++0x03 line.long 0x00 "HW_LCDIF_TRANSFER_COUNT,LCDIF Horizontal and Vertical Valid Data Count Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data" hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (pixels) in each horizontal line" group.long 0x30++0x03 line.long 0x00 "HW_LCDIF_CUR_BUF,LCD Interface Current Buffer Address Register" group.long 0x40++0x03 line.long 0x00 "HW_LCDIF_NEXT_BUF,LCD Interface Next Buffer Address Register" group.long 0x60++0x03 line.long 0x00 "HW_LCDIF_TIMING,LCD Interface Timing Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of PIXCLK cycles that the DCn signal is active after CEn is deasserted" hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of PIXCLK cycles that the the DCn signal is active before CEn is asserted" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in PIXCLK cycles" hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in PIXCLK cycles" group.long 0x70++0x0f line.long 0x00 "HW_LCDIF_VDCTRL0,LCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC pin mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "Not generated,Generated" textline " " bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Normal,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Normal,Inverted" textline " " bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Normal,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,ENABLE polarity" "Normal,Inverted" textline " " bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "PIXCLKS,Complete horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "PIXCLKS,Complete horizontal lines" textline " " bitfld.long 0x00 19. " HALF_LINE ,Half line (VSYNC period equal to)" "VSYNC,VSYNC + 1/2 HORIZONTAL" bitfld.long 0x00 18. " HALF_LINE_MODE ,Half line mode " "First/Second,All/None" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x04 "HW_LCDIF_VDCTRL0_SET,LCDIF VSYNC Mode and Dotclk Mode Control Set Register 0" bitfld.long 0x04 29. " VSYNC_OEB ,VSYNC pin mode" "No effect,Set" bitfld.long 0x04 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "No effect,Set" textline " " bitfld.long 0x04 27. " VSYNC_POL ,VSYNC polarity" "No effect,Set" bitfld.long 0x04 26. " HSYNC_POL ,HSYNC polarity" "No effect,Set" textline " " bitfld.long 0x04 25. " DOTCLK_POL ,DOTCLK polarity" "No effect,Set" bitfld.long 0x04 24. " ENABLE_POL ,ENABLE polarity" "No effect,Set" textline " " bitfld.long 0x04 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "No effect,Set" bitfld.long 0x04 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "No effect,Set" textline " " bitfld.long 0x04 19. " HALF_LINE ,Half line (VSYNC period equal to)" "No effect,Set" bitfld.long 0x04 18. " HALF_LINE_MODE ,Half line mode " "No effect,Set" textline " " hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x08 "HW_LCDIF_VDCTRL0_CLR,LCDIF VSYNC Mode and Dotclk Mode Control Clear Register 0" bitfld.long 0x08 29. " VSYNC_OEB ,VSYNC pin mode" "No effect,Clear" bitfld.long 0x08 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "No effect,Clear" textline " " bitfld.long 0x08 27. " VSYNC_POL ,VSYNC polarity" "No effect,Clear" bitfld.long 0x08 26. " HSYNC_POL ,HSYNC polarity" "No effect,Clear" textline " " bitfld.long 0x08 25. " DOTCLK_POL ,DOTCLK polarity" "No effect,Clear" bitfld.long 0x08 24. " ENABLE_POL ,ENABLE polarity" "No effect,Clear" textline " " bitfld.long 0x08 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "No effect,Clear" bitfld.long 0x08 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "No effect,Clear" textline " " bitfld.long 0x08 19. " HALF_LINE ,Half line (VSYNC period equal to)" "No effect,Clear" bitfld.long 0x08 18. " HALF_LINE_MODE ,Half line mode " "No effect,Clear" textline " " hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x0c "HW_LCDIF_VDCTRL0_TOG,LCDIF VSYNC Mode and Dotclk Mode Control Toggle Register 0" bitfld.long 0x0c 29. " VSYNC_OEB ,VSYNC pin mode" "Not toggle,Toggle" bitfld.long 0x0c 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " VSYNC_POL ,VSYNC polarity" "Not toggle,Toggle" bitfld.long 0x0c 26. " HSYNC_POL ,HSYNC polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " DOTCLK_POL ,DOTCLK polarity" "Not toggle,Toggle" bitfld.long 0x0c 24. " ENABLE_POL ,ENABLE polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "Not toggle,Toggle" bitfld.long 0x0c 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " HALF_LINE ,Half line (VSYNC period equal to)" "Not toggle,Toggle" bitfld.long 0x0c 18. " HALF_LINE_MODE ,Half line mode " "Not toggle,Toggle" textline " " hexmask.long.tbyte 0x0c 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" group.long 0x80++0x03 line.long 0x00 "HW_LCDIF_VDCTRL1,LCDIF VSYNC Mode and Dotclk Mode Control Register 1" group.long 0x90++0x03 line.long 0x00 "HW_LCDIF_VDCTRL2,LCDIF VSYNC Mode and Dotclk Mode Control Register 2" hexmask.long.byte 0x00 24.--31. 1. " HSYNC_PULSE_WIDTH ,Number of PIXCLKs for which HSYNC signal is active" hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of PIXCLKs between two positive or two negative edges of the HSYNC signal" group.long 0xa0++0x03 line.long 0x00 "HW_LCDIF_VDCTRL3,LCDIF VSYNC Mode and Dotclk Mode Control Register 3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Mux sync signals (HSYNC with LCD_D14,DOTCLK with LCD_D13,ENABLE with LCD_D12)" "Not muxed,Muxed" bitfld.long 0x00 28. " VSYNC_ONLY ,VSYNC only" "DOTCLK,VSYNC" textline " " hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Horizontal wait count" hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Vertical wait count" group.long 0xb0++0x03 line.long 0x00 "HW_LCDIF_VDCTRL4,LCDIF VSYNC Mode and Dotclk Mode Control Register 4" bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,Sync signals active at least one frame before data" "Not active,Active" hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of PIXCLKs on each horizontal line that carry valid data in DOTCLK mode" group.long 0xc0++0x03 line.long 0x00 "HW_LCDIF_DVICTRL0,Digital Video Interface Control 0 Register" hexmask.long.word 0x00 20.--30. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted" hexmask.long.word 0x00 10.--19. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval" textline " " hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Total number of vertical lines per frame" group.long 0xd0++0x03 line.long 0x00 "HW_LCDIF_DVICTRL1,Digital Video Interface Control 1 Register" hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which Field 1 begins" hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which Field1 ends" textline " " hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which Field 2 begins" group.long 0xe0++0x03 line.long 0x00 "HW_LCDIF_DVICTRL2,Digital Video Interface Control 2 Register" hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which Field 2 ends" hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of Field1" textline " " hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of Field2" group.long 0xf0++0x03 line.long 0x00 "HW_LCDIF_DVICTRL3,Digital Video Interface Control 3 Register" hexmask.long.word 0x00 16.--25. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of Field2" hexmask.long.word 0x00 0.--9. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of Field1" group.long 0x100++0x03 line.long 0x00 "HW_LCDIF_DVICTRL4,Digital Video Interface Control 4 Register" hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data" hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data" textline " " hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data" hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval" group.long 0x110++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF0,RGB to YCbCr 4:2:2 CSC Coefficient 0 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Two complement red multiplier coefficient for Y" bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme to be performed on the chroma components" "Sample and hold,Reserved,Interstitial,Cosited" group.long 0x120++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF1,RGB to YCbCr 4:2:2 CSC Coefficient 1 Register" hexmask.long.word 0x00 16.--25. 1. " C2 ,Two complement blue multiplier coefficient for Y" hexmask.long.word 0x00 0.--9. 1. " C1 ,Two complement green multiplier coefficient for Y" group.long 0x130++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF2,RGB to YCbCr 4:2:2 CSC Coefficent 2 Register" hexmask.long.word 0x00 16.--25. 1. " C4 ,Two complement green multiplier coefficient for Cb" hexmask.long.word 0x00 0.--9. 1. " C3 ,Two complement red multiplier coefficient for Cb" group.long 0x140++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF3,RGB to YCbCr 4:2:2 CSC Coefficient 3 Register" hexmask.long.word 0x00 16.--25. 1. " C6 ,Two complement red multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C5 ,Two complement blue multiplier coefficient for Cb" group.long 0x150++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF4,RGB to YCbCr 4:2:2 CSC Coefficient 4 Register" hexmask.long.word 0x00 16.--25. 1. " C8 ,Two complement blue multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C7 ,Two complement green multiplier coefficient for Cr" group.long 0x160++0x03 line.long 0x00 "HW_LCDIF_CSC_OFFSET,RGB to YCbCr 4:2:2 CSC Offset Register" hexmask.long.word 0x00 16.--24. 1. " CBCR_OFFSET ,Two complement offset for the Cb and Cr components" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two complement offset for the Y component" group.long 0x170++0x03 line.long 0x00 "HW_LCDIF_CSC_LIMIT,RGB to YCbCr 4:2:2 CSC Limit Register" hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" textline " " hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 YCbCr conversion" group.long 0x1b0++0x03 line.long 0x00 "HW_LCDIF_DATA,LCD Interface Data Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (most significant byte) of data written to LCDIF by the CPU" hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to LCDIF by the CPU" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to LCDIF by the CPU" hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (least significant byte) of data written to LCDIF by the CPU" group.long 0x1c0++0x03 line.long 0x00 "HW_LCDIF_BM_ERROR_STAT,Bus Master Error Status Register" rgroup.long 0x1d0++0x03 line.long 0x00 "HW_LCDIF_STAT,LCD Interface Status Register" bitfld.long 0x00 31. " PRESENT ,LCDIF is present" "Not present,Present" bitfld.long 0x00 30. " DMA_REQ ,Reflects the current state of the DMA Request line for the LCDIF" "Not requested,Requested" textline " " bitfld.long 0x00 29. " LFIFO_FULL ,LCD read datapath FIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,LCD read datapath FIFO is empty" "Not empty,Empty" textline " " bitfld.long 0x00 27. " TXFIFO_FULL ,LCD write datapath FIFO is full" "Not full,Full" bitfld.long 0x00 26. " TXFIFO_EMPTY ,LCD write datapath FIFO is empty" "Not empty,Empty" textline " " bitfld.long 0x00 25. " BUSY ,View of the input busy signal from the external LCD controller" "Not busy,Busy" bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,View of the current field being transmitted" "Field 1,Field 2" group.long 0x1e0++0x03 line.long 0x00 "HW_LCDIF_VERSION,LCD Interface Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" rgroup.long 0x1f0++0x03 line.long 0x00 "HW_LCDIF_DEBUG0,LCD Interface Debug 0 Register" bitfld.long 0x00 31. " STREAMING_END_DETECTED ,view of the DOTCLK_MODE or DVI_MODE bit going from 1 to 0" "0,1" bitfld.long 0x00 30. " WAIT_FOR_VSYNC_EDGE_OUT ,view of WAIT_FOR_VSYNC_EDGE bit in the VSYNC mode after it comes out of the TXFIFO" "0,1" textline " " bitfld.long 0x00 29. " SYNC_SIGNALS_ON_REG ,View of internal sync_signals_on_reg signal" "0,1" bitfld.long 0x00 27. " ENABLE ,View of ENABLE signal" "0,1" textline " " bitfld.long 0x00 26. " HSYNC ,View of HSYNC signal" "0,1" bitfld.long 0x00 25. " VSYNC ,View of VSYNC signal" "0,1" textline " " bitfld.long 0x00 24. " CUR_FRAME_TX ,Current Frame is being transmitted in the VSYNC mode" "No,Yes" bitfld.long 0x00 23. " EMPTY_WORD ,Indicates that the current word is empty" "Not empty,Empty" textline " " hexmask.long.byte 0x00 16.--22. 1. " CUR_STATE ,View of the current state machine state in the current mode of operation" rgroup.long 0x200++0x03 line.long 0x00 "HW_LCDIF_DEBUG1,LCD Interface Debug 1 Register" hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,View of the current state of the horizontal data counter" hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,view of the current state of the vertical data counter" width 0xb tree.end tree "TVENC (TV-Out NTSC/PAL Encoder)" base asd:0x80038000 width 28. group.long 0x00++0x0f line.long 0x00 "HW_TVENC_CTRL,TV Encoder Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a block wide reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 29. " TVENC_MACROVISION_PRESENT ,TV Encoder is present in this product" "Not present,Present" bitfld.long 0x00 28. " TVENC_COMPOSITE_PRESENT ,TV Encoder is present in this product" "Not present,Present" textline " " bitfld.long 0x00 27. " TVENC_SVIDEO_PRESENT ,TV Encoder is present in this product" "Not present,Present" bitfld.long 0x00 26. " TVENC_COMPONENT_PRESENT ,TV Encoder is present in this product" "Not present,Present" textline " " bitfld.long 0x00 5. " DAC_FIFO_NO_WRITE ,Prohibit writes the DAC data fifo" "Not prohibited,Prohibited" bitfld.long 0x00 4. " DAC_FIFO_NO_READ ,Prohibit reads from the DAC data fifo" "Not prohibited,Prohibited" textline " " bitfld.long 0x00 3. " DAC_DATA_FIFO_RST ,Clear the DAC data FIFO and reset the FIFO pointers" "No reset,Reset" bitfld.long 0x00 0. " DAC_MUX_MODE ,Specifies the meaning of the output stream to each DAC" "Default,DAC Test mode" line.long 0x04 "HW_TVENC_CTRL_SET,TV Encoder Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a block wide reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " TVENC_MACROVISION_PRESENT ,TV Encoder is present in this product" "No effect,Set" bitfld.long 0x04 28. " TVENC_COMPOSITE_PRESENT ,TV Encoder is present in this product" "No effect,Set" textline " " bitfld.long 0x04 27. " TVENC_SVIDEO_PRESENT ,TV Encoder is present in this product" "No effect,Set" bitfld.long 0x04 26. " TVENC_COMPONENT_PRESENT ,TV Encoder is present in this product" "No effect,Set" textline " " bitfld.long 0x04 5. " DAC_FIFO_NO_WRITE ,Prohibit writes the DAC data fifo" "No effect,Set" bitfld.long 0x04 4. " DAC_FIFO_NO_READ ,Prohibit reads from the DAC data fifo" "No effect,Set" textline " " bitfld.long 0x04 3. " DAC_DATA_FIFO_RST ,Clear the DAC data FIFO and reset the FIFO pointers" "No effect,Set" bitfld.long 0x04 0. " DAC_MUX_MODE ,Specifies the meaning of the output stream to each DAC" "No effect,Set" line.long 0x08 "HW_TVENC_CTRL_CLR,TV Encoder Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a block wide reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " TVENC_MACROVISION_PRESENT ,TV Encoder is present in this product" "No effect,Clear" bitfld.long 0x08 28. " TVENC_COMPOSITE_PRESENT ,TV Encoder is present in this product" "No effect,Clear" textline " " bitfld.long 0x08 27. " TVENC_SVIDEO_PRESENT ,TV Encoder is present in this product" "No effect,Clear" bitfld.long 0x08 26. " TVENC_COMPONENT_PRESENT ,TV Encoder is present in this product" "No effect,Clear" textline " " bitfld.long 0x08 5. " DAC_FIFO_NO_WRITE ,Prohibit writes the DAC data fifo" "No effect,Clear" bitfld.long 0x08 4. " DAC_FIFO_NO_READ ,Prohibit reads from the DAC data fifo" "No effect,Clear" textline " " bitfld.long 0x08 3. " DAC_DATA_FIFO_RST ,Clear the DAC data FIFO and reset the FIFO pointers" "No effect,Clear" bitfld.long 0x08 0. " DAC_MUX_MODE ,Specifies the meaning of the output stream to each DAC" "No effect,Clear" line.long 0x0c "HW_TVENC_CTRL_TOG,TV Encoder Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a block wide reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " TVENC_MACROVISION_PRESENT ,TV Encoder is present in this product" "Not toggle,Toggle" bitfld.long 0x0c 28. " TVENC_COMPOSITE_PRESENT ,TV Encoder is present in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " TVENC_SVIDEO_PRESENT ,TV Encoder is present in this product" "Not toggle,Toggle" bitfld.long 0x0c 26. " TVENC_COMPONENT_PRESENT ,TV Encoder is present in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " DAC_FIFO_NO_WRITE ,Prohibit writes the DAC data fifo" "Not toggle,Toggle" bitfld.long 0x0c 4. " DAC_FIFO_NO_READ ,Prohibit reads from the DAC data fifo" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " DAC_DATA_FIFO_RST ,Clear the DAC data FIFO and reset the FIFO pointers" "Not toggle,Toggle" bitfld.long 0x0c 0. " DAC_MUX_MODE ,Specifies the meaning of the output stream to each DAC" "Not toggle,Toggle" group.long 0x10++0x0f line.long 0x00 "HW_TVENC_CONFIG,TV Encoder Configuration Register" bitfld.long 0x00 27. " DEFAULT_PICFORM ,Permit use of a set of default parameters" "Not permited,Permited" bitfld.long 0x00 24.--26. " YDEL_ADJ ,Delay luma versus chroma for composite output" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 21. " ADD_YPBPR_PED ,Permit the insertion of a black pedestal when sync is inserted on one or more component signals" "Not permited,Permited" bitfld.long 0x00 20. " PAL_SHAPE ,Impose a 250nS edge shape as required by PAL" "Not imposed,Imposed" textline " " bitfld.long 0x00 19. " NO_PED ,Prevent insertion of a black pedestal as required by NTSC-J" "Not prevented,Prevented" bitfld.long 0x00 18. " COLOR_BAR_EN ,Enable insertion of internally generated color bars" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--17. " YGAIN_SEL ,Control the luma gain" "NTSC,PAL,No gain,No gain" bitfld.long 0x00 14.--15. " CGAIN ,Control chroma gain for composite" "NTSC gain,PAL gain,No gain,No gain" textline " " bitfld.long 0x00 12.--13. " CLK_PHS ,Phase adjustment of pixel clock at line-end" "0,1,2,3" bitfld.long 0x00 10. " FSYNC_ENBL ,External Sync sub-block control" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " FSYNC_PHS ,Internal field polarity to those of the input and/or output signals in interlaced modes" "PAL,NTSC" bitfld.long 0x00 8. " HSYNC_PHS ,Edge of an external hsync input" "Rising edge,Falling edge" textline " " bitfld.long 0x00 7. " VSYNC_PHS ,Edge of an external vsync input" "Rising edge,Falling edge" bitfld.long 0x00 4.--6. " SYNC_MODE ,Define the manner in which the input is synchronized to the display" "Ext slave 8-bit Y/C in SYNC in,Ext slave 16-bit Y/C in SYNC in,Master 8-bit Y/C in SYNC in,Master 16-bit Y/C in SYNC in,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out" textline " " bitfld.long 0x00 0.--2. " ENCD_MODE ,Define the video mode" "NTSC-M,PAL-B,PAL-M,PAL-N,PAL-CN,NTSC with 700:300 scalling,PAL-60,NTSC Progressive" line.long 0x04 "HW_TVENC_CONFIG_SET,TV Encoder Configuration Set Register" bitfld.long 0x04 27. " DEFAULT_PICFORM ,Permit use of a set of default parameters" "No effect,Set" bitfld.long 0x04 24.--26. " YDEL_ADJ ,Delay luma versus chroma for composite output" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 21. " ADD_YPBPR_PED ,Permit the insertion of a black pedestal when sync is inserted on one or more component signals" "No effect,Set" bitfld.long 0x04 20. " PAL_SHAPE ,Impose a 250nS edge shape as required by PAL" "No effect,Set" textline " " bitfld.long 0x04 19. " NO_PED ,Prevent insertion of a black pedestal as required by NTSC-J" "No effect,Set" bitfld.long 0x04 18. " COLOR_BAR_EN ,Enable insertion of internally generated color bars" "No effect,Set" textline " " bitfld.long 0x04 16.--17. " YGAIN_SEL ,Control the luma gain" "NTSC,PAL,No gain,No gain" bitfld.long 0x04 14.--15. " CGAIN ,Control chroma gain for composite" "NTSC gain,PAL gain,No gain,No gain" textline " " bitfld.long 0x04 12.--13. " CLK_PHS ,Phase adjustment of pixel clock at line-end" "0,1,2,3" bitfld.long 0x04 10. " FSYNC_ENBL ,External Sync sub-block control" "No effect,Set" textline " " bitfld.long 0x04 9. " FSYNC_PHS ,Internal field polarity to those of the input and/or output signals in interlaced modes" "No effect,Set" bitfld.long 0x04 8. " HSYNC_PHS ,Edge of an external hsync input" "No effect,Set" textline " " bitfld.long 0x04 7. " VSYNC_PHS ,Edge of an external vsync input" "No effect,Set" bitfld.long 0x04 4.--6. " SYNC_MODE ,Define the manner in which the input is synchronized to the display" "Ext slave 8-bit Y/C in SYNC in,Ext slave 16-bit Y/C in SYNC in,Master 8-bit Y/C in SYNC in,Master 16-bit Y/C in SYNC in,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out" textline " " bitfld.long 0x04 0.--2. " ENCD_MODE ,Define the video mode" "NTSC-M,PAL-B,PAL-M,PAL-N,PAL-CN,NTSC with 700:300 scalling,PAL-60,NTSC Progressive" line.long 0x08 "HW_TVENC_CONFIG_CLR,TV Encoder Configuration Clear Register" bitfld.long 0x08 27. " DEFAULT_PICFORM ,Permit use of a set of default parameters" "No effect,Clear" bitfld.long 0x08 24.--26. " YDEL_ADJ ,Delay luma versus chroma for composite output" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 21. " ADD_YPBPR_PED ,Permit the insertion of a black pedestal when sync is inserted on one or more component signals" "No effect,Clear" bitfld.long 0x08 20. " PAL_SHAPE ,Impose a 250nS edge shape as required by PAL" "No effect,Clear" textline " " bitfld.long 0x08 19. " NO_PED ,Prevent insertion of a black pedestal as required by NTSC-J" "No effect,Clear" bitfld.long 0x08 18. " COLOR_BAR_EN ,Enable insertion of internally generated color bars" "No effect,Clear" textline " " bitfld.long 0x08 16.--17. " YGAIN_SEL ,Control the luma gain" "NTSC,PAL,No gain,No gain" bitfld.long 0x08 14.--15. " CGAIN ,Control chroma gain for composite" "NTSC gain,PAL gain,No gain,No gain" textline " " bitfld.long 0x08 12.--13. " CLK_PHS ,Phase adjustment of pixel clock at line-end" "0,1,2,3" bitfld.long 0x08 10. " FSYNC_ENBL ,External Sync sub-block control" "No effect,Clear" textline " " bitfld.long 0x08 9. " FSYNC_PHS ,Internal field polarity to those of the input and/or output signals in interlaced modes" "No effect,Clear" bitfld.long 0x08 8. " HSYNC_PHS ,Edge of an external hsync input" "No effect,Clear" textline " " bitfld.long 0x08 7. " VSYNC_PHS ,Edge of an external vsync input" "No effect,Clear" bitfld.long 0x08 4.--6. " SYNC_MODE ,Define the manner in which the input is synchronized to the display" "Ext slave 8-bit Y/C in SYNC in,Ext slave 16-bit Y/C in SYNC in,Master 8-bit Y/C in SYNC in,Master 16-bit Y/C in SYNC in,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out" textline " " bitfld.long 0x08 0.--2. " ENCD_MODE ,Define the video mode" "NTSC-M,PAL-B,PAL-M,PAL-N,PAL-CN,NTSC with 700:300 scalling,PAL-60,NTSC Progressive" line.long 0x0c "HW_TVENC_CONFIG_TOG,TV Encoder Configuration Toggle Register" bitfld.long 0x0c 27. " DEFAULT_PICFORM ,Permit use of a set of default parameters" "Not toggle,Toggle" bitfld.long 0x0c 24.--26. " YDEL_ADJ ,Delay luma versus chroma for composite output" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 21. " ADD_YPBPR_PED ,Permit the insertion of a black pedestal when sync is inserted on one or more component signals" "Not toggle,Toggle" bitfld.long 0x0c 20. " PAL_SHAPE ,Impose a 250nS edge shape as required by PAL" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " NO_PED ,Prevent insertion of a black pedestal as required by NTSC-J" "Not toggle,Toggle" bitfld.long 0x0c 18. " COLOR_BAR_EN ,Enable insertion of internally generated color bars" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--17. " YGAIN_SEL ,Control the luma gain" "NTSC,PAL,No gain,No gain" bitfld.long 0x0c 14.--15. " CGAIN ,Control chroma gain for composite" "NTSC gain,PAL gain,No gain,No gain" textline " " bitfld.long 0x0c 12.--13. " CLK_PHS ,Phase adjustment of pixel clock at line-end" "0,1,2,3" bitfld.long 0x0c 10. " FSYNC_ENBL ,External Sync sub-block control" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " FSYNC_PHS ,Internal field polarity to those of the input and/or output signals in interlaced modes" "Not toggle,Toggle" bitfld.long 0x0c 8. " HSYNC_PHS ,Edge of an external hsync input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " VSYNC_PHS ,Edge of an external vsync input" "Not toggle,Toggle" bitfld.long 0x0c 4.--6. " SYNC_MODE ,Define the manner in which the input is synchronized to the display" "Ext slave 8-bit Y/C in SYNC in,Ext slave 16-bit Y/C in SYNC in,Master 8-bit Y/C in SYNC in,Master 16-bit Y/C in SYNC in,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out,D1 mode Y/C in SYNC out" textline " " bitfld.long 0x0c 0.--2. " ENCD_MODE ,Define the video mode" "NTSC-M,PAL-B,PAL-M,PAL-N,PAL-CN,NTSC with 700:300 scalling,PAL-60,NTSC Progressive" group.long 0x20++0x0f line.long 0x00 "HW_TVENC_FILTCTRL,TV Encoder Filter Control Register" bitfld.long 0x00 19. " YSHARP_BW ,Control the luma sharpness filter bandwidth inside the luma filter sub-block" "0,1" bitfld.long 0x00 18. " YD_OFFSETSEL ,Control the luma offset" "Not substracted,Substracted 16 from luma" textline " " bitfld.long 0x00 17. " SEL_YLPF ,Enable the luma low pass filter" "Disabled,Enabled" bitfld.long 0x00 16. " SEL_CLPF ,Enable the chroma low pass filter" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " SEL_YSHARP ,Enable the luma sharpness filter" "Disabled,Enabled" bitfld.long 0x00 14. " YLPF_COEFSEL ,Control the luma low pass filter bandwidth" "5.5MHz,4.2MHz" textline " " bitfld.long 0x00 13. " COEFSEL_CLPF ,Control the chroma low pass filter bandwidth" "1.3MHz,0.6MHz" bitfld.long 0x00 12. " YS_GAINSGN ,Control the sign of the sharpness modification" "Positive,Negative" textline " " bitfld.long 0x00 10.--11. " YS_GAINSEL ,Control the degree of luma sharpness enhancement by luma sharpness filter" "3dB,6dB,9dB,12dB" line.long 0x04 "HW_TVENC_FILTCTRL_SET,TV Encoder Filter Control Set Register" bitfld.long 0x04 19. " YSHARP_BW ,Control the luma sharpness filter bandwidth inside the luma filter sub-block" "No effect,Set" bitfld.long 0x04 18. " YD_OFFSETSEL ,Control the luma offset" "No effect,Set" textline " " bitfld.long 0x04 17. " SEL_YLPF ,Enable the luma low pass filter" "No effect,Set" bitfld.long 0x04 16. " SEL_CLPF ,Enable the chroma low pass filter" "No effect,Set" textline " " bitfld.long 0x04 15. " SEL_YSHARP ,Enable the luma sharpness filter" "No effect,Set" bitfld.long 0x04 14. " YLPF_COEFSEL ,Control the luma low pass filter bandwidth" "No effect,Set" textline " " bitfld.long 0x04 13. " COEFSEL_CLPF ,Control the chroma low pass filter bandwidth" "No effect,Set" bitfld.long 0x04 12. " YS_GAINSGN ,Control the sign of the sharpness modification" "No effect,Set" textline " " bitfld.long 0x04 10.--11. " YS_GAINSEL ,Control the degree of luma sharpness enhancement by luma sharpness filter" "3dB,6dB,9dB,12dB" line.long 0x08 "HW_TVENC_FILTCTRL_CLR,TV Encoder Filter Control Clear Register" bitfld.long 0x08 19. " YSHARP_BW ,Control the luma sharpness filter bandwidth inside the luma filter sub-block" "No effect,Clear" bitfld.long 0x08 18. " YD_OFFSETSEL ,Control the luma offset" "No effect,Clear" textline " " bitfld.long 0x08 17. " SEL_YLPF ,Enable the luma low pass filter" "No effect,Clear" bitfld.long 0x08 16. " SEL_CLPF ,Enable the chroma low pass filter" "No effect,Clear" textline " " bitfld.long 0x08 15. " SEL_YSHARP ,Enable the luma sharpness filter" "No effect,Clear" bitfld.long 0x08 14. " YLPF_COEFSEL ,Control the luma low pass filter bandwidth" "No effect,Clear" textline " " bitfld.long 0x08 13. " COEFSEL_CLPF ,Control the chroma low pass filter bandwidth" "No effect,Clear" bitfld.long 0x08 12. " YS_GAINSGN ,Control the sign of the sharpness modification" "No effect,Clear" textline " " bitfld.long 0x08 10.--11. " YS_GAINSEL ,Control the degree of luma sharpness enhancement by luma sharpness filter" "3dB,6dB,9dB,12dB" line.long 0x0c "HW_TVENC_FILTCTRL_TOG,TV Encoder Filter Control Toggle Register" bitfld.long 0x0c 19. " YSHARP_BW ,Control the luma sharpness filter bandwidth inside the luma filter sub-block" "Not toggle,Toggle" bitfld.long 0x0c 18. " YD_OFFSETSEL ,Control the luma offset" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " SEL_YLPF ,Enable the luma low pass filter" "Not toggle,Toggle" bitfld.long 0x0c 16. " SEL_CLPF ,Enable the chroma low pass filter" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " SEL_YSHARP ,Enable the luma sharpness filter" "Not toggle,Toggle" bitfld.long 0x0c 14. " YLPF_COEFSEL ,Control the luma low pass filter bandwidth" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " COEFSEL_CLPF ,Control the chroma low pass filter bandwidth" "Not toggle,Toggle" bitfld.long 0x0c 12. " YS_GAINSGN ,Control the sign of the sharpness modification" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10.--11. " YS_GAINSEL ,Control the degree of luma sharpness enhancement by luma sharpness filter" "3dB,6dB,9dB,12dB" group.long 0x30++0x0f line.long 0x00 "HW_TVENC_SYNCOFFSET,TV Sync Offset Register" hexmask.long.word 0x00 20.--30. 1. " HSO ,Horizontal linestart in counts of CLK27 following the external sync edge" hexmask.long.word 0x00 10.--19. 1. " VSO ,Vertical fieldstart in units of lines following the designated edge of the external vertical sync" textline " " hexmask.long.word 0x00 0.--9. 1. " HLC ,Pixel count (pixels per line minus 1)" line.long 0x04 "HW_TVENC_SYNCOFFSET_SET,TV Sync Offset Set Register" hexmask.long.word 0x04 20.--30. 1. " HSO ,Horizontal linestart in counts of CLK27 following the external sync edge" hexmask.long.word 0x04 10.--19. 1. " VSO ,Vertical fieldstart in units of lines following the designated edge of the external vertical sync" textline " " hexmask.long.word 0x04 0.--9. 1. " HLC ,Pixel count (pixels per line minus 1)" line.long 0x08 "HW_TVENC_SYNCOFFSET_CLR,TV Sync Offset Clear Register" hexmask.long.word 0x08 20.--30. 1. " HSO ,Horizontal linestart in counts of CLK27 following the external sync edge" hexmask.long.word 0x08 10.--19. 1. " VSO ,Vertical fieldstart in units of lines following the designated edge of the external vertical sync" textline " " hexmask.long.word 0x08 0.--9. 1. " HLC ,Pixel count (pixels per line minus 1)" line.long 0x0c "HW_TVENC_SYNCOFFSET_TOG,TV Sync Offset Toggle Register" hexmask.long.word 0x0c 20.--30. 1. " HSO ,Horizontal linestart in counts of CLK27 following the external sync edge" hexmask.long.word 0x0c 10.--19. 1. " VSO ,Vertical fieldstart in units of lines following the designated edge of the external vertical sync" textline " " hexmask.long.word 0x0c 0.--9. 1. " HLC ,Pixel count (pixels per line minus 1)" group.long 0x40++0x11f line.long 0x00 "HW_TVENC_HTIMINGSYNC0,TV Encoder Horizontal Timing Sync Register 0" hexmask.long.word 0x00 16.--25. 1. " SYNC_END ,Normal end of sync pulse in first half line of video line" hexmask.long.word 0x00 0.--9. 1. " SYNC_STRT ,Start of sync pulse in line or half-line" line.long 0x04 "HW_TVENC_HTIMINGSYNC0_SET,TV Encoder Horizontal Timing Sync Set Register 0" hexmask.long.word 0x04 16.--25. 1. " SYNC_END ,Normal end of sync pulse in first half line of video line" hexmask.long.word 0x04 0.--9. 1. " SYNC_STRT ,Start of sync pulse in line or half-line" line.long 0x08 "HW_TVENC_HTIMINGSYNC0_CLR,TV Encoder Horizontal Timing Sync Clear Register 0" hexmask.long.word 0x08 16.--25. 1. " SYNC_END ,Normal end of sync pulse in first half line of video line" hexmask.long.word 0x08 0.--9. 1. " SYNC_STRT ,Start of sync pulse in line or half-line" line.long 0x0c "HW_TVENC_HTIMINGSYNC0_TOG,TV Encoder Horizontal Timing Sync Toggle Register 0" hexmask.long.word 0x0c 16.--25. 1. " SYNC_END ,Normal end of sync pulse in first half line of video line" hexmask.long.word 0x0c 0.--9. 1. " SYNC_STRT ,Start of sync pulse in line or half-line" line.long 0x10 "HW_TVENC_HTIMINGSYNC1,TV Encoder Horizontal Timing Sync Register 1" hexmask.long.word 0x10 16.--25. 1. " SYNC_EQND ,End of sync pulse in each half line in equalization regions of vertical blanking" hexmask.long.word 0x10 0.--9. 1. " SYNC_SREND ,End of sync pulse in each half line in serration region of vertical blanking" line.long 0x14 "HW_TVENC_HTIMINGSYNC1_SET,TV Encoder Horizontal Timing Sync Set Register 1" hexmask.long.word 0x14 16.--25. 1. " SYNC_EQND ,End of sync pulse in each half line in equalization regions of vertical blanking" hexmask.long.word 0x14 0.--9. 1. " SYNC_SREND ,End of sync pulse in each half line in serration region of vertical blanking" line.long 0x18 "HW_TVENC_HTIMINGSYNC1_CLR,TV Encoder Horizontal Timing Sync Clear Register 1" hexmask.long.word 0x18 16.--25. 1. " SYNC_EQND ,End of sync pulse in each half line in equalization regions of vertical blanking" hexmask.long.word 0x18 0.--9. 1. " SYNC_SREND ,End of sync pulse in each half line in serration region of vertical blanking" line.long 0x1c "HW_TVENC_HTIMINGSYNC1_TOG,TV Encoder Horizontal Timing Sync Toggle Register 1" hexmask.long.word 0x1c 16.--25. 1. " SYNC_EQND ,End of sync pulse in each half line in equalization regions of vertical blanking" hexmask.long.word 0x1c 0.--9. 1. " SYNC_SREND ,End of sync pulse in each half line in serration region of vertical blanking" line.long 0x20 "HW_TVENC_HTIMINGACTIVE,TV Encoder Horizontal Timing Active Register" hexmask.long.word 0x20 16.--25. 1. " ACTV_END ,Horizontal end of active video" hexmask.long.word 0x20 0.--9. 1. " ACTV_END ,Horizontal start of active video" line.long 0x24 "HW_TVENC_HTIMINGACTIVE_SET,TV Encoder Horizontal Timing Active Set Register" hexmask.long.word 0x24 16.--25. 1. " ACTV_END ,Horizontal end of active video" hexmask.long.word 0x24 0.--9. 1. " ACTV_END ,Horizontal start of active video" line.long 0x28 "HW_TVENC_HTIMINGACTIVE_CLR,TV Encoder Horizontal Timing Active Clear Register" hexmask.long.word 0x28 16.--25. 1. " ACTV_END ,Horizontal end of active video" hexmask.long.word 0x28 0.--9. 1. " ACTV_END ,Horizontal start of active video" line.long 0x2c "HW_TVENC_HTIMINGACTIVE_TOG,TV Encoder Horizontal Timing Active Toggle Register" hexmask.long.word 0x2c 16.--25. 1. " ACTV_END ,Horizontal end of active video" hexmask.long.word 0x2c 0.--9. 1. " ACTV_END ,Horizontal start of active video" line.long 0x30 "HW_TVENC_HTIMINGBURST0,TV Encoder Horizontal Timing Color Burst Register 0" hexmask.long.word 0x30 16.--25. 1. " WBRST_STRT ,Start of wide color burst for Macrovision" hexmask.long.word 0x30 0.--9. 1. " NBRST_STRT ,Start of normal color burst" line.long 0x34 "HW_TVENC_HTIMINGBURST0_SET,TV Encoder Horizontal Timing Color Burst Set Register 0" hexmask.long.word 0x34 16.--25. 1. " WBRST_STRT ,Start of wide color burst for Macrovision" hexmask.long.word 0x34 0.--9. 1. " NBRST_STRT ,Start of normal color burst" line.long 0x38 "HW_TVENC_HTIMINGBURST0_CLR,TV Encoder Horizontal Timing Color Burst Clear Register 0" hexmask.long.word 0x38 16.--25. 1. " WBRST_STRT ,Start of wide color burst for Macrovision" hexmask.long.word 0x38 0.--9. 1. " NBRST_STRT ,Start of normal color burst" line.long 0x3c "HW_TVENC_HTIMINGBURST0_TOG,TV Encoder Horizontal Timing Color Burst Toggle Register 0" hexmask.long.word 0x3c 16.--25. 1. " WBRST_STRT ,Start of wide color burst for Macrovision" hexmask.long.word 0x3c 0.--9. 1. " NBRST_STRT ,Start of normal color burst" line.long 0x40 "HW_TVENC_HTIMINGBURST1,TV Encoder Horizontal Timing Color Burst Register 1" hexmask.long.word 0x40 0.--9. 1. " BRST_END ,End of normal or wide color burst" line.long 0x44 "HW_TVENC_HTIMINGBURST1_SET,TV Encoder Horizontal Timing Color Burst Set Register 1" hexmask.long.word 0x44 0.--9. 1. " BRST_END ,End of normal or wide color burst" line.long 0x48 "HW_TVENC_HTIMINGBURST1_CLR,TV Encoder Horizontal Timing Color Burst Clear Register 1" hexmask.long.word 0x48 0.--9. 1. " BRST_END ,End of normal or wide color burst" line.long 0x4c "HW_TVENC_HTIMINGBURST1_TOG,TV Encoder Horizontal Timing Color Burst Toggle Register 1" hexmask.long.word 0x4c 0.--9. 1. " BRST_END ,End of normal or wide color burst" line.long 0x50 "HW_TVENC_VTIMING0,TV Encoder Vertical Timing Register 0" hexmask.long.word 0x50 16.--25. 1. " VSTRT_PREEQ ,Last half line of active video followed by pre-equalization" bitfld.long 0x50 8.--13. " VSTRT_ACTV ,Last half line of sub-phase followed by active video" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x50 0.--5. " VSTRT_SUBPH ,Last half line of post equalization followed by sub-phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x54 "HW_TVENC_VTIMING0_SET,TV Encoder Vertical Timing Set Register 0" hexmask.long.word 0x54 16.--25. 1. " VSTRT_PREEQ ,Last half line of active video followed by pre-equalization" bitfld.long 0x54 8.--13. " VSTRT_ACTV ,Last half line of sub-phase followed by active video" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x54 0.--5. " VSTRT_SUBPH ,Last half line of post equalization followed by sub-phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x58 "HW_TVENC_VTIMING0_CLR,TV Encoder Vertical Timing Clear Register 0" hexmask.long.word 0x58 16.--25. 1. " VSTRT_PREEQ ,Last half line of active video followed by pre-equalization" bitfld.long 0x58 8.--13. " VSTRT_ACTV ,Last half line of sub-phase followed by active video" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x58 0.--5. " VSTRT_SUBPH ,Last half line of post equalization followed by sub-phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x5c "HW_TVENC_VTIMING0_TOG,TV Encoder Vertical Timing Toggle Register 0" hexmask.long.word 0x5c 16.--25. 1. " VSTRT_PREEQ ,Last half line of active video followed by pre-equalization" bitfld.long 0x5c 8.--13. " VSTRT_ACTV ,Last half line of sub-phase followed by active video" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x5c 0.--5. " VSTRT_SUBPH ,Last half line of post equalization followed by sub-phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x60 "HW_TVENC_VTIMING1,TV Encoder Vertical Timing Register 1" bitfld.long 0x60 24.--29. " VSTRT_POSTEQ ,Last half line of serration followed by post-equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x60 16.--21. " VSTRT_SERRA ,Last half line of pre-equalization followed by serration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x60 0.--9. 1. " LAST_FLD_LN ,Last half line of field" line.long 0x64 "HW_TVENC_VTIMING1_SET,TV Encoder Vertical Timing Set Register 1" bitfld.long 0x64 24.--29. " VSTRT_POSTEQ ,Last half line of serration followed by post-equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x64 16.--21. " VSTRT_SERRA ,Last half line of pre-equalization followed by serration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x64 0.--9. 1. " LAST_FLD_LN ,Last half line of field" line.long 0x68 "HW_TVENC_VTIMING1_CLR,TV Encoder Vertical Timing Clear Register 1" bitfld.long 0x68 24.--29. " VSTRT_POSTEQ ,Last half line of serration followed by post-equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x68 16.--21. " VSTRT_SERRA ,Last half line of pre-equalization followed by serration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x68 0.--9. 1. " LAST_FLD_LN ,Last half line of field" line.long 0x6c "HW_TVENC_VTIMING1_TOG,TV Encoder Vertical Timing Toggle Register 1" bitfld.long 0x6c 24.--29. " VSTRT_POSTEQ ,Last half line of serration followed by post-equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x6c 16.--21. " VSTRT_SERRA ,Last half line of pre-equalization followed by serration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x6c 0.--9. 1. " LAST_FLD_LN ,Last half line of field" line.long 0x70 "HW_TVENC_MISC,TV Encoder Miscellaneous Line Control Register" hexmask.long.word 0x70 16.--24. 1. " LPF_RST_OFF ,Programs the time to generate a pulse" bitfld.long 0x70 11. " NTSC_LN_CNT ,Aligns even/odd field identification with internal field count in Sync Gen unit" "PAL-B,NTSC" textline " " bitfld.long 0x70 10. " PAL_FSC_PHASE_ALT ,Enables PAL manner of phase alternation by field of color subcarrier in Sync Gen unit" "Disabled,Enabled" bitfld.long 0x70 8.--9. " FSC_PHASE_RST ,Controls timing of color subcarrier phase reset in Sync Gen unit" "Progressive,NTSC,PAL-M/PAL-N/PAL-60,Other PAL cases" textline " " bitfld.long 0x70 6.--7. " BRUCHB ,Controls Bruch blanking in Sync Gen unit" "Progressive,525 line cases with NTSC,PAL-M/PAl-60,Other PAL cases" bitfld.long 0x70 4.--5. " AGC_LVL_CTRL ,Controls AGC levels in Macrovision sub-block" "Mixed NTSC,NTSC,PAL,Progressive" textline " " bitfld.long 0x70 2. " CS_INVERT_CTRL ,Disables illegal color stripe inversion modes in Macrovision sub-block" "No,Yes" bitfld.long 0x70 0.--1. " Y_BLANK_CTRL ,Controls the blanking level in the luma processing sub-block" "700:300 blanking for progressive,714:286 blanking for composite and component,714:286 blanking for composite/700:300 blanking for component,700:300 blanking for PAL" line.long 0x74 "HW_TVENC_MISC_SET,TV Encoder Miscellaneous Line Control Set Register" hexmask.long.word 0x74 16.--24. 1. " LPF_RST_OFF ,Programs the time to generate a pulse" bitfld.long 0x74 11. " NTSC_LN_CNT ,Aligns even/odd field identification with internal field count in Sync Gen unit" "No effect,Set" textline " " bitfld.long 0x74 10. " PAL_FSC_PHASE_ALT ,Enables PAL manner of phase alternation by field of color subcarrier in Sync Gen unit" "No effect,Set" bitfld.long 0x74 8.--9. " FSC_PHASE_RST ,Controls timing of color subcarrier phase reset in Sync Gen unit" "Progressive,NTSC,PAL-M/PAL-N/PAL-60,Other PAL cases" textline " " bitfld.long 0x74 6.--7. " BRUCHB ,Controls Bruch blanking in Sync Gen unit" "Progressive,525 line cases with NTSC,PAL-M/PAl-60,Other PAL cases" bitfld.long 0x74 4.--5. " AGC_LVL_CTRL ,Controls AGC levels in Macrovision sub-block" "Mixed NTSC,NTSC,PAL,Progressive" textline " " bitfld.long 0x74 2. " CS_INVERT_CTRL ,Disables illegal color stripe inversion modes in Macrovision sub-block" "No effect,Set" bitfld.long 0x74 0.--1. " Y_BLANK_CTRL ,Controls the blanking level in the luma processing sub-block" "700:300 blanking for progressive,714:286 blanking for composite and component,714:286 blanking for composite/700:300 blanking for component,700:300 blanking for PAL" line.long 0x78 "HW_TVENC_MISC_CLR,TV Encoder Miscellaneous Line Control Clear Register" hexmask.long.word 0x78 16.--24. 1. " LPF_RST_OFF ,Programs the time to generate a pulse" bitfld.long 0x78 11. " NTSC_LN_CNT ,Aligns even/odd field identification with internal field count in Sync Gen unit" "No effect,Clear" textline " " bitfld.long 0x78 10. " PAL_FSC_PHASE_ALT ,Enables PAL manner of phase alternation by field of color subcarrier in Sync Gen unit" "No effect,Clear" bitfld.long 0x78 8.--9. " FSC_PHASE_RST ,Controls timing of color subcarrier phase reset in Sync Gen unit" "Progressive,NTSC,PAL-M/PAL-N/PAL-60,Other PAL cases" textline " " bitfld.long 0x78 6.--7. " BRUCHB ,Controls Bruch blanking in Sync Gen unit" "Progressive,525 line cases with NTSC,PAL-M/PAl-60,Other PAL cases" bitfld.long 0x78 4.--5. " AGC_LVL_CTRL ,Controls AGC levels in Macrovision sub-block" "Mixed NTSC,NTSC,PAL,Progressive" textline " " bitfld.long 0x78 2. " CS_INVERT_CTRL ,Disables illegal color stripe inversion modes in Macrovision sub-block" "No effect,Clear" bitfld.long 0x78 0.--1. " Y_BLANK_CTRL ,Controls the blanking level in the luma processing sub-block" "700:300 blanking for progressive,714:286 blanking for composite and component,714:286 blanking for composite/700:300 blanking for component,700:300 blanking for PAL" line.long 0x7c "HW_TVENC_MISC_TOG,TV Encoder Miscellaneous Line Control Toggle Register" hexmask.long.word 0x7c 16.--24. 1. " LPF_RST_OFF ,Programs the time to generate a pulse" bitfld.long 0x7c 11. " NTSC_LN_CNT ,Aligns even/odd field identification with internal field count in Sync Gen unit" "Not toggle,Toggle" textline " " bitfld.long 0x7c 10. " PAL_FSC_PHASE_ALT ,Enables PAL manner of phase alternation by field of color subcarrier in Sync Gen unit" "Not toggle,Toggle" bitfld.long 0x7c 8.--9. " FSC_PHASE_RST ,Controls timing of color subcarrier phase reset in Sync Gen unit" "Progressive,NTSC,PAL-M/PAL-N/PAL-60,Other PAL cases" textline " " bitfld.long 0x7c 6.--7. " BRUCHB ,Controls Bruch blanking in Sync Gen unit" "Progressive,525 line cases with NTSC,PAL-M/PAl-60,Other PAL cases" bitfld.long 0x7c 4.--5. " AGC_LVL_CTRL ,Controls AGC levels in Macrovision sub-block" "Mixed NTSC,NTSC,PAL,Progressive" textline " " bitfld.long 0x7c 2. " CS_INVERT_CTRL ,Disables illegal color stripe inversion modes in Macrovision sub-block" "Not toggle,Toggle" bitfld.long 0x7c 0.--1. " Y_BLANK_CTRL ,Controls the blanking level in the luma processing sub-block" "700:300 blanking for progressive,714:286 blanking for composite and component,714:286 blanking for composite/700:300 blanking for component,700:300 blanking for PAL" line.long 0x80 "HW_TVENC_COLORSUB0,TV Encoder Color Subcarrier Register 0" line.long 0x84 "HW_TVENC_COLORSUB0_SET,TV Encoder Color Subcarrier Set Register 0" line.long 0x88 "HW_TVENC_COLORSUB0_CLR,TV Encoder Color Subcarrier Clear Register 0" line.long 0x8c "HW_TVENC_COLORSUB0_TOG,TV Encoder Color Subcarrier Toggle Register 0" line.long 0x90 "HW_TVENC_COLORSUB1,TV Encoder Color Subcarrier Register 1" line.long 0x94 "HW_TVENC_COLORSUB1_SET,TV Encoder Color Subcarrier Set Register 1" line.long 0x98 "HW_TVENC_COLORSUB1_CLR,TV Encoder Color Subcarrier Clear Register 1" line.long 0x9c "HW_TVENC_COLORSUB1_TOG,TV Encoder Color Subcarrier Toggle Register 1" line.long 0xa0 "HW_TVENC_COPYPROTECT,TV Encoder Copy Protect Register" bitfld.long 0xa0 15. " WSS_ENBL ,Enable WSS insertion for 625 line modes" "Disabled,Enabled" bitfld.long 0xa0 14. " CGMS_ENBL ,Enable CGMS insertion for 525 line modes" "Disabled,Enabled" textline " " hexmask.long.word 0xa0 0.--13. 1. " WSS_CGMS_DATA ,Payload data for insertion in either WSS or CGMS mode" line.long 0xa4 "HW_TVENC_COPYPROTECT_SET,TV Encoder Copy Protect Set Register" bitfld.long 0xa4 15. " WSS_ENBL ,Enable WSS insertion for 625 line modes" "No effect,Set" bitfld.long 0xa4 14. " CGMS_ENBL ,Enable CGMS insertion for 525 line modes" "No effect,Set" textline " " hexmask.long.word 0xa4 0.--13. 1. " WSS_CGMS_DATA ,Payload data for insertion in either WSS or CGMS mode" line.long 0xa8 "HW_TVENC_COPYPROTECT_CLR,TV Encoder Copy Protect Clear Register" bitfld.long 0xa8 15. " WSS_ENBL ,Enable WSS insertion for 625 line modes" "No effect,Clear" bitfld.long 0xa8 14. " CGMS_ENBL ,Enable CGMS insertion for 525 line modes" "No effect,Clear" textline " " hexmask.long.word 0xa8 0.--13. 1. " WSS_CGMS_DATA ,Payload data for insertion in either WSS or CGMS mode" line.long 0xac "HW_TVENC_COPYPROTECT_TOG,TV Encoder Copy Protect Toggle Register" bitfld.long 0xac 15. " WSS_ENBL ,Enable WSS insertion for 625 line modes" "Not toggle,Toggle" bitfld.long 0xac 14. " CGMS_ENBL ,Enable CGMS insertion for 525 line modes" "Not toggle,Toggle" textline " " hexmask.long.word 0xac 0.--13. 1. " WSS_CGMS_DATA ,Payload data for insertion in either WSS or CGMS mode" line.long 0xb0 "HW_TVENC_CLOSEDCAPTION,TV Encoder Closed Caption Register" bitfld.long 0xb0 19. " CC_ENBL1 ,Enable Closed Caption insertion in even (bottom) field" "Disabled,Enabled" bitfld.long 0xb0 18. " CC_ENBL0 ,Enable Closed Caption insertion in odd (top) field" "Disabled,Enabled" textline " " bitfld.long 0xb0 17. " CC_FILL1 ,Insert CC_DATA in the even (lower) field" "Not inserted,Inserted" bitfld.long 0xb0 16. " CC_FILL0 ,Insert CC_DATA in the odd (upper) field" "Not inserted,Inserted" textline " " hexmask.long.word 0xb0 0.--15. 1. " CC_DATA ,Data to be inserted" line.long 0xb4 "HW_TVENC_CLOSEDCAPTION_SET,TV Encoder Closed Caption Set Register" bitfld.long 0xb4 19. " CC_ENBL1 ,Enable Closed Caption insertion in even (bottom) field" "No effect,Set" bitfld.long 0xb4 18. " CC_ENBL0 ,Enable Closed Caption insertion in odd (top) field" "No effect,Set" textline " " bitfld.long 0xb4 17. " CC_FILL1 ,Insert CC_DATA in the even (lower) field" "No effect,Set" bitfld.long 0xb4 16. " CC_FILL0 ,Insert CC_DATA in the odd (upper) field" "No effect,Set" textline " " hexmask.long.word 0xb4 0.--15. 1. " CC_DATA ,Data to be inserted" line.long 0xb8 "HW_TVENC_CLOSEDCAPTION_CLR,TV Encoder Closed Caption Clear Register" bitfld.long 0xb8 19. " CC_ENBL1 ,Enable Closed Caption insertion in even (bottom) field" "No effect,Clear" bitfld.long 0xb8 18. " CC_ENBL0 ,Enable Closed Caption insertion in odd (top) field" "No effect,Clear" textline " " bitfld.long 0xb8 17. " CC_FILL1 ,Insert CC_DATA in the even (lower) field" "No effect,Clear" bitfld.long 0xb8 16. " CC_FILL0 ,Insert CC_DATA in the odd (upper) field" "No effect,Clear" textline " " hexmask.long.word 0xb8 0.--15. 1. " CC_DATA ,Data to be inserted" line.long 0xbc "HW_TVENC_CLOSEDCAPTION_TOG,TV Encoder Closed Caption Toggle Register" bitfld.long 0xbc 19. " CC_ENBL1 ,Enable Closed Caption insertion in even (bottom) field" "Not toggle,Toggle" bitfld.long 0xbc 18. " CC_ENBL0 ,Enable Closed Caption insertion in odd (top) field" "Not toggle,Toggle" textline " " bitfld.long 0xbc 17. " CC_FILL1 ,Insert CC_DATA in the even (lower) field" "Not toggle,Toggle" bitfld.long 0xbc 16. " CC_FILL0 ,Insert CC_DATA in the odd (upper) field" "Not toggle,Toggle" textline " " hexmask.long.word 0xbc 0.--15. 1. " CC_DATA ,Data to be inserted" group.long 0x140++0x0f line.long 0x00 "HW_TVENC_COLORBURST,TV Encoder Color Burst Register" hexmask.long.byte 0x00 24.--31. 1. " NBA ,Parameter to define color burst" hexmask.long.byte 0x00 16.--23. 1. " PBA ,Parameter to define color burst" line.long 0x04 "HW_TVENC_COLORBURST_SET,TV Encoder Color Burst Set Register" hexmask.long.byte 0x04 24.--31. 1. " NBA ,Parameter to define color burst" hexmask.long.byte 0x04 16.--23. 1. " PBA ,Parameter to define color burst" line.long 0x08 "HW_TVENC_COLORBURST_CLR,TV Encoder Color Burst Clear Register" hexmask.long.byte 0x08 24.--31. 1. " NBA ,Parameter to define color burst" hexmask.long.byte 0x08 16.--23. 1. " PBA ,Parameter to define color burst" line.long 0x0c "HW_TVENC_COLORBURST_TOG,TV Encoder Color Burst Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " NBA ,Parameter to define color burst" hexmask.long.byte 0x0c 16.--23. 1. " PBA ,Parameter to define color burst" group.long 0x1a0++0x2f line.long 0x00 "HW_TVENC_DACCTRL,TV Encoder DAC Control Register" bitfld.long 0x00 31. " TEST3 ,Test bit" "0,1" bitfld.long 0x00 28. " JACK1_DIS_DET_EN ,Enables the jack1 disconnect detector" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " TEST2 ,Test bit" "0,1" bitfld.long 0x00 24. " JACK1_DET_EN ,Enables the jack1 connect detector" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " TEST1 ,Test bit" "0,1" bitfld.long 0x00 22. " DISABLE_GND_DETECT ,Disable GND detect" "No,Yes" textline " " bitfld.long 0x00 20.--21. " JACK_DIS_ADJ ,Adjust the trip voltage for the disconnect detector" "1.35,1.50,1.65,1.80" bitfld.long 0x00 19. " GAINDN ,Set to gain the digital code down" "Nominal,-20%" textline " " bitfld.long 0x00 18. " GAINUP ,Set to gain the digital code up by 25%" "Nominal,+25%" bitfld.long 0x00 17. " INVERT_CLK ,Invert the dac clk" "Not inverted,Inverted" textline " " bitfld.long 0x00 16. " SELECT_CLK ,Selects sample rate for the video DACs" "27MHz,108MHz" bitfld.long 0x00 15. " BYPASS_ACT_CASCODE ,Bypasses/disables the active cascode amp that is used to improve the low frequency PSRR of the video DACs" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 12. " PWRUP1 ,Power up video dac channel 1" "Powered down,Powered up" bitfld.long 0x00 11. " WELL_TOVDD ,Change the nwell connection for the current steering PFET switched from VDDA to VDDD for all 3 video DACs" "Not changed,Changed" textline " " bitfld.long 0x00 8. " DUMP_TOVDD1 ,Enable low power feature for video DAC1 to dump the unused DAC current to the VDDD rail instead of ground" "Disabled,Enabled" bitfld.long 0x00 7. " LOWER_SIGNAL ,Decreases video DAC output swings by 33% to save corresponding power" "Not decreased,Decreased" textline " " bitfld.long 0x00 4.--6. " RVAL ,Adjust the on-chip resistances that set the termination resistor and the peak output current" "+20%,+12.4%,+5.8%,Nominal,-4.4%,-10%,-14.2%,-17.3%" bitfld.long 0x00 3. " NO_INTERNAL_TERM ,Disable the internal termination mode for all three video DACs" "No,Yes" textline " " bitfld.long 0x00 2. " HALF_CURRENT ,Nominal peak output current" "34.67mA,17.3mA" bitfld.long 0x00 0.--1. " CASC_ADJ ,Adjusts the cascode voltage for the current sources" "Nominal,-50mV,+50mV,+100mV" line.long 0x04 "HW_TVENC_DACCTRL_SET,TV Encoder DAC Control Set Register" bitfld.long 0x04 31. " TEST3 ,Test bit" "No effect,Set" bitfld.long 0x04 28. " JACK1_DIS_DET_EN ,Enables the jack1 disconnect detector" "No effect,Set" textline " " bitfld.long 0x04 27. " TEST2 ,Test bit" "No effect,Set" bitfld.long 0x04 24. " JACK1_DET_EN ,Enables the jack1 connect detector" "No effect,Set" textline " " bitfld.long 0x04 23. " TEST1 ,Test bit" "No effect,Set" bitfld.long 0x04 22. " DISABLE_GND_DETECT ,Disable GND detect" "No effect,Set" textline " " bitfld.long 0x04 20.--21. " JACK_DIS_ADJ ,Adjust the trip voltage for the disconnect detector" "1.35,1.50,1.65,1.80" bitfld.long 0x04 19. " GAINDN ,Set to gain the digital code down" "No effect,Set" textline " " bitfld.long 0x04 18. " GAINUP ,Set to gain the digital code up by 25%" "No effect,Set" bitfld.long 0x04 17. " INVERT_CLK ,Invert the dac clk" "No effect,Set" textline " " bitfld.long 0x04 16. " SELECT_CLK ,Selects sample rate for the video DACs" "No effect,Set" bitfld.long 0x04 15. " BYPASS_ACT_CASCODE ,Bypasses/disables the active cascode amp that is used to improve the low frequency PSRR of the video DACs" "No effect,Set" textline " " bitfld.long 0x04 12. " PWRUP1 ,Power up video dac channel 1" "No effect,Set" bitfld.long 0x04 11. " WELL_TOVDD ,Change the nwell connection for the current steering PFET switched from VDDA to VDDD for all 3 video DACs" "No effect,Set" textline " " bitfld.long 0x04 8. " DUMP_TOVDD1 ,Enable low power feature for video DAC1 to dump the unused DAC current to the VDDD rail instead of ground" "No effect,Set" bitfld.long 0x04 7. " LOWER_SIGNAL ,Decreases video DAC output swings by 33% to save corresponding power" "No effect,Set" textline " " bitfld.long 0x04 4.--6. " RVAL ,Adjust the on-chip resistances that set the termination resistor and the peak output current" "+20%,+12.4%,+5.8%,Nominal,-4.4%,-10%,-14.2%,-17.3%" bitfld.long 0x04 3. " NO_INTERNAL_TERM ,Disable the internal termination mode for all three video DACs" "No effect,Set" textline " " bitfld.long 0x04 2. " HALF_CURRENT ,Nominal peak output current" "No effect,Set" bitfld.long 0x04 0.--1. " CASC_ADJ ,Adjusts the cascode voltage for the current sources" "Nominal,-50mV,+50mV,+100mV" line.long 0x08 "HW_TVENC_DACCTRL_CLR,TV Encoder DAC Control Clear Register" bitfld.long 0x08 31. " TEST3 ,Test bit" "No effect,Clear" bitfld.long 0x08 28. " JACK1_DIS_DET_EN ,Enables the jack1 disconnect detector" "No effect,Clear" textline " " bitfld.long 0x08 27. " TEST2 ,Test bit" "No effect,Clear" bitfld.long 0x08 24. " JACK1_DET_EN ,Enables the jack1 connect detector" "No effect,Clear" textline " " bitfld.long 0x08 23. " TEST1 ,Test bit" "No effect,Clear" bitfld.long 0x08 22. " DISABLE_GND_DETECT ,Disable GND detect" "No effect,Clear" textline " " bitfld.long 0x08 20.--21. " JACK_DIS_ADJ ,Adjust the trip voltage for the disconnect detector" "1.35,1.50,1.65,1.80" bitfld.long 0x08 19. " GAINDN ,Set to gain the digital code down" "No effect,Clear" textline " " bitfld.long 0x08 18. " GAINUP ,Set to gain the digital code up by 25%" "No effect,Clear" bitfld.long 0x08 17. " INVERT_CLK ,Invert the dac clk" "No effect,Clear" textline " " bitfld.long 0x08 16. " SELECT_CLK ,Selects sample rate for the video DACs" "No effect,Clear" bitfld.long 0x08 15. " BYPASS_ACT_CASCODE ,Bypasses/disables the active cascode amp that is used to improve the low frequency PSRR of the video DACs" "No effect,Clear" textline " " bitfld.long 0x08 12. " PWRUP1 ,Power up video dac channel 1" "No effect,Clear" bitfld.long 0x08 11. " WELL_TOVDD ,Change the nwell connection for the current steering PFET switched from VDDA to VDDD for all 3 video DACs" "No effect,Clear" textline " " bitfld.long 0x08 8. " DUMP_TOVDD1 ,Enable low power feature for video DAC1 to dump the unused DAC current to the VDDD rail instead of ground" "No effect,Clear" bitfld.long 0x08 7. " LOWER_SIGNAL ,Decreases video DAC output swings by 33% to save corresponding power" "No effect,Clear" textline " " bitfld.long 0x08 4.--6. " RVAL ,Adjust the on-chip resistances that set the termination resistor and the peak output current" "+20%,+12.4%,+5.8%,Nominal,-4.4%,-10%,-14.2%,-17.3%" bitfld.long 0x08 3. " NO_INTERNAL_TERM ,Disable the internal termination mode for all three video DACs" "No effect,Clear" textline " " bitfld.long 0x08 2. " HALF_CURRENT ,Nominal peak output current" "No effect,Clear" bitfld.long 0x08 0.--1. " CASC_ADJ ,Adjusts the cascode voltage for the current sources" "Nominal,-50mV,+50mV,+100mV" line.long 0x0c "HW_TVENC_DACCTRL_TOG,TV Encoder DAC Control Toggle Register" bitfld.long 0x0c 31. " TEST3 ,Test bit" "Not toggle,Toggle" bitfld.long 0x0c 28. " JACK1_DIS_DET_EN ,Enables the jack1 disconnect detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " TEST2 ,Test bit" "Not toggle,Toggle" bitfld.long 0x0c 24. " JACK1_DET_EN ,Enables the jack1 connect detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " TEST1 ,Test bit" "Not toggle,Toggle" bitfld.long 0x0c 22. " DISABLE_GND_DETECT ,Disable GND detect" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20.--21. " JACK_DIS_ADJ ,Adjust the trip voltage for the disconnect detector" "1.35,1.50,1.65,1.80" bitfld.long 0x0c 19. " GAINDN ,Set to gain the digital code down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " GAINUP ,Set to gain the digital code up by 25%" "Not toggle,Toggle" bitfld.long 0x0c 17. " INVERT_CLK ,Invert the dac clk" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " SELECT_CLK ,Selects sample rate for the video DACs" "Not toggle,Toggle" bitfld.long 0x0c 15. " BYPASS_ACT_CASCODE ,Bypasses/disables the active cascode amp that is used to improve the low frequency PSRR of the video DACs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " PWRUP1 ,Power up video dac channel 1" "Not toggle,Toggle" bitfld.long 0x0c 11. " WELL_TOVDD ,Change the nwell connection for the current steering PFET switched from VDDA to VDDD for all 3 video DACs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " DUMP_TOVDD1 ,Enable low power feature for video DAC1 to dump the unused DAC current to the VDDD rail instead of ground" "Not toggle,Toggle" bitfld.long 0x0c 7. " LOWER_SIGNAL ,Decreases video DAC output swings by 33% to save corresponding power" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--6. " RVAL ,Adjust the on-chip resistances that set the termination resistor and the peak output current" "+20%,+12.4%,+5.8%,Nominal,-4.4%,-10%,-14.2%,-17.3%" bitfld.long 0x0c 3. " NO_INTERNAL_TERM ,Disable the internal termination mode for all three video DACs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " HALF_CURRENT ,Nominal peak output current" "Not toggle,Toggle" bitfld.long 0x0c 0.--1. " CASC_ADJ ,Adjusts the cascode voltage for the current sources" "Nominal,-50mV,+50mV,+100mV" line.long 0x10 "HW_TVENC_DACSTATUS,TV Encoder DAC Status Register" bitfld.long 0x10 10. " JACK1_DET_STATUS ,Output is pulled to ground with an impedance less than 20ohm" "Not pulled,Pulled" bitfld.long 0x10 7. " JACK1_GROUNDED ,Output is pulled to ground with an impedance less than 20ohm" "Not pulled,Pulled" textline " " bitfld.long 0x10 4. " JACK1_DIS_DET_IRQ ,Jack1 disconnect detect interrupt status bit" "Not detected,Detected" bitfld.long 0x10 1. " JACK1_DET_IRQ ,Jack1 detect interrupt status bit" "Not detected,Detected" textline " " bitfld.long 0x10 0. " ENIRQ_JACK ,Enable all DAC jack detect interrupt sources" "Disabled,Enabled" line.long 0x14 "HW_TVENC_DACSTATUS_SET,TV Encoder DAC Status Set Register" bitfld.long 0x14 10. " JACK1_DET_STATUS ,Output is pulled to ground with an impedance less than 20ohm" "No effect,Set" bitfld.long 0x14 7. " JACK1_GROUNDED ,Output is pulled to ground with an impedance less than 20ohm" "No effect,Set" textline " " bitfld.long 0x14 4. " JACK1_DIS_DET_IRQ ,Jack1 disconnect detect interrupt status bit" "No effect,Set" bitfld.long 0x14 1. " JACK1_DET_IRQ ,Jack1 detect interrupt status bit" "No effect,Set" textline " " bitfld.long 0x14 0. " ENIRQ_JACK ,Enable all DAC jack detect interrupt sources" "No effect,Set" line.long 0x18 "HW_TVENC_DACSTATUS_CLR,TV Encoder DAC Status Clear Register" bitfld.long 0x18 10. " JACK1_DET_STATUS ,Output is pulled to ground with an impedance less than 20ohm" "No effect,Clear" bitfld.long 0x18 7. " JACK1_GROUNDED ,Output is pulled to ground with an impedance less than 20ohm" "No effect,Clear" textline " " bitfld.long 0x18 4. " JACK1_DIS_DET_IRQ ,Jack1 disconnect detect interrupt status bit" "No effect,Clear" bitfld.long 0x18 1. " JACK1_DET_IRQ ,Jack1 detect interrupt status bit" "No effect,Clear" textline " " bitfld.long 0x18 0. " ENIRQ_JACK ,Enable all DAC jack detect interrupt sources" "No effect,Clear" line.long 0x1c "HW_TVENC_DACSTATUS_TOG,TV Encoder DAC Status Toggle Register" bitfld.long 0x1c 10. " JACK1_DET_STATUS ,Output is pulled to ground with an impedance less than 20ohm" "Not toggle,Toggle" bitfld.long 0x1c 7. " JACK1_GROUNDED ,Output is pulled to ground with an impedance less than 20ohm" "Not toggle,Toggle" textline " " bitfld.long 0x1c 4. " JACK1_DIS_DET_IRQ ,Jack1 disconnect detect interrupt status bit" "Not toggle,Toggle" bitfld.long 0x1c 1. " JACK1_DET_IRQ ,Jack1 detect interrupt status bit" "Not toggle,Toggle" textline " " bitfld.long 0x1c 0. " ENIRQ_JACK ,Enable all DAC jack detect interrupt sources" "Not toggle,Toggle" line.long 0x20 "HW_TVENC_VDACTEST,TV Encoder vDAC Test Register" bitfld.long 0x20 13. " ENABLE_PIX_INT_GAIN ,Enabling this bit will attenuate the output of the pix_int block to ensure that the frequency response is never greater than 0.0dB" "Disabled,Enabled" bitfld.long 0x20 12. " BYPASS_PIX_INT ,Pixel interpolator is bypassed" "Not bypassed,Bypassed" textline " " bitfld.long 0x20 11. " BYPASS_PIX_INT_DROOP ,Bypass the droop compensation portion of the pixel interpolator" "Not bypassed,Bypassed" bitfld.long 0x20 10. " TEST_FIFO_FULL ,Test fifo is full" "Not full,Full" textline " " hexmask.long.word 0x20 0.--9. 1. " DATA ,Digital data sample going to DAC 0" line.long 0x24 "HW_TVENC_VDACTEST_SET,TV Encoder vDAC Test Set Register" bitfld.long 0x24 13. " ENABLE_PIX_INT_GAIN ,Enabling this bit will attenuate the output of the pix_int block to ensure that the frequency response is never greater than 0.0dB" "No effect,Set" bitfld.long 0x24 12. " BYPASS_PIX_INT ,Pixel interpolator is bypassed" "No effect,Set" textline " " bitfld.long 0x24 11. " BYPASS_PIX_INT_DROOP ,Bypass the droop compensation portion of the pixel interpolator" "No effect,Set" bitfld.long 0x24 10. " TEST_FIFO_FULL ,Test fifo is full" "No effect,Set" textline " " hexmask.long.word 0x24 0.--9. 1. " DATA ,Digital data sample going to DAC 0" line.long 0x28 "HW_TVENC_VDACTEST_CLR,TV Encoder vDAC Test Clear Register" bitfld.long 0x28 13. " ENABLE_PIX_INT_GAIN ,Enabling this bit will attenuate the output of the pix_int block to ensure that the frequency response is never greater than 0.0dB" "No effect,Clear" bitfld.long 0x28 12. " BYPASS_PIX_INT ,Pixel interpolator is bypassed" "No effect,Clear" textline " " bitfld.long 0x28 11. " BYPASS_PIX_INT_DROOP ,Bypass the droop compensation portion of the pixel interpolator" "No effect,Clear" bitfld.long 0x28 10. " TEST_FIFO_FULL ,Test fifo is full" "No effect,Clear" textline " " hexmask.long.word 0x28 0.--9. 1. " DATA ,Digital data sample going to DAC 0" line.long 0x2c "HW_TVENC_VDACTEST_TOG,TV Encoder vDAC Test Toggle Register" bitfld.long 0x2c 13. " ENABLE_PIX_INT_GAIN ,Enabling this bit will attenuate the output of the pix_int block to ensure that the frequency response is never greater than 0.0dB" "Not toggle,Toggle" bitfld.long 0x2c 12. " BYPASS_PIX_INT ,Pixel interpolator is bypassed" "Not toggle,Toggle" textline " " bitfld.long 0x2c 11. " BYPASS_PIX_INT_DROOP ,Bypass the droop compensation portion of the pixel interpolator" "Not toggle,Toggle" bitfld.long 0x2c 10. " TEST_FIFO_FULL ,Test fifo is full" "Not toggle,Toggle" textline " " hexmask.long.word 0x2c 0.--9. 1. " DATA ,Digital data sample going to DAC 0" rgroup.long 0x1d0++0x03 line.long 0x00 "HW_TVENC_VERSION,TV Encoder Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree.open "SSP (Synchronous Serial Ports)" tree "SSP 1" base asd:0x80010000 width 17. if (((d.l(asd:(0x80010000+0x60)))&0xf)==0x0) ;SPI group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not asserted,Asserted" textline " " bitfld.long 0x00 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Asserted,Deasserted" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x00 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Set" textline " " bitfld.long 0x04 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x04 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Clear" textline " " bitfld.long 0x08 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x08 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x0c 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words to transfer" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x00 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" bitfld.long 0x04 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x04 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x04 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" bitfld.long 0x08 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x08 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0c 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" elif (((d.l(asd:(0x80010000+0x60)))&0xf)==0x1) ;SSI group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not asserted,Asserted" textline " " bitfld.long 0x00 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Asserted,Deasserted" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x00 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Set" textline " " bitfld.long 0x04 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x04 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Clear" textline " " bitfld.long 0x08 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x08 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x0c 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words to transfer" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x00 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" bitfld.long 0x04 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x04 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x04 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" bitfld.long 0x08 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x08 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0c 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" elif (((d.l(asd:(0x80010000+0x60)))&0xf)==0x3) ;SDMMC group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Look for CRC,Ignore CRC" bitfld.long 0x00 26. " IGNORE_CRC ,Ignores the Response CRC" "Not ignored,Ignored" textline " " bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" textline " " bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not wait,Wait" textline " " bitfld.long 0x00 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not wait,Wait" bitfld.long 0x00 19. " LONG_RESP ,Get Long Response" "Short,Long" textline " " bitfld.long 0x00 18. " CHECK_RESP ,Check Response" "Not checked,Checked" bitfld.long 0x00 17. " GET_RESP ,Get Response" "Not wait for response,Wait for response" textline " " bitfld.long 0x00 16. " ENABLE ,Command Transmit Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Set" textline " " bitfld.long 0x04 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Set" bitfld.long 0x04 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Set" textline " " bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" textline " " bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x04 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Set" textline " " bitfld.long 0x04 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Set" bitfld.long 0x04 19. " LONG_RESP ,Get Long Response" "No effect,Set" textline " " bitfld.long 0x04 18. " CHECK_RESP ,Check Response" "No effect,Set" bitfld.long 0x04 17. " GET_RESP ,Get Response" "No effect,Set" textline " " bitfld.long 0x04 16. " ENABLE ,Command Transmit Enable" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Clear" bitfld.long 0x08 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Clear" textline " " bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" textline " " bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x08 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Clear" textline " " bitfld.long 0x08 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Clear" bitfld.long 0x08 19. " LONG_RESP ,Get Long Response" "No effect,Clear" textline " " bitfld.long 0x08 18. " CHECK_RESP ,Check Response" "No effect,Clear" bitfld.long 0x08 17. " GET_RESP ,Get Response" "No effect,Clear" textline " " bitfld.long 0x08 16. " ENABLE ,Command Transmit Enable" "No effect,Clear" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " IGNORE_CRC ,Ignores the Response CRC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x0c 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not toggle,Toggle" bitfld.long 0x0c 19. " LONG_RESP ,Get Long Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " CHECK_RESP ,Check Response" "Not toggle,Toggle" bitfld.long 0x0c 17. " GET_RESP ,Get Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " ENABLE ,Command Transmit Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words to transfer" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" bitfld.long 0x00 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" bitfld.long 0x04 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x04 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" bitfld.long 0x04 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" bitfld.long 0x08 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" bitfld.long 0x08 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0c 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" bitfld.long 0x0c 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." else group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words to transfer" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" bitfld.long 0x04 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x04 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" hexmask.long.byte 0x04 0.--7. 1. " CMD ,Command" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" bitfld.long 0x08 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" hexmask.long.byte 0x08 0.--7. 1. " CMD ,Command" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0c 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,Command" endif group.long 0x20++0x03 line.long 0x00 "HW_SSP_CMD1,SD/MMC Command Register 1" group.long 0x30++0x03 line.long 0x00 "HW_SSP_COMPREF,SD/MMC Compare Reference" group.long 0x40++0x03 line.long 0x00 "HW_SSP_COMPMASK,SD/MMC Compare Mask Register" bitfld.long 0x00 31. " MASK[31:0] ,SD/MMC Compare mode Mask bit 31" "0,1" bitfld.long 0x00 30. ",SD/MMC Compare mode Mask bit 30" "0,1" bitfld.long 0x00 29. ",SD/MMC Compare mode Mask bit 29" "0,1" bitfld.long 0x00 28. ",SD/MMC Compare mode Mask bit 28" "0,1" bitfld.long 0x00 27. ",SD/MMC Compare mode Mask bit 27" "0,1" bitfld.long 0x00 26. ",SD/MMC Compare mode Mask bit 26" "0,1" bitfld.long 0x00 25. ",SD/MMC Compare mode Mask bit 25" "0,1" bitfld.long 0x00 24. ",SD/MMC Compare mode Mask bit 24" "0,1" bitfld.long 0x00 23. ",SD/MMC Compare mode Mask bit 23" "0,1" bitfld.long 0x00 22. ",SD/MMC Compare mode Mask bit 22" "0,1" bitfld.long 0x00 21. ",SD/MMC Compare mode Mask bit 21" "0,1" bitfld.long 0x00 20. ",SD/MMC Compare mode Mask bit 20" "0,1" bitfld.long 0x00 19. ",SD/MMC Compare mode Mask bit 19" "0,1" bitfld.long 0x00 18. ",SD/MMC Compare mode Mask bit 18" "0,1" bitfld.long 0x00 17. ",SD/MMC Compare mode Mask bit 17" "0,1" bitfld.long 0x00 16. ",SD/MMC Compare mode Mask bit 16" "0,1" bitfld.long 0x00 15. ",SD/MMC Compare mode Mask bit 15" "0,1" bitfld.long 0x00 14. ",SD/MMC Compare mode Mask bit 14" "0,1" bitfld.long 0x00 13. ",SD/MMC Compare mode Mask bit 13" "0,1" bitfld.long 0x00 12. ",SD/MMC Compare mode Mask bit 12" "0,1" bitfld.long 0x00 11. ",SD/MMC Compare mode Mask bit 11" "0,1" bitfld.long 0x00 10. ",SD/MMC Compare mode Mask bit 10" "0,1" bitfld.long 0x00 9. ",SD/MMC Compare mode Mask bit 9" "0,1" bitfld.long 0x00 8. ",SD/MMC Compare mode Mask bit 8" "0,1" bitfld.long 0x00 7. ",SD/MMC Compare mode Mask bit 7" "0,1" bitfld.long 0x00 6. ",SD/MMC Compare mode Mask bit 6" "0,1" bitfld.long 0x00 5. ",SD/MMC Compare mode Mask bit 5" "0,1" bitfld.long 0x00 4. ",SD/MMC Compare mode Mask bit 4" "0,1" bitfld.long 0x00 3. ",SD/MMC Compare mode Mask bit 3" "0,1" bitfld.long 0x00 2. ",SD/MMC Compare mode Mask bit 2" "0,1" bitfld.long 0x00 1. ",SD/MMC Compare mode Mask bit 1" "0,1" bitfld.long 0x00 0. ",SD/MMC Compare mode Mask bit 0" "0,1" group.long 0x50++0x03 line.long 0x00 "HW_SSP_TIMING,SSP Timing Register" hexmask.long.word 0x00 16.--31. 1. " TIMEOUT ,Timeout counter" hexmask.long.byte 0x00 8.--15. 1. " CLOCK_DIVIDE ,Clock Pre-Divider" textline " " hexmask.long.byte 0x00 0.--7. 1. " CLOCK_RATE ,Serial Clock Rate" if (((d.l(asd:(0x80010000+0x60)))&0xf)==0x0) ;SPI group.long 0x60++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not occurred,Occurred" bitfld.long 0x00 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 10. " PHASE ,Serial Clock Phase" "0,1" bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Steady-state 0,Steady-state 1" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Set" bitfld.long 0x04 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 10. " PHASE ,Serial Clock Phase" "No effect,Set" bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Clear" bitfld.long 0x08 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 10. " PHASE ,Serial Clock Phase" "No effect,Clear" bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " PHASE ,Serial Clock Phase" "Not toggle,Toggle" bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80010000+0x60)))&0xf)==0x1) ;SSI group.long 0x60++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80010000+0x60)))&0xf)==0x3) ;SDMMC group.long 0x60++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Set" bitfld.long 0x04 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Clear" bitfld.long 0x08 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." else group.long 0x60++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." endif group.long 0x70++0x03 line.long 0x00 "HW_SSP_DATA,SSP Data Register" rgroup.long 0x80++0x03 line.long 0x00 "HW_SSP_SDRESP0,SD/MMC Card Response Register 0" rgroup.long 0x90++0x03 line.long 0x00 "HW_SSP_SDRESP1,SD/MMC Card Response Register 1" rgroup.long 0xa0++0x03 line.long 0x00 "HW_SSP_SDRESP2,SD/MMC Card Response Register 2" rgroup.long 0xb0++0x03 line.long 0x00 "HW_SSP_SDRESP3,SD/MMC Card Response Register 3" rgroup.long 0xc0++0x03 line.long 0x00 "HW_SSP_STATUS,SSP Status Register" bitfld.long 0x00 31. " PRESENT ,SSP Present Bit" "Not present,Present" bitfld.long 0x00 29. " SD_PRESENT ,SD/MMC Controller Present bit" "Not present,Present" textline " " bitfld.long 0x00 28. " CARD_DETECT ,Reflects the state of the SSP_DETECT input pin" "Low,High" bitfld.long 0x00 21. " DMASENSE ,Reflects the state of the ssp_dmasense output port" "Low,High" textline " " bitfld.long 0x00 20. " DMATERM ,Reflects the state of the ssp_dmaterm output port" "Low,High" bitfld.long 0x00 19. " DMAREQ ,Reflects the state of the ssp_dmareq output port" "Low,High" textline " " bitfld.long 0x00 18. " DMAEND ,Reflects the state of the ssp_dmaend output port" "Low,High" bitfld.long 0x00 17. " SDIO_IRQ ,SDIO IRQ has been detected" "Not detected,Detected" textline " " bitfld.long 0x00 16. " RESP_CRC_ERR ,SD/MMC Response failed CRC check" "No error,Error" bitfld.long 0x00 15. " RESP_ERR ,SD/MMC Card Responded to Command with an Error Condition" "No error,Error" textline " " bitfld.long 0x00 14. " RESP_TIMEOUT ,SD/MMC Card Expected Command Response not received within 64 CLK cycles" "No timeout,Timeout" bitfld.long 0x00 13. " DATA_CRC_ERR ,Data CRC Error" "No error,Error" textline " " bitfld.long 0x00 12. " TIMEOUT ,SD/MMC - timeout counter expired before data bus was ready" "No timeout,Timeout" bitfld.long 0x00 11. " RECV_TIMEOUT_STAT ,Raw Receive Timeout Status" "No timeout,Timeout" textline " " bitfld.long 0x00 9. " FIFO_OVRFLW ,FIFO Overflow Interrupt" "Not occurred,Occurred" bitfld.long 0x00 8. " FIFO_FULL ,FIFO FULL" "Not full,Full" textline " " bitfld.long 0x00 5. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " FIFO_UNDRFLW ,FIFO Underflow has occurred" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " CMD_BUSY ,SD/MMC command controller is busy SD/MMC command controller is busy sending a command" "Not busy,Busy" bitfld.long 0x00 2. " DATA_BUSY ,SD/MMC command controller is busy transferring data" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUSY ,SSP State Machines are Busy" "Not busy,Busy" rgroup.long 0x100++0x03 line.long 0x00 "HW_SSP_DEBUG,SSP Debug Register" bitfld.long 0x00 28.--31. " DATACRC_ERR ,Data CRC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DATA_STALL ,MMC mode" "0,1" textline " " bitfld.long 0x00 24.--26. " DAT_SM ,MMC dataxfer state machine" "DSM IDLE,Reserved,DSM WORD,DSM CRC1,DSM CRC2,DSM END,?..." bitfld.long 0x00 19. " CMD_OE ,Enable for SSP_CMD" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--18. " DMA_SM ,DMA state machine" "DMA IDLE,DMA DMAREQ,DMA DMAACK,DMA STALL,DMA BUSY,DMA DDONE,DMA COUNT,?..." bitfld.long 0x00 12.--15. " MMC_SM ,MMC_state machine" "MMC IDLE,MMC CMD,MMC TRC,MMC RESP,MMC RPRX,MMC TX,MMC CTOK,MMC RX,MMC CCS,MMC PUP,MMC WAIT,?..." textline " " bitfld.long 0x00 10.--11. " CMD_SM ,MMC command_state machine" "CSM IDLE,CSM INDEX,CSM ARG,CSM CRC" bitfld.long 0x00 9. " SSP_CMD ,SSP_CMD" "0,1" textline " " bitfld.long 0x00 8. " SSP_RESP ,SSP_RESP" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSP_RXD ,SSP_RXD" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_VERSION,SSP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "SSP 2" base asd:0x80034000 width 17. if (((d.l(asd:(0x80034000+0x60)))&0xf)==0x0) ;SPI group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not asserted,Asserted" textline " " bitfld.long 0x00 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Asserted,Deasserted" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x00 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Set" textline " " bitfld.long 0x04 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x04 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Clear" textline " " bitfld.long 0x08 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x08 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x0c 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words to transfer" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x00 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" bitfld.long 0x04 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x04 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x04 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" bitfld.long 0x08 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x08 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0c 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" elif (((d.l(asd:(0x80034000+0x60)))&0xf)==0x1) ;SSI group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not asserted,Asserted" textline " " bitfld.long 0x00 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Asserted,Deasserted" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x00 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Set" textline " " bitfld.long 0x04 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x04 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Clear" textline " " bitfld.long 0x08 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x08 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x0c 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words to transfer" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x00 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" bitfld.long 0x04 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x04 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x04 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" bitfld.long 0x08 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x08 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0c 8.--15. 1. " BLOCK_COUNT ,SPI/SSI control word[7:0] for RX transfers" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" elif (((d.l(asd:(0x80034000+0x60)))&0xf)==0x3) ;SDMMC group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Look for CRC,Ignore CRC" bitfld.long 0x00 26. " IGNORE_CRC ,Ignores the Response CRC" "Not ignored,Ignored" textline " " bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" textline " " bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not wait,Wait" textline " " bitfld.long 0x00 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not wait,Wait" bitfld.long 0x00 19. " LONG_RESP ,Get Long Response" "Short,Long" textline " " bitfld.long 0x00 18. " CHECK_RESP ,Check Response" "Not checked,Checked" bitfld.long 0x00 17. " GET_RESP ,Get Response" "Not wait for response,Wait for response" textline " " bitfld.long 0x00 16. " ENABLE ,Command Transmit Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Set" textline " " bitfld.long 0x04 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Set" bitfld.long 0x04 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Set" textline " " bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" textline " " bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x04 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Set" textline " " bitfld.long 0x04 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Set" bitfld.long 0x04 19. " LONG_RESP ,Get Long Response" "No effect,Set" textline " " bitfld.long 0x04 18. " CHECK_RESP ,Check Response" "No effect,Set" bitfld.long 0x04 17. " GET_RESP ,Get Response" "No effect,Set" textline " " bitfld.long 0x04 16. " ENABLE ,Command Transmit Enable" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Clear" bitfld.long 0x08 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Clear" textline " " bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" textline " " bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x08 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Clear" textline " " bitfld.long 0x08 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Clear" bitfld.long 0x08 19. " LONG_RESP ,Get Long Response" "No effect,Clear" textline " " bitfld.long 0x08 18. " CHECK_RESP ,Check Response" "No effect,Clear" bitfld.long 0x08 17. " GET_RESP ,Get Response" "No effect,Clear" textline " " bitfld.long 0x08 16. " ENABLE ,Command Transmit Enable" "No effect,Clear" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " IGNORE_CRC ,Ignores the Response CRC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x0c 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not toggle,Toggle" bitfld.long 0x0c 19. " LONG_RESP ,Get Long Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " CHECK_RESP ,Check Response" "Not toggle,Toggle" bitfld.long 0x0c 17. " GET_RESP ,Get Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " ENABLE ,Command Transmit Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words to transfer" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" bitfld.long 0x00 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" bitfld.long 0x04 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x04 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" bitfld.long 0x04 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" bitfld.long 0x08 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" bitfld.long 0x08 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0c 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" bitfld.long 0x0c 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." else group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words to transfer" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words to transfer" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" bitfld.long 0x04 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x04 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" hexmask.long.byte 0x04 0.--7. 1. " CMD ,Command" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" bitfld.long 0x08 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x08 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" hexmask.long.byte 0x08 0.--7. 1. " CMD ,Command" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" bitfld.long 0x0c 16.--19. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0c 8.--15. 1. " BLOCK_COUNT ,SD/MMC block size encode" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,Command" endif group.long 0x20++0x03 line.long 0x00 "HW_SSP_CMD1,SD/MMC Command Register 1" group.long 0x30++0x03 line.long 0x00 "HW_SSP_COMPREF,SD/MMC Compare Reference" group.long 0x40++0x03 line.long 0x00 "HW_SSP_COMPMASK,SD/MMC Compare Mask Register" bitfld.long 0x00 31. " MASK[31:0] ,SD/MMC Compare mode Mask bit 31" "0,1" bitfld.long 0x00 30. ",SD/MMC Compare mode Mask bit 30" "0,1" bitfld.long 0x00 29. ",SD/MMC Compare mode Mask bit 29" "0,1" bitfld.long 0x00 28. ",SD/MMC Compare mode Mask bit 28" "0,1" bitfld.long 0x00 27. ",SD/MMC Compare mode Mask bit 27" "0,1" bitfld.long 0x00 26. ",SD/MMC Compare mode Mask bit 26" "0,1" bitfld.long 0x00 25. ",SD/MMC Compare mode Mask bit 25" "0,1" bitfld.long 0x00 24. ",SD/MMC Compare mode Mask bit 24" "0,1" bitfld.long 0x00 23. ",SD/MMC Compare mode Mask bit 23" "0,1" bitfld.long 0x00 22. ",SD/MMC Compare mode Mask bit 22" "0,1" bitfld.long 0x00 21. ",SD/MMC Compare mode Mask bit 21" "0,1" bitfld.long 0x00 20. ",SD/MMC Compare mode Mask bit 20" "0,1" bitfld.long 0x00 19. ",SD/MMC Compare mode Mask bit 19" "0,1" bitfld.long 0x00 18. ",SD/MMC Compare mode Mask bit 18" "0,1" bitfld.long 0x00 17. ",SD/MMC Compare mode Mask bit 17" "0,1" bitfld.long 0x00 16. ",SD/MMC Compare mode Mask bit 16" "0,1" bitfld.long 0x00 15. ",SD/MMC Compare mode Mask bit 15" "0,1" bitfld.long 0x00 14. ",SD/MMC Compare mode Mask bit 14" "0,1" bitfld.long 0x00 13. ",SD/MMC Compare mode Mask bit 13" "0,1" bitfld.long 0x00 12. ",SD/MMC Compare mode Mask bit 12" "0,1" bitfld.long 0x00 11. ",SD/MMC Compare mode Mask bit 11" "0,1" bitfld.long 0x00 10. ",SD/MMC Compare mode Mask bit 10" "0,1" bitfld.long 0x00 9. ",SD/MMC Compare mode Mask bit 9" "0,1" bitfld.long 0x00 8. ",SD/MMC Compare mode Mask bit 8" "0,1" bitfld.long 0x00 7. ",SD/MMC Compare mode Mask bit 7" "0,1" bitfld.long 0x00 6. ",SD/MMC Compare mode Mask bit 6" "0,1" bitfld.long 0x00 5. ",SD/MMC Compare mode Mask bit 5" "0,1" bitfld.long 0x00 4. ",SD/MMC Compare mode Mask bit 4" "0,1" bitfld.long 0x00 3. ",SD/MMC Compare mode Mask bit 3" "0,1" bitfld.long 0x00 2. ",SD/MMC Compare mode Mask bit 2" "0,1" bitfld.long 0x00 1. ",SD/MMC Compare mode Mask bit 1" "0,1" bitfld.long 0x00 0. ",SD/MMC Compare mode Mask bit 0" "0,1" group.long 0x50++0x03 line.long 0x00 "HW_SSP_TIMING,SSP Timing Register" hexmask.long.word 0x00 16.--31. 1. " TIMEOUT ,Timeout counter" hexmask.long.byte 0x00 8.--15. 1. " CLOCK_DIVIDE ,Clock Pre-Divider" textline " " hexmask.long.byte 0x00 0.--7. 1. " CLOCK_RATE ,Serial Clock Rate" if (((d.l(asd:(0x80034000+0x60)))&0xf)==0x0) ;SPI group.long 0x60++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not occurred,Occurred" bitfld.long 0x00 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 10. " PHASE ,Serial Clock Phase" "0,1" bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Steady-state 0,Steady-state 1" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Set" bitfld.long 0x04 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 10. " PHASE ,Serial Clock Phase" "No effect,Set" bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Clear" bitfld.long 0x08 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 10. " PHASE ,Serial Clock Phase" "No effect,Clear" bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " PHASE ,Serial Clock Phase" "Not toggle,Toggle" bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80034000+0x60)))&0xf)==0x1) ;SSI group.long 0x60++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80034000+0x60)))&0xf)==0x3) ;SDMMC group.long 0x60++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Set" bitfld.long 0x04 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Clear" bitfld.long 0x08 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." else group.long 0x60++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." endif group.long 0x70++0x03 line.long 0x00 "HW_SSP_DATA,SSP Data Register" rgroup.long 0x80++0x03 line.long 0x00 "HW_SSP_SDRESP0,SD/MMC Card Response Register 0" rgroup.long 0x90++0x03 line.long 0x00 "HW_SSP_SDRESP1,SD/MMC Card Response Register 1" rgroup.long 0xa0++0x03 line.long 0x00 "HW_SSP_SDRESP2,SD/MMC Card Response Register 2" rgroup.long 0xb0++0x03 line.long 0x00 "HW_SSP_SDRESP3,SD/MMC Card Response Register 3" rgroup.long 0xc0++0x03 line.long 0x00 "HW_SSP_STATUS,SSP Status Register" bitfld.long 0x00 31. " PRESENT ,SSP Present Bit" "Not present,Present" bitfld.long 0x00 29. " SD_PRESENT ,SD/MMC Controller Present bit" "Not present,Present" textline " " bitfld.long 0x00 28. " CARD_DETECT ,Reflects the state of the SSP_DETECT input pin" "Low,High" bitfld.long 0x00 21. " DMASENSE ,Reflects the state of the ssp_dmasense output port" "Low,High" textline " " bitfld.long 0x00 20. " DMATERM ,Reflects the state of the ssp_dmaterm output port" "Low,High" bitfld.long 0x00 19. " DMAREQ ,Reflects the state of the ssp_dmareq output port" "Low,High" textline " " bitfld.long 0x00 18. " DMAEND ,Reflects the state of the ssp_dmaend output port" "Low,High" bitfld.long 0x00 17. " SDIO_IRQ ,SDIO IRQ has been detected" "Not detected,Detected" textline " " bitfld.long 0x00 16. " RESP_CRC_ERR ,SD/MMC Response failed CRC check" "No error,Error" bitfld.long 0x00 15. " RESP_ERR ,SD/MMC Card Responded to Command with an Error Condition" "No error,Error" textline " " bitfld.long 0x00 14. " RESP_TIMEOUT ,SD/MMC Card Expected Command Response not received within 64 CLK cycles" "No timeout,Timeout" bitfld.long 0x00 13. " DATA_CRC_ERR ,Data CRC Error" "No error,Error" textline " " bitfld.long 0x00 12. " TIMEOUT ,SD/MMC - timeout counter expired before data bus was ready" "No timeout,Timeout" bitfld.long 0x00 11. " RECV_TIMEOUT_STAT ,Raw Receive Timeout Status" "No timeout,Timeout" textline " " bitfld.long 0x00 9. " FIFO_OVRFLW ,FIFO Overflow Interrupt" "Not occurred,Occurred" bitfld.long 0x00 8. " FIFO_FULL ,FIFO FULL" "Not full,Full" textline " " bitfld.long 0x00 5. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty" bitfld.long 0x00 4. " FIFO_UNDRFLW ,FIFO Underflow has occurred" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " CMD_BUSY ,SD/MMC command controller is busy SD/MMC command controller is busy sending a command" "Not busy,Busy" bitfld.long 0x00 2. " DATA_BUSY ,SD/MMC command controller is busy transferring data" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUSY ,SSP State Machines are Busy" "Not busy,Busy" rgroup.long 0x100++0x03 line.long 0x00 "HW_SSP_DEBUG,SSP Debug Register" bitfld.long 0x00 28.--31. " DATACRC_ERR ,Data CRC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DATA_STALL ,MMC mode" "0,1" textline " " bitfld.long 0x00 24.--26. " DAT_SM ,MMC dataxfer state machine" "DSM IDLE,Reserved,DSM WORD,DSM CRC1,DSM CRC2,DSM END,?..." bitfld.long 0x00 19. " CMD_OE ,Enable for SSP_CMD" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--18. " DMA_SM ,DMA state machine" "DMA IDLE,DMA DMAREQ,DMA DMAACK,DMA STALL,DMA BUSY,DMA DDONE,DMA COUNT,?..." bitfld.long 0x00 12.--15. " MMC_SM ,MMC_state machine" "MMC IDLE,MMC CMD,MMC TRC,MMC RESP,MMC RPRX,MMC TX,MMC CTOK,MMC RX,MMC CCS,MMC PUP,MMC WAIT,?..." textline " " bitfld.long 0x00 10.--11. " CMD_SM ,MMC command_state machine" "CSM IDLE,CSM INDEX,CSM ARG,CSM CRC" bitfld.long 0x00 9. " SSP_CMD ,SSP_CMD" "0,1" textline " " bitfld.long 0x00 8. " SSP_RESP ,SSP_RESP" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSP_RXD ,SSP_RXD" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_VERSION,SSP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree.end tree "TIMROT (Timers and Rotary Decoder)" base asd:0x80068000 width 24. group.long 0x00++0x0f line.long 0x00 "HW_TIMROT_ROTCTRL,Rotary Decoder Control Register" bitfld.long 0x00 31. " SFTRST ,Force a block-level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 29. " ROTARY_PRESENT ,Rotary decoder is present is in this product" "Not present,Present" bitfld.long 0x00 28. " TIM3_PRESENT ,TIMER3 is present is in this product" "Not present,Present" textline " " bitfld.long 0x00 27. " TIM2_PRESENT ,TIMER2 is present is in this product" "Not present,Present" bitfld.long 0x00 26. " TIM1_PRESENT ,TIMER1 is present is in this product" "Not present,Present" textline " " bitfld.long 0x00 25. " TIM0_PRESENT ,TIMER0 is present is in this product" "Not present,Present" bitfld.long 0x00 22.--24. " STATE ,View of the rotary decoder transition detecting state machine" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16.--21. " DIVIDER ,Divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 12. " RELATIVE ,Reset to zero rotary decoders updown counter whenever it is read" "No reset,Reset" textline " " bitfld.long 0x00 10.--11. " OVERSAMPLE ,Determine the oversample rate to use in debouncing Rotary A and B inputs" "8x,4x,2x,1x" bitfld.long 0x00 9. " POLARITY_B ,Invert the input to the edge detector" "Not inverted,Inverted" textline " " bitfld.long 0x00 8. " POLARITY_A ,Invert the input to the edge detector" "Not inverted,Inverted" bitfld.long 0x00 4.--6. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B" textline " " bitfld.long 0x00 0.--2. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B" line.long 0x04 "HW_TIMROT_ROTCTRL_SET,Rotary Decoder Control Set Register" bitfld.long 0x04 31. " SFTRST ,Force a block-level reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " ROTARY_PRESENT ,Rotary decoder is present is in this product" "No effect,Set" bitfld.long 0x04 28. " TIM3_PRESENT ,TIMER3 is present is in this product" "No effect,Set" textline " " bitfld.long 0x04 27. " TIM2_PRESENT ,TIMER2 is present is in this product" "No effect,Set" bitfld.long 0x04 26. " TIM1_PRESENT ,TIMER1 is present is in this product" "No effect,Set" textline " " bitfld.long 0x04 25. " TIM0_PRESENT ,TIMER0 is present is in this product" "No effect,Set" bitfld.long 0x04 22.--24. " STATE ,View of the rotary decoder transition detecting state machine" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 16.--21. " DIVIDER ,Divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x04 12. " RELATIVE ,Reset to zero rotary decoders updown counter whenever it is read" "No effect,Set" textline " " bitfld.long 0x04 10.--11. " OVERSAMPLE ,Determine the oversample rate to use in debouncing Rotary A and B inputs" "8x,4x,2x,1x" bitfld.long 0x04 9. " POLARITY_B ,Invert the input to the edge detector" "No effect,Set" textline " " bitfld.long 0x04 8. " POLARITY_A ,Invert the input to the edge detector" "No effect,Set" bitfld.long 0x04 4.--6. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B" textline " " bitfld.long 0x04 0.--2. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B" line.long 0x08 "HW_TIMROT_ROTCTRL_CLR,Rotary Decoder Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Force a block-level reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " ROTARY_PRESENT ,Rotary decoder is present is in this product" "No effect,Clear" bitfld.long 0x08 28. " TIM3_PRESENT ,TIMER3 is present is in this product" "No effect,Clear" textline " " bitfld.long 0x08 27. " TIM2_PRESENT ,TIMER2 is present is in this product" "No effect,Clear" bitfld.long 0x08 26. " TIM1_PRESENT ,TIMER1 is present is in this product" "No effect,Clear" textline " " bitfld.long 0x08 25. " TIM0_PRESENT ,TIMER0 is present is in this product" "No effect,Clear" bitfld.long 0x08 22.--24. " STATE ,View of the rotary decoder transition detecting state machine" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 16.--21. " DIVIDER ,Divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 12. " RELATIVE ,Reset to zero rotary decoders updown counter whenever it is read" "No effect,Clear" textline " " bitfld.long 0x08 10.--11. " OVERSAMPLE ,Determine the oversample rate to use in debouncing Rotary A and B inputs" "8x,4x,2x,1x" bitfld.long 0x08 9. " POLARITY_B ,Invert the input to the edge detector" "No effect,Clear" textline " " bitfld.long 0x08 8. " POLARITY_A ,Invert the input to the edge detector" "No effect,Clear" bitfld.long 0x08 4.--6. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B" textline " " bitfld.long 0x08 0.--2. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B" line.long 0x0c "HW_TIMROT_ROTCTRL_TOG,Rotary Decoder Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Force a block-level reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " ROTARY_PRESENT ,Rotary decoder is present is in this product" "Not toggle,Toggle" bitfld.long 0x0c 28. " TIM3_PRESENT ,TIMER3 is present is in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " TIM2_PRESENT ,TIMER2 is present is in this product" "Not toggle,Toggle" bitfld.long 0x0c 26. " TIM1_PRESENT ,TIMER1 is present is in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " TIM0_PRESENT ,TIMER0 is present is in this product" "Not toggle,Toggle" bitfld.long 0x0c 22.--24. " STATE ,View of the rotary decoder transition detecting state machine" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 16.--21. " DIVIDER ,Divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x0c 12. " RELATIVE ,Reset to zero rotary decoders updown counter whenever it is read" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10.--11. " OVERSAMPLE ,Determine the oversample rate to use in debouncing Rotary A and B inputs" "8x,4x,2x,1x" bitfld.long 0x0c 9. " POLARITY_B ,Invert the input to the edge detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " POLARITY_A ,Invert the input to the edge detector" "Not toggle,Toggle" bitfld.long 0x0c 4.--6. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B" textline " " bitfld.long 0x0c 0.--2. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B" rgroup.long 0x10++0x03 line.long 0x00 "HW_TIMROT_ROTCOUNT,Rotary Decoder Up/Down Counter Register" hexmask.long.word 0x00 0.--15. 1. " UPDOWN ,Counter value" group.long 0x20++0x13 "Timer 0 Registers" line.long 0x00 "HW_TIMROT_TIMCTRL0,Timer 0 Control and Status Register" bitfld.long 0x00 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "Clear,Zero" bitfld.long 0x00 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POLARITY ,Invert the input to the edge detector" "Not inverted,Inverted" bitfld.long 0x00 7. " UPDATE ,Running count update" "Not updated,Updated" textline " " bitfld.long 0x00 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not reloaded,Reloaded" bitfld.long 0x00 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x00 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x04 "HW_TIMROT_TIMCTRL0_SET,Timer 0 Control and Status Set Register" bitfld.long 0x04 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "No effect,Set" bitfld.long 0x04 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Set" textline " " bitfld.long 0x04 8. " POLARITY ,Invert the input to the edge detector" "No effect,Set" bitfld.long 0x04 7. " UPDATE ,Running count update" "No effect,Set" textline " " bitfld.long 0x04 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Set" bitfld.long 0x04 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x04 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x08 "HW_TIMROT_TIMCTRL0_CLR,Timer 0 Control and Status Clear Register" bitfld.long 0x08 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "No effect,Clear" bitfld.long 0x08 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Clear" textline " " bitfld.long 0x08 8. " POLARITY ,Invert the input to the edge detector" "No effect,Clear" bitfld.long 0x08 7. " UPDATE ,Running count update" "No effect,Clear" textline " " bitfld.long 0x08 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Clear" bitfld.long 0x08 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x08 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x0c "HW_TIMROT_TIMCTRL0_TOG,Timer 0 Control and Status Toggle Register" bitfld.long 0x0c 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " POLARITY ,Invert the input to the edge detector" "Not toggle,Toggle" bitfld.long 0x0c 7. " UPDATE ,Running count update" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x0c 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x10 "HW_TIMROT_TIMCOUNT0,Timer 0 Count Register" hexmask.long.word 0x10 16.--31. 1. " RUNNING_COUNT ,Shows the current state of the running count as it decrements" hexmask.long.word 0x10 0.--15. 1. " FIXED_COUNT ,Software loads the fixed count bit field with the value to down count" group.long 0x40++0x13 "Timer 1 Registers" line.long 0x00 "HW_TIMROT_TIMCTRL1,Timer 1 Control and Status Register" bitfld.long 0x00 15. " IRQ ,This bit is set to one when Timer 1 decrements to zero" "Clear,Zero" bitfld.long 0x00 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POLARITY ,Invert the input to the edge detector" "Not inverted,Inverted" bitfld.long 0x00 7. " UPDATE ,Running count update" "Not updated,Updated" textline " " bitfld.long 0x00 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not reloaded,Reloaded" bitfld.long 0x00 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x00 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x04 "HW_TIMROT_TIMCTRL1_SET,Timer 1 Control and Status Set Register" bitfld.long 0x04 15. " IRQ ,This bit is set to one when Timer 1 decrements to zero" "No effect,Set" bitfld.long 0x04 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Set" textline " " bitfld.long 0x04 8. " POLARITY ,Invert the input to the edge detector" "No effect,Set" bitfld.long 0x04 7. " UPDATE ,Running count update" "No effect,Set" textline " " bitfld.long 0x04 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Set" bitfld.long 0x04 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x04 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x08 "HW_TIMROT_TIMCTRL1_CLR,Timer 1 Control and Status Clear Register" bitfld.long 0x08 15. " IRQ ,This bit is set to one when Timer 1 decrements to zero" "No effect,Clear" bitfld.long 0x08 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Clear" textline " " bitfld.long 0x08 8. " POLARITY ,Invert the input to the edge detector" "No effect,Clear" bitfld.long 0x08 7. " UPDATE ,Running count update" "No effect,Clear" textline " " bitfld.long 0x08 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Clear" bitfld.long 0x08 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x08 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x0c "HW_TIMROT_TIMCTRL1_TOG,Timer 1 Control and Status Toggle Register" bitfld.long 0x0c 15. " IRQ ,This bit is set to one when Timer 1 decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " POLARITY ,Invert the input to the edge detector" "Not toggle,Toggle" bitfld.long 0x0c 7. " UPDATE ,Running count update" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x0c 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x10 "HW_TIMROT_TIMCOUNT1,Timer 1 Count Register" hexmask.long.word 0x10 16.--31. 1. " RUNNING_COUNT ,Shows the current state of the running count as it decrements" hexmask.long.word 0x10 0.--15. 1. " FIXED_COUNT ,Software loads the fixed count bit field with the value to down count" group.long 0x60++0x13 "Timer 2 Registers" line.long 0x00 "HW_TIMROT_TIMCTRL2,Timer 2 Control and Status Register" bitfld.long 0x00 15. " IRQ ,This bit is set to one when Timer 2 decrements to zero" "Clear,Zero" bitfld.long 0x00 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POLARITY ,Invert the input to the edge detector" "Not inverted,Inverted" bitfld.long 0x00 7. " UPDATE ,Running count update" "Not updated,Updated" textline " " bitfld.long 0x00 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not reloaded,Reloaded" bitfld.long 0x00 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x00 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x04 "HW_TIMROT_TIMCTRL2_SET,Timer 2 Control and Status Set Register" bitfld.long 0x04 15. " IRQ ,This bit is set to one when Timer 2 decrements to zero" "No effect,Set" bitfld.long 0x04 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Set" textline " " bitfld.long 0x04 8. " POLARITY ,Invert the input to the edge detector" "No effect,Set" bitfld.long 0x04 7. " UPDATE ,Running count update" "No effect,Set" textline " " bitfld.long 0x04 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Set" bitfld.long 0x04 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x04 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x08 "HW_TIMROT_TIMCTRL2_CLR,Timer 2 Control and Status Clear Register" bitfld.long 0x08 15. " IRQ ,This bit is set to one when Timer 2 decrements to zero" "No effect,Clear" bitfld.long 0x08 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Clear" textline " " bitfld.long 0x08 8. " POLARITY ,Invert the input to the edge detector" "No effect,Clear" bitfld.long 0x08 7. " UPDATE ,Running count update" "No effect,Clear" textline " " bitfld.long 0x08 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Clear" bitfld.long 0x08 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x08 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x0c "HW_TIMROT_TIMCTRL2_TOG,Timer 2 Control and Status Toggle Register" bitfld.long 0x0c 15. " IRQ ,This bit is set to one when Timer 2 decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " POLARITY ,Invert the input to the edge detector" "Not toggle,Toggle" bitfld.long 0x0c 7. " UPDATE ,Running count update" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x0c 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x10 "HW_TIMROT_TIMCOUNT2,Timer 2 Count Register" hexmask.long.word 0x10 16.--31. 1. " RUNNING_COUNT ,Shows the current state of the running count as it decrements" hexmask.long.word 0x10 0.--15. 1. " FIXED_COUNT ,Software loads the fixed count bit field with the value to down count" group.long 0x80++0x13 "Timer 3 Registers" line.long 0x00 "HW_TIMROT_TIMCTRL3,Timer 3 Control and Status Register" bitfld.long 0x00 16.--19. " TEST_SIGNAL ,Selects the source of the signal to be measured in duty cycle mode" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." bitfld.long 0x00 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "Clear,Zero" textline " " bitfld.long 0x00 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Disabled,Enabled" bitfld.long 0x00 10. " DUTY_VALID ,Duty cycle valid" "Not valid,Valid" textline " " bitfld.long 0x00 9. " DUTY_CYCLE ,Enable Timer to operate in duty cycle measuring mode" "Disabled,Enabled" bitfld.long 0x00 8. " POLARITY ,Invert the input to the edge detector" "Not inverted,Inverted" textline " " bitfld.long 0x00 7. " UPDATE ,Running count update" "Not updated,Updated" bitfld.long 0x00 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not reloaded,Reloaded" textline " " bitfld.long 0x00 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x00 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x04 "HW_TIMROT_TIMCTRL3_SET,Timer 3 Control and Status Set Register" bitfld.long 0x04 16.--19. " TEST_SIGNAL ,Selects the source of the signal to be measured in duty cycle mode" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." bitfld.long 0x04 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "No effect,Set" textline " " bitfld.long 0x04 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Set" bitfld.long 0x04 10. " DUTY_VALID ,Duty cycle valid" "No effect,Set" textline " " bitfld.long 0x04 9. " DUTY_CYCLE ,Enable Timer to operate in duty cycle measuring mode" "No effect,Set" bitfld.long 0x04 8. " POLARITY ,Invert the input to the edge detector" "No effect,Set" textline " " bitfld.long 0x04 7. " UPDATE ,Running count update" "No effect,Set" bitfld.long 0x04 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Set" textline " " bitfld.long 0x04 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x04 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x08 "HW_TIMROT_TIMCTRL3_CLR,Timer 3 Control and Status Clear Register" bitfld.long 0x08 16.--19. " TEST_SIGNAL ,Selects the source of the signal to be measured in duty cycle mode" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." bitfld.long 0x08 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "No effect,Clear" textline " " bitfld.long 0x08 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Clear" bitfld.long 0x08 10. " DUTY_VALID ,Duty cycle valid" "No effect,Clear" textline " " bitfld.long 0x08 9. " DUTY_CYCLE ,Enable Timer to operate in duty cycle measuring mode" "No effect,Clear" bitfld.long 0x08 8. " POLARITY ,Invert the input to the edge detector" "No effect,Clear" textline " " bitfld.long 0x08 7. " UPDATE ,Running count update" "No effect,Clear" bitfld.long 0x08 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Clear" textline " " bitfld.long 0x08 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x08 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x0c "HW_TIMROT_TIMCTRL3_TOG,Timer 3 Control and Status Toggle Register" bitfld.long 0x0c 16.--19. " TEST_SIGNAL ,Selects the source of the signal to be measured in duty cycle mode" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." bitfld.long 0x0c 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Not toggle,Toggle" bitfld.long 0x0c 10. " DUTY_VALID ,Duty cycle valid" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " DUTY_CYCLE ,Enable Timer to operate in duty cycle measuring mode" "Not toggle,Toggle" bitfld.long 0x0c 8. " POLARITY ,Invert the input to the edge detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " UPDATE ,Running count update" "Not toggle,Toggle" bitfld.long 0x0c 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x0c 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always,?..." line.long 0x10 "HW_TIMROT_TIMCOUNT3,Timer 3 Count Register" hexmask.long.word 0x10 16.--31. 1. " LOW_RUNNING_COUNT ,Running counter" hexmask.long.word 0x10 0.--15. 1. " HIGH_FIXED_COUNT ,Software loads the fixed count bit field with the value to down count" rgroup.long 0xa0++0x03 "Version Register" line.long 0x00 "HW_TIMROT_VERSION,TIMROT Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " MINOR ,Fixed read-only value reflecting the stepping of the RTL version" width 0x0b tree.end tree "RTC (Real Time Clock)" base asd:0x8005c000 width 24. group.long 0x00++0x0f line.long 0x00 "HW_RTC_CTRL,Real-Time Clock Control Register" bitfld.long 0x00 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 6. " SUPPRESS_COPY2ANALOG ,Suppress the automatic copy that normally occurs to the analog side" "Normal,Suppressed" bitfld.long 0x00 5. " FORCE_UPDATE ,Udate shadow registers" "Not forced,Forced" textline " " bitfld.long 0x00 4. " WATCHDOGEN ,Enable Watchdog Timer" "Disabled,Enabled" bitfld.long 0x00 3. " ONEMSEC_IRQ ,One millisecond interrupt request status" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " ALARM_IRQ ,Alarm Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " ONEMSEC_IRQ_EN ,Enable one millisecond interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ALARM_IRQ_EN ,Enable Alarm Interrupt" "Disabled,Enabled" line.long 0x04 "HW_RTC_CTRL_SET,Real-Time Clock Control Set Register" bitfld.long 0x04 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 6. " SUPPRESS_COPY2ANALOG ,Suppress the automatic copy that normally occurs to the analog side" "No effect,Set" bitfld.long 0x04 5. " FORCE_UPDATE ,Udate shadow registers" "No effect,Set" textline " " bitfld.long 0x04 4. " WATCHDOGEN ,Enable Watchdog Timer" "No effect,Set" bitfld.long 0x04 3. " ONEMSEC_IRQ ,One millisecond interrupt request status" "No effect,Set" textline " " bitfld.long 0x04 2. " ALARM_IRQ ,Alarm Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " ONEMSEC_IRQ_EN ,Enable one millisecond interrupt" "No effect,Set" textline " " bitfld.long 0x04 0. " ALARM_IRQ_EN ,Enable Alarm Interrupt" "No effect,Set" line.long 0x08 "HW_RTC_CTRL_CLR,Real-Time Clock Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 6. " SUPPRESS_COPY2ANALOG ,Suppress the automatic copy that normally occurs to the analog side" "No effect,Clear" bitfld.long 0x08 5. " FORCE_UPDATE ,Udate shadow registers" "No effect,Clear" textline " " bitfld.long 0x08 4. " WATCHDOGEN ,Enable Watchdog Timer" "No effect,Clear" bitfld.long 0x08 3. " ONEMSEC_IRQ ,One millisecond interrupt request status" "No effect,Clear" textline " " bitfld.long 0x08 2. " ALARM_IRQ ,Alarm Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " ONEMSEC_IRQ_EN ,Enable one millisecond interrupt" "No effect,Clear" textline " " bitfld.long 0x08 0. " ALARM_IRQ_EN ,Enable Alarm Interrupt" "No effect,Clear" line.long 0x0c "HW_RTC_CTRL_TOG,Real-Time Clock Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Hold real time clock digital side in soft reset state" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " SUPPRESS_COPY2ANALOG ,Suppress the automatic copy that normally occurs to the analog side" "Not toggle,Toggle" bitfld.long 0x0c 5. " FORCE_UPDATE ,Udate shadow registers" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " WATCHDOGEN ,Enable Watchdog Timer" "Not toggle,Toggle" bitfld.long 0x0c 3. " ONEMSEC_IRQ ,One millisecond interrupt request status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ALARM_IRQ ,Alarm Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " ONEMSEC_IRQ_EN ,Enable one millisecond interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " ALARM_IRQ_EN ,Enable Alarm Interrupt" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_RTC_STAT,Real-Time Clock Status Register" bitfld.long 0x00 31. " RTC_PRESENT ,RTC is present in the device" "Not present,Present" bitfld.long 0x00 30. " ALARM_PRESENT ,Alarm function is present in the device" "Not present,Present" textline " " bitfld.long 0x00 29. " WATCHDOG_PRESENT ,Watchdog Timer function is present in the device" "Not present,Present" bitfld.long 0x00 28. " XTAL32000_PRESENT ,32.000-kHz crystal oscillator function is present in the device" "Not present,Present" textline " " bitfld.long 0x00 27. " XTAL32768_PRESENT ,32.768-kHz crystal oscillator function is present in the device" "Not present,Present" bitfld.long 0x00 23. " STALE_REG7 ,Shadow register 7 contents is older than the analog side contents" "Not older,Older" textline " " bitfld.long 0x00 22. " STALE_REG6 ,Shadow register 6 contents is older than the analog side contents" "Not older,Older" bitfld.long 0x00 21. " STALE_REG5 ,Shadow register 5 contents is older than the analog side contents" "Not older,Older" textline " " bitfld.long 0x00 20. " STALE_REG4 ,Shadow register 4 contents is older than the analog side contents" "Not older,Older" bitfld.long 0x00 19. " STALE_REG3 ,Shadow register 3 contents is older than the analog side contents" "Not older,Older" textline " " bitfld.long 0x00 18. " STALE_REG2 ,Shadow register 2 contents is older than the analog side contents" "Not older,Older" bitfld.long 0x00 17. " STALE_REG1 ,Shadow register 1 contents is older than the analog side contents" "Not older,Older" textline " " bitfld.long 0x00 16. " STALE_REG0 ,Shadow register 0 contents is older than the analog side contents" "Not older,Older" bitfld.long 0x00 15. " NEW_REG7 ,Shadow register 7 contents is newer than the analog side contents" "Not newer,Newer" textline " " bitfld.long 0x00 14. " NEW_REG6 ,Shadow register 6 contents is newer than the analog side contents" "Not newer,Newer" bitfld.long 0x00 13. " NEW_REG5 ,Shadow register 5 contents is newer than the analog side contents" "Not newer,Newer" textline " " bitfld.long 0x00 12. " NEW_REG4 ,Shadow register 4 contents is newer than the analog side contents" "Not newer,Newer" bitfld.long 0x00 11. " NEW_REG3 ,Shadow register 3 contents is newer than the analog side contents" "Not newer,Newer" textline " " bitfld.long 0x00 10. " NEW_REG2 ,Shadow register 2 contents is newer than the analog side contents" "Not newer,Newer" bitfld.long 0x00 9. " NEW_REG1 ,Shadow register 1 contents is newer than the analog side contents" "Not newer,Newer" textline " " bitfld.long 0x00 8. " NEW_REG0 ,Shadow register 0 contents is newer than the analog side contents" "Not newer,Newer" group.long 0x14++0x0b line.long 0x00 "HW_RTC_STAT_SET,Real-Time Clock Status Set Register" bitfld.long 0x00 31. " RTC_PRESENT ,RTC is present in the device" "No effect,Set" bitfld.long 0x00 30. " ALARM_PRESENT ,Alarm function is present in the device" "No effect,Set" textline " " bitfld.long 0x00 29. " WATCHDOG_PRESENT ,Watchdog Timer function is present in the device" "No effect,Set" bitfld.long 0x00 28. " XTAL32000_PRESENT ,32.000-kHz crystal oscillator function is present in the device" "No effect,Set" textline " " bitfld.long 0x00 27. " XTAL32768_PRESENT ,32.768-kHz crystal oscillator function is present in the device" "No effect,Set" bitfld.long 0x00 23. " STALE_REG7 ,Shadow register 7 contents is older than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 22. " STALE_REG6 ,Shadow register 6 contents is older than the analog side contents" "No effect,Set" bitfld.long 0x00 21. " STALE_REG5 ,Shadow register 5 contents is older than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 20. " STALE_REG4 ,Shadow register 4 contents is older than the analog side contents" "No effect,Set" bitfld.long 0x00 19. " STALE_REG3 ,Shadow register 3 contents is older than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 18. " STALE_REG2 ,Shadow register 2 contents is older than the analog side contents" "No effect,Set" bitfld.long 0x00 17. " STALE_REG1 ,Shadow register 1 contents is older than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 16. " STALE_REG0 ,Shadow register 0 contents is older than the analog side contents" "No effect,Set" bitfld.long 0x00 15. " NEW_REG7 ,Shadow register 7 contents is newer than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 14. " NEW_REG6 ,Shadow register 6 contents is newer than the analog side contents" "No effect,Set" bitfld.long 0x00 13. " NEW_REG5 ,Shadow register 5 contents is newer than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 12. " NEW_REG4 ,Shadow register 4 contents is newer than the analog side contents" "No effect,Set" bitfld.long 0x00 11. " NEW_REG3 ,Shadow register 3 contents is newer than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 10. " NEW_REG2 ,Shadow register 2 contents is newer than the analog side contents" "No effect,Set" bitfld.long 0x00 9. " NEW_REG1 ,Shadow register 1 contents is newer than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 8. " NEW_REG0 ,Shadow register 0 contents is newer than the analog side contents" "No effect,Set" line.long 0x04 "HW_RTC_STAT_CLR,Real-Time Clock Status Clear Register" bitfld.long 0x04 31. " RTC_PRESENT ,RTC is present in the device" "No effect,Clear" bitfld.long 0x04 30. " ALARM_PRESENT ,Alarm function is present in the device" "No effect,Clear" textline " " bitfld.long 0x04 29. " WATCHDOG_PRESENT ,Watchdog Timer function is present in the device" "No effect,Clear" bitfld.long 0x04 28. " XTAL32000_PRESENT ,32.000-kHz crystal oscillator function is present in the device" "No effect,Clear" textline " " bitfld.long 0x04 27. " XTAL32768_PRESENT ,32.768-kHz crystal oscillator function is present in the device" "No effect,Clear" bitfld.long 0x04 23. " STALE_REG7 ,Shadow register 7 contents is older than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 22. " STALE_REG6 ,Shadow register 6 contents is older than the analog side contents" "No effect,Clear" bitfld.long 0x04 21. " STALE_REG5 ,Shadow register 5 contents is older than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 20. " STALE_REG4 ,Shadow register 4 contents is older than the analog side contents" "No effect,Clear" bitfld.long 0x04 19. " STALE_REG3 ,Shadow register 3 contents is older than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 18. " STALE_REG2 ,Shadow register 2 contents is older than the analog side contents" "No effect,Clear" bitfld.long 0x04 17. " STALE_REG1 ,Shadow register 1 contents is older than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 16. " STALE_REG0 ,Shadow register 0 contents is older than the analog side contents" "No effect,Clear" bitfld.long 0x04 15. " NEW_REG7 ,Shadow register 7 contents is newer than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 14. " NEW_REG6 ,Shadow register 6 contents is newer than the analog side contents" "No effect,Clear" bitfld.long 0x04 13. " NEW_REG5 ,Shadow register 5 contents is newer than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 12. " NEW_REG4 ,Shadow register 4 contents is newer than the analog side contents" "No effect,Clear" bitfld.long 0x04 11. " NEW_REG3 ,Shadow register 3 contents is newer than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 10. " NEW_REG2 ,Shadow register 2 contents is newer than the analog side contents" "No effect,Clear" bitfld.long 0x04 9. " NEW_REG1 ,Shadow register 1 contents is newer than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 8. " NEW_REG0 ,Shadow register 0 contents is newer than the analog side contents" "No effect,Clear" line.long 0x08 "HW_RTC_STAT_TOG,Real-Time Clock Status Toggle Register" bitfld.long 0x08 31. " RTC_PRESENT ,RTC is present in the device" "Not toggle,Toggle" bitfld.long 0x08 30. " ALARM_PRESENT ,Alarm function is present in the device" "Not toggle,Toggle" textline " " bitfld.long 0x08 29. " WATCHDOG_PRESENT ,Watchdog Timer function is present in the device" "Not toggle,Toggle" bitfld.long 0x08 28. " XTAL32000_PRESENT ,32.000-kHz crystal oscillator function is present in the device" "Not toggle,Toggle" textline " " bitfld.long 0x08 27. " XTAL32768_PRESENT ,32.768-kHz crystal oscillator function is present in the device" "Not toggle,Toggle" bitfld.long 0x08 23. " STALE_REG7 ,Shadow register 7 contents is older than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 22. " STALE_REG6 ,Shadow register 6 contents is older than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 21. " STALE_REG5 ,Shadow register 5 contents is older than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 20. " STALE_REG4 ,Shadow register 4 contents is older than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 19. " STALE_REG3 ,Shadow register 3 contents is older than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 18. " STALE_REG2 ,Shadow register 2 contents is older than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 17. " STALE_REG1 ,Shadow register 1 contents is older than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 16. " STALE_REG0 ,Shadow register 0 contents is older than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 15. " NEW_REG7 ,Shadow register 7 contents is newer than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 14. " NEW_REG6 ,Shadow register 6 contents is newer than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 13. " NEW_REG5 ,Shadow register 5 contents is newer than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 12. " NEW_REG4 ,Shadow register 4 contents is newer than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 11. " NEW_REG3 ,Shadow register 3 contents is newer than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 10. " NEW_REG2 ,Shadow register 2 contents is newer than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 9. " NEW_REG1 ,Shadow register 1 contents is newer than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 8. " NEW_REG0 ,Shadow register 0 contents is newer than the analog side contents" "Not toggle,Toggle" group.long 0x20++0x4f line.long 0x00 "HW_RTC_MILLISECONDS,Real-Time Clock Milliseconds Counter" line.long 0x04 "HW_RTC_MILLISECONDS_SET,Real-Time Clock Milliseconds Counter Set" line.long 0x08 "HW_RTC_MILLISECONDS_CLR,Real-Time Clock Milliseconds Counter Clear" line.long 0x0c "HW_RTC_MILLISECONDS_TOG,Real-Time Clock Milliseconds Counter Toggle" line.long 0x10 "HW_RTC_SECONDS,Real-Time Clock Seconds Counter" line.long 0x14 "HW_RTC_SECONDS_SET,Real-Time Clock Seconds Counter Set" line.long 0x18 "HW_RTC_SECONDS_CLR,Real-Time Clock Seconds Counter Clear" line.long 0x1c "HW_RTC_SECONDS_TOG,Real-Time Clock Seconds Counter Toggle" line.long 0x20 "HW_RTC_ALARM,Real-Time Clock Alarm Register" line.long 0x24 "HW_RTC_ALARM_SET,Real-Time Clock Alarm Set Register" line.long 0x28 "HW_RTC_ALARM_CLR,Real-Time Clock Alarm Clear Register" line.long 0x2c "HW_RTC_ALARM_TOG,Real-Time Clock Alarm Toggle Register" line.long 0x30 "HW_RTC_WATCHDOG,Watchdog Timer Register" line.long 0x34 "HW_RTC_WATCHDOG_SET,Watchdog Timer Set Register" line.long 0x38 "HW_RTC_WATCHDOG_CLR,Watchdog Timer Clear Register" line.long 0x3c "HW_RTC_WATCHDOG_TOG,Watchdog Timer Toggle Register" line.long 0x40 "HW_RTC_PERSISTENT0,Persistent State Register 0" bitfld.long 0x40 28.--31. " ADJ_POSLIMITBUCK ,Minimum startup voltage" "2.83V,2.78V,2.73V,2.68V,2.62V,2.57V,2.52V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V" bitfld.long 0x40 19. " RELEASE_GND ,Remove the pulldown resistors on the headphone outputs" "Not removed,Removed" textline " " bitfld.long 0x40 18. " ENABLE_LRADC_PWRUP ,Enable a low voltage on LRADC0 to powerup the chip" "Disabled,Enabled" bitfld.long 0x40 17. " AUTO_RESTART ,Enable the chip to automatically power up approximately 180 ms after powering down" "Disabled,Enabled" textline " " bitfld.long 0x40 16. " DISABLE_PSWITCH ,Disable the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage" "No,Yes" bitfld.long 0x40 14.--15. " LOWERBIAS ,Reduce bias current of 24mhz crystal" "Nominal,-25%,-25%,-50%" textline " " bitfld.long 0x40 13. " DISABLE_XTALOK ,Disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz" "No,Yes" bitfld.long 0x40 8.--12. " MSEC_RES ,Encodes the value of the millisecond count resolution in a one-hot format" "Reserved,1msec,2msec,Reserved,4msec,Reserved,Reserved,Reserved,8msec,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16msec,?..." textline " " bitfld.long 0x40 7. " ALARM_WAKE ,Set when the chip is powered up by an alarm event from rtc_ana" "Disabled,Enabled" bitfld.long 0x40 6. " XTAL32_FREQ ,Frequency of the 32kHz crystal" "32.768kHz,32.000kHz" textline " " bitfld.long 0x40 5. " XTAL32KHZ_PWRUP ,Power up the 32kHz crystal oscillator" "Powered down,Powered up" bitfld.long 0x40 4. " XTAL24MHZ_PWRUP ,Keep the 24.0-MHz crystal oscillator powered up while the chip is powered down" "Powered down,Powered up" textline " " bitfld.long 0x40 3. " LCK_SECS ,Lock down the seconds count" "Not locked,Locked" bitfld.long 0x40 2. " ALARM_EN ,Enable the detection of an alarm event" "Disabled,Enabled" textline " " bitfld.long 0x40 1. " ALARM_WAKE_EN ,This bit is set to one to upon the arrival of an alarm event that powers up the chip" "Disabled,Enabled" bitfld.long 0x40 0. " CLOCKSOURCE ,Select crystal oscillator as the source for the 32-kHz clock domain" "24Mhz,32kHz" line.long 0x44 "HW_RTC_PERSISTENT0_SET,Persistent State Set Register 0" bitfld.long 0x44 28.--31. " ADJ_POSLIMITBUCK ,Minimum startup voltage" "2.83V,2.78V,2.73V,2.68V,2.62V,2.57V,2.52V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V" bitfld.long 0x44 19. " RELEASE_GND ,Remove the pulldown resistors on the headphone outputs" "No effect,Set" textline " " bitfld.long 0x44 18. " ENABLE_LRADC_PWRUP ,Enable a low voltage on LRADC0 to powerup the chip" "No effect,Set" bitfld.long 0x44 17. " AUTO_RESTART ,Enable the chip to automatically power up approximately 180 ms after powering down" "No effect,Set" textline " " bitfld.long 0x44 16. " DISABLE_PSWITCH ,Disable the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage" "No effect,Set" bitfld.long 0x44 14.--15. " LOWERBIAS ,Reduce bias current of 24mhz crystal" "Nominal,-25%,-25%,-50%" textline " " bitfld.long 0x44 13. " DISABLE_XTALOK ,Disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz" "No effect,Set" bitfld.long 0x44 8.--12. " MSEC_RES ,Encodes the value of the millisecond count resolution in a one-hot format" "Reserved,1msec,2msec,Reserved,4msec,Reserved,Reserved,Reserved,8msec,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16msec,?..." textline " " bitfld.long 0x44 7. " ALARM_WAKE ,Set when the chip is powered up by an alarm event from rtc_ana" "No effect,Set" bitfld.long 0x44 6. " XTAL32_FREQ ,Frequency of the 32kHz crystal" "No effect,Set" textline " " bitfld.long 0x44 5. " XTAL32KHZ_PWRUP ,Power up the 32kHz crystal oscillator" "No effect,Set" bitfld.long 0x44 4. " XTAL24MHZ_PWRUP ,Keep the 24.0-MHz crystal oscillator powered up while the chip is powered down" "No effect,Set" textline " " bitfld.long 0x44 3. " LCK_SECS ,Lock down the seconds count" "No effect,Set" bitfld.long 0x44 2. " ALARM_EN ,Enable the detection of an alarm event" "No effect,Set" textline " " bitfld.long 0x44 1. " ALARM_WAKE_EN ,This bit is set to one to upon the arrival of an alarm event that powers up the chip" "No effect,Set" bitfld.long 0x44 0. " CLOCKSOURCE ,Select crystal oscillator as the source for the 32-kHz clock domain" "No effect,Set" line.long 0x48 "HW_RTC_PERSISTENT0_CLR,Persistent State Clear Register 0" bitfld.long 0x48 28.--31. " ADJ_POSLIMITBUCK ,Minimum startup voltage" "2.83V,2.78V,2.73V,2.68V,2.62V,2.57V,2.52V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V" bitfld.long 0x48 19. " RELEASE_GND ,Remove the pulldown resistors on the headphone outputs" "No effect,Clear" textline " " bitfld.long 0x48 18. " ENABLE_LRADC_PWRUP ,Enable a low voltage on LRADC0 to powerup the chip" "No effect,Clear" bitfld.long 0x48 17. " AUTO_RESTART ,Enable the chip to automatically power up approximately 180 ms after powering down" "No effect,Clear" textline " " bitfld.long 0x48 16. " DISABLE_PSWITCH ,Disable the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage" "No effect,Clear" bitfld.long 0x48 14.--15. " LOWERBIAS ,Reduce bias current of 24mhz crystal" "Nominal,-25%,-25%,-50%" textline " " bitfld.long 0x48 13. " DISABLE_XTALOK ,Disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz" "No effect,Clear" bitfld.long 0x48 8.--12. " MSEC_RES ,Encodes the value of the millisecond count resolution in a one-hot format" "Reserved,1msec,2msec,Reserved,4msec,Reserved,Reserved,Reserved,8msec,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16msec,?..." textline " " bitfld.long 0x48 7. " ALARM_WAKE ,Set when the chip is powered up by an alarm event from rtc_ana" "No effect,Clear" bitfld.long 0x48 6. " XTAL32_FREQ ,Frequency of the 32kHz crystal" "No effect,Clear" textline " " bitfld.long 0x48 5. " XTAL32KHZ_PWRUP ,Power up the 32kHz crystal oscillator" "No effect,Clear" bitfld.long 0x48 4. " XTAL24MHZ_PWRUP ,Keep the 24.0-MHz crystal oscillator powered up while the chip is powered down" "No effect,Clear" textline " " bitfld.long 0x48 3. " LCK_SECS ,Lock down the seconds count" "No effect,Clear" bitfld.long 0x48 2. " ALARM_EN ,Enable the detection of an alarm event" "No effect,Clear" textline " " bitfld.long 0x48 1. " ALARM_WAKE_EN ,This bit is set to one to upon the arrival of an alarm event that powers up the chip" "No effect,Clear" bitfld.long 0x48 0. " CLOCKSOURCE ,Select crystal oscillator as the source for the 32-kHz clock domain" "No effect,Clear" line.long 0x4c "HW_RTC_PERSISTENT0_TOG,Persistent State Toggle Register 0" bitfld.long 0x4c 28.--31. " ADJ_POSLIMITBUCK ,Minimum startup voltage" "2.83V,2.78V,2.73V,2.68V,2.62V,2.57V,2.52V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V" bitfld.long 0x4c 19. " RELEASE_GND ,Remove the pulldown resistors on the headphone outputs" "Not toggle,Toggle" textline " " bitfld.long 0x4c 18. " ENABLE_LRADC_PWRUP ,Enable a low voltage on LRADC0 to powerup the chip" "Not toggle,Toggle" bitfld.long 0x4c 17. " AUTO_RESTART ,Enable the chip to automatically power up approximately 180 ms after powering down" "Not toggle,Toggle" textline " " bitfld.long 0x4c 16. " DISABLE_PSWITCH ,Disable the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage" "Not toggle,Toggle" bitfld.long 0x4c 14.--15. " LOWERBIAS ,Reduce bias current of 24mhz crystal" "Nominal,-25%,-25%,-50%" textline " " bitfld.long 0x4c 13. " DISABLE_XTALOK ,Disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz" "Not toggle,Toggle" bitfld.long 0x4c 8.--12. " MSEC_RES ,Encodes the value of the millisecond count resolution in a one-hot format" "Reserved,1msec,2msec,Reserved,4msec,Reserved,Reserved,Reserved,8msec,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16msec,?..." textline " " bitfld.long 0x4c 7. " ALARM_WAKE ,Set when the chip is powered up by an alarm event from rtc_ana" "Not toggle,Toggle" bitfld.long 0x4c 6. " XTAL32_FREQ ,Frequency of the 32kHz crystal" "Not toggle,Toggle" textline " " bitfld.long 0x4c 5. " XTAL32KHZ_PWRUP ,Power up the 32kHz crystal oscillator" "Not toggle,Toggle" bitfld.long 0x4c 4. " XTAL24MHZ_PWRUP ,Keep the 24.0-MHz crystal oscillator powered up while the chip is powered down" "Not toggle,Toggle" textline " " bitfld.long 0x4c 3. " LCK_SECS ,Lock down the seconds count" "Not toggle,Toggle" bitfld.long 0x4c 2. " ALARM_EN ,Enable the detection of an alarm event" "Not toggle,Toggle" textline " " bitfld.long 0x4c 1. " ALARM_WAKE_EN ,This bit is set to one to upon the arrival of an alarm event that powers up the chip" "Not toggle,Toggle" bitfld.long 0x4c 0. " CLOCKSOURCE ,Select crystal oscillator as the source for the 32-kHz clock domain" "Not toggle,Toggle" group.long 0x70++0x4f line.long 0x0 "HW_RTC_PERSISTENT1,Persistent State Register 1" line.long (0x0+0x04) "HW_RTC_PERSISTENT1_SET,Persistent State Set Register 1" line.long (0x0+0x0c) "HW_RTC_PERSISTENT1_CLR,Persistent State Clear Register 1" line.long (0x0+0x0c) "HW_RTC_PERSISTENT1_TOG,Persistent State Toggle Register 1" line.long 0x10 "HW_RTC_PERSISTENT2,Persistent State Register 2" line.long (0x10+0x04) "HW_RTC_PERSISTENT2_SET,Persistent State Set Register 2" line.long (0x10+0x0c) "HW_RTC_PERSISTENT2_CLR,Persistent State Clear Register 2" line.long (0x10+0x0c) "HW_RTC_PERSISTENT2_TOG,Persistent State Toggle Register 2" line.long 0x20 "HW_RTC_PERSISTENT3,Persistent State Register 3" line.long (0x20+0x04) "HW_RTC_PERSISTENT3_SET,Persistent State Set Register 3" line.long (0x20+0x0c) "HW_RTC_PERSISTENT3_CLR,Persistent State Clear Register 3" line.long (0x20+0x0c) "HW_RTC_PERSISTENT3_TOG,Persistent State Toggle Register 3" line.long 0x30 "HW_RTC_PERSISTENT4,Persistent State Register 4" line.long (0x30+0x04) "HW_RTC_PERSISTENT4_SET,Persistent State Set Register 4" line.long (0x30+0x0c) "HW_RTC_PERSISTENT4_CLR,Persistent State Clear Register 4" line.long (0x30+0x0c) "HW_RTC_PERSISTENT4_TOG,Persistent State Toggle Register 4" line.long 0x40 "HW_RTC_PERSISTENT5,Persistent State Register 5" line.long (0x40+0x04) "HW_RTC_PERSISTENT5_SET,Persistent State Set Register 5" line.long (0x40+0x0c) "HW_RTC_PERSISTENT5_CLR,Persistent State Clear Register 5" line.long (0x40+0x0c) "HW_RTC_PERSISTENT5_TOG,Persistent State Toggle Register 5" group.long 0xc0++0x0f line.long 0x00 "HW_RTC_DEBUG,Real-Time Clock Debug Register" bitfld.long 0x00 1. " WATCHDOG_RESET_MASK ,Mask the reset generation by the watchdog timer" "Not masked,Masked" bitfld.long 0x00 0. " WATCHDOG_RESET ,Watchdog reset" "No reset,Reset" line.long 0x04 "HW_RTC_DEBUG_SET,Real-Time Clock Debug Set Register" bitfld.long 0x04 1. " WATCHDOG_RESET_MASK ,Mask the reset generation by the watchdog timer" "No effect,Set" bitfld.long 0x04 0. " WATCHDOG_RESET ,Watchdog reset" "No effect,Set" line.long 0x08 "HW_RTC_DEBUG_CLR,Real-Time Clock Debug Clear Register" bitfld.long 0x08 1. " WATCHDOG_RESET_MASK ,Mask the reset generation by the watchdog timer" "No effect,Clear" bitfld.long 0x08 0. " WATCHDOG_RESET ,Watchdog reset" "No effect,Clear" line.long 0x0c "HW_RTC_DEBUG_TOG,Real-Time Clock Debug Toggle Register" bitfld.long 0x0c 1. " WATCHDOG_RESET_MASK ,Mask the reset generation by the watchdog timer" "Not toggle,Toggle" bitfld.long 0x0c 0. " WATCHDOG_RESET ,Watchdog reset" "Not toggle,Toggle" rgroup.long 0xd0++0x03 line.long 0x00 "HW_RTC_VERSION,Real-Time Clock Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end tree "PWM (Pulse-Width Modulator)" base asd:0x80064000 width 20. group.long 0x00++0x0f line.long 0x00 "HW_PWM_CTRL,PWM Control and Status Register" bitfld.long 0x00 31. " SFTRST ,Force a block-wide reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clock to the block" "Normal,Gated off" textline " " bitfld.long 0x00 29. " PWM4_PRESENT ,PWM4 is not present in this product" "Not present,Present" bitfld.long 0x00 28. " PWM3_PRESENT ,PWM3 is not present in this product" "Not present,Present" textline " " bitfld.long 0x00 27. " PWM2_PRESENT ,PWM2 is not present in this product" "Not present,Present" bitfld.long 0x00 26. " PWM1_PRESENT ,PWM1 is not present in this product" "Not present,Present" textline " " bitfld.long 0x00 25. " PWM0_PRESENT ,PWM0 is not present in this product" "Not present,Present" bitfld.long 0x00 6. " OUTPUT_CUTOFF_EN ,Enable the block to automatically Hi-Z state the outputs whenever the clkgate is asserted" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " PWM2_ANA_CTRL_EN ,Enable PWM Channel 2 output to be enabled by analog circuitry outside this block" "Disabled,Enabled" bitfld.long 0x00 4. " PWM4_EN ,Enable PWM channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PWM3_EN ,Enable PWM channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " PWM2_EN ,Enable PWM channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PWM1_EN ,Enable PWM channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " PWM0_EN ,Enable PWM channel 0" "Disabled,Enabled" line.long 0x04 "HW_PWM_CTRL_SET,PWM Control and Status Set Register" bitfld.long 0x04 31. " SFTRST ,Force a block-wide reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate off the clock to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " PWM4_PRESENT ,PWM4 is not present in this product" "No effect,Set" bitfld.long 0x04 28. " PWM3_PRESENT ,PWM3 is not present in this product" "No effect,Set" textline " " bitfld.long 0x04 27. " PWM2_PRESENT ,PWM2 is not present in this product" "No effect,Set" bitfld.long 0x04 26. " PWM1_PRESENT ,PWM1 is not present in this product" "No effect,Set" textline " " bitfld.long 0x04 25. " PWM0_PRESENT ,PWM0 is not present in this product" "No effect,Set" bitfld.long 0x04 6. " OUTPUT_CUTOFF_EN ,Enable the block to automatically Hi-Z state the outputs whenever the clkgate is asserted" "No effect,Set" textline " " bitfld.long 0x04 5. " PWM2_ANA_CTRL_EN ,Enable PWM Channel 2 output to be enabled by analog circuitry outside this block" "No effect,Set" bitfld.long 0x04 4. " PWM4_EN ,Enable PWM channel 4" "No effect,Set" textline " " bitfld.long 0x04 3. " PWM3_EN ,Enable PWM channel 3" "No effect,Set" bitfld.long 0x04 2. " PWM2_EN ,Enable PWM channel 2" "No effect,Set" textline " " bitfld.long 0x04 1. " PWM1_EN ,Enable PWM channel 1" "No effect,Set" bitfld.long 0x04 0. " PWM0_EN ,Enable PWM channel 0" "No effect,Set" line.long 0x08 "HW_PWM_CTRL_CLR,PWM Control and Status Clear Register" bitfld.long 0x08 31. " SFTRST ,Force a block-wide reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate off the clock to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " PWM4_PRESENT ,PWM4 is not present in this product" "No effect,Clear" bitfld.long 0x08 28. " PWM3_PRESENT ,PWM3 is not present in this product" "No effect,Clear" textline " " bitfld.long 0x08 27. " PWM2_PRESENT ,PWM2 is not present in this product" "No effect,Clear" bitfld.long 0x08 26. " PWM1_PRESENT ,PWM1 is not present in this product" "No effect,Clear" textline " " bitfld.long 0x08 25. " PWM0_PRESENT ,PWM0 is not present in this product" "No effect,Clear" bitfld.long 0x08 6. " OUTPUT_CUTOFF_EN ,Enable the block to automatically Hi-Z state the outputs whenever the clkgate is asserted" "No effect,Clear" textline " " bitfld.long 0x08 5. " PWM2_ANA_CTRL_EN ,Enable PWM Channel 2 output to be enabled by analog circuitry outside this block" "No effect,Clear" bitfld.long 0x08 4. " PWM4_EN ,Enable PWM channel 4" "No effect,Clear" textline " " bitfld.long 0x08 3. " PWM3_EN ,Enable PWM channel 3" "No effect,Clear" bitfld.long 0x08 2. " PWM2_EN ,Enable PWM channel 2" "No effect,Clear" textline " " bitfld.long 0x08 1. " PWM1_EN ,Enable PWM channel 1" "No effect,Clear" bitfld.long 0x08 0. " PWM0_EN ,Enable PWM channel 0" "No effect,Set" line.long 0x0c "HW_PWM_CTRL_TOG,PWM Control and Status Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Force a block-wide reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate off the clock to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " PWM4_PRESENT ,PWM4 is not present in this product" "Not toggle,Toggle" bitfld.long 0x0c 28. " PWM3_PRESENT ,PWM3 is not present in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " PWM2_PRESENT ,PWM2 is not present in this product" "Not toggle,Toggle" bitfld.long 0x0c 26. " PWM1_PRESENT ,PWM1 is not present in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " PWM0_PRESENT ,PWM0 is not present in this product" "Not toggle,Toggle" bitfld.long 0x0c 6. " OUTPUT_CUTOFF_EN ,Enable the block to automatically Hi-Z state the outputs whenever the clkgate is asserted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " PWM2_ANA_CTRL_EN ,Enable PWM Channel 2 output to be enabled by analog circuitry outside this block" "Not toggle,Toggle" bitfld.long 0x0c 4. " PWM4_EN ,Enable PWM channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " PWM3_EN ,Enable PWM channel 3" "Not toggle,Toggle" bitfld.long 0x0c 2. " PWM2_EN ,Enable PWM channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " PWM1_EN ,Enable PWM channel 1" "Not toggle,Toggle" bitfld.long 0x0c 0. " PWM0_EN ,Enable PWM channel 0" "Not toggle,Toggle" group.long 0x10++0x1f "PWM 0 Registers" line.long 0x00 "HW_PWM_ACTIVE0,PWM Channel 0 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE0_SET,PWM Channel 0 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE0_CLR,PWM Channel 0 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE0_TOG,PWM Channel 0 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD0,PWM Channel 0 Period Register" bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD0_SET,PWM Channel 0 Period Set Register" bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD0_CLR,PWM Channel 0 Period Clear Register" bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD0_TOG,PWM Channel 0 Period Toggle Register" bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0x30++0x1f "PWM 1 Registers" line.long 0x00 "HW_PWM_ACTIVE1,PWM Channel 1 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE1_SET,PWM Channel 1 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE1_CLR,PWM Channel 1 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE1_TOG,PWM Channel 1 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD1,PWM Channel 1 Period Register" bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD1_SET,PWM Channel 1 Period Set Register" bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD1_CLR,PWM Channel 1 Period Clear Register" bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD1_TOG,PWM Channel 1 Period Toggle Register" bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0x50++0x1f "PWM 2 Registers" line.long 0x00 "HW_PWM_ACTIVE2,PWM Channel 2 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE2_SET,PWM Channel 2 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE2_CLR,PWM Channel 2 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE2_TOG,PWM Channel 2 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD2,PWM Channel 2 Period Register" bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD2_SET,PWM Channel 2 Period Set Register" bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD2_CLR,PWM Channel 2 Period Clear Register" bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD2_TOG,PWM Channel 2 Period Toggle Register" bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0x70++0x1f "PWM 3 Registers" line.long 0x00 "HW_PWM_ACTIVE3,PWM Channel 3 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE3_SET,PWM Channel 3 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE3_CLR,PWM Channel 3 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE3_TOG,PWM Channel 3 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD3,PWM Channel 3 Period Register" bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD3_SET,PWM Channel 3 Period Set Register" bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD3_CLR,PWM Channel 3 Period Clear Register" bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD3_TOG,PWM Channel 3 Period Toggle Register" bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0x90++0x1f "PWM 4 Registers" line.long 0x00 "HW_PWM_ACTIVE4,PWM Channel 4 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE4_SET,PWM Channel 4 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE4_CLR,PWM Channel 4 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE4_TOG,PWM Channel 4 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD4,PWM Channel 4 Period Register" bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD4_SET,PWM Channel 4 Period Set Register" bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD4_CLR,PWM Channel 4 Period Clear Register" bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD4_TOG,PWM Channel 4 Period Toggle Register" bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Low,High,?..." hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" rgroup.long 0xb0++0x03 "Version Register" line.long 0x00 "HW_PWM_VERSION,PWM Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end tree "I2C (Inter-Intergrated Circuit)" base asd:0x80058000 width 20. group.long 0x00++0x4f line.long 0x00 "HW_I2C_CTRL0,I2C Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Run,Not clock" textline " " bitfld.long 0x00 29. " RUN ,Enable the I2C Controller operation" "Halted,Run" bitfld.long 0x00 26. " ACKNOWLEDGE ,Acknowledge" "Snak,Ack" textline " " bitfld.long 0x00 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "Send ACK,Send NAK" bitfld.long 0x00 24. " PIO_MODE ,Enable PIO mode of operation for the I2C master" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "Release,Hold low" bitfld.long 0x00 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Release,Hold low" textline " " bitfld.long 0x00 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No stop,Send stop" bitfld.long 0x00 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No stop,Send stop" textline " " bitfld.long 0x00 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "Disabled,Enabled" bitfld.long 0x00 17. " MASTER_MODE ,Enable master mode" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " DIRECTION ,Select an I2C transmit operation" "Receive,Transmit" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x04 "HW_I2C_CTRL0_SET,I2C Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Enable the I2C Controller operation" "No effect,Set" bitfld.long 0x04 26. " ACKNOWLEDGE ,Acknowledge" "No effect,Set" textline " " bitfld.long 0x04 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "No effect,Set" bitfld.long 0x04 24. " PIO_MODE ,Enable PIO mode of operation for the I2C master" "No effect,Set" textline " " bitfld.long 0x04 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "No effect,Set" bitfld.long 0x04 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Set" textline " " bitfld.long 0x04 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Set" bitfld.long 0x04 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No effect,Set" textline " " bitfld.long 0x04 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "No effect,Set" bitfld.long 0x04 17. " MASTER_MODE ,Enable master mode" "No effect,Set" textline " " bitfld.long 0x04 16. " DIRECTION ,Select an I2C transmit operation" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x08 "HW_I2C_CTRL0_CLR,I2C Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Enable the I2C Controller operation" "No effect,Clear" bitfld.long 0x08 26. " ACKNOWLEDGE ,Acknowledge" "No effect,Clear" textline " " bitfld.long 0x08 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "No effect,Clear" bitfld.long 0x08 24. " PIO_MODE ,Enable PIO mode of operation for the I2C master" "No effect,Clear" textline " " bitfld.long 0x08 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "No effect,Clear" bitfld.long 0x08 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Clear" textline " " bitfld.long 0x08 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Clear" bitfld.long 0x08 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No effect,Clear" textline " " bitfld.long 0x08 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "No effect,Clear" bitfld.long 0x08 17. " MASTER_MODE ,Enable master mode" "No effect,Clear" textline " " bitfld.long 0x08 16. " DIRECTION ,Select an I2C transmit operation" "No effect,Clear" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x0c "HW_I2C_CTRL0_TOG,I2C Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Enable the I2C Controller operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " ACKNOWLEDGE ,Acknowledge" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "Not toggle,Toggle" bitfld.long 0x0c 24. " PIO_MODE ,Enable PIO mode of operation for the I2C master" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "Not toggle,Toggle" bitfld.long 0x0c 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "Not toggle,Toggle" bitfld.long 0x0c 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "Not toggle,Toggle" bitfld.long 0x0c 17. " MASTER_MODE ,Enable master mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " DIRECTION ,Select an I2C transmit operation" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x10 "HW_I2C_TIMING0,I2C Timing Register 0" hexmask.long.word 0x10 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x10 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x14 "HW_I2C_TIMING0_SET,I2C Timing Set Register 0" hexmask.long.word 0x14 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x14 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x18 "HW_I2C_TIMING0_CLR,I2C Timing Clear Register 0" hexmask.long.word 0x18 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x18 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x1c "HW_I2C_TIMING0_TOG,I2C Timing Toggle Register 0" hexmask.long.word 0x1c 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x1c 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x20 "HW_I2C_TIMING1,I2C Timing Register 1" hexmask.long.word 0x20 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x20 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x24 "HW_I2C_TIMING1_SET,I2C Timing Set Register 1" hexmask.long.word 0x24 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x24 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x28 "HW_I2C_TIMING1_CLR,I2C Timing Clear Register 1" hexmask.long.word 0x28 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x28 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x2c "HW_I2C_TIMING1_TOG,I2C Timing Toggle Register 1" hexmask.long.word 0x2c 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x2c 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x30 "HW_I2C_TIMING2,I2C Timing Register 2" hexmask.long.word 0x30 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x30 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x34 "HW_I2C_TIMING2_SET,I2C Timing Set Register 2" hexmask.long.word 0x34 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x34 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x38 "HW_I2C_TIMING2_CLR,I2C Timing Clear Register 2" hexmask.long.word 0x38 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x38 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x3c "HW_I2C_TIMING2_TOG,I2C Timing Toggle Register 2" hexmask.long.word 0x3c 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x3c 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x40 "HW_I2C_CTRL1,I2C Control Register 1" bitfld.long 0x40 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Clear" bitfld.long 0x40 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "Ack after hold low,Ack before hold low" textline " " bitfld.long 0x40 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "Not idle,Idle" bitfld.long 0x40 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "Not idle,Idle" textline " " bitfld.long 0x40 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "Not search,Search" bitfld.long 0x40 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "Disabled,Enabled" bitfld.long 0x40 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 8. " SLAVE_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 7. " BUS_FREE_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 3. " EARLY_TERM_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 2. " MASTER_LOSS_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 1. " SLAVE_STOP_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 0. " SLAVE_IRQ ,Interrupt status" "Not requested,Requested" line.long 0x44 "HW_I2C_CTRL1_SET,I2C Control Set Register 1" bitfld.long 0x44 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Set" bitfld.long 0x44 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "No effect,Set" textline " " bitfld.long 0x44 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "No effect,Set" bitfld.long 0x44 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "No effect,Set" textline " " bitfld.long 0x44 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "No effect,Set" bitfld.long 0x44 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "No effect,Set" textline " " bitfld.long 0x44 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "No effect,Set" bitfld.long 0x44 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 8. " SLAVE_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 7. " BUS_FREE_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 3. " EARLY_TERM_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 2. " MASTER_LOSS_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 1. " SLAVE_STOP_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 0. " SLAVE_IRQ ,Interrupt status" "No effect,Set" line.long 0x48 "HW_I2C_CTRL1_CLR,I2C Control Clear Register 1" bitfld.long 0x48 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Clear" bitfld.long 0x48 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "No effect,Clear" textline " " bitfld.long 0x48 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "No effect,Clear" bitfld.long 0x48 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "No effect,Clear" textline " " bitfld.long 0x48 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "No effect,Clear" bitfld.long 0x48 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "No effect,Clear" textline " " bitfld.long 0x48 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "No effect,Clear" bitfld.long 0x48 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 8. " SLAVE_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 7. " BUS_FREE_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 3. " EARLY_TERM_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 2. " MASTER_LOSS_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 1. " SLAVE_STOP_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 0. " SLAVE_IRQ ,Interrupt status" "No effect,Clear" line.long 0x4c "HW_I2C_CTRL1_TOG,I2C Control Toggle Register 1" bitfld.long 0x4c 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "Not toggle,Toggle" bitfld.long 0x4c 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "Not toggle,Toggle" textline " " bitfld.long 0x4c 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "Not toggle,Toggle" bitfld.long 0x4c 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "Not toggle,Toggle" textline " " bitfld.long 0x4c 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "Not toggle,Toggle" bitfld.long 0x4c 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "Not toggle,Toggle" bitfld.long 0x4c 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 8. " SLAVE_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 7. " BUS_FREE_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 3. " EARLY_TERM_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 2. " MASTER_LOSS_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 1. " SLAVE_STOP_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 0. " SLAVE_IRQ ,Interrupt status" "Not toggle,Toggle" rgroup.long 0x50++0x03 line.long 0x00 "HW_I2C_STAT,I2C Status Register" bitfld.long 0x00 31. " MASTER_PRESENT ,I2C master function is present" "Not present,Present" bitfld.long 0x00 29. " ANY_ENABLED_IRQ ,I2C controller has at least one enable interrupt requesting service" "No requests,At least one request" textline " " bitfld.long 0x00 28. " GOT_A_NAK ,View of the got-a-nak signal" "Not detected,Detected" hexmask.long.byte 0x00 16.--23. 1. " RCVD_SLAVE_ADDR ,State of the slave I2C address byte received" textline " " bitfld.long 0x00 15. " SLAVE_ADDR_EQ_ZERO ,Address match was found for the exact adderss 0x00" "Not found,Found" bitfld.long 0x00 14. " SLAVE_FOUND ,Address match was found and the I2C clock is frozen by the slave search" "Idle,Found" textline " " bitfld.long 0x00 13. " SLAVE_SEARCHING ,I2C slave function is searching for a transaction that matches the current slave address" "Idle,Searching" bitfld.long 0x00 12. " DATA_ENGINE_DMA_WAIT ,Data engine is waitng for data from a DMA device" "Not waiting,Waiting" textline " " bitfld.long 0x00 11. " BUS_BUSY ,I2C bus is busy with a transaction" "Idle,Busy" bitfld.long 0x00 10. " CLK_GEN_BUSY ,Clock generator is busy with a transaction" "Idle,Busy" textline " " bitfld.long 0x00 9. " DATA_ENGINE_BUSY ,Data transfer engine is busy with a data transmit or recieve opertion" "Idle,Busy" bitfld.long 0x00 8. " SLAVE_BUSY ,Slave address search engine is busy with a transaction" "Idle,Busy" textline " " bitfld.long 0x00 7. " BUS_FREE_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 6. " DATA_ENGINE_CMPLT_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NO_SLAVE_ACK_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 4. " OVERSIZE_XFER_TERM_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 3. " EARLY_TERM_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 2. " MASTER_LOSS_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 1. " SLAVE_STOP_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 0. " SLAVE_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" group.long 0x60++0x03 line.long 0x00 "HW_I2C_DATA,I2C Controller DMA Read and Write Data Register" group.long 0x70++0x0f line.long 0x00 "HW_I2C_DEBUG0,I2C Device Debug Register 0" bitfld.long 0x00 31. " DMAREQ ,View of the toggle state of the DMA request signal" "0,1" bitfld.long 0x00 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "0,1" textline " " bitfld.long 0x00 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "0,1" bitfld.long 0x00 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "0,1" textline " " hexmask.long.word 0x00 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" bitfld.long 0x00 15. " START_TOGGLE ,View of the start detector" "0,1" textline " " bitfld.long 0x00 14. " STOP_TOGGLE ,View of the stop detector" "0,1" bitfld.long 0x00 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "0,1" textline " " bitfld.long 0x00 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "0,1" bitfld.long 0x00 11. " TESTMODE ,To be completed by designer" "0,1" textline " " bitfld.long 0x00 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "0,1" hexmask.long.word 0x00 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x04 "HW_I2C_DEBUG0_SET,I2C Device Debug Set Register 0" bitfld.long 0x04 31. " DMAREQ ,View of the toggle state of the DMA request signal" "No effect,Set" bitfld.long 0x04 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "No effect,Set" textline " " bitfld.long 0x04 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "No effect,Set" bitfld.long 0x04 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "No effect,Set" textline " " hexmask.long.word 0x04 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" bitfld.long 0x04 15. " START_TOGGLE ,View of the start detector" "No effect,Set" textline " " bitfld.long 0x04 14. " STOP_TOGGLE ,View of the stop detector" "No effect,Set" bitfld.long 0x04 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "No effect,Set" textline " " bitfld.long 0x04 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "No effect,Set" bitfld.long 0x04 11. " TESTMODE ,To be completed by designer" "No effect,Set" textline " " bitfld.long 0x04 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "No effect,Set" hexmask.long.word 0x04 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x08 "HW_I2C_DEBUG0_CLR,I2C Device Debug Clear Register 0" bitfld.long 0x08 31. " DMAREQ ,View of the toggle state of the DMA request signal" "No effect,Clear" bitfld.long 0x08 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "No effect,Clear" textline " " bitfld.long 0x08 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "No effect,Clear" bitfld.long 0x08 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "No effect,Clear" textline " " hexmask.long.word 0x08 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" bitfld.long 0x08 15. " START_TOGGLE ,View of the start detector" "No effect,Clear" textline " " bitfld.long 0x08 14. " STOP_TOGGLE ,View of the stop detector" "No effect,Clear" bitfld.long 0x08 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "No effect,Clear" textline " " bitfld.long 0x08 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "No effect,Clear" bitfld.long 0x08 11. " TESTMODE ,To be completed by designer" "No effect,Clear" textline " " bitfld.long 0x08 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "No effect,Clear" hexmask.long.word 0x08 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x0c "HW_I2C_DEBUG0_TOG,I2C Device Debug Toggle Register 0" bitfld.long 0x0c 31. " DMAREQ ,View of the toggle state of the DMA request signal" "Not toggle,Toggle" bitfld.long 0x0c 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "Not toggle,Toggle" bitfld.long 0x0c 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "Not toggle,Toggle" textline " " hexmask.long.word 0x0c 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" bitfld.long 0x0c 15. " START_TOGGLE ,View of the start detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " STOP_TOGGLE ,View of the stop detector" "Not toggle,Toggle" bitfld.long 0x0c 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "Not toggle,Toggle" bitfld.long 0x0c 11. " TESTMODE ,To be completed by designer" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" group.long 0x80++0x0f line.long 0x00 "HW_I2C_DEBUG1,I2C Device Debug Register 1" bitfld.long 0x00 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "0,1" bitfld.long 0x00 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "0,1" textline " " bitfld.long 0x00 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x00 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x00 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "Normal,Test mode" textline " " bitfld.long 0x00 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "Not forced,Forced" bitfld.long 0x00 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "Not forced,Forced" textline " " bitfld.long 0x00 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "Not forced,Forced" bitfld.long 0x00 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "Not forced,Forced" textline " " bitfld.long 0x00 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "Not forced,Forced" line.long 0x04 "HW_I2C_DEBUG1_SET,I2C Device Debug Set Register 1" bitfld.long 0x04 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Set" bitfld.long 0x04 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Set" textline " " bitfld.long 0x04 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x04 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x04 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "No effect,Set" textline " " bitfld.long 0x04 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "No effect,Set" bitfld.long 0x04 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "No effect,Set" textline " " bitfld.long 0x04 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "No effect,Set" bitfld.long 0x04 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "No effect,Set" textline " " bitfld.long 0x04 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "No effect,Set" line.long 0x08 "HW_I2C_DEBUG1_CLR,I2C Device Debug Clear Register 1" bitfld.long 0x08 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Clear" bitfld.long 0x08 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Clear" textline " " bitfld.long 0x08 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x08 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x08 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "No effect,Clear" textline " " bitfld.long 0x08 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "No effect,Clear" bitfld.long 0x08 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "No effect,Clear" textline " " bitfld.long 0x08 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "No effect,Clear" bitfld.long 0x08 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "No effect,Clear" textline " " bitfld.long 0x08 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "No effect,Clear" line.long 0x0c "HW_I2C_DEBUG1_TOG,I2C Device Debug Toggle Register 1" bitfld.long 0x0c 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "Not toggle,Toggle" bitfld.long 0x0c 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0c 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x0c 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x0c 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "Not toggle,Toggle" bitfld.long 0x0c 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "Not toggle,Toggle" bitfld.long 0x0c 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "Not toggle,Toggle" rgroup.long 0x90++0x03 line.long 0x00 "HW_I2C_VERSION,I2C Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0x0b tree.end tree.open "APPUART (Application Universal Asynchronous Receiver and Transmitter)" tree "UART 1" base asd:0x8006c000 width 26. group.long 0x00++0x2f line.long 0x00 "HW_UARTAPP_CTRL0,UART Receive DMA Control Register" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates all of the block level clocks off" "Normal,Gated off" textline " " bitfld.long 0x00 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Run" bitfld.long 0x00 28. " RX_SOURCE ,Source of Receive Data" "Rx data,Status register" textline " " bitfld.long 0x00 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x04 "HW_UARTAPP_CTRL0_SET,UART Receive DMA Control Set Register" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Set" bitfld.long 0x04 28. " RX_SOURCE ,Source of Receive Data" "No effect,Set" textline " " bitfld.long 0x04 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Set" hexmask.long.word 0x04 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x08 "HW_UARTAPP_CTRL0_CLR,UART Receive DMA Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Clear" bitfld.long 0x08 28. " RX_SOURCE ,Source of Receive Data" "No effect,Clear" textline " " bitfld.long 0x08 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Clear" hexmask.long.word 0x08 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x0c "HW_UARTAPP_CTRL0_TOG,UART Receive DMA Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates all of the block level clocks off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Tell the UART to execute the RX DMA Command" "Not toggle,Toggle" bitfld.long 0x0c 28. " RX_SOURCE ,Source of Receive Data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x10 "HW_UARTAPP_CTRL1,UART Transmit DMA Control Register" bitfld.long 0x10 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Run" hexmask.long.word 0x10 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x14 "HW_UARTAPP_CTRL1_SET,UART Transmit DMA Control Set Register" bitfld.long 0x14 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Set" hexmask.long.word 0x14 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x18 "HW_UARTAPP_CTRL1_CLR,UART Transmit DMA Control Clear Register" bitfld.long 0x18 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Clear" hexmask.long.word 0x18 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x1c "HW_UARTAPP_CTRL1_TOG,UART Transmit DMA Control Toggle Register" bitfld.long 0x1c 28. " RUN ,Tell the UART to execute the TX DMA Command" "Not toggle,Toggle" hexmask.long.word 0x1c 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x20 "HW_UARTAPP_CTRL2,UART Control Register" bitfld.long 0x20 31. " INVERT_RTS ,Invert RTS signal" "Not inverted,Inverted" bitfld.long 0x20 30. " INVERT_CTS ,Invert CTS signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 29. " INVERT_TX ,Invert TX signal" "Not inverted,Inverted" bitfld.long 0x20 28. " INVERT_RX ,Invert RX signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Asserted,Deasserted" bitfld.long 0x20 26. " DMAONERR ,DMA On Error" "Not terminate,Terminate" textline " " bitfld.long 0x20 25. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x20 24. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x20 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x20 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x20 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " RTS ,Request To Send" "0,1" bitfld.long 0x20 10. " DTR ,Data Transmit Ready" "Not ready,Ready" textline " " bitfld.long 0x20 9. " RXE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x20 8. " TXE ,Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " LBE ,Loop Back Enable" "Disabled,Enabled" bitfld.long 0x20 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not use,Use" textline " " bitfld.long 0x20 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x24 "HW_UARTAPP_CTRL2_SET,UART Control Set Register" bitfld.long 0x24 31. " INVERT_RTS ,Invert RTS signal" "No effect,Set" bitfld.long 0x24 30. " INVERT_CTS ,Invert CTS signal" "No effect,Set" textline " " bitfld.long 0x24 29. " INVERT_TX ,Invert TX signal" "No effect,Set" bitfld.long 0x24 28. " INVERT_RX ,Invert RX signal" "No effect,Set" textline " " bitfld.long 0x24 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Set" bitfld.long 0x24 26. " DMAONERR ,DMA On Error" "No effect,Set" textline " " bitfld.long 0x24 25. " TXDMAE ,Transmit DMA Enable" "No effect,Set" bitfld.long 0x24 24. " RXDMAE ,Receive DMA Enable" "No effect,Set" textline " " bitfld.long 0x24 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x24 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x24 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Set" bitfld.long 0x24 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Set" textline " " bitfld.long 0x24 11. " RTS ,Request To Send" "No effect,Set" bitfld.long 0x24 10. " DTR ,Data Transmit Ready" "No effect,Set" textline " " bitfld.long 0x24 9. " RXE ,Receive Enable" "No effect,Set" bitfld.long 0x24 8. " TXE ,Transmit Enable" "No effect,Set" textline " " bitfld.long 0x24 7. " LBE ,Loop Back Enable" "No effect,Set" bitfld.long 0x24 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Set" textline " " bitfld.long 0x24 0. " UARTEN ,UART Enable" "No effect,Set" line.long 0x28 "HW_UARTAPP_CTRL2_CLR,UART Control Clear Register" bitfld.long 0x28 31. " INVERT_RTS ,Invert RTS signal" "No effect,Clear" bitfld.long 0x28 30. " INVERT_CTS ,Invert CTS signal" "No effect,Clear" textline " " bitfld.long 0x28 29. " INVERT_TX ,Invert TX signal" "No effect,Clear" bitfld.long 0x28 28. " INVERT_RX ,Invert RX signal" "No effect,Clear" textline " " bitfld.long 0x28 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Clear" bitfld.long 0x28 26. " DMAONERR ,DMA On Error" "No effect,Clear" textline " " bitfld.long 0x28 25. " TXDMAE ,Transmit DMA Enable" "No effect,Clear" bitfld.long 0x28 24. " RXDMAE ,Receive DMA Enable" "No effect,Clear" textline " " bitfld.long 0x28 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x28 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x28 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Clear" bitfld.long 0x28 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Clear" textline " " bitfld.long 0x28 11. " RTS ,Request To Send" "No effect,Clear" bitfld.long 0x28 10. " DTR ,Data Transmit Ready" "No effect,Clear" textline " " bitfld.long 0x28 9. " RXE ,Receive Enable" "No effect,Clear" bitfld.long 0x28 8. " TXE ,Transmit Enable" "No effect,Clear" textline " " bitfld.long 0x28 7. " LBE ,Loop Back Enable" "No effect,Clear" bitfld.long 0x28 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Clear" textline " " bitfld.long 0x28 0. " UARTEN ,UART Enable" "No effect,Clear" line.long 0x2c "HW_UARTAPP_CTRL2_TOG,UART Control Toggle Register" bitfld.long 0x2c 31. " INVERT_RTS ,Invert RTS signal" "Not toggle,Toggle" bitfld.long 0x2c 30. " INVERT_CTS ,Invert CTS signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " INVERT_TX ,Invert TX signal" "Not toggle,Toggle" bitfld.long 0x2c 28. " INVERT_RX ,Invert RX signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Not toggle,Toggle" bitfld.long 0x2c 26. " DMAONERR ,DMA On Error" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " TXDMAE ,Transmit DMA Enable" "Not toggle,Toggle" bitfld.long 0x2c 24. " RXDMAE ,Receive DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x2c 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x2c 15. " CTSEN ,CTS Hardware Flow Control Enable" "Not toggle,Toggle" bitfld.long 0x2c 14. " RTSEN ,RTS Hardware Flow Control Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 11. " RTS ,Request To Send" "Not toggle,Toggle" bitfld.long 0x2c 10. " DTR ,Data Transmit Ready" "Not toggle,Toggle" textline " " bitfld.long 0x2c 9. " RXE ,Receive Enable" "Not toggle,Toggle" bitfld.long 0x2c 8. " TXE ,Transmit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 7. " LBE ,Loop Back Enable" "Not toggle,Toggle" bitfld.long 0x2c 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " UARTEN ,UART Enable" "Not toggle,Toggle" if (((d.l(asd:(0x8006c000+0x30)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006c000+0x30)))&0x6)==0x2) group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=0; else group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" endif if (((d.l(asd:(0x8006c000+0x40)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006c000+0x40)))&0x6)==0x2) group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=0; else group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" endif group.long 0x50++0x0f line.long 0x00 "HW_UARTAPP_INTR,UART Interrupt Register" bitfld.long 0x00 26. " OEIEN ,Overrun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " BEIEN ,Break Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PEIEN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " FEIEN ,Framing Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RTIEN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TXIEN ,Transmit Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " RXIEN ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OEIS ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIS ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIS ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIS ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIS ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIS ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIS ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTAPP_INTR_SET,UART Interrupt Set Register" bitfld.long 0x04 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Set" bitfld.long 0x04 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 20. " RXIEN ,Receive Interrupt Enable" "No effect,Set" bitfld.long 0x04 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Set" bitfld.long 0x04 9. " BEIS ,Break Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 8. " PEIS ,Parity Error Interrupt Status" "No effect,Set" bitfld.long 0x04 7. " FEIS ,Framing Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Set" bitfld.long 0x04 5. " TXIS ,Transmit Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 4. " RXIS ,Receive Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Set" line.long 0x08 "HW_UARTAPP_INTR_CLR,UART Interrupt Clear Register" bitfld.long 0x08 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Clear" bitfld.long 0x08 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 20. " RXIEN ,Receive Interrupt Enable" "No effect,Clear" bitfld.long 0x08 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 9. " BEIS ,Break Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 8. " PEIS ,Parity Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 7. " FEIS ,Framing Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Clear" bitfld.long 0x08 5. " TXIS ,Transmit Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 4. " RXIS ,Receive Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Clear" line.long 0x0c "HW_UARTAPP_INTR_TOG,UART Interrupt Toggle Register" bitfld.long 0x0c 26. " OEIEN ,Overrun Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " BEIEN ,Break Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PEIEN ,Parity Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 23. " FEIEN ,Framing Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " RTIEN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 21. " TXIEN ,Transmit Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " RXIEN ,Receive Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " OEIS ,Overrun Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 9. " BEIS ,Break Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " PEIS ,Parity Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 7. " FEIS ,Framing Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RTIS ,Receive Timeout Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 5. " TXIS ,Transmit Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " RXIS ,Receive Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not toggle,Toggle" group.long 0x60++0x03 line.long 0x00 "HW_UARTAPP_DATA,UART Data Register" group.long 0x70++0x03 line.long 0x00 "HW_UARTAPP_STAT,UART Status Register" bitfld.long 0x00 31. " PRESENT ,Application UART function is present" "Not present,Present" bitfld.long 0x00 30. " HISPEED ,High-speed function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " BUSY ,UART Busy" "Not busy,Busy" bitfld.long 0x00 28. " CTS ,Clear To Send" "0,1" textline " " bitfld.long 0x00 27. " TXFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 26. " RXFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 25. " TXFF ,Transmit FIFO Full" "Not full,Full" bitfld.long 0x00 24. " RXFE ,Receive FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 23. " RXBYTE_INVALID3 ,The invalid state of the last read of Receive Data byte 3" "Valid,Invalid" bitfld.long 0x00 22. " RXBYTE_INVALID2 ,The invalid state of the last read of Receive Data byte 2" "Valid,Invalid" textline " " bitfld.long 0x00 21. " RXBYTE_INVALID1 ,The invalid state of the last read of Receive Data byte 1" "Valid,Invalid" bitfld.long 0x00 20. " RXBYTE_INVALID0 ,The invalid state of the last read of Receive Data byte 0" "Valid,Invalid" textline " " bitfld.long 0x00 19. " OERR ,Overrun Error" "No error,Error" bitfld.long 0x00 18. " BERR ,Break Error" "No error,Error" textline " " bitfld.long 0x00 17. " PERR ,Parity Error" "No error,Error" bitfld.long 0x00 16. " FERR ,Framing Error" "No error,Error" textline " " hexmask.long.word 0x00 0.--15. 1. " RXCOUNT ,Number of bytes received during a Receive DMA command" rgroup.long 0x80++0x03 line.long 0x00 "HW_UARTAPP_DEBUG,UART Debug Register" hexmask.long.word 0x00 16.--31. 1. " RXIBAUD_DIV ,RX Integer Baud Divisor" hexmask.long.byte 0x00 10.--15. 1. " RXFBAUD_DIV ,RX Fractional Baud Divisor" textline " " bitfld.long 0x00 5. " TXDMARUN ,DMA Command Run Status for TXDMARUN" "0,1" bitfld.long 0x00 4. " RXDMARUN ,DMA Command Run Status for RXDMARUN" "0,1" textline " " bitfld.long 0x00 3. " TXCMDEND ,DMA Request Status for UART_TXCMDEND" "0,1" bitfld.long 0x00 2. " RXCMDEND ,DMA Request Status for UART_RXCMDEND" "0,1" textline " " bitfld.long 0x00 1. " TXDMARQ ,DMA Request Status for UART_TXDMAREQ" "0,1" bitfld.long 0x00 0. " RXDMARQ ,DMA Request Status for UART_RXDMAREQ" "0,1" rgroup.long 0x90++0x03 line.long 0x00 "HW_UARTAPP_VERSION,UART Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" group.long 0xa0++0x03 line.long 0x00 "HW_UARTAPP_AUTOBAUD,UART AutoBaud Register" hexmask.long.byte 0x00 24.--31. 1. " REFCHAR1 ,Second reference character used in baud rate detection" hexmask.long.byte 0x00 16.--23. 1. " REFCHAR0 ,First reference character used in baud rate detection" textline " " bitfld.long 0x00 4. " UPDATE_TX ,TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic" "Not updated,Updated" bitfld.long 0x00 3. " TWO_REF_CHARS ,Use 2 referenfce characters" "1 reference char,2 reference char" textline " " bitfld.long 0x00 2. " START_WITH_RUNBIT ,Assertion of HW_UARTAPP_CTRL0_RUN or START_BAUD_DETECT" "START_BAUD_DETECT,HW_UARTAPP_CTRL0_RUN" bitfld.long 0x00 1. " START_BAUD_DETECT ,Set to 1 to start automatic baudrate detection" "No effect,Start" textline " " bitfld.long 0x00 0. " BAUD_DETECT_EN ,Enable automatic baudrate detection" "Disabled,Enabled" tree.end tree "UART 2" base asd:0x8006e000 width 26. group.long 0x00++0x2f line.long 0x00 "HW_UARTAPP_CTRL0,UART Receive DMA Control Register" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates all of the block level clocks off" "Normal,Gated off" textline " " bitfld.long 0x00 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Run" bitfld.long 0x00 28. " RX_SOURCE ,Source of Receive Data" "Rx data,Status register" textline " " bitfld.long 0x00 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x04 "HW_UARTAPP_CTRL0_SET,UART Receive DMA Control Set Register" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Set" bitfld.long 0x04 28. " RX_SOURCE ,Source of Receive Data" "No effect,Set" textline " " bitfld.long 0x04 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Set" hexmask.long.word 0x04 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x08 "HW_UARTAPP_CTRL0_CLR,UART Receive DMA Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Clear" bitfld.long 0x08 28. " RX_SOURCE ,Source of Receive Data" "No effect,Clear" textline " " bitfld.long 0x08 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Clear" hexmask.long.word 0x08 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x0c "HW_UARTAPP_CTRL0_TOG,UART Receive DMA Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates all of the block level clocks off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Tell the UART to execute the RX DMA Command" "Not toggle,Toggle" bitfld.long 0x0c 28. " RX_SOURCE ,Source of Receive Data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x10 "HW_UARTAPP_CTRL1,UART Transmit DMA Control Register" bitfld.long 0x10 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Run" hexmask.long.word 0x10 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x14 "HW_UARTAPP_CTRL1_SET,UART Transmit DMA Control Set Register" bitfld.long 0x14 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Set" hexmask.long.word 0x14 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x18 "HW_UARTAPP_CTRL1_CLR,UART Transmit DMA Control Clear Register" bitfld.long 0x18 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Clear" hexmask.long.word 0x18 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x1c "HW_UARTAPP_CTRL1_TOG,UART Transmit DMA Control Toggle Register" bitfld.long 0x1c 28. " RUN ,Tell the UART to execute the TX DMA Command" "Not toggle,Toggle" hexmask.long.word 0x1c 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x20 "HW_UARTAPP_CTRL2,UART Control Register" bitfld.long 0x20 31. " INVERT_RTS ,Invert RTS signal" "Not inverted,Inverted" bitfld.long 0x20 30. " INVERT_CTS ,Invert CTS signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 29. " INVERT_TX ,Invert TX signal" "Not inverted,Inverted" bitfld.long 0x20 28. " INVERT_RX ,Invert RX signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Asserted,Deasserted" bitfld.long 0x20 26. " DMAONERR ,DMA On Error" "Not terminate,Terminate" textline " " bitfld.long 0x20 25. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x20 24. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x20 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x20 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x20 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " RTS ,Request To Send" "0,1" bitfld.long 0x20 10. " DTR ,Data Transmit Ready" "Not ready,Ready" textline " " bitfld.long 0x20 9. " RXE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x20 8. " TXE ,Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " LBE ,Loop Back Enable" "Disabled,Enabled" bitfld.long 0x20 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not use,Use" textline " " bitfld.long 0x20 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x24 "HW_UARTAPP_CTRL2_SET,UART Control Set Register" bitfld.long 0x24 31. " INVERT_RTS ,Invert RTS signal" "No effect,Set" bitfld.long 0x24 30. " INVERT_CTS ,Invert CTS signal" "No effect,Set" textline " " bitfld.long 0x24 29. " INVERT_TX ,Invert TX signal" "No effect,Set" bitfld.long 0x24 28. " INVERT_RX ,Invert RX signal" "No effect,Set" textline " " bitfld.long 0x24 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Set" bitfld.long 0x24 26. " DMAONERR ,DMA On Error" "No effect,Set" textline " " bitfld.long 0x24 25. " TXDMAE ,Transmit DMA Enable" "No effect,Set" bitfld.long 0x24 24. " RXDMAE ,Receive DMA Enable" "No effect,Set" textline " " bitfld.long 0x24 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x24 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x24 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Set" bitfld.long 0x24 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Set" textline " " bitfld.long 0x24 11. " RTS ,Request To Send" "No effect,Set" bitfld.long 0x24 10. " DTR ,Data Transmit Ready" "No effect,Set" textline " " bitfld.long 0x24 9. " RXE ,Receive Enable" "No effect,Set" bitfld.long 0x24 8. " TXE ,Transmit Enable" "No effect,Set" textline " " bitfld.long 0x24 7. " LBE ,Loop Back Enable" "No effect,Set" bitfld.long 0x24 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Set" textline " " bitfld.long 0x24 0. " UARTEN ,UART Enable" "No effect,Set" line.long 0x28 "HW_UARTAPP_CTRL2_CLR,UART Control Clear Register" bitfld.long 0x28 31. " INVERT_RTS ,Invert RTS signal" "No effect,Clear" bitfld.long 0x28 30. " INVERT_CTS ,Invert CTS signal" "No effect,Clear" textline " " bitfld.long 0x28 29. " INVERT_TX ,Invert TX signal" "No effect,Clear" bitfld.long 0x28 28. " INVERT_RX ,Invert RX signal" "No effect,Clear" textline " " bitfld.long 0x28 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Clear" bitfld.long 0x28 26. " DMAONERR ,DMA On Error" "No effect,Clear" textline " " bitfld.long 0x28 25. " TXDMAE ,Transmit DMA Enable" "No effect,Clear" bitfld.long 0x28 24. " RXDMAE ,Receive DMA Enable" "No effect,Clear" textline " " bitfld.long 0x28 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x28 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x28 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Clear" bitfld.long 0x28 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Clear" textline " " bitfld.long 0x28 11. " RTS ,Request To Send" "No effect,Clear" bitfld.long 0x28 10. " DTR ,Data Transmit Ready" "No effect,Clear" textline " " bitfld.long 0x28 9. " RXE ,Receive Enable" "No effect,Clear" bitfld.long 0x28 8. " TXE ,Transmit Enable" "No effect,Clear" textline " " bitfld.long 0x28 7. " LBE ,Loop Back Enable" "No effect,Clear" bitfld.long 0x28 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Clear" textline " " bitfld.long 0x28 0. " UARTEN ,UART Enable" "No effect,Clear" line.long 0x2c "HW_UARTAPP_CTRL2_TOG,UART Control Toggle Register" bitfld.long 0x2c 31. " INVERT_RTS ,Invert RTS signal" "Not toggle,Toggle" bitfld.long 0x2c 30. " INVERT_CTS ,Invert CTS signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " INVERT_TX ,Invert TX signal" "Not toggle,Toggle" bitfld.long 0x2c 28. " INVERT_RX ,Invert RX signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Not toggle,Toggle" bitfld.long 0x2c 26. " DMAONERR ,DMA On Error" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " TXDMAE ,Transmit DMA Enable" "Not toggle,Toggle" bitfld.long 0x2c 24. " RXDMAE ,Receive DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x2c 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x2c 15. " CTSEN ,CTS Hardware Flow Control Enable" "Not toggle,Toggle" bitfld.long 0x2c 14. " RTSEN ,RTS Hardware Flow Control Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 11. " RTS ,Request To Send" "Not toggle,Toggle" bitfld.long 0x2c 10. " DTR ,Data Transmit Ready" "Not toggle,Toggle" textline " " bitfld.long 0x2c 9. " RXE ,Receive Enable" "Not toggle,Toggle" bitfld.long 0x2c 8. " TXE ,Transmit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 7. " LBE ,Loop Back Enable" "Not toggle,Toggle" bitfld.long 0x2c 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " UARTEN ,UART Enable" "Not toggle,Toggle" if (((d.l(asd:(0x8006e000+0x30)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006e000+0x30)))&0x6)==0x2) group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=0; else group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" endif if (((d.l(asd:(0x8006e000+0x40)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006e000+0x40)))&0x6)==0x2) group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=0; else group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" endif group.long 0x50++0x0f line.long 0x00 "HW_UARTAPP_INTR,UART Interrupt Register" bitfld.long 0x00 26. " OEIEN ,Overrun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " BEIEN ,Break Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PEIEN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " FEIEN ,Framing Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RTIEN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TXIEN ,Transmit Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " RXIEN ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " OEIS ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIS ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIS ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIS ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIS ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIS ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIS ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTAPP_INTR_SET,UART Interrupt Set Register" bitfld.long 0x04 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Set" bitfld.long 0x04 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 20. " RXIEN ,Receive Interrupt Enable" "No effect,Set" bitfld.long 0x04 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Set" bitfld.long 0x04 9. " BEIS ,Break Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 8. " PEIS ,Parity Error Interrupt Status" "No effect,Set" bitfld.long 0x04 7. " FEIS ,Framing Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Set" bitfld.long 0x04 5. " TXIS ,Transmit Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 4. " RXIS ,Receive Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Set" line.long 0x08 "HW_UARTAPP_INTR_CLR,UART Interrupt Clear Register" bitfld.long 0x08 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Clear" bitfld.long 0x08 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 20. " RXIEN ,Receive Interrupt Enable" "No effect,Clear" bitfld.long 0x08 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 9. " BEIS ,Break Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 8. " PEIS ,Parity Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 7. " FEIS ,Framing Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Clear" bitfld.long 0x08 5. " TXIS ,Transmit Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 4. " RXIS ,Receive Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Clear" line.long 0x0c "HW_UARTAPP_INTR_TOG,UART Interrupt Toggle Register" bitfld.long 0x0c 26. " OEIEN ,Overrun Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " BEIEN ,Break Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PEIEN ,Parity Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 23. " FEIEN ,Framing Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " RTIEN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 21. " TXIEN ,Transmit Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " RXIEN ,Receive Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " OEIS ,Overrun Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 9. " BEIS ,Break Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " PEIS ,Parity Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 7. " FEIS ,Framing Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RTIS ,Receive Timeout Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 5. " TXIS ,Transmit Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " RXIS ,Receive Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not toggle,Toggle" group.long 0x60++0x03 line.long 0x00 "HW_UARTAPP_DATA,UART Data Register" group.long 0x70++0x03 line.long 0x00 "HW_UARTAPP_STAT,UART Status Register" bitfld.long 0x00 31. " PRESENT ,Application UART function is present" "Not present,Present" bitfld.long 0x00 30. " HISPEED ,High-speed function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " BUSY ,UART Busy" "Not busy,Busy" bitfld.long 0x00 28. " CTS ,Clear To Send" "0,1" textline " " bitfld.long 0x00 27. " TXFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 26. " RXFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 25. " TXFF ,Transmit FIFO Full" "Not full,Full" bitfld.long 0x00 24. " RXFE ,Receive FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 23. " RXBYTE_INVALID3 ,The invalid state of the last read of Receive Data byte 3" "Valid,Invalid" bitfld.long 0x00 22. " RXBYTE_INVALID2 ,The invalid state of the last read of Receive Data byte 2" "Valid,Invalid" textline " " bitfld.long 0x00 21. " RXBYTE_INVALID1 ,The invalid state of the last read of Receive Data byte 1" "Valid,Invalid" bitfld.long 0x00 20. " RXBYTE_INVALID0 ,The invalid state of the last read of Receive Data byte 0" "Valid,Invalid" textline " " bitfld.long 0x00 19. " OERR ,Overrun Error" "No error,Error" bitfld.long 0x00 18. " BERR ,Break Error" "No error,Error" textline " " bitfld.long 0x00 17. " PERR ,Parity Error" "No error,Error" bitfld.long 0x00 16. " FERR ,Framing Error" "No error,Error" textline " " hexmask.long.word 0x00 0.--15. 1. " RXCOUNT ,Number of bytes received during a Receive DMA command" rgroup.long 0x80++0x03 line.long 0x00 "HW_UARTAPP_DEBUG,UART Debug Register" hexmask.long.word 0x00 16.--31. 1. " RXIBAUD_DIV ,RX Integer Baud Divisor" hexmask.long.byte 0x00 10.--15. 1. " RXFBAUD_DIV ,RX Fractional Baud Divisor" textline " " bitfld.long 0x00 5. " TXDMARUN ,DMA Command Run Status for TXDMARUN" "0,1" bitfld.long 0x00 4. " RXDMARUN ,DMA Command Run Status for RXDMARUN" "0,1" textline " " bitfld.long 0x00 3. " TXCMDEND ,DMA Request Status for UART_TXCMDEND" "0,1" bitfld.long 0x00 2. " RXCMDEND ,DMA Request Status for UART_RXCMDEND" "0,1" textline " " bitfld.long 0x00 1. " TXDMARQ ,DMA Request Status for UART_TXDMAREQ" "0,1" bitfld.long 0x00 0. " RXDMARQ ,DMA Request Status for UART_RXDMAREQ" "0,1" rgroup.long 0x90++0x03 line.long 0x00 "HW_UARTAPP_VERSION,UART Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" group.long 0xa0++0x03 line.long 0x00 "HW_UARTAPP_AUTOBAUD,UART AutoBaud Register" hexmask.long.byte 0x00 24.--31. 1. " REFCHAR1 ,Second reference character used in baud rate detection" hexmask.long.byte 0x00 16.--23. 1. " REFCHAR0 ,First reference character used in baud rate detection" textline " " bitfld.long 0x00 4. " UPDATE_TX ,TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic" "Not updated,Updated" bitfld.long 0x00 3. " TWO_REF_CHARS ,Use 2 referenfce characters" "1 reference char,2 reference char" textline " " bitfld.long 0x00 2. " START_WITH_RUNBIT ,Assertion of HW_UARTAPP_CTRL0_RUN or START_BAUD_DETECT" "START_BAUD_DETECT,HW_UARTAPP_CTRL0_RUN" bitfld.long 0x00 1. " START_BAUD_DETECT ,Set to 1 to start automatic baudrate detection" "No effect,Start" textline " " bitfld.long 0x00 0. " BAUD_DETECT_EN ,Enable automatic baudrate detection" "Disabled,Enabled" tree.end tree.end tree "DBGUART (Debug Universal Asynchronous Receiver and Transmitter)" base asd:0x80070000 width 19. group.long 0x00++0x03 line.long 0x00 "HW_UARTDBGDR,UART Data Register" bitfld.long 0x00 11. " OE ,Overrun Error" "No error,Error" bitfld.long 0x00 10. " BE ,Break Error" "No error,Error" textline " " bitfld.long 0x00 9. " PE ,Parity Error" "No error,Error" bitfld.long 0x00 8. " FE ,Framing Error" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit (write) data character" group.long 0x04++0x03 line.long 0x00 "HW_UARTDBGRSR_ECR,UART Receive Status Register/Error Clear Register" bitfld.long 0x00 7. " EC3 ,Overrun Error Clear" "0,1" bitfld.long 0x00 6. " EC2 ,Break Error Clear" "0,1" textline " " bitfld.long 0x00 5. " EC1 ,Parity Error Clear" "0,1" bitfld.long 0x00 4. " EC0 ,Framing Error Clear" "0,1" textline " " bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error" bitfld.long 0x00 2. " BE ,Break Error" "No error,Error" textline " " bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error" bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error" rgroup.long 0x18++0x03 line.long 0x00 "HW_UARTDBGFR,UART Flag Register" bitfld.long 0x00 8. " RI ,Ring Indicator" "0,1" bitfld.long 0x00 7. " TXFE ,Transmit FIFO/Transmit holding register Empty" "Not empty,Empty" textline " " bitfld.long 0x00 6. " RXFF ,Receive FIFO Full" "Not full,Full" bitfld.long 0x00 5. " TXFF ,Transmit FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 4. " RXFE ,Receive FIFO Empty" "Not empty,Empty" bitfld.long 0x00 3. " BUSY ,UART Busy" "Not busy,Busy" textline " " bitfld.long 0x00 2. " DCD ,Data Carrier Detect" "Not detected,Detected" bitfld.long 0x00 1. " DSR ,Data Set Ready" "Not ready,Ready" textline " " bitfld.long 0x00 0. " CTS ,Clear To Send" "0,1" group.long 0x20++0x0b line.long 0x00 "HW_UARTDBGILPR,UART IrDA Low-Power Counter Register" hexmask.long.byte 0x00 0.--7. 1. " ILPDVSR ,IrDA Low Power Divisor [7:0]" line.long 0x04 "HW_UARTDBGIBRD,UART Integer Baud Rate Divisor Register" hexmask.long.word 0x04 0.--15. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" line.long 0x08 "HW_UARTDBGFBRD,UART Fractional Baud Rate Divisor Register" hexmask.long.byte 0x08 0.--5. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" if (((d.l(asd:(0x80070000+0x2c)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x2c++0x03 line.long 0x00 "HW_UARTDBGLCR_H,UART Line Control Register High" bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "No effect,Send" ;PEN=1,EPS=0 elif (((d.l(asd:(0x80070000+0x2c)))&0x6)==0x2) group.long 0x2c++0x03 line.long 0x00 "HW_UARTDBGLCR_H,UART Line Control Register High" bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "No effect,Send" ;PEN=0; else group.long 0x2c++0x03 line.long 0x00 "HW_UARTDBGLCR_H,UART Line Control Register High" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "No effect,Send" endif group.long 0x30++0x0b line.long 0x00 "HW_UARTDBGCR,UART Control Register" bitfld.long 0x00 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " RTS ,Request To Send" "0,1" bitfld.long 0x00 9. " RXE ,Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 7. " LBE ,Loop Back Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTDBGIFLS,UART Interrupt FIFO Level Select Register" bitfld.long 0x04 3.--5. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,2/8,4/8,6/8,7/8,?..." bitfld.long 0x04 0.--2. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,2/8,4/8,6/8,7/8,?..." line.long 0x08 "HW_UARTDBGIMSC,UART Interrupt Mask Set/Clear Register" bitfld.long 0x08 10. " OEIM ,Overrun Error Interrupt Mask" "Clear,Set" bitfld.long 0x08 9. " BEIM ,Break Error Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 8. " PEIM ,Parity Error Interrupt Mask" "Clear,Set" bitfld.long 0x08 7. " FEIM ,Framing Error Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 6. " RTIM ,Receive Timeout Interrupt Mask" "Clear,Set" bitfld.long 0x08 5. " TXIM ,Transmit Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 4. " RXIM ,Receive Interrupt Mask" "Clear,Set" bitfld.long 0x08 3. " DSRMIM ,nUARTDSR Modem Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 2. " DCDMIM ,nUARTDCD Modem Interrupt Mask" "Clear,Set" bitfld.long 0x08 1. " CTSMIM ,nUARTCTS Modem Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 0. " RIMIM ,nUARTRI Modem Interrupt Mask" "Clear,Set" rgroup.long 0x3c++0x07 line.long 0x00 "HW_UARTDBGRIS,UART Raw Interrupt Status Register" bitfld.long 0x00 10. " OEIM ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIM ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIM ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIM ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIM ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIM ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIM ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 3. " DSRMIM ,nUARTDSR Modem Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " DCDMIM ,nUARTDCD Modem Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIM ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " RIMIM ,nUARTRI Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTDBGMIS,UART Masked Interrupt Status Register" bitfld.long 0x04 10. " OEMIS ,Overrun Error Masked Interrupt Status" "Not masked,Masked" bitfld.long 0x04 9. " BEMIS ,Break Error Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 8. " PEMIS ,Parity Error Masked Interrupt Status" "Not masked,Masked" bitfld.long 0x04 7. " FEMIS ,Framing Error Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 6. " RTMIS ,Receive Masked Timeout Interrupt Status" "Not masked,Masked" bitfld.long 0x04 5. " TXMIS ,Transmit Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 4. " RXMIS ,Receive Masked Interrupt Status" "Not masked,Masked" bitfld.long 0x04 3. " DSRMMIS ,nUARTDSR Modem Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 2. " DCDMMIS ,nUARTDCD Modem Masked Interrupt Status" "Not masked,Masked" bitfld.long 0x04 1. " CTSMMIS ,nUARTCTS Modem Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 0. " RIMMIS ,nUARTRI Modem Masked Interrupt Status" "Not masked,Masked" wgroup.long 0x44++0x03 line.long 0x00 "HW_UARTDBGICR,UART Interrupt Clear Register" bitfld.long 0x00 10. " OEIC ,Overrun Error Interrupt Clear" "No effect,Clear" bitfld.long 0x00 9. " BEIC ,Break Error Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 8. " PEIC ,Parity Error Interrupt Clear" "No effect,Clear" bitfld.long 0x00 7. " FEIC ,Framing Error Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 6. " RTIC ,Receive Timeout Interrupt Clear" "No effect,Clear" bitfld.long 0x00 5. " TXIC ,Transmit Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " RXIC ,Receive Interrupt Clear" "No effect,Clear" bitfld.long 0x00 3. " DSRMIC ,nUARTDSR Modem Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 2. " DCDMIC ,nUARTDCD Modem Interrupt Clear" "No effect,Clear" bitfld.long 0x00 1. " CTSMIC ,nUARTCTS Modem Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 0. " RIMIC ,nUARTRI Modem Interrupt Clear" "No effect,Clear" tree.end tree "AUDIOIN/ADC" base asd:0x8004c000 width 27. group.long 0x00++0x0f line.long 0x00 "HW_AUDIOIN_CTRL,AUDIOIN Control Register" bitfld.long 0x00 31. " SFTRST ,AUDIOIN Module Soft Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,AUDIOIN Clock Gate Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " LR_SWAP ,Left/Right Input Channel Swap Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EDGE_SYNC ,Serial Input Clock Edge Sync Select" "Rising edge,Falling edge" bitfld.long 0x00 8. " INVERT_1BIT ,Invert Serial Audio Input Enable" "Normal,Inverted" textline " " bitfld.long 0x00 7. " OFFSET_ENABLE ,ADC Analog High-Pass Filter Offset Calculation Enable" "Disabled,Enabled" bitfld.long 0x00 6. " HPF_ENABLE ,ADC High-Pass Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " WORD_LENGTH ,PCM Audio Bit Size Select" "32-bit,16-bit" bitfld.long 0x00 4. " LOOPBACK ,AUDIOOUT-to-AUDIOIN Loopback Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FIFO_UNDERFLOW_IRQ ,FIFO Underflow Interrupt Status Bit" "Not occurred,Occurred" bitfld.long 0x00 2. " FIFO_OVERFLOW_IRQ ,FIFO Overflow Interrupt Status Bit" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FIFO_ERROR_IRQ_EN ,FIFO Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " RUN ,AUDIOIN Enable" "Disabled,Enabled" line.long 0x04 "HW_AUDIOIN_CTRL_SET,AUDIOIN Control Set Register" bitfld.long 0x04 31. " SFTRST ,AUDIOIN Module Soft Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,AUDIOIN Clock Gate Enable" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 10. " LR_SWAP ,Left/Right Input Channel Swap Enable" "No effect,Set" textline " " bitfld.long 0x04 9. " EDGE_SYNC ,Serial Input Clock Edge Sync Select" "No effect,Set" bitfld.long 0x04 8. " INVERT_1BIT ,Invert Serial Audio Input Enable" "No effect,Set" textline " " bitfld.long 0x04 7. " OFFSET_ENABLE ,ADC Analog High-Pass Filter Offset Calculation Enable" "No effect,Set" bitfld.long 0x04 6. " HPF_ENABLE ,ADC High-Pass Filter Enable" "No effect,Set" textline " " bitfld.long 0x04 5. " WORD_LENGTH ,PCM Audio Bit Size Select" "No effect,Set" bitfld.long 0x04 4. " LOOPBACK ,AUDIOOUT-to-AUDIOIN Loopback Enable" "No effect,Set" textline " " bitfld.long 0x04 3. " FIFO_UNDERFLOW_IRQ ,FIFO Underflow Interrupt Status Bit" "No effect,Set" bitfld.long 0x04 2. " FIFO_OVERFLOW_IRQ ,FIFO Overflow Interrupt Status Bit" "No effect,Set" textline " " bitfld.long 0x04 1. " FIFO_ERROR_IRQ_EN ,FIFO Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 0. " RUN ,AUDIOIN Enable" "No effect,Set" line.long 0x08 "HW_AUDIOIN_CTRL_CLR,AUDIOIN Control Clear Register" bitfld.long 0x08 31. " SFTRST ,AUDIOIN Module Soft Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,AUDIOIN Clock Gate Enable" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 10. " LR_SWAP ,Left/Right Input Channel Swap Enable" "No effect,Clear" textline " " bitfld.long 0x08 9. " EDGE_SYNC ,Serial Input Clock Edge Sync Select" "No effect,Clear" bitfld.long 0x08 8. " INVERT_1BIT ,Invert Serial Audio Input Enable" "No effect,Clear" textline " " bitfld.long 0x08 7. " OFFSET_ENABLE ,ADC Analog High-Pass Filter Offset Calculation Enable" "No effect,Clear" bitfld.long 0x08 6. " HPF_ENABLE ,ADC High-Pass Filter Enable" "No effect,Clear" textline " " bitfld.long 0x08 5. " WORD_LENGTH ,PCM Audio Bit Size Select" "No effect,Clear" bitfld.long 0x08 4. " LOOPBACK ,AUDIOOUT-to-AUDIOIN Loopback Enable" "No effect,Clear" textline " " bitfld.long 0x08 3. " FIFO_UNDERFLOW_IRQ ,FIFO Underflow Interrupt Status Bit" "No effect,Clear" bitfld.long 0x08 2. " FIFO_OVERFLOW_IRQ ,FIFO Overflow Interrupt Status Bit" "No effect,Clear" textline " " bitfld.long 0x08 1. " FIFO_ERROR_IRQ_EN ,FIFO Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 0. " RUN ,AUDIOIN Enable" "No effect,Clear" line.long 0x0c "HW_AUDIOIN_CTRL_TOG,AUDIOIN Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,AUDIOIN Module Soft Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,AUDIOIN Clock Gate Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 10. " LR_SWAP ,Left/Right Input Channel Swap Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " EDGE_SYNC ,Serial Input Clock Edge Sync Select" "Not toggle,Toggle" bitfld.long 0x0c 8. " INVERT_1BIT ,Invert Serial Audio Input Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " OFFSET_ENABLE ,ADC Analog High-Pass Filter Offset Calculation Enable" "Not toggle,Toggle" bitfld.long 0x0c 6. " HPF_ENABLE ,ADC High-Pass Filter Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " WORD_LENGTH ,PCM Audio Bit Size Select" "Not toggle,Toggle" bitfld.long 0x0c 4. " LOOPBACK ,AUDIOOUT-to-AUDIOIN Loopback Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " FIFO_UNDERFLOW_IRQ ,FIFO Underflow Interrupt Status Bit" "Not toggle,Toggle" bitfld.long 0x0c 2. " FIFO_OVERFLOW_IRQ ,FIFO Overflow Interrupt Status Bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " FIFO_ERROR_IRQ_EN ,FIFO Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,AUDIOIN Enable" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_AUDIOIN_STAT,AUDIOIN Status Register" bitfld.long 0x00 31. " ADC_PRESENT ,AUDIOIN Functionality Present" "Not present,Present" group.long 0x20++0x5f line.long 0x00 "HW_AUDIOIN_ADCSRR,AUDIOIN Sample Rate Register" bitfld.long 0x00 31. " OSR ,AUDIOIN Oversample Rate" "6MHz,12MHz" bitfld.long 0x00 28.--30. " BASEMULT ,Base Sample Rate Multiplier" "Reserved,Single-rate,Double-rate,Reserved,Quad-rate,?..." textline " " bitfld.long 0x00 24.--26. " SRC_HOLD ,Sample Rate Conversion Hold Factor" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " SRC_INT ,Sample Rate Conversion Integer Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--12. 1. " SRC_FRAC ,Sample Rate Conversion Fraction Factor" line.long 0x04 "HW_AUDIOIN_ADCSRR_SET,AUDIOIN Sample Rate Set Register" bitfld.long 0x04 31. " OSR ,AUDIOIN Oversample Rate" "No effect,Set" bitfld.long 0x04 28.--30. " BASEMULT ,Base Sample Rate Multiplier" "Reserved,Single-rate,Double-rate,Reserved,Quad-rate,?..." textline " " bitfld.long 0x04 24.--26. " SRC_HOLD ,Sample Rate Conversion Hold Factor" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. " SRC_INT ,Sample Rate Conversion Integer Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x04 0.--12. 1. " SRC_FRAC ,Sample Rate Conversion Fraction Factor" line.long 0x08 "HW_AUDIOIN_ADCSRR_CLR,AUDIOIN Sample Rate Clear Register" bitfld.long 0x08 31. " OSR ,AUDIOIN Oversample Rate" "No effect,Clear" bitfld.long 0x08 28.--30. " BASEMULT ,Base Sample Rate Multiplier" "Reserved,Single-rate,Double-rate,Reserved,Quad-rate,?..." textline " " bitfld.long 0x08 24.--26. " SRC_HOLD ,Sample Rate Conversion Hold Factor" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--20. " SRC_INT ,Sample Rate Conversion Integer Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x08 0.--12. 1. " SRC_FRAC ,Sample Rate Conversion Fraction Factor" line.long 0x0c "HW_AUDIOIN_ADCSRR_TOG,AUDIOIN Sample Rate Toggle Register" bitfld.long 0x0c 31. " OSR ,AUDIOIN Oversample Rate" "Not toggle,Toggle" bitfld.long 0x0c 28.--30. " BASEMULT ,Base Sample Rate Multiplier" "Reserved,Single-rate,Double-rate,Reserved,Quad-rate,?..." textline " " bitfld.long 0x0c 24.--26. " SRC_HOLD ,Sample Rate Conversion Hold Factor" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--20. " SRC_INT ,Sample Rate Conversion Integer Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0c 0.--12. 1. " SRC_FRAC ,Sample Rate Conversion Fraction Factor" line.long 0x10 "HW_AUDIOIN_ADCVOLUME,AUDIOIN Volume Register" bitfld.long 0x10 28. " VOLUME_UPDATE_LEFT ,Left Channel Volume Update Pending" "Not pending,Pending" bitfld.long 0x10 25. " EN_ZCD ,Enable Zero Cross Detect" "Disabled,Enabled" textline " " hexmask.long.byte 0x10 16.--23. 1. " VOLUME_LEFT ,Left Channel Volume Setting" bitfld.long 0x10 12. " VOLUME_UPDATE_RIGHT ,Right Channel Volume Update Pending" "Not pending,Pending" textline " " hexmask.long.byte 0x10 0.--7. 1. " VOLUME_RIGHT ,Right Channel Volume Setting" line.long 0x14 "HW_AUDIOIN_ADCVOLUME_SET,AUDIOIN Volume Set Register" bitfld.long 0x14 28. " VOLUME_UPDATE_LEFT ,Left Channel Volume Update Pending" "No effect,Set" bitfld.long 0x14 25. " EN_ZCD ,Enable Zero Cross Detect" "No effect,Set" textline " " hexmask.long.byte 0x14 16.--23. 1. " VOLUME_LEFT ,Left Channel Volume Setting" bitfld.long 0x14 12. " VOLUME_UPDATE_RIGHT ,Right Channel Volume Update Pending" "No effect,Set" textline " " hexmask.long.byte 0x14 0.--7. 1. " VOLUME_RIGHT ,Right Channel Volume Setting" line.long 0x18 "HW_AUDIOIN_ADCVOLUME_CLR,AUDIOIN Volume Clear Register" bitfld.long 0x18 28. " VOLUME_UPDATE_LEFT ,Left Channel Volume Update Pending" "No effect,Clear" bitfld.long 0x18 25. " EN_ZCD ,Enable Zero Cross Detect" "No effect,Clear" textline " " hexmask.long.byte 0x18 16.--23. 1. " VOLUME_LEFT ,Left Channel Volume Setting" bitfld.long 0x18 12. " VOLUME_UPDATE_RIGHT ,Right Channel Volume Update Pending" "No effect,Clear" textline " " hexmask.long.byte 0x18 0.--7. 1. " VOLUME_RIGHT ,Right Channel Volume Setting" line.long 0x1c "HW_AUDIOIN_ADCVOLUME_TOG,AUDIOIN Volume Toggle Register" bitfld.long 0x1c 28. " VOLUME_UPDATE_LEFT ,Left Channel Volume Update Pending" "Not toggle,Toggle" bitfld.long 0x1c 25. " EN_ZCD ,Enable Zero Cross Detect" "Not toggle,Toggle" textline " " hexmask.long.byte 0x1c 16.--23. 1. " VOLUME_LEFT ,Left Channel Volume Setting" bitfld.long 0x1c 12. " VOLUME_UPDATE_RIGHT ,Right Channel Volume Update Pending" "Not toggle,Toggle" textline " " hexmask.long.byte 0x1c 0.--7. 1. " VOLUME_RIGHT ,Right Channel Volume Setting" line.long 0x20 "HW_AUDIOIN_ADCDEBUG,AUDIOIN Debug Register" bitfld.long 0x20 31. " ENABLE_ADCDMA ,AUDIOIN Digital Path Test Enable" "Disabled,Enabled" bitfld.long 0x20 3. " ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS ,DMA Request Sync Status" "No interrupt,Interrupt" textline " " bitfld.long 0x20 2. " SET_INTERRUPT3_HAND_SHAKE ,Interrupt[3] Status" "No interrupt,Interrupt" bitfld.long 0x20 1. " DMA_PREQ ,DMA Request Status" "Not requested,Requested" textline " " bitfld.long 0x20 0. " FIFO_STATUS ,FIFO Status" "Empty,Data" line.long 0x24 "HW_AUDIOIN_ADCDEBUG_SET,AUDIOIN Debug Set Register" bitfld.long 0x24 31. " ENABLE_ADCDMA ,AUDIOIN Digital Path Test Enable" "No effect,Set" bitfld.long 0x24 3. " ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS ,DMA Request Sync Status" "No effect,Set" textline " " bitfld.long 0x24 2. " SET_INTERRUPT3_HAND_SHAKE ,Interrupt[3] Status" "No effect,Set" bitfld.long 0x24 1. " DMA_PREQ ,DMA Request Status" "No effect,Set" textline " " bitfld.long 0x24 0. " FIFO_STATUS ,FIFO Status" "No effect,Set" line.long 0x28 "HW_AUDIOIN_ADCDEBUG_CLR,AUDIOIN Debug Clear Register" bitfld.long 0x28 31. " ENABLE_ADCDMA ,AUDIOIN Digital Path Test Enable" "No effect,Clear" bitfld.long 0x28 3. " ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS ,DMA Request Sync Status" "No effect,Clear" textline " " bitfld.long 0x28 2. " SET_INTERRUPT3_HAND_SHAKE ,Interrupt[3] Status" "No effect,Clear" bitfld.long 0x28 1. " DMA_PREQ ,DMA Request Status" "No effect,Clear" textline " " bitfld.long 0x28 0. " FIFO_STATUS ,FIFO Status" "No effect,Clear" line.long 0x2c "HW_AUDIOIN_ADCDEBUG_TOG,AUDIOIN Debug Toggle Register" bitfld.long 0x2c 31. " ENABLE_ADCDMA ,AUDIOIN Digital Path Test Enable" "Not toggle,Toggle" bitfld.long 0x2c 3. " ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS ,DMA Request Sync Status" "Not toggle,Toggle" textline " " bitfld.long 0x2c 2. " SET_INTERRUPT3_HAND_SHAKE ,Interrupt[3] Status" "Not toggle,Toggle" bitfld.long 0x2c 1. " DMA_PREQ ,DMA Request Status" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " FIFO_STATUS ,FIFO Status" "Not toggle,Toggle" line.long 0x30 "HW_AUDIOIN_ADCVOL,ADC Mux Volume and Select Control Register" bitfld.long 0x30 28. " VOLUME_UPDATE_PENDING ,Volume Update Pending" "Not pending,Pending" bitfld.long 0x30 25. " EN_ADC_ZCD ,Enable Zero Cross Detect for ADC Amplifier" "Disabled,Enabled" textline " " bitfld.long 0x30 24. " MUTE ,ADC Mute" "Unmute,Mute" bitfld.long 0x30 12.--13. " SELECT_LEFT ,ADC Left Channel Input Source Select" "Microphone,Line 1,Headphone,Line 2" textline " " bitfld.long 0x30 8.--11. " GAIN_LEFT ,Left Channel ADC Gain" "0dB,1.5dB,3dB,4.5dB,6dB,7.5dB,9dB,10.5dB,12dB,13.5dB,15dB,16.5dB,18dB,19.5dB,21dB,22.5dB" bitfld.long 0x30 4.--5. " SELECT_RIGHT ,ADC Right Channel Input Source Select" "Microphone,Line 1,Headphone,Line 2" textline " " bitfld.long 0x30 0.--3. " GAIN_RIGHT ,Right Channel ADC Gain" "0dB,1.5dB,3dB,4.5dB,6dB,7.5dB,9dB,10.5dB,12dB,13.5dB,15dB,16.5dB,18dB,19.5dB,21dB,22.5dB" line.long 0x34 "HW_AUDIOIN_ADCVOL_SET,ADC Mux Volume and Select Control Set Register" bitfld.long 0x34 28. " VOLUME_UPDATE_PENDING ,Volume Update Pending" "No effect,Set" bitfld.long 0x34 25. " EN_ADC_ZCD ,Enable Zero Cross Detect for ADC Amplifier" "No effect,Set" textline " " bitfld.long 0x34 24. " MUTE ,ADC Mute" "No effect,Set" bitfld.long 0x34 12.--13. " SELECT_LEFT ,ADC Left Channel Input Source Select" "Microphone,Line 1,Headphone,Line 2" textline " " bitfld.long 0x34 8.--11. " GAIN_LEFT ,Left Channel ADC Gain" "0dB,1.5dB,3dB,4.5dB,6dB,7.5dB,9dB,10.5dB,12dB,13.5dB,15dB,16.5dB,18dB,19.5dB,21dB,22.5dB" bitfld.long 0x34 4.--5. " SELECT_RIGHT ,ADC Right Channel Input Source Select" "Microphone,Line 1,Headphone,Line 2" textline " " bitfld.long 0x34 0.--3. " GAIN_RIGHT ,Right Channel ADC Gain" "0dB,1.5dB,3dB,4.5dB,6dB,7.5dB,9dB,10.5dB,12dB,13.5dB,15dB,16.5dB,18dB,19.5dB,21dB,22.5dB" line.long 0x38 "HW_AUDIOIN_ADCVOL_CLR,ADC Mux Volume and Select Control Clear Register" bitfld.long 0x38 28. " VOLUME_UPDATE_PENDING ,Volume Update Pending" "No effect,Clear" bitfld.long 0x38 25. " EN_ADC_ZCD ,Enable Zero Cross Detect for ADC Amplifier" "No effect,Clear" textline " " bitfld.long 0x38 24. " MUTE ,ADC Mute" "No effect,Clear" bitfld.long 0x38 12.--13. " SELECT_LEFT ,ADC Left Channel Input Source Select" "Microphone,Line 1,Headphone,Line 2" textline " " bitfld.long 0x38 8.--11. " GAIN_LEFT ,Left Channel ADC Gain" "0dB,1.5dB,3dB,4.5dB,6dB,7.5dB,9dB,10.5dB,12dB,13.5dB,15dB,16.5dB,18dB,19.5dB,21dB,22.5dB" bitfld.long 0x38 4.--5. " SELECT_RIGHT ,ADC Right Channel Input Source Select" "Microphone,Line 1,Headphone,Line 2" textline " " bitfld.long 0x38 0.--3. " GAIN_RIGHT ,Right Channel ADC Gain" "0dB,1.5dB,3dB,4.5dB,6dB,7.5dB,9dB,10.5dB,12dB,13.5dB,15dB,16.5dB,18dB,19.5dB,21dB,22.5dB" line.long 0x3c "HW_AUDIOIN_ADCVOL_TOG,ADC Mux Volume and Select Control Toggle Register" bitfld.long 0x3c 28. " VOLUME_UPDATE_PENDING ,Volume Update Pending" "Not toggle,Toggle" bitfld.long 0x3c 25. " EN_ADC_ZCD ,Enable Zero Cross Detect for ADC Amplifier" "Not toggle,Toggle" textline " " bitfld.long 0x3c 24. " MUTE ,ADC Mute" "Not toggle,Toggle" bitfld.long 0x3c 12.--13. " SELECT_LEFT ,ADC Left Channel Input Source Select" "Microphone,Line 1,Headphone,Line 2" textline " " bitfld.long 0x3c 8.--11. " GAIN_LEFT ,Left Channel ADC Gain" "0dB,1.5dB,3dB,4.5dB,6dB,7.5dB,9dB,10.5dB,12dB,13.5dB,15dB,16.5dB,18dB,19.5dB,21dB,22.5dB" bitfld.long 0x3c 4.--5. " SELECT_RIGHT ,ADC Right Channel Input Source Select" "Microphone,Line 1,Headphone,Line 2" textline " " bitfld.long 0x3c 0.--3. " GAIN_RIGHT ,Right Channel ADC Gain" "0dB,1.5dB,3dB,4.5dB,6dB,7.5dB,9dB,10.5dB,12dB,13.5dB,15dB,16.5dB,18dB,19.5dB,21dB,22.5dB" line.long 0x40 "HW_AUDIOIN_MICLINE,Microphone and Line Control Register" bitfld.long 0x40 29. " DIVIDE_LINE1 ,Attenuate Line1 Input" "Not attenuated,Attenuated" bitfld.long 0x40 28. " DIVIDE_LINE2 ,Attenuate Line2 Input" "Not attenuated,Attenuated" textline " " bitfld.long 0x40 24. " MIC_SELECT ,Microphone Bias Pin Select" "LRADC0,LRADC1" bitfld.long 0x40 20.--21. " MIC_RESISTOR ,Microphone Bias Resistor Select" "Disabled,2K Ohm,4K Ohm,8K Ohm" textline " " bitfld.long 0x40 16.--18. " MIC_BIAS ,Microphone Bias Voltage Select" "1.21V,1.46V,1.71V,1.96V,2.21V,2.46V,2.71V,2.96V" bitfld.long 0x40 4.--5. " MIC_CHOPCLK ,Enable chopping in the microphone amplifier" "Disabled,192KHz,96KHz,48KHz" textline " " bitfld.long 0x40 0.--1. " MIC_GAIN ,Microphone Gain" "0dB,20dB,30dB,40dB" line.long 0x44 "HW_AUDIOIN_MICLINE_SET,Microphone and Line Control Set Register" bitfld.long 0x44 29. " DIVIDE_LINE1 ,Attenuate Line1 Input" "No effect,Set" bitfld.long 0x44 28. " DIVIDE_LINE2 ,Attenuate Line2 Input" "No effect,Set" textline " " bitfld.long 0x44 24. " MIC_SELECT ,Microphone Bias Pin Select" "No effect,Set" bitfld.long 0x44 20.--21. " MIC_RESISTOR ,Microphone Bias Resistor Select" "Disabled,2K Ohm,4K Ohm,8K Ohm" textline " " bitfld.long 0x44 16.--18. " MIC_BIAS ,Microphone Bias Voltage Select" "1.21V,1.46V,1.71V,1.96V,2.21V,2.46V,2.71V,2.96V" bitfld.long 0x44 4.--5. " MIC_CHOPCLK ,Enable chopping in the microphone amplifier" "Disabled,192KHz,96KHz,48KHz" textline " " bitfld.long 0x44 0.--1. " MIC_GAIN ,Microphone Gain" "0dB,20dB,30dB,40dB" line.long 0x48 "HW_AUDIOIN_MICLINE_CLR,Microphone and Line Control Clear Register" bitfld.long 0x48 29. " DIVIDE_LINE1 ,Attenuate Line1 Input" "No effect,Clear" bitfld.long 0x48 28. " DIVIDE_LINE2 ,Attenuate Line2 Input" "No effect,Clear" textline " " bitfld.long 0x48 24. " MIC_SELECT ,Microphone Bias Pin Select" "No effect,Clear" bitfld.long 0x48 20.--21. " MIC_RESISTOR ,Microphone Bias Resistor Select" "Disabled,2K Ohm,4K Ohm,8K Ohm" textline " " bitfld.long 0x48 16.--18. " MIC_BIAS ,Microphone Bias Voltage Select" "1.21V,1.46V,1.71V,1.96V,2.21V,2.46V,2.71V,2.96V" bitfld.long 0x48 4.--5. " MIC_CHOPCLK ,Enable chopping in the microphone amplifier" "Disabled,192KHz,96KHz,48KHz" textline " " bitfld.long 0x48 0.--1. " MIC_GAIN ,Microphone Gain" "0dB,20dB,30dB,40dB" line.long 0x4c "HW_AUDIOIN_MICLINE_TOG,Microphone and Line Control Toggle Register" bitfld.long 0x4c 29. " DIVIDE_LINE1 ,Attenuate Line1 Input" "Not toggle,Toggle" bitfld.long 0x4c 28. " DIVIDE_LINE2 ,Attenuate Line2 Input" "Not toggle,Toggle" textline " " bitfld.long 0x4c 24. " MIC_SELECT ,Microphone Bias Pin Select" "Not toggle,Toggle" bitfld.long 0x4c 20.--21. " MIC_RESISTOR ,Microphone Bias Resistor Select" "Disabled,2K Ohm,4K Ohm,8K Ohm" textline " " bitfld.long 0x4c 16.--18. " MIC_BIAS ,Microphone Bias Voltage Select" "1.21V,1.46V,1.71V,1.96V,2.21V,2.46V,2.71V,2.96V" bitfld.long 0x4c 4.--5. " MIC_CHOPCLK ,Enable chopping in the microphone amplifier" "Disabled,192KHz,96KHz,48KHz" textline " " bitfld.long 0x4c 0.--1. " MIC_GAIN ,Microphone Gain" "0dB,20dB,30dB,40dB" line.long 0x50 "HW_AUDIOIN_ANACLKCTRL,Analog Clock Control Register" bitfld.long 0x50 31. " CLKGATE ,Analog Clock Gate" "Not gated,Gated" bitfld.long 0x50 10. " DITHER_OFF ,ADC Dither Disable" "No,Yes" textline " " bitfld.long 0x50 9. " SLOW_DITHER ,Slow Dither" "Disabled,Enabled" bitfld.long 0x50 8. " INVERT_ADCCLK ,ADC clock invert" "Not inverted,Inverted" textline " " bitfld.long 0x50 4.--5. " ADCCLK_SHIFT ,ADC Analog Clock Phase Shift" "No shift,20ns,40ns,60ns" bitfld.long 0x50 0.--2. " ADCDIV ,ADC Analog Clock Divider" "6MHz,4MHz,3MHz,2MHz,3MHz,2MHz,1.5MHz,1MHz" line.long 0x54 "HW_AUDIOIN_ANACLKCTRL_SET,Analog Clock Control Set Register" bitfld.long 0x54 31. " CLKGATE ,Analog Clock Gate" "No effect,Set" bitfld.long 0x54 10. " DITHER_OFF ,ADC Dither Disable" "No effect,Set" textline " " bitfld.long 0x54 9. " SLOW_DITHER ,Slow Dither" "No effect,Set" bitfld.long 0x54 8. " INVERT_ADCCLK ,ADC clock invert" "No effect,Set" textline " " bitfld.long 0x54 4.--5. " ADCCLK_SHIFT ,ADC Analog Clock Phase Shift" "No shift,20ns,40ns,60ns" bitfld.long 0x54 0.--2. " ADCDIV ,ADC Analog Clock Divider" "6MHz,4MHz,3MHz,2MHz,3MHz,2MHz,1.5MHz,1MHz" line.long 0x58 "HW_AUDIOIN_ANACLKCTRL_CLR,Analog Clock Control Clear Register" bitfld.long 0x58 31. " CLKGATE ,Analog Clock Gate" "No effect,Clear" bitfld.long 0x58 10. " DITHER_OFF ,ADC Dither Disable" "No effect,Clear" textline " " bitfld.long 0x58 9. " SLOW_DITHER ,Slow Dither" "No effect,Clear" bitfld.long 0x58 8. " INVERT_ADCCLK ,ADC clock invert" "No effect,Clear" textline " " bitfld.long 0x58 4.--5. " ADCCLK_SHIFT ,ADC Analog Clock Phase Shift" "No shift,20ns,40ns,60ns" bitfld.long 0x58 0.--2. " ADCDIV ,ADC Analog Clock Divider" "6MHz,4MHz,3MHz,2MHz,3MHz,2MHz,1.5MHz,1MHz" line.long 0x5c "HW_AUDIOIN_ANACLKCTRL_TOG,Analog Clock Control Toggle Register" bitfld.long 0x5c 31. " CLKGATE ,Analog Clock Gate" "Not toggle,Toggle" bitfld.long 0x5c 10. " DITHER_OFF ,ADC Dither Disable" "Not toggle,Toggle" textline " " bitfld.long 0x5c 9. " SLOW_DITHER ,Slow Dither" "Not toggle,Toggle" bitfld.long 0x5c 8. " INVERT_ADCCLK ,ADC clock invert" "Not toggle,Toggle" textline " " bitfld.long 0x5c 4.--5. " ADCCLK_SHIFT ,ADC Analog Clock Phase Shift" "No shift,20ns,40ns,60ns" bitfld.long 0x5c 0.--2. " ADCDIV ,ADC Analog Clock Divider" "6MHz,4MHz,3MHz,2MHz,3MHz,2MHz,1.5MHz,1MHz" rgroup.long 0x80++0x03 line.long 0x00 "HW_AUDIOIN_DATA,AUDIOIN Read Data Register" hexmask.long.word 0x00 16.--31. 1. " HIGH ,Right Sample or Sample High Half-Word" hexmask.long.word 0x00 0.--15. 1. " LOW ,Left Sample or Sample Low Half-Word" group.long 0x84++0x0b line.long 0x00 "HW_AUDIOIN_DATA_SET,AUDIOIN Read Data Set Register" hexmask.long.word 0x00 16.--31. 1. " HIGH ,Right Sample or Sample High Half-Word" hexmask.long.word 0x00 0.--15. 1. " LOW ,Left Sample or Sample Low Half-Word" line.long 0x04 "HW_AUDIOIN_DATA_CLR,AUDIOIN Read Data Clear Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,Right Sample or Sample High Half-Word" hexmask.long.word 0x04 0.--15. 1. " LOW ,Left Sample or Sample Low Half-Word" line.long 0x08 "HW_AUDIOIN_DATA_TOG,AUDIOIN Read Data Toggle Register" hexmask.long.word 0x08 16.--31. 1. " HIGH ,Right Sample or Sample High Half-Word" hexmask.long.word 0x08 0.--15. 1. " LOW ,Left Sample or Sample Low Half-Word" width 0x0b tree.end tree "AUDIOOUT/DAC" base asd:0x80048000 width 29. group.long 0x00++0x0f line.long 0x00 "HW_AUDIOOUT_CTRL,AUDIOOUT Control Register" bitfld.long 0x00 31. " SFTRST ,AUDIOOUT Module Soft Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,AUDIOOUT Clock Gate Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. " LR_SWAP ,Left/Right Output Channel Swap Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " EDGE_SYNC ,Serial Output Clock Edge Sync Select" "Rising edge,Falling edge" bitfld.long 0x00 12. " INVERT_1BIT ,Invert Serial Audio Output Enable" "Normal,Inverted" textline " " bitfld.long 0x00 8.--9. " SS3D_EFFECT ,Virtual 3D Effect Enable" "Disabled,Low,Medium,High" bitfld.long 0x00 6. " WORD_LENGTH ,PCM Audio Bit Size Select" "32-bit,16-bit" textline " " bitfld.long 0x00 5. " DAC_ZERO_EN ,Never set DAC_ZERO_ENABLE!" "Disabled,?..." bitfld.long 0x00 4. " LOOPBACK ,AUDIOIN-to-AUDIOOUT Loopback Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FIFO_UNDERFLOW_IRQ ,FIFO Underflow Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 2. " FIFO_OVERFLOW_IRQ ,FIFO Overflow Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " FIFO_ERROR_IRQ_EN ,FIFO Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " RUN ,AUDIOOUT Enable" "Disabled,Enabled" line.long 0x04 "HW_AUDIOOUT_CTRL_SET,AUDIOOUT Control Set Register" bitfld.long 0x04 31. " SFTRST ,AUDIOOUT Module Soft Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,AUDIOOUT Clock Gate Enable" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14. " LR_SWAP ,Left/Right Output Channel Swap Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " EDGE_SYNC ,Serial Output Clock Edge Sync Select" "No effect,Set" bitfld.long 0x04 12. " INVERT_1BIT ,Invert Serial Audio Output Enable" "No effect,Set" textline " " bitfld.long 0x04 8.--9. " SS3D_EFFECT ,Virtual 3D Effect Enable" "Disabled,Low,Medium,High" bitfld.long 0x04 6. " WORD_LENGTH ,PCM Audio Bit Size Select" "No effect,Set" textline " " bitfld.long 0x04 5. " DAC_ZERO_EN ,Never set DAC_ZERO_ENABLE!" "No effect,Set" bitfld.long 0x04 4. " LOOPBACK ,AUDIOIN-to-AUDIOOUT Loopback Enable" "No effect,Set" textline " " bitfld.long 0x04 3. " FIFO_UNDERFLOW_IRQ ,FIFO Underflow Interrupt Status" "No effect,Set" bitfld.long 0x04 2. " FIFO_OVERFLOW_IRQ ,FIFO Overflow Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 1. " FIFO_ERROR_IRQ_EN ,FIFO Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 0. " RUN ,AUDIOOUT Enable" "No effect,Set" line.long 0x08 "HW_AUDIOOUT_CTRL_CLR,AUDIOOUT Control Clear Register" bitfld.long 0x08 31. " SFTRST ,AUDIOOUT Module Soft Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,AUDIOOUT Clock Gate Enable" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14. " LR_SWAP ,Left/Right Output Channel Swap Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " EDGE_SYNC ,Serial Output Clock Edge Sync Select" "No effect,Clear" bitfld.long 0x08 12. " INVERT_1BIT ,Invert Serial Audio Output Enable" "No effect,Clear" textline " " bitfld.long 0x08 8.--9. " SS3D_EFFECT ,Virtual 3D Effect Enable" "Disabled,Low,Medium,High" bitfld.long 0x08 6. " WORD_LENGTH ,PCM Audio Bit Size Select" "No effect,Clear" textline " " bitfld.long 0x08 5. " DAC_ZERO_EN ,Never set DAC_ZERO_ENABLE!" "No effect,Clear" bitfld.long 0x08 4. " LOOPBACK ,AUDIOIN-to-AUDIOOUT Loopback Enable" "No effect,Clear" textline " " bitfld.long 0x08 3. " FIFO_UNDERFLOW_IRQ ,FIFO Underflow Interrupt Status" "No effect,Clear" bitfld.long 0x08 2. " FIFO_OVERFLOW_IRQ ,FIFO Overflow Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 1. " FIFO_ERROR_IRQ_EN ,FIFO Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 0. " RUN ,AUDIOOUT Enable" "No effect,Clear" line.long 0x0c "HW_AUDIOOUT_CTRL_TOG,AUDIOOUT Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,AUDIOOUT Module Soft Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,AUDIOOUT Clock Gate Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14. " LR_SWAP ,Left/Right Output Channel Swap Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " EDGE_SYNC ,Serial Output Clock Edge Sync Select" "Not toggle,Toggle" bitfld.long 0x0c 12. " INVERT_1BIT ,Invert Serial Audio Output Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8.--9. " SS3D_EFFECT ,Virtual 3D Effect Enable" "Disabled,Low,Medium,High" bitfld.long 0x0c 6. " WORD_LENGTH ,PCM Audio Bit Size Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " DAC_ZERO_EN ,Never set DAC_ZERO_ENABLE!" "Not toggle,Toggle" bitfld.long 0x0c 4. " LOOPBACK ,AUDIOIN-to-AUDIOOUT Loopback Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " FIFO_UNDERFLOW_IRQ ,FIFO Underflow Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 2. " FIFO_OVERFLOW_IRQ ,FIFO Overflow Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " FIFO_ERROR_IRQ_EN ,FIFO Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,AUDIOOUT Enable" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_AUDIOOUT_STAT,AUDIOOUT Status Register" bitfld.long 0x00 31. " DAC_PRESENT ,AUDIOOUT Functionality Present" "Not present,Present" group.long 0x14++0x0b line.long 0x00 "HW_AUDIOOUT_STAT_SET,AUDIOOUT Status Set Register" bitfld.long 0x00 31. " DAC_PRESENT ,AUDIOOUT Functionality Present" "No effect,Set" line.long 0x04 "HW_AUDIOOUT_STAT_CLR,AUDIOOUT Status Clear Register" bitfld.long 0x04 31. " DAC_PRESENT ,AUDIOOUT Functionality Present" "No effect,Clear" line.long 0x08 "HW_AUDIOOUT_STAT_TOG,AUDIOOUT Status Toggle Register" bitfld.long 0x08 31. " DAC_PRESENT ,AUDIOOUT Functionality Present" "Not toggle,Toggle" group.long 0x20++0x3f line.long 0x00 "HW_AUDIOOUT_DACSRR,AUDIOOUT Sample Rate Register" bitfld.long 0x00 31. " OSR ,AUDIOOUT Oversample Rate" "6MHz,12MHz" bitfld.long 0x00 28.--31. " BASEMULT ,Base Sample Rate Multiplier" "Reserved,Single-rate,Double-rate,Reserved,Quad-rate,?..." textline " " bitfld.long 0x00 24.--26. " SRC_HOLD ,Sample Rate Conversion Hold Factor" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. " SRC_INT ,Sample Rate Conversion Integer Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x00 0.--12. 1. " SRC_FRAC ,Sample Rate Conversion Fraction Factor" line.long 0x04 "HW_AUDIOOUT_DACSRR_SET,AUDIOOUT Sample Rate Set Register" bitfld.long 0x04 31. " OSR ,AUDIOOUT Oversample Rate" "No effect,Set" bitfld.long 0x04 28.--31. " BASEMULT ,Base Sample Rate Multiplier" "Reserved,Single-rate,Double-rate,Reserved,Quad-rate,?..." textline " " bitfld.long 0x04 24.--26. " SRC_HOLD ,Sample Rate Conversion Hold Factor" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--20. " SRC_INT ,Sample Rate Conversion Integer Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x04 0.--12. 1. " SRC_FRAC ,Sample Rate Conversion Fraction Factor" line.long 0x08 "HW_AUDIOOUT_DACSRR_CLR,AUDIOOUT Sample Rate Clear Register" bitfld.long 0x08 31. " OSR ,AUDIOOUT Oversample Rate" "No effect,Clear" bitfld.long 0x08 28.--31. " BASEMULT ,Base Sample Rate Multiplier" "Reserved,Single-rate,Double-rate,Reserved,Quad-rate,?..." textline " " bitfld.long 0x08 24.--26. " SRC_HOLD ,Sample Rate Conversion Hold Factor" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--20. " SRC_INT ,Sample Rate Conversion Integer Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x08 0.--12. 1. " SRC_FRAC ,Sample Rate Conversion Fraction Factor" line.long 0x0c "HW_AUDIOOUT_DACSRR_TOG,AUDIOOUT Sample Rate Toggle Register" bitfld.long 0x0c 31. " OSR ,AUDIOOUT Oversample Rate" "Not toggle,Toggle" bitfld.long 0x0c 28.--31. " BASEMULT ,Base Sample Rate Multiplier" "Reserved,Single-rate,Double-rate,Reserved,Quad-rate,?..." textline " " bitfld.long 0x0c 24.--26. " SRC_HOLD ,Sample Rate Conversion Hold Factor" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--20. " SRC_INT ,Sample Rate Conversion Integer Factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0c 0.--12. 1. " SRC_FRAC ,Sample Rate Conversion Fraction Factor" line.long 0x10 "HW_AUDIOOUT_DACVOLUME,AUDIOOUT Volume Register" bitfld.long 0x10 28. " VOLUME_UPDATE_LEFT ,Left Channel Volume Update Pending" "Not pending,Pending" bitfld.long 0x10 25. " EN_ZCD ,Enable Zero Cross Detect" "Disabled,Enabled" textline " " bitfld.long 0x10 24. " MUTE_LEFT ,Mute Left Channel" "Unmute,Mute" hexmask.long.byte 0x10 16.--23. 1. " VOLUME_LEFT ,Left Channel Volume Setting" textline " " bitfld.long 0x10 12. " VOLUME_UPDATE_RIGHT ,Right Channel Volume Update Pending" "Not pending,Pending" bitfld.long 0x10 8. " MUTE_RIGHT ,Mute Right Channel" "Unmute,Mute" textline " " hexmask.long.byte 0x10 0.--7. 1. " VOLUME_RIGHT ,Right Channel Volume Setting" line.long 0x14 "HW_AUDIOOUT_DACVOLUME_SET,AUDIOOUT Volume Set Register" bitfld.long 0x14 28. " VOLUME_UPDATE_LEFT ,Left Channel Volume Update Pending" "No effect,Set" bitfld.long 0x14 25. " EN_ZCD ,Enable Zero Cross Detect" "No effect,Set" textline " " bitfld.long 0x14 24. " MUTE_LEFT ,Mute Left Channel" "No effect,Set" hexmask.long.byte 0x14 16.--23. 1. " VOLUME_LEFT ,Left Channel Volume Setting" textline " " bitfld.long 0x14 12. " VOLUME_UPDATE_RIGHT ,Right Channel Volume Update Pending" "No effect,Set" bitfld.long 0x14 8. " MUTE_RIGHT ,Mute Right Channel" "No effect,Set" textline " " hexmask.long.byte 0x14 0.--7. 1. " VOLUME_RIGHT ,Right Channel Volume Setting" line.long 0x18 "HW_AUDIOOUT_DACVOLUME_CLR,AUDIOOUT Volume Clear Register" bitfld.long 0x18 28. " VOLUME_UPDATE_LEFT ,Left Channel Volume Update Pending" "No effect,Clear" bitfld.long 0x18 25. " EN_ZCD ,Enable Zero Cross Detect" "No effect,Clear" textline " " bitfld.long 0x18 24. " MUTE_LEFT ,Mute Left Channel" "No effect,Clear" hexmask.long.byte 0x18 16.--23. 1. " VOLUME_LEFT ,Left Channel Volume Setting" textline " " bitfld.long 0x18 12. " VOLUME_UPDATE_RIGHT ,Right Channel Volume Update Pending" "No effect,Clear" bitfld.long 0x18 8. " MUTE_RIGHT ,Mute Right Channel" "No effect,Clear" textline " " hexmask.long.byte 0x18 0.--7. 1. " VOLUME_RIGHT ,Right Channel Volume Setting" line.long 0x1c "HW_AUDIOOUT_DACVOLUME_TOG,AUDIOOUT Volume Toggle Register" bitfld.long 0x1c 28. " VOLUME_UPDATE_LEFT ,Left Channel Volume Update Pending" "Not toggle,Toggle" bitfld.long 0x1c 25. " EN_ZCD ,Enable Zero Cross Detect" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MUTE_LEFT ,Mute Left Channel" "Not toggle,Toggle" hexmask.long.byte 0x1c 16.--23. 1. " VOLUME_LEFT ,Left Channel Volume Setting" textline " " bitfld.long 0x1c 12. " VOLUME_UPDATE_RIGHT ,Right Channel Volume Update Pending" "Not toggle,Toggle" bitfld.long 0x1c 8. " MUTE_RIGHT ,Mute Right Channel" "Not toggle,Toggle" textline " " hexmask.long.byte 0x1c 0.--7. 1. " VOLUME_RIGHT ,Right Channel Volume Setting" line.long 0x20 "HW_AUDIOOUT_DACDEBUG,AUDIOOUT Debug Register" bitfld.long 0x20 31. " EN_DACDMA ,AUDIOOUT Digital Path Test Enable" "Disabled,Enabled" bitfld.long 0x20 8.--11. " RAM_SS ,DIGFILT RAM Speed Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x20 5. " SET_INTERRUPT1_CLK_CROSS ,Interrupt[1] Sync Status" "No interrupt,Interrupt" bitfld.long 0x20 4. " SET_INTERRUPT0_CLK_CROSS ,Interrupt[0] Sync Status" "No interrupt,Interrupt" textline " " bitfld.long 0x20 3. " SET_INTERRUPT1_HAND_SHAKE ,Interrupt[1] Status" "No interrupt,Interrupt" bitfld.long 0x20 2. " SET_INTERRUPT0_HAND_SHAKE ,Interrupt[0] Status" "No interrupt,Interrupt" textline " " bitfld.long 0x20 1. " DMA_PREQ ,DMA Request Status" "Not reguested,Requested" bitfld.long 0x20 0. " FIFO_STATUS ,FIFO Status" "Full,Empty" line.long 0x24 "HW_AUDIOOUT_DACDEBUG_SET,AUDIOOUT Debug Set Register" bitfld.long 0x24 31. " EN_DACDMA ,AUDIOOUT Digital Path Test Enable" "No effect,Set" bitfld.long 0x24 8.--11. " RAM_SS ,DIGFILT RAM Speed Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x24 5. " SET_INTERRUPT1_CLK_CROSS ,Interrupt[1] Sync Status" "No effect,Set" bitfld.long 0x24 4. " SET_INTERRUPT0_CLK_CROSS ,Interrupt[0] Sync Status" "No effect,Set" textline " " bitfld.long 0x24 3. " SET_INTERRUPT1_HAND_SHAKE ,Interrupt[1] Status" "No effect,Set" bitfld.long 0x24 2. " SET_INTERRUPT0_HAND_SHAKE ,Interrupt[0] Status" "No effect,Set" textline " " bitfld.long 0x24 1. " DMA_PREQ ,DMA Request Status" "No effect,Set" bitfld.long 0x24 0. " FIFO_STATUS ,FIFO Status" "No effect,Set" line.long 0x28 "HW_AUDIOOUT_DACDEBUG_CLR,AUDIOOUT Debug Clear Register" bitfld.long 0x28 31. " EN_DACDMA ,AUDIOOUT Digital Path Test Enable" "No effect,Clear" bitfld.long 0x28 8.--11. " RAM_SS ,DIGFILT RAM Speed Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x28 5. " SET_INTERRUPT1_CLK_CROSS ,Interrupt[1] Sync Status" "No effect,Clear" bitfld.long 0x28 4. " SET_INTERRUPT0_CLK_CROSS ,Interrupt[0] Sync Status" "No effect,Clear" textline " " bitfld.long 0x28 3. " SET_INTERRUPT1_HAND_SHAKE ,Interrupt[1] Status" "No effect,Clear" bitfld.long 0x28 2. " SET_INTERRUPT0_HAND_SHAKE ,Interrupt[0] Status" "No effect,Clear" textline " " bitfld.long 0x28 1. " DMA_PREQ ,DMA Request Status" "No effect,Clear" bitfld.long 0x28 0. " FIFO_STATUS ,FIFO Status" "No effect,Clear" line.long 0x2c "HW_AUDIOOUT_DACDEBUG_TOG,AUDIOOUT Debug Toggle Register" bitfld.long 0x2c 31. " EN_DACDMA ,AUDIOOUT Digital Path Test Enable" "Not toggle,Toggle" bitfld.long 0x2c 8.--11. " RAM_SS ,DIGFILT RAM Speed Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x2c 5. " SET_INTERRUPT1_CLK_CROSS ,Interrupt[1] Sync Status" "Not toggle,Toggle" bitfld.long 0x2c 4. " SET_INTERRUPT0_CLK_CROSS ,Interrupt[0] Sync Status" "Not toggle,Toggle" textline " " bitfld.long 0x2c 3. " SET_INTERRUPT1_HAND_SHAKE ,Interrupt[1] Status" "Not toggle,Toggle" bitfld.long 0x2c 2. " SET_INTERRUPT0_HAND_SHAKE ,Interrupt[0] Status" "Not toggle,Toggle" textline " " bitfld.long 0x2c 1. " DMA_PREQ ,DMA Request Status" "Not toggle,Toggle" bitfld.long 0x2c 0. " FIFO_STATUS ,FIFO Status" "Not toggle,Toggle" line.long 0x30 "HW_AUDIOOUT_HPVOL,Headphone Volume and Select Control Register" bitfld.long 0x30 28. " VOLUME_UPDATE_PENDING ,Volume Update Pending" "Not pending,Pending" bitfld.long 0x30 25. " EN_MSTR_ZCD ,Enable Zero Cross Detect for Headphone Amplifier" "Disabled,Enabled" textline " " bitfld.long 0x30 16. " SELECT ,Input Signal Select" "DAC,Line 1" hexmask.long.byte 0x30 8.--14. 1. " VOL_LEFT ,Left Headphone Volume Control" textline " " hexmask.long.byte 0x30 0.--6. 1. " VOL_RIGHT ,Right Headphone Volume Control" line.long 0x34 "HW_AUDIOOUT_HPVOL_SET,Headphone Volume and Select Control Set Register" bitfld.long 0x34 28. " VOLUME_UPDATE_PENDING ,Volume Update Pending" "No effect,Set" bitfld.long 0x34 25. " EN_MSTR_ZCD ,Enable Zero Cross Detect for Headphone Amplifier" "No effect,Set" textline " " bitfld.long 0x34 16. " SELECT ,Input Signal Select" "No effect,Set" hexmask.long.byte 0x34 8.--14. 1. " VOL_LEFT ,Left Headphone Volume Control" textline " " hexmask.long.byte 0x34 0.--6. 1. " VOL_RIGHT ,Right Headphone Volume Control" line.long 0x38 "HW_AUDIOOUT_HPVOL_CLR,Headphone Volume and Select Control Clear Register" bitfld.long 0x38 28. " VOLUME_UPDATE_PENDING ,Volume Update Pending" "No effect,Clear" bitfld.long 0x38 25. " EN_MSTR_ZCD ,Enable Zero Cross Detect for Headphone Amplifier" "No effect,Clear" textline " " bitfld.long 0x38 16. " SELECT ,Input Signal Select" "No effect,Clear" hexmask.long.byte 0x38 8.--14. 1. " VOL_LEFT ,Left Headphone Volume Control" textline " " hexmask.long.byte 0x38 0.--6. 1. " VOL_RIGHT ,Right Headphone Volume Control" line.long 0x3c "HW_AUDIOOUT_HPVOL_TOG,Headphone Volume and Select Control Toggle Register" bitfld.long 0x3c 28. " VOLUME_UPDATE_PENDING ,Volume Update Pending" "Not toggle,Toggle" bitfld.long 0x3c 25. " EN_MSTR_ZCD ,Enable Zero Cross Detect for Headphone Amplifier" "Not toggle,Toggle" textline " " bitfld.long 0x3c 16. " SELECT ,Input Signal Select" "Not toggle,Toggle" hexmask.long.byte 0x3c 8.--14. 1. " VOL_LEFT ,Left Headphone Volume Control" textline " " hexmask.long.byte 0x3c 0.--6. 1. " VOL_RIGHT ,Right Headphone Volume Control" group.long 0x70++0x0f line.long 0x00 "HW_AUDIOOUT_PWRDN,Audio Power-Down Control Register" bitfld.long 0x00 24. " SPEAKER ,Speaker Power-Down" "Powered up,Powered down" bitfld.long 0x00 20. " SELFBIAS ,This bit currently does not control any logic" "0,1" textline " " bitfld.long 0x00 16. " RIGHT_ADC ,Right ADC Power Down" "Powered up,Powered down" bitfld.long 0x00 12. " DAC ,Power Down DAC Analog Circuitry" "Powered up,Powered down" textline " " bitfld.long 0x00 8. " ADC ,Power Down ADC and Input Mux Circuitry" "Powered up,Powered down" bitfld.long 0x00 4. " CAPLESS ,Power Down Headphone Common Amplifier" "Powered up,Powered down" textline " " bitfld.long 0x00 0. " HEADPHONE ,Master (Headphone) Power Down" "Powered up,Powered down" line.long 0x04 "HW_AUDIOOUT_PWRDN_SET,Audio Power-Down Control Set Register" bitfld.long 0x04 24. " SPEAKER ,Speaker Power-Down" "No effect,Set" bitfld.long 0x04 20. " SELFBIAS ,This bit currently does not control any logic" "No effect,Set" textline " " bitfld.long 0x04 16. " RIGHT_ADC ,Right ADC Power Down" "No effect,Set" bitfld.long 0x04 12. " DAC ,Power Down DAC Analog Circuitry" "No effect,Set" textline " " bitfld.long 0x04 8. " ADC ,Power Down ADC and Input Mux Circuitry" "No effect,Set" bitfld.long 0x04 4. " CAPLESS ,Power Down Headphone Common Amplifier" "No effect,Set" textline " " bitfld.long 0x04 0. " HEADPHONE ,Master (Headphone) Power Down" "No effect,Set" line.long 0x08 "HW_AUDIOOUT_PWRDN_CLR,Audio Power-Down Control Clear Register" bitfld.long 0x08 24. " SPEAKER ,Speaker Power-Down" "No effect,Clear" bitfld.long 0x08 20. " SELFBIAS ,This bit currently does not control any logic" "No effect,Clear" textline " " bitfld.long 0x08 16. " RIGHT_ADC ,Right ADC Power Down" "No effect,Clear" bitfld.long 0x08 12. " DAC ,Power Down DAC Analog Circuitry" "No effect,Clear" textline " " bitfld.long 0x08 8. " ADC ,Power Down ADC and Input Mux Circuitry" "No effect,Clear" bitfld.long 0x08 4. " CAPLESS ,Power Down Headphone Common Amplifier" "No effect,Clear" textline " " bitfld.long 0x08 0. " HEADPHONE ,Master (Headphone) Power Down" "No effect,Clear" line.long 0x0c "HW_AUDIOOUT_PWRDN_TOG,Audio Power-Down Control Toggle Register" bitfld.long 0x0c 24. " SPEAKER ,Speaker Power-Down" "Not toggle,Toggle" bitfld.long 0x0c 20. " SELFBIAS ,This bit currently does not control any logic" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " RIGHT_ADC ,Right ADC Power Down" "Not toggle,Toggle" bitfld.long 0x0c 12. " DAC ,Power Down DAC Analog Circuitry" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " ADC ,Power Down ADC and Input Mux Circuitry" "Not toggle,Toggle" bitfld.long 0x0c 4. " CAPLESS ,Power Down Headphone Common Amplifier" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " HEADPHONE ,Master (Headphone) Power Down" "Not toggle,Toggle" if (((d.l(asd:(0x80048000+0x80)))&0x2000000)==0x2000000) ;RAISE_REF=1; group.long 0x80++0x0f line.long 0x00 "HW_AUDIOOUT_REFCTRL,AUDIOOUT Reference Control Register" bitfld.long 0x00 26. " FASTSETTLING ,Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time" "Not increased,Increased" bitfld.long 0x00 25. " RAISE_REF ,RAISE_REF" "0,1" textline " " bitfld.long 0x00 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "Self-bias,Bandgap-based bias" bitfld.long 0x00 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x00 19. " LOW_PWR ,Lowers power (100 uA) in the bandgap amplifier" "Not lower,Lower" bitfld.long 0x00 18. " LW_REF ,This bit currently does not control any logic" "0,1" textline " " bitfld.long 0x00 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" bitfld.long 0x00 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "0,1" textline " " bitfld.long 0x00 13. " ADJ_ADC ,ADC Reference Voltage Adjust" "No effect,Bias current drop by 20%" bitfld.long 0x00 12. " ADJ_VAG ,Adjust VAG" "VDD/2,VAGVAL[7:4]" textline " " bitfld.long 0x00 8.--11. " ADC_REFVAL ,ADC Reference Value" "1.75*VAG,1.85*VAG,1.97*VAG,?..." bitfld.long 0x00 7. " VAG_VAL1 ,DAC reference buffer is bypassed which can improve SNR performance" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 4.--6. " VAG_VAL0 ,VAG Reference Value" "0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1.0V" bitfld.long 0x00 0.--2. " DAC_ADJ ,Adjusts the reference current (signal swing) in the DAC" "Nominal,+0.25dB,+0.5dB,+0.75dB,-0.25dB,-0.5dB,-0.75dB,-6.0dB" line.long 0x04 "HW_AUDIOOUT_REFCTRL_SET,AUDIOOUT Reference Control Set Register" bitfld.long 0x04 26. " FASTSETTLING ,Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time" "No effect,Set" bitfld.long 0x04 25. " RAISE_REF ,RAISE_REF" "No effect,Set" textline " " bitfld.long 0x04 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "No effect,Set" bitfld.long 0x04 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x04 19. " LOW_PWR ,Lowers power (100 uA) in the bandgap amplifier" "No effect,Set" bitfld.long 0x04 18. " LW_REF ,This bit currently does not control any logic" "No effect,Set" textline " " bitfld.long 0x04 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" bitfld.long 0x04 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "No effect,Set" textline " " bitfld.long 0x04 13. " ADJ_ADC ,ADC Reference Voltage Adjust" "No effect,Set" bitfld.long 0x04 12. " ADJ_VAG ,Adjust VAG" "No effect,Set" textline " " bitfld.long 0x04 8.--11. " ADC_REFVAL ,ADC Reference Value" "1.75*VAG,1.85*VAG,1.97*VAG,?..." bitfld.long 0x04 7. " VAG_VAL1 ,DAC reference buffer is bypassed which can improve SNR performance" "No effect,Set" textline " " bitfld.long 0x04 4.--6. " VAG_VAL0 ,VAG Reference Value" "0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1.0V" bitfld.long 0x04 0.--2. " DAC_ADJ ,Adjusts the reference current (signal swing) in the DAC" "Nominal,+0.25dB,+0.5dB,+0.75dB,-0.25dB,-0.5dB,-0.75dB,-6.0dB" line.long 0x08 "HW_AUDIOOUT_REFCTRL_CLR,AUDIOOUT Reference Control Clear Register" bitfld.long 0x08 26. " FASTSETTLING ,Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time" "No effect,Clear" bitfld.long 0x08 25. " RAISE_REF ,RAISE_REF" "No effect,Clear" textline " " bitfld.long 0x08 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "No effect,Clear" bitfld.long 0x08 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x08 19. " LOW_PWR ,Lowers power (100 uA) in the bandgap amplifier" "No effect,Clear" bitfld.long 0x08 18. " LW_REF ,This bit currently does not control any logic" "No effect,Clear" textline " " bitfld.long 0x08 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" bitfld.long 0x08 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "No effect,Clear" textline " " bitfld.long 0x08 13. " ADJ_ADC ,ADC Reference Voltage Adjust" "No effect,Clear" bitfld.long 0x08 12. " ADJ_VAG ,Adjust VAG" "No effect,Clear" textline " " bitfld.long 0x08 8.--11. " ADC_REFVAL ,ADC Reference Value" "1.75*VAG,1.85*VAG,1.97*VAG,?..." bitfld.long 0x08 7. " VAG_VAL1 ,DAC reference buffer is bypassed which can improve SNR performance" "No effect,Clear" textline " " bitfld.long 0x08 4.--6. " VAG_VAL0 ,VAG Reference Value" "0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1.0V" bitfld.long 0x08 0.--2. " DAC_ADJ ,Adjusts the reference current (signal swing) in the DAC" "Nominal,+0.25dB,+0.5dB,+0.75dB,-0.25dB,-0.5dB,-0.75dB,-6.0dB" line.long 0x0c "HW_AUDIOOUT_REFCTRL_TOG,AUDIOOUT Reference Control Toggle Register" bitfld.long 0x0c 26. " FASTSETTLING ,Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time" "Not toggle,Toggle" bitfld.long 0x0c 25. " RAISE_REF ,RAISE_REF" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "Not toggle,Toggle" bitfld.long 0x0c 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x0c 19. " LOW_PWR ,Lowers power (100 uA) in the bandgap amplifier" "Not toggle,Toggle" bitfld.long 0x0c 18. " LW_REF ,This bit currently does not control any logic" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" bitfld.long 0x0c 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " ADJ_ADC ,ADC Reference Voltage Adjust" "Not toggle,Toggle" bitfld.long 0x0c 12. " ADJ_VAG ,Adjust VAG" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8.--11. " ADC_REFVAL ,ADC Reference Value" "1.75*VAG,1.85*VAG,1.97*VAG,?..." bitfld.long 0x0c 7. " VAG_VAL1 ,DAC reference buffer is bypassed which can improve SNR performance" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--6. " VAG_VAL0 ,VAG Reference Value" "0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1.0V" bitfld.long 0x0c 0.--2. " DAC_ADJ ,Adjusts the reference current (signal swing) in the DAC" "Nominal,+0.25dB,+0.5dB,+0.75dB,-0.25dB,-0.5dB,-0.75dB,-6.0dB" else ;RAISE_REF=0; group.long 0x80++0x0f line.long 0x00 "HW_AUDIOOUT_REFCTRL,AUDIOOUT Reference Control Register" bitfld.long 0x00 26. " FASTSETTLING ,Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time" "Not increased,Increased" bitfld.long 0x00 25. " RAISE_REF ,RAISE_REF" "0,1" textline " " bitfld.long 0x00 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "Self-bias,Bandgap-based bias" bitfld.long 0x00 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x00 19. " LOW_PWR ,Lowers power (100 uA) in the bandgap amplifier" "Not lower,Lower" bitfld.long 0x00 18. " LW_REF ,This bit currently does not control any logic" "0,1" textline " " bitfld.long 0x00 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" bitfld.long 0x00 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "0,1" textline " " bitfld.long 0x00 13. " ADJ_ADC ,ADC Reference Voltage Adjust" "No effect,Bias current drop by 20%" bitfld.long 0x00 12. " ADJ_VAG ,Adjust VAG" "VDD/2,VAGVAL[7:4]" textline " " bitfld.long 0x00 8.--11. " ADC_REFVAL ,ADC Reference Value" "1.75*VAG,1.85*VAG,1.97*VAG,?..." bitfld.long 0x00 7. " VAG_VAL1 ,DAC reference buffer is bypassed which can improve SNR performance" "Not bypassed,Bypassed" textline " " bitfld.long 0x00 4.--6. " VAG_VAL0 ,VAG Reference Value" "0.722V,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0.875V" bitfld.long 0x00 0.--2. " DAC_ADJ ,Adjusts the reference current (signal swing) in the DAC" "Nominal,+0.25dB,+0.5dB,+0.75dB,-0.25dB,-0.5dB,-0.75dB,-6.0dB" line.long 0x04 "HW_AUDIOOUT_REFCTRL_SET,AUDIOOUT Reference Control Set Register" bitfld.long 0x04 26. " FASTSETTLING ,Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time" "No effect,Set" bitfld.long 0x04 25. " RAISE_REF ,RAISE_REF" "No effect,Set" textline " " bitfld.long 0x04 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "No effect,Set" bitfld.long 0x04 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x04 19. " LOW_PWR ,Lowers power (100 uA) in the bandgap amplifier" "No effect,Set" bitfld.long 0x04 18. " LW_REF ,This bit currently does not control any logic" "No effect,Set" textline " " bitfld.long 0x04 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" bitfld.long 0x04 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "No effect,Set" textline " " bitfld.long 0x04 13. " ADJ_ADC ,ADC Reference Voltage Adjust" "No effect,Set" bitfld.long 0x04 12. " ADJ_VAG ,Adjust VAG" "No effect,Set" textline " " bitfld.long 0x04 8.--11. " ADC_REFVAL ,ADC Reference Value" "1.75*VAG,1.85*VAG,1.97*VAG,?..." bitfld.long 0x04 7. " VAG_VAL1 ,DAC reference buffer is bypassed which can improve SNR performance" "No effect,Set" textline " " bitfld.long 0x04 4.--6. " VAG_VAL0 ,VAG Reference Value" "0.722V,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0.875V" bitfld.long 0x04 0.--2. " DAC_ADJ ,Adjusts the reference current (signal swing) in the DAC" "Nominal,+0.25dB,+0.5dB,+0.75dB,-0.25dB,-0.5dB,-0.75dB,-6.0dB" line.long 0x08 "HW_AUDIOOUT_REFCTRL_CLR,AUDIOOUT Reference Control Clear Register" bitfld.long 0x08 26. " FASTSETTLING ,Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time" "No effect,Clear" bitfld.long 0x08 25. " RAISE_REF ,RAISE_REF" "No effect,Clear" textline " " bitfld.long 0x08 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "No effect,Clear" bitfld.long 0x08 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x08 19. " LOW_PWR ,Lowers power (100 uA) in the bandgap amplifier" "No effect,Clear" bitfld.long 0x08 18. " LW_REF ,This bit currently does not control any logic" "No effect,Clear" textline " " bitfld.long 0x08 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" bitfld.long 0x08 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "No effect,Clear" textline " " bitfld.long 0x08 13. " ADJ_ADC ,ADC Reference Voltage Adjust" "No effect,Clear" bitfld.long 0x08 12. " ADJ_VAG ,Adjust VAG" "No effect,Clear" textline " " bitfld.long 0x08 8.--11. " ADC_REFVAL ,ADC Reference Value" "1.75*VAG,1.85*VAG,1.97*VAG,?..." bitfld.long 0x08 7. " VAG_VAL1 ,DAC reference buffer is bypassed which can improve SNR performance" "No effect,Clear" textline " " bitfld.long 0x08 4.--6. " VAG_VAL0 ,VAG Reference Value" "0.722V,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0.875V" bitfld.long 0x08 0.--2. " DAC_ADJ ,Adjusts the reference current (signal swing) in the DAC" "Nominal,+0.25dB,+0.5dB,+0.75dB,-0.25dB,-0.5dB,-0.75dB,-6.0dB" line.long 0x0c "HW_AUDIOOUT_REFCTRL_TOG,AUDIOOUT Reference Control Toggle Register" bitfld.long 0x0c 26. " FASTSETTLING ,Increases the output current for vag buffer by 2X to 20uA to improve the startup settling time" "Not toggle,Toggle" bitfld.long 0x0c 25. " RAISE_REF ,RAISE_REF" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "Not toggle,Toggle" bitfld.long 0x0c 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x0c 19. " LOW_PWR ,Lowers power (100 uA) in the bandgap amplifier" "Not toggle,Toggle" bitfld.long 0x0c 18. " LW_REF ,This bit currently does not control any logic" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" bitfld.long 0x0c 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " ADJ_ADC ,ADC Reference Voltage Adjust" "Not toggle,Toggle" bitfld.long 0x0c 12. " ADJ_VAG ,Adjust VAG" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8.--11. " ADC_REFVAL ,ADC Reference Value" "1.75*VAG,1.85*VAG,1.97*VAG,?..." bitfld.long 0x0c 7. " VAG_VAL1 ,DAC reference buffer is bypassed which can improve SNR performance" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--6. " VAG_VAL0 ,VAG Reference Value" "0.722V,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,0.875V" bitfld.long 0x0c 0.--2. " DAC_ADJ ,Adjusts the reference current (signal swing) in the DAC" "Nominal,+0.25dB,+0.5dB,+0.75dB,-0.25dB,-0.5dB,-0.75dB,-6.0dB" endif group.long 0x90++0x1f line.long 0x00 "HW_AUDIOOUT_ANACTRL,Miscellaneous Audio Controls Register" bitfld.long 0x00 28. " SHORT_CM_STS ,Status of common mode amplifier short detection" "No short,Short" bitfld.long 0x00 24. " SHORT_LR_STS ,Status of headphone amplifier short detection" "No short,Short" textline " " bitfld.long 0x00 20.--21. " SHORTMODE_CM ,Headphone Common Mode Amplifier Short Control Mode" "Reset analog latch,Latch short signal,?..." bitfld.long 0x00 17.--18. " SHORTMODE_LR ,Headphone Left and Right Channel Short Control mode" "Reset analog latch,Latch short signal,?..." textline " " bitfld.long 0x00 12.--14. " SHORT_LVLADJL ,Adjust the left headphone current short detect trip point" "Nominal,-25%,-50%,-75%,+25%,+50%,+75%,+100%" bitfld.long 0x00 8.--10. " SHORT_LVLADJR ,Adjust the right headphone current short detect trip point" "Nominal,-25%,-50%,-75%,+25%,+50%,+75%,+100%" textline " " bitfld.long 0x00 5. " HP_HOLD_GND ,Hold Headphone Output to Ground" "Not hold,Hold" bitfld.long 0x00 4. " HP_CLASSAB ,Class mode" "Class A,Class AB" line.long 0x04 "HW_AUDIOOUT_ANACTRL_SET,Miscellaneous Audio Controls Set Register" bitfld.long 0x04 28. " SHORT_CM_STS ,Status of common mode amplifier short detection" "No effect,Set" bitfld.long 0x04 24. " SHORT_LR_STS ,Status of headphone amplifier short detection" "No effect,Set" textline " " bitfld.long 0x04 20.--21. " SHORTMODE_CM ,Headphone Common Mode Amplifier Short Control Mode" "Reset analog latch,Latch short signal,?..." bitfld.long 0x04 17.--18. " SHORTMODE_LR ,Headphone Left and Right Channel Short Control mode" "Reset analog latch,Latch short signal,?..." textline " " bitfld.long 0x04 12.--14. " SHORT_LVLADJL ,Adjust the left headphone current short detect trip point" "Nominal,-25%,-50%,-75%,+25%,+50%,+75%,+100%" bitfld.long 0x04 8.--10. " SHORT_LVLADJR ,Adjust the right headphone current short detect trip point" "Nominal,-25%,-50%,-75%,+25%,+50%,+75%,+100%" textline " " bitfld.long 0x04 5. " HP_HOLD_GND ,Hold Headphone Output to Ground" "No effect,Set" bitfld.long 0x04 4. " HP_CLASSAB ,Class mode" "No effect,Set" line.long 0x08 "HW_AUDIOOUT_ANACTRL_CLR,Miscellaneous Audio Controls Clear Register" bitfld.long 0x08 28. " SHORT_CM_STS ,Status of common mode amplifier short detection" "No effect,Clear" bitfld.long 0x08 24. " SHORT_LR_STS ,Status of headphone amplifier short detection" "No effect,Clear" textline " " bitfld.long 0x08 20.--21. " SHORTMODE_CM ,Headphone Common Mode Amplifier Short Control Mode" "Reset analog latch,Latch short signal,?..." bitfld.long 0x08 17.--18. " SHORTMODE_LR ,Headphone Left and Right Channel Short Control mode" "Reset analog latch,Latch short signal,?..." textline " " bitfld.long 0x08 12.--14. " SHORT_LVLADJL ,Adjust the left headphone current short detect trip point" "Nominal,-25%,-50%,-75%,+25%,+50%,+75%,+100%" bitfld.long 0x08 8.--10. " SHORT_LVLADJR ,Adjust the right headphone current short detect trip point" "Nominal,-25%,-50%,-75%,+25%,+50%,+75%,+100%" textline " " bitfld.long 0x08 5. " HP_HOLD_GND ,Hold Headphone Output to Ground" "No effect,Clear" bitfld.long 0x08 4. " HP_CLASSAB ,Class mode" "No effect,Clear" line.long 0x0c "HW_AUDIOOUT_ANACTRL_TOG,Miscellaneous Audio Controls Toggle Register" bitfld.long 0x0c 28. " SHORT_CM_STS ,Status of common mode amplifier short detection" "Not toggle,Toggle" bitfld.long 0x0c 24. " SHORT_LR_STS ,Status of headphone amplifier short detection" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20.--21. " SHORTMODE_CM ,Headphone Common Mode Amplifier Short Control Mode" "Reset analog latch,Latch short signal,?..." bitfld.long 0x0c 17.--18. " SHORTMODE_LR ,Headphone Left and Right Channel Short Control mode" "Reset analog latch,Latch short signal,?..." textline " " bitfld.long 0x0c 12.--14. " SHORT_LVLADJL ,Adjust the left headphone current short detect trip point" "Nominal,-25%,-50%,-75%,+25%,+50%,+75%,+100%" bitfld.long 0x0c 8.--10. " SHORT_LVLADJR ,Adjust the right headphone current short detect trip point" "Nominal,-25%,-50%,-75%,+25%,+50%,+75%,+100%" textline " " bitfld.long 0x0c 5. " HP_HOLD_GND ,Hold Headphone Output to Ground" "Not toggle,Toggle" bitfld.long 0x0c 4. " HP_CLASSAB ,Class mode" "Not toggle,Toggle" line.long 0x10 "HW_AUDIOOUT_TEST,Miscellaneous Test Audio Controls Register" bitfld.long 0x10 26. " TM_ADCIN_TOHP ,Testmode to pipe ADC Mux Out (ADC In) to Headphone Output pins" "Normal,Test" bitfld.long 0x10 25. " TM_LOOP ,Testmode to connect headphone out left to the microphone input to the ADC, and speaker to the ADC" "Normal,Test" textline " " bitfld.long 0x10 24. " TM_HPCOMMON ,Uses headphone common VAG, instead of vaggate in ADC Mux" "Normal,Test" bitfld.long 0x10 22.--23. " HP_I1_ADJ ,Adjusts bias current in first stage of headphone amplifier" "Nominal,-50%,+100%,+50%" textline " " bitfld.long 0x10 20.--21. " HP_IALL_ADJ ,Adjusts all bias current in headphone amplifier" "Nominal,-50%,+50%,-40%" bitfld.long 0x10 13. " VAG_CLASSA ,Disable ClassAB mode in VAG Amp" "No,Yes" textline " " bitfld.long 0x10 12. " VAG_DOUBLE_I ,Double ClassA current in VAG amplifier (+240uA)" "Not double,Double" bitfld.long 0x10 3. " ADCTODAC_LOOP ,Loop the 1-bit SDM ADC data in to the 1-bit SDM DAC data out for test" "Normal,Loop" textline " " bitfld.long 0x10 2. " DAC_CLASSA ,Disable ClassAB mode in DAC" "No,Yes" bitfld.long 0x10 1. " DAC_DOUBLE_I ,Double ClassA current in DAC amplifier (+360 uA in each DAC)" "Not double,Double" textline " " bitfld.long 0x10 0. " DAC_DIS_RTZ ,Disable DAC RTZ mode" "No,Yes" line.long 0x14 "HW_AUDIOOUT_TEST_SET,Miscellaneous Test Audio Controls Set Register" bitfld.long 0x14 26. " TM_ADCIN_TOHP ,Testmode to pipe ADC Mux Out (ADC In) to Headphone Output pins" "No effect,Set" bitfld.long 0x14 25. " TM_LOOP ,Testmode to connect headphone out left to the microphone input to the ADC, and speaker to the ADC" "No effect,Set" textline " " bitfld.long 0x14 24. " TM_HPCOMMON ,Uses headphone common VAG, instead of vaggate in ADC Mux" "No effect,Set" bitfld.long 0x14 22.--23. " HP_I1_ADJ ,Adjusts bias current in first stage of headphone amplifier" "Nominal,-50%,+100%,+50%" textline " " bitfld.long 0x14 20.--21. " HP_IALL_ADJ ,Adjusts all bias current in headphone amplifier" "Nominal,-50%,+50%,-40%" bitfld.long 0x14 13. " VAG_CLASSA ,Disable ClassAB mode in VAG Amp" "No effect,Set" textline " " bitfld.long 0x14 12. " VAG_DOUBLE_I ,Double ClassA current in VAG amplifier (+240uA)" "No effect,Set" bitfld.long 0x14 3. " ADCTODAC_LOOP ,Loop the 1-bit SDM ADC data in to the 1-bit SDM DAC data out for test" "No effect,Set" textline " " bitfld.long 0x14 2. " DAC_CLASSA ,Disable ClassAB mode in DAC" "No effect,Set" bitfld.long 0x14 1. " DAC_DOUBLE_I ,Double ClassA current in DAC amplifier (+360 uA in each DAC)" "No effect,Set" textline " " bitfld.long 0x14 0. " DAC_DIS_RTZ ,Disable DAC RTZ mode" "No effect,Set" line.long 0x18 "HW_AUDIOOUT_TEST_CLR,Miscellaneous Test Audio Controls Clear Register" bitfld.long 0x18 26. " TM_ADCIN_TOHP ,Testmode to pipe ADC Mux Out (ADC In) to Headphone Output pins" "No effect,Clear" bitfld.long 0x18 25. " TM_LOOP ,Testmode to connect headphone out left to the microphone input to the ADC, and speaker to the ADC" "No effect,Clear" textline " " bitfld.long 0x18 24. " TM_HPCOMMON ,Uses headphone common VAG, instead of vaggate in ADC Mux" "No effect,Clear" bitfld.long 0x18 22.--23. " HP_I1_ADJ ,Adjusts bias current in first stage of headphone amplifier" "Nominal,-50%,+100%,+50%" textline " " bitfld.long 0x18 20.--21. " HP_IALL_ADJ ,Adjusts all bias current in headphone amplifier" "Nominal,-50%,+50%,-40%" bitfld.long 0x18 13. " VAG_CLASSA ,Disable ClassAB mode in VAG Amp" "No effect,Clear" textline " " bitfld.long 0x18 12. " VAG_DOUBLE_I ,Double ClassA current in VAG amplifier (+240uA)" "No effect,Clear" bitfld.long 0x18 3. " ADCTODAC_LOOP ,Loop the 1-bit SDM ADC data in to the 1-bit SDM DAC data out for test" "No effect,Clear" textline " " bitfld.long 0x18 2. " DAC_CLASSA ,Disable ClassAB mode in DAC" "No effect,Clear" bitfld.long 0x18 1. " DAC_DOUBLE_I ,Double ClassA current in DAC amplifier (+360 uA in each DAC)" "No effect,Clear" textline " " bitfld.long 0x18 0. " DAC_DIS_RTZ ,Disable DAC RTZ mode" "No effect,Clear" line.long 0x1c "HW_AUDIOOUT_TEST_TOG,Miscellaneous Test Audio Controls Toggle Register" bitfld.long 0x1c 26. " TM_ADCIN_TOHP ,Testmode to pipe ADC Mux Out (ADC In) to Headphone Output pins" "Not toggle,Toggle" bitfld.long 0x1c 25. " TM_LOOP ,Testmode to connect headphone out left to the microphone input to the ADC, and speaker to the ADC" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " TM_HPCOMMON ,Uses headphone common VAG, instead of vaggate in ADC Mux" "Not toggle,Toggle" bitfld.long 0x1c 22.--23. " HP_I1_ADJ ,Adjusts bias current in first stage of headphone amplifier" "Nominal,-50%,+100%,+50%" textline " " bitfld.long 0x1c 20.--21. " HP_IALL_ADJ ,Adjusts all bias current in headphone amplifier" "Nominal,-50%,+50%,-40%" bitfld.long 0x1c 13. " VAG_CLASSA ,Disable ClassAB mode in VAG Amp" "Not toggle,Toggle" textline " " bitfld.long 0x1c 12. " VAG_DOUBLE_I ,Double ClassA current in VAG amplifier (+240uA)" "Not toggle,Toggle" bitfld.long 0x1c 3. " ADCTODAC_LOOP ,Loop the 1-bit SDM ADC data in to the 1-bit SDM DAC data out for test" "Not toggle,Toggle" textline " " bitfld.long 0x1c 2. " DAC_CLASSA ,Disable ClassAB mode in DAC" "Not toggle,Toggle" bitfld.long 0x1c 1. " DAC_DOUBLE_I ,Double ClassA current in DAC amplifier (+360 uA in each DAC)" "Not toggle,Toggle" textline " " bitfld.long 0x1c 0. " DAC_DIS_RTZ ,Disable DAC RTZ mode" "Not toggle,Toggle" rgroup.long 0xb0++0x03 line.long 0x00 "HW_AUDIOOUT_BISTCTRL,BIST Control and Status Register" bitfld.long 0x00 3. " FAIL ,BIST has failed" "Not failed,Failed" bitfld.long 0x00 2. " PASS ,BIST has passed" "Not passed,Passed" textline " " bitfld.long 0x00 1. " DONE ,BIST has completed" "Not completed,Completed" bitfld.long 0x00 0. " START ,Initiate BIST of internal memory" "No effect,Start" group.long 0xb4++0x0b line.long 0x00 "HW_AUDIOOUT_BISTCTRL_SET,BIST Control and Status Set Register" bitfld.long 0x00 3. " FAIL ,BIST has failed" "No effect,Set" bitfld.long 0x00 2. " PASS ,BIST has passed" "No effect,Set" textline " " bitfld.long 0x00 1. " DONE ,BIST has completed" "No effect,Set" bitfld.long 0x00 0. " START ,Initiate BIST of internal memory" "No effect,Set" line.long 0x04 "HW_AUDIOOUT_BISTCTRL_CLR,BIST Control and Status Clear Register" bitfld.long 0x04 3. " FAIL ,BIST has failed" "No effect,Clear" bitfld.long 0x04 2. " PASS ,BIST has passed" "No effect,Clear" textline " " bitfld.long 0x04 1. " DONE ,BIST has completed" "No effect,Clear" bitfld.long 0x04 0. " START ,Initiate BIST of internal memory" "No effect,Clear" line.long 0x08 "HW_AUDIOOUT_BISTCTRL_TOG,BIST Control and Status Toggle Register" bitfld.long 0x08 3. " FAIL ,BIST has failed" "Not toggle,Toggle" bitfld.long 0x08 2. " PASS ,BIST has passed" "Not toggle,Toggle" textline " " bitfld.long 0x08 1. " DONE ,BIST has completed" "Not toggle,Toggle" bitfld.long 0x08 0. " START ,Initiate BIST of internal memory" "Not toggle,Toggle" rgroup.long 0xc0++0x03 line.long 0x00 "HW_AUDIOOUT_BISTSTAT0,Hardware BIST Status 0 Register" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Failing data at the failing address" group.long 0xc4++0x0b line.long 0x00 "HW_AUDIOOUT_BISTSTAT0_SET,Hardware BIST Status 0 Set Register" hexmask.long.tbyte 0x00 0.--23. 1. " DATA ,Failing data at the failing address" line.long 0x04 "HW_AUDIOOUT_BISTSTAT0_CLR,Hardware BIST Status 0 Clear Register" hexmask.long.tbyte 0x04 0.--23. 1. " DATA ,Failing data at the failing address" line.long 0x08 "HW_AUDIOOUT_BISTSTAT0_TOG,Hardware BIST Status 0 Toggle Register" hexmask.long.tbyte 0x08 0.--23. 1. " DATA ,Failing data at the failing address" rgroup.long 0xd0++0x03 line.long 0x00 "HW_AUDIOOUT_BISTSTAT1,Hardware AUDIOUT BIST Status 1 Register" hexmask.long.byte 0x00 24.--28. 1. " STATE ,Fail state of the BIST engine" hexmask.long.byte 0x00 0.--7. 1. " ADDR ,Failing data at the failing address" group.long 0xd4++0x0b line.long 0x00 "HW_AUDIOOUT_BISTSTAT1_SET,Hardware AUDIOUT BIST Status 1 Set Register" hexmask.long.byte 0x00 24.--28. 1. " STATE ,Fail state of the BIST engine" hexmask.long.byte 0x00 0.--7. 1. " ADDR ,Failing data at the failing address" line.long 0x04 "HW_AUDIOOUT_BISTSTAT1_CLR,Hardware AUDIOUT BIST Status 1 Clear Register" hexmask.long.byte 0x04 24.--28. 1. " STATE ,Fail state of the BIST engine" hexmask.long.byte 0x04 0.--7. 1. " ADDR ,Failing data at the failing address" line.long 0x08 "HW_AUDIOOUT_BISTSTAT1_TOG,Hardware AUDIOUT BIST Status 1 Toggle Register" hexmask.long.byte 0x08 24.--28. 1. " STATE ,Fail state of the BIST engine" hexmask.long.byte 0x08 0.--7. 1. " ADDR ,Failing data at the failing address" group.long 0xe0++0x0f line.long 0x00 "HW_AUDIOOUT_ANACLKCTRL,Analog Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,Analog clock Gate" "Not gated,Gated" bitfld.long 0x00 4. " INVERT_DACCLK ,DAC Clock Invert" "Not inverted,Inverted" textline " " bitfld.long 0x00 0.--2. " DACDIV ,DAC Analog Clock Divider" "6MHz,4MHz,3MHz,2MHz,3MHz,2MHz,1.5MHz,1MHz" line.long 0x04 "HW_AUDIOOUT_ANACLKCTRL_SET,Analog Clock Control Set Register" bitfld.long 0x04 31. " CLKGATE ,Analog clock Gate" "No effect,Set" bitfld.long 0x04 4. " INVERT_DACCLK ,DAC Clock Invert" "No effect,Set" textline " " bitfld.long 0x04 0.--2. " DACDIV ,DAC Analog Clock Divider" "6MHz,4MHz,3MHz,2MHz,3MHz,2MHz,1.5MHz,1MHz" line.long 0x08 "HW_AUDIOOUT_ANACLKCTRL_CLR,Analog Clock Control Clear Register" bitfld.long 0x08 31. " CLKGATE ,Analog clock Gate" "No effect,Clear" bitfld.long 0x08 4. " INVERT_DACCLK ,DAC Clock Invert" "No effect,Clear" textline " " bitfld.long 0x08 0.--2. " DACDIV ,DAC Analog Clock Divider" "6MHz,4MHz,3MHz,2MHz,3MHz,2MHz,1.5MHz,1MHz" line.long 0x0c "HW_AUDIOOUT_ANACLKCTRL_TOG,Analog Clock Control Toggle Register" bitfld.long 0x0c 31. " CLKGATE ,Analog clock Gate" "Not toggle,Toggle" bitfld.long 0x0c 4. " INVERT_DACCLK ,DAC Clock Invert" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--2. " DACDIV ,DAC Analog Clock Divider" "6MHz,4MHz,3MHz,2MHz,3MHz,2MHz,1.5MHz,1MHz" group.long 0xf0++0x0f line.long 0x00 "HW_AUDIOOUT_DATA,AUDIOOUT Write Data Register" hexmask.long.word 0x00 16.--31. 1. " HIGH ,Right Sample or Sample High Half-Word" hexmask.long.word 0x00 0.--15. 1. " LOW ,Left Sample or Sample Low Half-Word" line.long 0x04 "HW_AUDIOOUT_DATA_SET,AUDIOOUT Write Data Set Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,Right Sample or Sample High Half-Word" hexmask.long.word 0x04 0.--15. 1. " LOW ,Left Sample or Sample Low Half-Word" line.long 0x08 "HW_AUDIOOUT_DATA_CLR,AUDIOOUT Write Data Clear Register" hexmask.long.word 0x08 16.--31. 1. " HIGH ,Right Sample or Sample High Half-Word" hexmask.long.word 0x08 0.--15. 1. " LOW ,Left Sample or Sample Low Half-Word" line.long 0x0c "HW_AUDIOOUT_DATA_TOG,AUDIOOUT Write Data Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " HIGH ,Right Sample or Sample High Half-Word" hexmask.long.word 0x0c 0.--15. 1. " LOW ,Left Sample or Sample Low Half-Word" group.long 0x100++0x0f line.long 0x00 "HW_AUDIOOUT_SPEAKERCTRL,AUDIOOUT Speaker Control Register" bitfld.long 0x00 24. " MUTE ,This bit mutes the speaker outputs SPEAKERP and SPEAKERN" "Unmute,Mute" bitfld.long 0x00 22.--23. " I1_ADJ ,Adjusts bias current in first stage of speaker amplifier" "Nominal,-50%,+100%,+50%" textline " " bitfld.long 0x00 20.--21. " IALL_ADJ ,Adjusts all bias current in speaker amplifier" "Nominal,-50%,+50%,-40%" bitfld.long 0x00 14.--15. " POSDRIVER ,SPEAKERP pin control" "Normal,Drive low,Drive high,Tri-state" textline " " bitfld.long 0x00 12.--13. " NEGDRIVER ,SPEAKERN pin control" "Normal,Drive low,Drive high,Tri-state" line.long 0x04 "HW_AUDIOOUT_SPEAKERCTRL_SET,AUDIOOUT Speaker Control Set Register" bitfld.long 0x04 24. " MUTE ,This bit mutes the speaker outputs SPEAKERP and SPEAKERN" "No effect,Set" bitfld.long 0x04 22.--23. " I1_ADJ ,Adjusts bias current in first stage of speaker amplifier" "Nominal,-50%,+100%,+50%" textline " " bitfld.long 0x04 20.--21. " IALL_ADJ ,Adjusts all bias current in speaker amplifier" "Nominal,-50%,+50%,-40%" bitfld.long 0x04 14.--15. " POSDRIVER ,SPEAKERP pin control" "Normal,Drive low,Drive high,Tri-state" textline " " bitfld.long 0x04 12.--13. " NEGDRIVER ,SPEAKERN pin control" "Normal,Drive low,Drive high,Tri-state" line.long 0x08 "HW_AUDIOOUT_SPEAKERCTRL_CLR,AUDIOOUT Speaker Control Clear Register" bitfld.long 0x08 24. " MUTE ,This bit mutes the speaker outputs SPEAKERP and SPEAKERN" "No effect,Clear" bitfld.long 0x08 22.--23. " I1_ADJ ,Adjusts bias current in first stage of speaker amplifier" "Nominal,-50%,+100%,+50%" textline " " bitfld.long 0x08 20.--21. " IALL_ADJ ,Adjusts all bias current in speaker amplifier" "Nominal,-50%,+50%,-40%" bitfld.long 0x08 14.--15. " POSDRIVER ,SPEAKERP pin control" "Normal,Drive low,Drive high,Tri-state" textline " " bitfld.long 0x08 12.--13. " NEGDRIVER ,SPEAKERN pin control" "Normal,Drive low,Drive high,Tri-state" line.long 0x0c "HW_AUDIOOUT_SPEAKERCTRL_TOG,AUDIOOUT Speaker Control Toggle Register" bitfld.long 0x0c 24. " MUTE ,This bit mutes the speaker outputs SPEAKERP and SPEAKERN" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " I1_ADJ ,Adjusts bias current in first stage of speaker amplifier" "Nominal,-50%,+100%,+50%" textline " " bitfld.long 0x0c 20.--21. " IALL_ADJ ,Adjusts all bias current in speaker amplifier" "Nominal,-50%,+50%,-40%" bitfld.long 0x0c 14.--15. " POSDRIVER ,SPEAKERP pin control" "Normal,Drive low,Drive high,Tri-state" textline " " bitfld.long 0x0c 12.--13. " NEGDRIVER ,SPEAKERN pin control" "Normal,Drive low,Drive high,Tri-state" rgroup.long 0x200++0x03 line.long 0x00 "HW_AUDIOOUT_VERSION,AUDIOOUT Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end tree "SPDIF (Sony-Philips Digital Interface Format)" base asd:0x80054000 width 24. group.long 0x00++0x0f line.long 0x00 "HW_SPDIF_CTRL,SPDIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block and then gates the clocks off" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " WAIT_END_XFER ,Wait until the internal FIFO is empty before halting transmission based on deassertion of RUN" "Not wait,Wait" textline " " bitfld.long 0x00 4. " WORD_LENGTH ,Mode" "32-bit,16-bit" bitfld.long 0x00 3. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SPDIF transmission" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SPDIF transmission" "Not occurred,Occurred" bitfld.long 0x00 1. " FIFO_ERROR_IRQ_EN ,Enable a SPDIF interrupt request on FIFO overflow or underflow status conditions" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RUN ,Begin converting data" "No run,Run" line.long 0x04 "HW_SPDIF_CTRL_SET,SPDIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block and then gates the clocks off" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5. " WAIT_END_XFER ,Wait until the internal FIFO is empty before halting transmission based on deassertion of RUN" "No effect,Set" textline " " bitfld.long 0x04 4. " WORD_LENGTH ,Mode" "No effect,Set" bitfld.long 0x04 3. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SPDIF transmission" "No effect,Set" textline " " bitfld.long 0x04 2. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SPDIF transmission" "No effect,Set" bitfld.long 0x04 1. " FIFO_ERROR_IRQ_EN ,Enable a SPDIF interrupt request on FIFO overflow or underflow status conditions" "No effect,Set" textline " " bitfld.long 0x04 0. " RUN ,Begin converting data" "No effect,Set" line.long 0x08 "HW_SPDIF_CTRL_CLR,SPDIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block and then gates the clocks off" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5. " WAIT_END_XFER ,Wait until the internal FIFO is empty before halting transmission based on deassertion of RUN" "No effect,Clear" textline " " bitfld.long 0x08 4. " WORD_LENGTH ,Mode" "No effect,Clear" bitfld.long 0x08 3. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SPDIF transmission" "No effect,Clear" textline " " bitfld.long 0x08 2. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SPDIF transmission" "No effect,Clear" bitfld.long 0x08 1. " FIFO_ERROR_IRQ_EN ,Enable a SPDIF interrupt request on FIFO overflow or underflow status conditions" "No effect,Clear" textline " " bitfld.long 0x08 0. " RUN ,Begin converting data" "No effect,Clear" line.long 0x0c "HW_SPDIF_CTRL_TOG,SPDIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block and then gates the clocks off" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 5. " WAIT_END_XFER ,Wait until the internal FIFO is empty before halting transmission based on deassertion of RUN" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " WORD_LENGTH ,Mode" "Not toggle,Toggle" bitfld.long 0x0c 3. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SPDIF transmission" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SPDIF transmission" "Not toggle,Toggle" bitfld.long 0x0c 1. " FIFO_ERROR_IRQ_EN ,Enable a SPDIF interrupt request on FIFO overflow or underflow status conditions" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " RUN ,Begin converting data" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_SPDIF_STAT,SPDIF Status Register" bitfld.long 0x00 31. " PRESENT ,SPDIF is present" "Not present,Present" bitfld.long 0x00 0. " END_XFER ,SPDIF module has completed transfer of all data" "Not completed,Completed" group.long 0x14++0x0b line.long 0x00 "HW_SPDIF_STAT_SET,SPDIF Status Set Register" bitfld.long 0x00 31. " PRESENT ,SPDIF is present" "No effect,Set" bitfld.long 0x00 0. " END_XFER ,SPDIF module has completed transfer of all data" "No effect,Set" line.long 0x04 "HW_SPDIF_STAT_CLR,SPDIF Status Clear Register" bitfld.long 0x04 31. " PRESENT ,SPDIF is present" "No effect,Clear" bitfld.long 0x04 0. " END_XFER ,SPDIF module has completed transfer of all data" "No effect,Clear" line.long 0x08 "HW_SPDIF_STAT_TOG,SPDIF Status Toggle Register" bitfld.long 0x08 31. " PRESENT ,SPDIF is present" "Not toggle,Toggle" bitfld.long 0x08 0. " END_XFER ,SPDIF module has completed transfer of all data" "Not toggle,Toggle" group.long 0x20++0x1f line.long 0x00 "HW_SPDIF_FRAMECTRL,SPDIF Frame Control Register" bitfld.long 0x00 17. " V_CONFIG ,Defines SPDIF behavior when sending invalid frames" "Do not tag invalid frames,Tag invalid frames" bitfld.long 0x00 16. " AUTO_MUTE ,Auto-Mute Stream on stream-suspend detect" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " USER_DATA ,User data transmitted during each sub-frame" "0,1" bitfld.long 0x00 13. " V ,Indicates that a sub-frame's samples are invalid" "Valid,Invalid" textline " " bitfld.long 0x00 12. " L ,Generation level is defined by the IEC standard" "0,1" hexmask.long.byte 0x00 4.--10. 1. " CC ,Category code is defined by the IEC standard" textline " " bitfld.long 0x00 3. " PRE ,Pre-Emphasis" "Disabled,50/15 us" bitfld.long 0x00 2. " COPY ,Copyright bit asserted" "Not asserted,Asserted" textline " " bitfld.long 0x00 1. " AUDIO ,AUDIO data" "PCM data,Non-PCM data" bitfld.long 0x00 0. " PRO ,Use of the channel" "Consumer,Professional" line.long 0x04 "HW_SPDIF_FRAMECTRL_SET,SPDIF Frame Control Set Register" bitfld.long 0x04 17. " V_CONFIG ,Defines SPDIF behavior when sending invalid frames" "No effect,Set" bitfld.long 0x04 16. " AUTO_MUTE ,Auto-Mute Stream on stream-suspend detect" "No effect,Set" textline " " bitfld.long 0x04 14. " USER_DATA ,User data transmitted during each sub-frame" "No effect,Set" bitfld.long 0x04 13. " V ,Indicates that a sub-frame's samples are invalid" "No effect,Set" textline " " bitfld.long 0x04 12. " L ,Generation level is defined by the IEC standard" "No effect,Set" hexmask.long.byte 0x04 4.--10. 1. " CC ,Category code is defined by the IEC standard" textline " " bitfld.long 0x04 3. " PRE ,Pre-Emphasis" "No effect,Set" bitfld.long 0x04 2. " COPY ,Copyright bit asserted" "No effect,Set" textline " " bitfld.long 0x04 1. " AUDIO ,AUDIO data" "No effect,Set" bitfld.long 0x04 0. " PRO ,Use of the channel" "No effect,Set" line.long 0x08 "HW_SPDIF_FRAMECTRL_CLR,SPDIF Frame Control Clear Register" bitfld.long 0x08 17. " V_CONFIG ,Defines SPDIF behavior when sending invalid frames" "No effect,Clear" bitfld.long 0x08 16. " AUTO_MUTE ,Auto-Mute Stream on stream-suspend detect" "No effect,Clear" textline " " bitfld.long 0x08 14. " USER_DATA ,User data transmitted during each sub-frame" "No effect,Clear" bitfld.long 0x08 13. " V ,Indicates that a sub-frame's samples are invalid" "No effect,Clear" textline " " bitfld.long 0x08 12. " L ,Generation level is defined by the IEC standard" "No effect,Clear" hexmask.long.byte 0x08 4.--10. 1. " CC ,Category code is defined by the IEC standard" textline " " bitfld.long 0x08 3. " PRE ,Pre-Emphasis" "No effect,Clear" bitfld.long 0x08 2. " COPY ,Copyright bit asserted" "No effect,Clear" textline " " bitfld.long 0x08 1. " AUDIO ,AUDIO data" "No effect,Clear" bitfld.long 0x08 0. " PRO ,Use of the channel" "No effect,Clear" line.long 0x0c "HW_SPDIF_FRAMECTRL_TOG,SPDIF Frame Control Toggle Register" bitfld.long 0x0c 17. " V_CONFIG ,Defines SPDIF behavior when sending invalid frames" "Not toggle,Toggle" bitfld.long 0x0c 16. " AUTO_MUTE ,Auto-Mute Stream on stream-suspend detect" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " USER_DATA ,User data transmitted during each sub-frame" "Not toggle,Toggle" bitfld.long 0x0c 13. " V ,Indicates that a sub-frame's samples are invalid" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " L ,Generation level is defined by the IEC standard" "Not toggle,Toggle" hexmask.long.byte 0x0c 4.--10. 1. " CC ,Category code is defined by the IEC standard" textline " " bitfld.long 0x0c 3. " PRE ,Pre-Emphasis" "Not toggle,Toggle" bitfld.long 0x0c 2. " COPY ,Copyright bit asserted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " AUDIO ,AUDIO data" "Not toggle,Toggle" bitfld.long 0x0c 0. " PRO ,Use of the channel" "Not toggle,Toggle" line.long 0x10 "HW_SPDIF_SRR,SPDIF Sample Rate Register" bitfld.long 0x10 28.--30. " BASEMULT ,Base-Rate Multiplier" "Reserved,Single-rate,Double-rate,?..." hexmask.long.tbyte 0x10 0.--19. 1. " RATE ,Sample-Rate Conversion Factor" line.long 0x14 "HW_SPDIF_SRR_SET,SPDIF Sample Rate Set Register" bitfld.long 0x14 28.--30. " BASEMULT ,Base-Rate Multiplier" "Reserved,Single-rate,Double-rate,?..." hexmask.long.tbyte 0x14 0.--19. 1. " RATE ,Sample-Rate Conversion Factor" line.long 0x18 "HW_SPDIF_SRR_CLR,SPDIF Sample Rate Clear Register" bitfld.long 0x18 28.--30. " BASEMULT ,Base-Rate Multiplier" "Reserved,Single-rate,Double-rate,?..." hexmask.long.tbyte 0x18 0.--19. 1. " RATE ,Sample-Rate Conversion Factor" line.long 0x1c "HW_SPDIF_SRR_TOG,SPDIF Sample Rate Toggle Register" bitfld.long 0x1c 28.--30. " BASEMULT ,Base-Rate Multiplier" "Reserved,Single-rate,Double-rate,?..." hexmask.long.tbyte 0x1c 0.--19. 1. " RATE ,Sample-Rate Conversion Factor" rgroup.long 0x40++0x03 line.long 0x00 "HW_SPDIF_DEBUG,SPDIF Debug Register" bitfld.long 0x00 1. " DMA_PREQ ,DMA request status" "Not reguested,Requested" bitfld.long 0x00 0. " FIFO_STATUS ,FIFO has empty space" "No,Yes" group.long 0x44++0x0b line.long 0x00 "HW_SPDIF_DEBUG_SET,SPDIF Debug Set Register" bitfld.long 0x00 1. " DMA_PREQ ,DMA request status" "No effect,Set" bitfld.long 0x00 0. " FIFO_STATUS ,FIFO has empty space" "No effect,Set" line.long 0x04 "HW_SPDIF_DEBUG_CLR,SPDIF Debug Clear Register" bitfld.long 0x04 1. " DMA_PREQ ,DMA request status" "No effect,Clear" bitfld.long 0x04 0. " FIFO_STATUS ,FIFO has empty space" "No effect,Clear" line.long 0x08 "HW_SPDIF_DEBUG_TOG,SPDIF Debug Toggle Register" bitfld.long 0x08 1. " DMA_PREQ ,DMA request status" "Not toggle,Toggle" bitfld.long 0x08 0. " FIFO_STATUS ,FIFO has empty space" "Not toggle,Toggle" group.long 0x50++0x0f line.long 0x00 "HW_SPDIF_DATA,SPDIF Write Data Register" hexmask.long.word 0x00 16.--31. 1. " HIGH ,For 16-bit mode,right channel sample. For 32-bit mode,16 MSBs of the 32-bit sample" hexmask.long.word 0x00 0.--15. 1. " LOW ,For 16-bit mode, left channel sample. For 32-bit mode, 16 LSBs of the 32-bit sample" line.long 0x04 "HW_SPDIF_DATA_SET,SPDIF Write Data Set Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,For 16-bit mode,right channel sample. For 32-bit mode,16 MSBs of the 32-bit sample" hexmask.long.word 0x04 0.--15. 1. " LOW ,For 16-bit mode, left channel sample. For 32-bit mode, 16 LSBs of the 32-bit sample" line.long 0x08 "HW_SPDIF_DATA_CLR,SPDIF Write Data Clear Register" hexmask.long.word 0x08 16.--31. 1. " HIGH ,For 16-bit mode,right channel sample. For 32-bit mode,16 MSBs of the 32-bit sample" hexmask.long.word 0x08 0.--15. 1. " LOW ,For 16-bit mode, left channel sample. For 32-bit mode, 16 LSBs of the 32-bit sample" line.long 0x0c "HW_SPDIF_DATA_TOG,SPDIF Write Data Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " HIGH ,For 16-bit mode,right channel sample. For 32-bit mode,16 MSBs of the 32-bit sample" hexmask.long.word 0x0c 0.--15. 1. " LOW ,For 16-bit mode, left channel sample. For 32-bit mode, 16 LSBs of the 32-bit sample" rgroup.long 0x60++0x03 line.long 0x00 "HW_SPDIF_VERSION,SPDIF Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the STEP field of the RTL version" width 0x0b tree.end tree.open "SAIF (Serial Audio Interface)" tree "SAIF 1" base asd:0x80042000 width 18. if (((d.l(asd:(0x80042000+0x00)))&0x4000000)==0x0) ;BITCLK_BASE_RATE=0; group.long 0x00++0x0f line.long 0x00 "HW_SAIF_CTRL,SAIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Normal,Gated off" textline " " bitfld.long 0x00 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x00 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "32x rate,48x rate" textline " " bitfld.long 0x00 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Disabled,Enabled" bitfld.long 0x00 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x00 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "MSB first,LSB first" bitfld.long 0x00 11. " DELAY ,SAIF Data Delay" "Not delayed,Delayed one BITCLK period" textline " " bitfld.long 0x00 10. " JUSTIFY ,SAIF Data Justification" "Left-justified,Right-justified" bitfld.long 0x00 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Left low/Right high,Left high/Right low" textline " " bitfld.long 0x00 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Falling edge/Rising edge,Rising edge/Falling edge" bitfld.long 0x00 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x00 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Master,Slave" textline " " bitfld.long 0x00 1. " READ_MODE ,SAIF Transmit/Receive Select" "Tx or write,Rx or read" bitfld.long 0x00 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Run" line.long 0x04 "HW_SAIF_CTRL_SET,SAIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Set" textline " " bitfld.long 0x04 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x04 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Set" textline " " bitfld.long 0x04 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Set" bitfld.long 0x04 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x04 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Set" bitfld.long 0x04 11. " DELAY ,SAIF Data Delay" "No effect,Set" textline " " bitfld.long 0x04 10. " JUSTIFY ,SAIF Data Justification" "No effect,Set" bitfld.long 0x04 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Set" textline " " bitfld.long 0x04 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Set" bitfld.long 0x04 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x04 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Set" bitfld.long 0x04 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Set" textline " " bitfld.long 0x04 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Set" bitfld.long 0x04 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Set" line.long 0x08 "HW_SAIF_CTRL_CLR,SAIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Clear" textline " " bitfld.long 0x08 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x08 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Clear" textline " " bitfld.long 0x08 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Clear" bitfld.long 0x08 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x08 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Clear" bitfld.long 0x08 11. " DELAY ,SAIF Data Delay" "No effect,Clear" textline " " bitfld.long 0x08 10. " JUSTIFY ,SAIF Data Justification" "No effect,Clear" bitfld.long 0x08 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Clear" textline " " bitfld.long 0x08 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Clear" bitfld.long 0x08 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x08 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Clear" bitfld.long 0x08 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Clear" textline " " bitfld.long 0x08 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Clear" line.long 0x0c "HW_SAIF_CTRL_TOG,SAIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x0c 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Not toggle,Toggle" bitfld.long 0x0c 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x0c 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "Not toggle,Toggle" bitfld.long 0x0c 11. " DELAY ,SAIF Data Delay" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " JUSTIFY ,SAIF Data Justification" "Not toggle,Toggle" bitfld.long 0x0c 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x0c 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " READ_MODE ,SAIF Transmit/Receive Select" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Begin transmitting or receiving serial PCM data" "Not toggle,Toggle" else ;BITCLK_BASE_RATE=1; group.long 0x00++0x0f line.long 0x00 "HW_SAIF_CTRL,SAIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Normal,Gated off" textline " " bitfld.long 0x00 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x00 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "32x rate,48x rate" textline " " bitfld.long 0x00 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Disabled,Enabled" bitfld.long 0x00 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x00 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "MSB first,LSB first" bitfld.long 0x00 11. " DELAY ,SAIF Data Delay" "Not delayed,Delayed one BITCLK period" textline " " bitfld.long 0x00 10. " JUSTIFY ,SAIF Data Justification" "Left-justified,Right-justified" bitfld.long 0x00 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Left low/Right high,Left high/Right low" textline " " bitfld.long 0x00 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Falling edge/Rising edge,Rising edge/Falling edge" bitfld.long 0x00 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x00 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Master,Slave" textline " " bitfld.long 0x00 1. " READ_MODE ,SAIF Transmit/Receive Select" "Tx or write,Rx or read" bitfld.long 0x00 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Run" line.long 0x04 "HW_SAIF_CTRL_SET,SAIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Set" textline " " bitfld.long 0x04 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x04 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Set" textline " " bitfld.long 0x04 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Set" bitfld.long 0x04 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x04 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Set" bitfld.long 0x04 11. " DELAY ,SAIF Data Delay" "No effect,Set" textline " " bitfld.long 0x04 10. " JUSTIFY ,SAIF Data Justification" "No effect,Set" bitfld.long 0x04 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Set" textline " " bitfld.long 0x04 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Set" bitfld.long 0x04 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x04 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Set" bitfld.long 0x04 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Set" textline " " bitfld.long 0x04 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Set" bitfld.long 0x04 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Set" line.long 0x08 "HW_SAIF_CTRL_CLR,SAIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Clear" textline " " bitfld.long 0x08 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x08 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Clear" textline " " bitfld.long 0x08 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Clear" bitfld.long 0x08 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x08 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Clear" bitfld.long 0x08 11. " DELAY ,SAIF Data Delay" "No effect,Clear" textline " " bitfld.long 0x08 10. " JUSTIFY ,SAIF Data Justification" "No effect,Clear" bitfld.long 0x08 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Clear" textline " " bitfld.long 0x08 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Clear" bitfld.long 0x08 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x08 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Clear" bitfld.long 0x08 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Clear" textline " " bitfld.long 0x08 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Clear" line.long 0x0c "HW_SAIF_CTRL_TOG,SAIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x0c 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Not toggle,Toggle" bitfld.long 0x0c 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x0c 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "Not toggle,Toggle" bitfld.long 0x0c 11. " DELAY ,SAIF Data Delay" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " JUSTIFY ,SAIF Data Justification" "Not toggle,Toggle" bitfld.long 0x0c 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x0c 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " READ_MODE ,SAIF Transmit/Receive Select" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Begin transmitting or receiving serial PCM data" "Not toggle,Toggle" endif group.long 0x10++0x0f line.long 0x00 "HW_SAIF_STAT,SAIF Status Register" bitfld.long 0x00 31. " PRESENT ,SAIF is present" "Not present,Present" bitfld.long 0x00 16. " DMA_PREQ ,DMA Request Status" "Not requested,Requested" textline " " bitfld.long 0x00 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "Not occurred,Occurred" bitfld.long 0x00 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "Not requested,Requested" bitfld.long 0x00 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "Not busy,Busy" line.long 0x04 "HW_SAIF_STAT_SET,SAIF Status Set Register" bitfld.long 0x04 31. " PRESENT ,SAIF is present" "No effect,Set" bitfld.long 0x04 16. " DMA_PREQ ,DMA Request Status" "No effect,Set" textline " " bitfld.long 0x04 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "No effect,Set" bitfld.long 0x04 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "No effect,Set" textline " " bitfld.long 0x04 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "No effect,Set" bitfld.long 0x04 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "No effect,Set" line.long 0x08 "HW_SAIF_STAT_CLR,SAIF Status Clear Register" bitfld.long 0x08 31. " PRESENT ,SAIF is present" "No effect,Clear" bitfld.long 0x08 16. " DMA_PREQ ,DMA Request Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "No effect,Clear" bitfld.long 0x08 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "No effect,Clear" textline " " bitfld.long 0x08 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "No effect,Clear" bitfld.long 0x08 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "No effect,Clear" line.long 0x0c "HW_SAIF_STAT_TOG,SAIF Status Toggle Register" bitfld.long 0x0c 31. " PRESENT ,SAIF is present" "Not toggle,Toggle" bitfld.long 0x0c 16. " DMA_PREQ ,DMA Request Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "Not toggle,Toggle" bitfld.long 0x0c 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "Not toggle,Toggle" bitfld.long 0x0c 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "Not toggle,Toggle" hgroup.long 0x20++0x03 hide.long 0x00 "HW_SAIF_DATA,SAIF Data Register" in group.long 0x24++0x03 line.long 0x00 "HW_SAIF_DATA_SET,SAIF Data Set Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" group.long 0x28++0x03 line.long 0x00 "HW_SAIF_DATA_CLR,SAIF Data Clear Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" group.long 0x2c++0x03 line.long 0x00 "HW_SAIF_DATA_TOG,SAIF Data Toggle Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" rgroup.long 0x30++0x03 line.long 0x00 "HW_SAIF_VERSION,SAIF Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the STEP field of the RTL version" width 0x0b tree.end tree "SAIF 2" base asd:0x80046000 width 18. if (((d.l(asd:(0x80046000+0x00)))&0x4000000)==0x0) ;BITCLK_BASE_RATE=0; group.long 0x00++0x0f line.long 0x00 "HW_SAIF_CTRL,SAIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Normal,Gated off" textline " " bitfld.long 0x00 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x00 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "32x rate,48x rate" textline " " bitfld.long 0x00 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Disabled,Enabled" bitfld.long 0x00 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x00 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "MSB first,LSB first" bitfld.long 0x00 11. " DELAY ,SAIF Data Delay" "Not delayed,Delayed one BITCLK period" textline " " bitfld.long 0x00 10. " JUSTIFY ,SAIF Data Justification" "Left-justified,Right-justified" bitfld.long 0x00 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Left low/Right high,Left high/Right low" textline " " bitfld.long 0x00 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Falling edge/Rising edge,Rising edge/Falling edge" bitfld.long 0x00 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x00 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Master,Slave" textline " " bitfld.long 0x00 1. " READ_MODE ,SAIF Transmit/Receive Select" "Tx or write,Rx or read" bitfld.long 0x00 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Run" line.long 0x04 "HW_SAIF_CTRL_SET,SAIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Set" textline " " bitfld.long 0x04 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x04 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Set" textline " " bitfld.long 0x04 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Set" bitfld.long 0x04 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x04 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Set" bitfld.long 0x04 11. " DELAY ,SAIF Data Delay" "No effect,Set" textline " " bitfld.long 0x04 10. " JUSTIFY ,SAIF Data Justification" "No effect,Set" bitfld.long 0x04 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Set" textline " " bitfld.long 0x04 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Set" bitfld.long 0x04 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x04 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Set" bitfld.long 0x04 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Set" textline " " bitfld.long 0x04 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Set" bitfld.long 0x04 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Set" line.long 0x08 "HW_SAIF_CTRL_CLR,SAIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Clear" textline " " bitfld.long 0x08 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x08 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Clear" textline " " bitfld.long 0x08 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Clear" bitfld.long 0x08 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x08 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Clear" bitfld.long 0x08 11. " DELAY ,SAIF Data Delay" "No effect,Clear" textline " " bitfld.long 0x08 10. " JUSTIFY ,SAIF Data Justification" "No effect,Clear" bitfld.long 0x08 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Clear" textline " " bitfld.long 0x08 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Clear" bitfld.long 0x08 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x08 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Clear" bitfld.long 0x08 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Clear" textline " " bitfld.long 0x08 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Clear" line.long 0x0c "HW_SAIF_CTRL_TOG,SAIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x0c 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Not toggle,Toggle" bitfld.long 0x0c 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x0c 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "Not toggle,Toggle" bitfld.long 0x0c 11. " DELAY ,SAIF Data Delay" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " JUSTIFY ,SAIF Data Justification" "Not toggle,Toggle" bitfld.long 0x0c 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x0c 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " READ_MODE ,SAIF Transmit/Receive Select" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Begin transmitting or receiving serial PCM data" "Not toggle,Toggle" else ;BITCLK_BASE_RATE=1; group.long 0x00++0x0f line.long 0x00 "HW_SAIF_CTRL,SAIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Normal,Gated off" textline " " bitfld.long 0x00 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x00 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "32x rate,48x rate" textline " " bitfld.long 0x00 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Disabled,Enabled" bitfld.long 0x00 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x00 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "MSB first,LSB first" bitfld.long 0x00 11. " DELAY ,SAIF Data Delay" "Not delayed,Delayed one BITCLK period" textline " " bitfld.long 0x00 10. " JUSTIFY ,SAIF Data Justification" "Left-justified,Right-justified" bitfld.long 0x00 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Left low/Right high,Left high/Right low" textline " " bitfld.long 0x00 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Falling edge/Rising edge,Rising edge/Falling edge" bitfld.long 0x00 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x00 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Master,Slave" textline " " bitfld.long 0x00 1. " READ_MODE ,SAIF Transmit/Receive Select" "Tx or write,Rx or read" bitfld.long 0x00 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Run" line.long 0x04 "HW_SAIF_CTRL_SET,SAIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Set" textline " " bitfld.long 0x04 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x04 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Set" textline " " bitfld.long 0x04 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Set" bitfld.long 0x04 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x04 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Set" bitfld.long 0x04 11. " DELAY ,SAIF Data Delay" "No effect,Set" textline " " bitfld.long 0x04 10. " JUSTIFY ,SAIF Data Justification" "No effect,Set" bitfld.long 0x04 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Set" textline " " bitfld.long 0x04 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Set" bitfld.long 0x04 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x04 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Set" bitfld.long 0x04 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Set" textline " " bitfld.long 0x04 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Set" bitfld.long 0x04 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Set" line.long 0x08 "HW_SAIF_CTRL_CLR,SAIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Clear" textline " " bitfld.long 0x08 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x08 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Clear" textline " " bitfld.long 0x08 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Clear" bitfld.long 0x08 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x08 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Clear" bitfld.long 0x08 11. " DELAY ,SAIF Data Delay" "No effect,Clear" textline " " bitfld.long 0x08 10. " JUSTIFY ,SAIF Data Justification" "No effect,Clear" bitfld.long 0x08 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Clear" textline " " bitfld.long 0x08 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Clear" bitfld.long 0x08 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x08 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Clear" bitfld.long 0x08 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Clear" textline " " bitfld.long 0x08 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Clear" line.long 0x0c "HW_SAIF_CTRL_TOG,SAIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x0c 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Not toggle,Toggle" bitfld.long 0x0c 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " bitfld.long 0x0c 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "Not toggle,Toggle" bitfld.long 0x0c 11. " DELAY ,SAIF Data Delay" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " JUSTIFY ,SAIF Data Justification" "Not toggle,Toggle" bitfld.long 0x0c 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x0c 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " READ_MODE ,SAIF Transmit/Receive Select" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Begin transmitting or receiving serial PCM data" "Not toggle,Toggle" endif group.long 0x10++0x0f line.long 0x00 "HW_SAIF_STAT,SAIF Status Register" bitfld.long 0x00 31. " PRESENT ,SAIF is present" "Not present,Present" bitfld.long 0x00 16. " DMA_PREQ ,DMA Request Status" "Not requested,Requested" textline " " bitfld.long 0x00 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "Not occurred,Occurred" bitfld.long 0x00 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "Not requested,Requested" bitfld.long 0x00 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "Not busy,Busy" line.long 0x04 "HW_SAIF_STAT_SET,SAIF Status Set Register" bitfld.long 0x04 31. " PRESENT ,SAIF is present" "No effect,Set" bitfld.long 0x04 16. " DMA_PREQ ,DMA Request Status" "No effect,Set" textline " " bitfld.long 0x04 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "No effect,Set" bitfld.long 0x04 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "No effect,Set" textline " " bitfld.long 0x04 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "No effect,Set" bitfld.long 0x04 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "No effect,Set" line.long 0x08 "HW_SAIF_STAT_CLR,SAIF Status Clear Register" bitfld.long 0x08 31. " PRESENT ,SAIF is present" "No effect,Clear" bitfld.long 0x08 16. " DMA_PREQ ,DMA Request Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "No effect,Clear" bitfld.long 0x08 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "No effect,Clear" textline " " bitfld.long 0x08 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "No effect,Clear" bitfld.long 0x08 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "No effect,Clear" line.long 0x0c "HW_SAIF_STAT_TOG,SAIF Status Toggle Register" bitfld.long 0x0c 31. " PRESENT ,SAIF is present" "Not toggle,Toggle" bitfld.long 0x0c 16. " DMA_PREQ ,DMA Request Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "Not toggle,Toggle" bitfld.long 0x0c 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "Not toggle,Toggle" bitfld.long 0x0c 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "Not toggle,Toggle" hgroup.long 0x20++0x03 hide.long 0x00 "HW_SAIF_DATA,SAIF Data Register" in group.long 0x24++0x03 line.long 0x00 "HW_SAIF_DATA_SET,SAIF Data Set Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" group.long 0x28++0x03 line.long 0x00 "HW_SAIF_DATA_CLR,SAIF Data Clear Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" group.long 0x2c++0x03 line.long 0x00 "HW_SAIF_DATA_TOG,SAIF Data Toggle Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" rgroup.long 0x30++0x03 line.long 0x00 "HW_SAIF_VERSION,SAIF Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the STEP field of the RTL version" width 0x0b tree.end tree.end tree "Power Supply" base asd:0x80044000 width 23. group.long 0x00++0x3f line.long 0x00 "HW_POWER_CTRL,Power Control Register" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" bitfld.long 0x00 27. " PSWITCH_MID_TRAN ,Selects the from-mid-transition interrupt functionality for PSWITCH" "Not selected,Selected" textline " " bitfld.long 0x00 24. " DCDC4P2_BO_IRQ ,Interrupt Status for 4P2_BO" "Not occurred,Occurred" bitfld.long 0x00 23. " ENIRQ_DCDC4P2_BO ,Enable interrupt for 4P2_BO" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "Not occurred,Occurred" bitfld.long 0x00 21. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " PSWITCH_IRQ ,Interrupt status for PSWITCH signals" "Not occurred,Occurred" bitfld.long 0x00 19. " PSWITCH_IRQ_SRC ,HW_POWER_STS_PSWITCH bit select" "Bit 0,Bit 1" textline " " bitfld.long 0x00 18. " POLARITY_PSWITCH ,Interrupt polarity" "Low,High" bitfld.long 0x00 17. " ENIRQ_PSWITCH ,Interrupt status for PSWITCH signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " POLARITY_DC_OK ,Debug use only,Select what to check" "5V disconnected,Linear regulators ok" bitfld.long 0x00 15. " DC_OK_IRQ ,Interrupt Status for DC_OK" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " ENIRQ_DC_OK ,Enable interrupt for DC_OK" "Disabled,Enabled" bitfld.long 0x00 13. " BATT_BO_IRQ ,Interrupt Status for BATT_BO" "Not occurred,Occurred" textline " " bitfld.long 0x00 12. " ENIRQBATT_BO ,Enable interrupt for battery brownout" "Disabled,Enabled" bitfld.long 0x00 11. " VDDIO_BO_IRQ ,Interrupt Status for VDDIO_BO" "Not occurred,Occurred" textline " " bitfld.long 0x00 10. " ENIRQ_VDDIO_BO ,Enable interrupt for VDDIO brownout" "Disabled,Enabled" bitfld.long 0x00 9. " VDDA_BO_IRQ ,Interrupt Status for VDDA_BO" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " ENIRQ_VDDA_BO ,Enable interrupt for VDDA brownout" "Disabled,Enabled" bitfld.long 0x00 7. " VDDD_BO_IRQ ,Interrupt Status for VDDD_BO" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " ENIRQ_VDDD_BO ,Enable interrupt for VDDD brownout" "Disabled,Enabled" bitfld.long 0x00 5. " POLARITY_VBUSVALID ,VBUSVALID polarity" "5V disconnected,5V connected" textline " " bitfld.long 0x00 4. " VBUSVALID_IRQ ,Interrupt status for VBUSVALID signal" "Not occurred,Occurred" bitfld.long 0x00 3. " ENIRQ_VBUS_VALID ,Enable interrupt for 5V detect using VBUSVALID" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " POLARITY_VDD5V_GT_VDDIO ,Set 5V polarity" "5V disconnected,5V connected" bitfld.long 0x00 1. " VDD5V_GT_VDDIO_IRQ ,Interrupt status for VDD5V_GT_VDDIO signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " ENIRQ_VDD5V_GT_VDDIO ,Enable interrupt for 5V detect" "Disabled,Enabled" line.long 0x04 "HW_POWER_CTRL_SET,Power Control Set Register" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" bitfld.long 0x04 27. " PSWITCH_MID_TRAN ,Selects the from-mid-transition interrupt functionality for PSWITCH" "No effect,Set" textline " " bitfld.long 0x04 24. " DCDC4P2_BO_IRQ ,Interrupt Status for 4P2_BO" "No effect,Set" bitfld.long 0x04 23. " ENIRQ_DCDC4P2_BO ,Enable interrupt for 4P2_BO" "No effect,Set" textline " " bitfld.long 0x04 22. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "No effect,Set" bitfld.long 0x04 21. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "No effect,Set" textline " " bitfld.long 0x04 20. " PSWITCH_IRQ ,Interrupt status for PSWITCH signals" "No effect,Set" bitfld.long 0x04 19. " PSWITCH_IRQ_SRC ,HW_POWER_STS_PSWITCH bit select" "No effect,Set" textline " " bitfld.long 0x04 18. " POLARITY_PSWITCH ,Interrupt polarity" "No effect,Set" bitfld.long 0x04 17. " ENIRQ_PSWITCH ,Interrupt status for PSWITCH signal" "No effect,Set" textline " " bitfld.long 0x04 16. " POLARITY_DC_OK ,Debug use only,Select what to check" "No effect,Set" bitfld.long 0x04 15. " DC_OK_IRQ ,Interrupt Status for DC_OK" "No effect,Set" textline " " bitfld.long 0x04 14. " ENIRQ_DC_OK ,Enable interrupt for DC_OK" "No effect,Set" bitfld.long 0x04 13. " BATT_BO_IRQ ,Interrupt Status for BATT_BO" "No effect,Set" textline " " bitfld.long 0x04 12. " ENIRQBATT_BO ,Enable interrupt for battery brownout" "No effect,Set" bitfld.long 0x04 11. " VDDIO_BO_IRQ ,Interrupt Status for VDDIO_BO" "No effect,Set" textline " " bitfld.long 0x04 10. " ENIRQ_VDDIO_BO ,Enable interrupt for VDDIO brownout" "No effect,Set" bitfld.long 0x04 9. " VDDA_BO_IRQ ,Interrupt Status for VDDA_BO" "No effect,Set" textline " " bitfld.long 0x04 8. " ENIRQ_VDDA_BO ,Enable interrupt for VDDA brownout" "No effect,Set" bitfld.long 0x04 7. " VDDD_BO_IRQ ,Interrupt Status for VDDD_BO" "No effect,Set" textline " " bitfld.long 0x04 6. " ENIRQ_VDDD_BO ,Enable interrupt for VDDD brownout" "No effect,Set" bitfld.long 0x04 5. " POLARITY_VBUSVALID ,VBUSVALID polarity" "No effect,Set" textline " " bitfld.long 0x04 4. " VBUSVALID_IRQ ,Interrupt status for VBUSVALID signal" "No effect,Set" bitfld.long 0x04 3. " ENIRQ_VBUS_VALID ,Enable interrupt for 5V detect using VBUSVALID" "No effect,Set" textline " " bitfld.long 0x04 2. " POLARITY_VDD5V_GT_VDDIO ,Set 5V polarity" "No effect,Set" bitfld.long 0x04 1. " VDD5V_GT_VDDIO_IRQ ,Interrupt status for VDD5V_GT_VDDIO signal" "No effect,Set" textline " " bitfld.long 0x04 0. " ENIRQ_VDD5V_GT_VDDIO ,Enable interrupt for 5V detect" "No effect,Set" line.long 0x08 "HW_POWER_CTRL_CLR,Power Control Clear Register" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" bitfld.long 0x08 27. " PSWITCH_MID_TRAN ,Selects the from-mid-transition interrupt functionality for PSWITCH" "No effect,Clear" textline " " bitfld.long 0x08 24. " DCDC4P2_BO_IRQ ,Interrupt Status for 4P2_BO" "No effect,Clear" bitfld.long 0x08 23. " ENIRQ_DCDC4P2_BO ,Enable interrupt for 4P2_BO" "No effect,Clear" textline " " bitfld.long 0x08 22. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "No effect,Clear" bitfld.long 0x08 21. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "No effect,Clear" textline " " bitfld.long 0x08 20. " PSWITCH_IRQ ,Interrupt status for PSWITCH signals" "No effect,Clear" bitfld.long 0x08 19. " PSWITCH_IRQ_SRC ,HW_POWER_STS_PSWITCH bit select" "No effect,Clear" textline " " bitfld.long 0x08 18. " POLARITY_PSWITCH ,Interrupt polarity" "No effect,Clear" bitfld.long 0x08 17. " ENIRQ_PSWITCH ,Interrupt status for PSWITCH signal" "No effect,Clear" textline " " bitfld.long 0x08 16. " POLARITY_DC_OK ,Debug use only,Select what to check" "No effect,Clear" bitfld.long 0x08 15. " DC_OK_IRQ ,Interrupt Status for DC_OK" "No effect,Clear" textline " " bitfld.long 0x08 14. " ENIRQ_DC_OK ,Enable interrupt for DC_OK" "No effect,Clear" bitfld.long 0x08 13. " BATT_BO_IRQ ,Interrupt Status for BATT_BO" "No effect,Clear" textline " " bitfld.long 0x08 12. " ENIRQBATT_BO ,Enable interrupt for battery brownout" "No effect,Clear" bitfld.long 0x08 11. " VDDIO_BO_IRQ ,Interrupt Status for VDDIO_BO" "No effect,Clear" textline " " bitfld.long 0x08 10. " ENIRQ_VDDIO_BO ,Enable interrupt for VDDIO brownout" "No effect,Clear" bitfld.long 0x08 9. " VDDA_BO_IRQ ,Interrupt Status for VDDA_BO" "No effect,Clear" textline " " bitfld.long 0x08 8. " ENIRQ_VDDA_BO ,Enable interrupt for VDDA brownout" "No effect,Clear" bitfld.long 0x08 7. " VDDD_BO_IRQ ,Interrupt Status for VDDD_BO" "No effect,Clear" textline " " bitfld.long 0x08 6. " ENIRQ_VDDD_BO ,Enable interrupt for VDDD brownout" "No effect,Clear" bitfld.long 0x08 5. " POLARITY_VBUSVALID ,VBUSVALID polarity" "No effect,Clear" textline " " bitfld.long 0x08 4. " VBUSVALID_IRQ ,Interrupt status for VBUSVALID signal" "No effect,Clear" bitfld.long 0x08 3. " ENIRQ_VBUS_VALID ,Enable interrupt for 5V detect using VBUSVALID" "No effect,Clear" textline " " bitfld.long 0x08 2. " POLARITY_VDD5V_GT_VDDIO ,Set 5V polarity" "No effect,Clear" bitfld.long 0x08 1. " VDD5V_GT_VDDIO_IRQ ,Interrupt status for VDD5V_GT_VDDIO signal" "No effect,Clear" textline " " bitfld.long 0x08 0. " ENIRQ_VDD5V_GT_VDDIO ,Enable interrupt for 5V detect" "No effect,Clear" line.long 0x0c "HW_POWER_CTRL_TOG,Power Control Toggle Register" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" bitfld.long 0x0c 27. " PSWITCH_MID_TRAN ,Selects the from-mid-transition interrupt functionality for PSWITCH" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DCDC4P2_BO_IRQ ,Interrupt Status for 4P2_BO" "Not toggle,Toggle" bitfld.long 0x0c 23. " ENIRQ_DCDC4P2_BO ,Enable interrupt for 4P2_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "Not toggle,Toggle" bitfld.long 0x0c 21. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " PSWITCH_IRQ ,Interrupt status for PSWITCH signals" "Not toggle,Toggle" bitfld.long 0x0c 19. " PSWITCH_IRQ_SRC ,HW_POWER_STS_PSWITCH bit select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " POLARITY_PSWITCH ,Interrupt polarity" "Not toggle,Toggle" bitfld.long 0x0c 17. " ENIRQ_PSWITCH ,Interrupt status for PSWITCH signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " POLARITY_DC_OK ,Debug use only,Select what to check" "Not toggle,Toggle" bitfld.long 0x0c 15. " DC_OK_IRQ ,Interrupt Status for DC_OK" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " ENIRQ_DC_OK ,Enable interrupt for DC_OK" "Not toggle,Toggle" bitfld.long 0x0c 13. " BATT_BO_IRQ ,Interrupt Status for BATT_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " ENIRQBATT_BO ,Enable interrupt for battery brownout" "Not toggle,Toggle" bitfld.long 0x0c 11. " VDDIO_BO_IRQ ,Interrupt Status for VDDIO_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " ENIRQ_VDDIO_BO ,Enable interrupt for VDDIO brownout" "Not toggle,Toggle" bitfld.long 0x0c 9. " VDDA_BO_IRQ ,Interrupt Status for VDDA_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " ENIRQ_VDDA_BO ,Enable interrupt for VDDA brownout" "Not toggle,Toggle" bitfld.long 0x0c 7. " VDDD_BO_IRQ ,Interrupt Status for VDDD_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " ENIRQ_VDDD_BO ,Enable interrupt for VDDD brownout" "Not toggle,Toggle" bitfld.long 0x0c 5. " POLARITY_VBUSVALID ,VBUSVALID polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " VBUSVALID_IRQ ,Interrupt status for VBUSVALID signal" "Not toggle,Toggle" bitfld.long 0x0c 3. " ENIRQ_VBUS_VALID ,Enable interrupt for 5V detect using VBUSVALID" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " POLARITY_VDD5V_GT_VDDIO ,Set 5V polarity" "Not toggle,Toggle" bitfld.long 0x0c 1. " VDD5V_GT_VDDIO_IRQ ,Interrupt status for VDD5V_GT_VDDIO signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " ENIRQ_VDD5V_GT_VDDIO ,Enable interrupt for 5V detect" "Not toggle,Toggle" line.long 0x10 "HW_POWER_5VCTRL,DC-DC 5V Control Register" bitfld.long 0x10 28.--29. " VBUSDROOP_TRSH ,Set the threshold for the VBUSDROOP comparator" "4.3V,4.4V,4.5V,4.7V" bitfld.long 0x10 24.--26. " HEADROOM_ADJ ,Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x10 20. " PWD_CHARGE_4P2 ,Controls the power down of both the battery charger and 4.2V regulation circuit" "Powered up,Powered down" bitfld.long 0x10 12.--17. " CHARGE_4P2_ILIMIT ,Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" textline " " bitfld.long 0x10 8.--10. " VBUSVALID_TRSH ,Set the threshold for the VBUSVALID comparator" "2.9V,4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V" bitfld.long 0x10 7. " PWDN_5VBRNOUT ,Automatic hardware powerdown" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " EN_LINREG_ILIMIT ,Enable the current limit in the linear regulators" "Disabled,Enabled" bitfld.long 0x10 5. " DCDC_XFER ,Enable automatic transition to switching DC-DC converter when VDD5V is removed" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " VBUSVALID_5VDETECT ,Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter" "Not used,Used" bitfld.long 0x10 3. " VBUSVALID_TO_B ,This bit muxes the Bvalid comparator to the VBUSVALID comparator" "Not muxed,Muxed" textline " " bitfld.long 0x10 2. " ILIMIT_EQ_ZERO ,The amount of current the device will consume from the 5V rail is minimized" "Not minimized,Minimized" bitfld.long 0x10 1. " PWRUP_VBUS_CMPS ,Powers up comparators for 5v" "Powered down,Powered up" textline " " bitfld.long 0x10 0. " ENABLE_DCDC ,Enables the switching DC-DC converter when 5V is present" "Disabled,Enabled" line.long 0x14 "HW_POWER_5VCTRL_SET,DC-DC 5V Control Set Register" bitfld.long 0x14 28.--29. " VBUSDROOP_TRSH ,Set the threshold for the VBUSDROOP comparator" "4.3V,4.4V,4.5V,4.7V" bitfld.long 0x14 24.--26. " HEADROOM_ADJ ,Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x14 20. " PWD_CHARGE_4P2 ,Controls the power down of both the battery charger and 4.2V regulation circuit" "No effect,Set" bitfld.long 0x14 12.--17. " CHARGE_4P2_ILIMIT ,Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" textline " " bitfld.long 0x14 8.--10. " VBUSVALID_TRSH ,Set the threshold for the VBUSVALID comparator" "2.9V,4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V" bitfld.long 0x14 7. " PWDN_5VBRNOUT ,Automatic hardware powerdown" "No effect,Set" textline " " bitfld.long 0x14 6. " EN_LINREG_ILIMIT ,Enable the current limit in the linear regulators" "No effect,Set" bitfld.long 0x14 5. " DCDC_XFER ,Enable automatic transition to switching DC-DC converter when VDD5V is removed" "No effect,Set" textline " " bitfld.long 0x14 4. " VBUSVALID_5VDETECT ,Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter" "No effect,Set" bitfld.long 0x14 3. " VBUSVALID_TO_B ,This bit muxes the Bvalid comparator to the VBUSVALID comparator" "No effect,Set" textline " " bitfld.long 0x14 2. " ILIMIT_EQ_ZERO ,The amount of current the device will consume from the 5V rail is minimized" "No effect,Set" bitfld.long 0x14 1. " PWRUP_VBUS_CMPS ,Powers up comparators for 5v" "No effect,Set" textline " " bitfld.long 0x14 0. " ENABLE_DCDC ,Enables the switching DC-DC converter when 5V is present" "No effect,Set" line.long 0x18 "HW_POWER_5VCTRL_CLR,DC-DC 5V Control Clear Register" bitfld.long 0x18 28.--29. " VBUSDROOP_TRSH ,Set the threshold for the VBUSDROOP comparator" "4.3V,4.4V,4.5V,4.7V" bitfld.long 0x18 24.--26. " HEADROOM_ADJ ,Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x18 20. " PWD_CHARGE_4P2 ,Controls the power down of both the battery charger and 4.2V regulation circuit" "No effect,Clear" bitfld.long 0x18 12.--17. " CHARGE_4P2_ILIMIT ,Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" textline " " bitfld.long 0x18 8.--10. " VBUSVALID_TRSH ,Set the threshold for the VBUSVALID comparator" "2.9V,4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V" bitfld.long 0x18 7. " PWDN_5VBRNOUT ,Automatic hardware powerdown" "No effect,Clear" textline " " bitfld.long 0x18 6. " EN_LINREG_ILIMIT ,Enable the current limit in the linear regulators" "No effect,Clear" bitfld.long 0x18 5. " DCDC_XFER ,Enable automatic transition to switching DC-DC converter when VDD5V is removed" "No effect,Clear" textline " " bitfld.long 0x18 4. " VBUSVALID_5VDETECT ,Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter" "No effect,Clear" bitfld.long 0x18 3. " VBUSVALID_TO_B ,This bit muxes the Bvalid comparator to the VBUSVALID comparator" "No effect,Clear" textline " " bitfld.long 0x18 2. " ILIMIT_EQ_ZERO ,The amount of current the device will consume from the 5V rail is minimized" "No effect,Clear" bitfld.long 0x18 1. " PWRUP_VBUS_CMPS ,Powers up comparators for 5v" "No effect,Clear" textline " " bitfld.long 0x18 0. " ENABLE_DCDC ,Enables the switching DC-DC converter when 5V is present" "No effect,Clear" line.long 0x1c "HW_POWER_5VCTRL_TOG,DC-DC 5V Control Toggle Register" bitfld.long 0x1c 28.--29. " VBUSDROOP_TRSH ,Set the threshold for the VBUSDROOP comparator" "4.3V,4.4V,4.5V,4.7V" bitfld.long 0x1c 24.--26. " HEADROOM_ADJ ,Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1c 20. " PWD_CHARGE_4P2 ,Controls the power down of both the battery charger and 4.2V regulation circuit" "Not toggle,Toggle" bitfld.long 0x1c 12.--17. " CHARGE_4P2_ILIMIT ,Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" textline " " bitfld.long 0x1c 8.--10. " VBUSVALID_TRSH ,Set the threshold for the VBUSVALID comparator" "2.9V,4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V" bitfld.long 0x1c 7. " PWDN_5VBRNOUT ,Automatic hardware powerdown" "Not toggle,Toggle" textline " " bitfld.long 0x1c 6. " EN_LINREG_ILIMIT ,Enable the current limit in the linear regulators" "Not toggle,Toggle" bitfld.long 0x1c 5. " DCDC_XFER ,Enable automatic transition to switching DC-DC converter when VDD5V is removed" "Not toggle,Toggle" textline " " bitfld.long 0x1c 4. " VBUSVALID_5VDETECT ,Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter" "Not toggle,Toggle" bitfld.long 0x1c 3. " VBUSVALID_TO_B ,This bit muxes the Bvalid comparator to the VBUSVALID comparator" "Not toggle,Toggle" textline " " bitfld.long 0x1c 2. " ILIMIT_EQ_ZERO ,The amount of current the device will consume from the 5V rail is minimized" "Not toggle,Toggle" bitfld.long 0x1c 1. " PWRUP_VBUS_CMPS ,Powers up comparators for 5v" "Not toggle,Toggle" textline " " bitfld.long 0x1c 0. " ENABLE_DCDC ,Enables the switching DC-DC converter when 5V is present" "Not toggle,Toggle" line.long 0x20 "HW_POWER_MINPWR,DC-DC Minimum Power and Miscellaneous Control Register" bitfld.long 0x20 14. " LOWPWR_4P2 ,Enable low power regulation of DCDC_4P2 limited to 2.5mA" "Disabled,Enabled" bitfld.long 0x20 13. " VDAC_DUMP_CTRL ,Dumps extra Video DAC current into the VDDD supply" "Not dumped,Dumped" textline " " bitfld.long 0x20 12. " PWD_BO ,Powers down supply brownout comparators" "Powered up,Powered down" bitfld.long 0x20 11. " USE_VDDXTAL_VBG ,Change the reference used in the dcdc converter to a low power, less accurate reference" "Not changed,Changed" textline " " bitfld.long 0x20 10. " PWD_ANA_CMPS ,Powers down analog comparators used in the power module" "Powered up,Powered down" bitfld.long 0x20 9. " ENABLE_OSC ,Enables the internal oscillator" "Disabled,Enabled" textline " " bitfld.long 0x20 8. " SELECT_OSC ,Switch internal 24mhz clock reference to the less accurate internal oscillator" "Not switched,Switched" bitfld.long 0x20 7. " VBG_OFF ,Powers down the bandgap reference" "Powered up,Powered down" textline " " bitfld.long 0x20 6. " DOUBLE_FETS ,Approximately doubles the size of power transistors in DC-DC converter" "No effect,Double" bitfld.long 0x20 5. " HALF_FETS ,Disable half the power transistors in DC-DC converter" "No,Yes" textline " " bitfld.long 0x20 4. " LESSANA_I ,Reduce DC-DC analog bias current 20%" "Not reduced,Reduced" bitfld.long 0x20 3. " PWD_XTAL24 ,Powers down the 24mhz oscillator" "Powered up,Powered down" textline " " bitfld.long 0x20 2. " DC_STOPCLK ,Stop the clock to internal logic of switching DC-DC converter" "Not stopped,Stopped" bitfld.long 0x20 1. " EN_DC_PFM ,Forces DC-DC to operate in a Pulse Frequency Modulation mode" "Not forced,Forced" textline " " bitfld.long 0x20 0. " DC_HALFCLK ,Slow down DC-DC clock from 1.5 MHz to 750 kHz" "No effect,Slow down" line.long 0x24 "HW_POWER_MINPWR_SET,DC-DC Minimum Power and Miscellaneous Control Set Register" bitfld.long 0x24 14. " LOWPWR_4P2 ,Enable low power regulation of DCDC_4P2 limited to 2.5mA" "No effect,Set" bitfld.long 0x24 13. " VDAC_DUMP_CTRL ,Dumps extra Video DAC current into the VDDD supply" "No effect,Set" textline " " bitfld.long 0x24 12. " PWD_BO ,Powers down supply brownout comparators" "No effect,Set" bitfld.long 0x24 11. " USE_VDDXTAL_VBG ,Change the reference used in the dcdc converter to a low power, less accurate reference" "No effect,Set" textline " " bitfld.long 0x24 10. " PWD_ANA_CMPS ,Powers down analog comparators used in the power module" "No effect,Set" bitfld.long 0x24 9. " ENABLE_OSC ,Enables the internal oscillator" "No effect,Set" textline " " bitfld.long 0x24 8. " SELECT_OSC ,Switch internal 24mhz clock reference to the less accurate internal oscillator" "No effect,Set" bitfld.long 0x24 7. " VBG_OFF ,Powers down the bandgap reference" "No effect,Set" textline " " bitfld.long 0x24 6. " DOUBLE_FETS ,Approximately doubles the size of power transistors in DC-DC converter" "No effect,Set" bitfld.long 0x24 5. " HALF_FETS ,Disable half the power transistors in DC-DC converter" "No effect,Set" textline " " bitfld.long 0x24 4. " LESSANA_I ,Reduce DC-DC analog bias current 20%" "No effect,Set" bitfld.long 0x24 3. " PWD_XTAL24 ,Powers down the 24mhz oscillator" "No effect,Set" textline " " bitfld.long 0x24 2. " DC_STOPCLK ,Stop the clock to internal logic of switching DC-DC converter" "No effect,Set" bitfld.long 0x24 1. " EN_DC_PFM ,Forces DC-DC to operate in a Pulse Frequency Modulation mode" "No effect,Set" textline " " bitfld.long 0x24 0. " DC_HALFCLK ,Slow down DC-DC clock from 1.5 MHz to 750 kHz" "No effect,Set" line.long 0x28 "HW_POWER_MINPWR_CLR,DC-DC Minimum Power and Miscellaneous Control Clear Register" bitfld.long 0x28 14. " LOWPWR_4P2 ,Enable low power regulation of DCDC_4P2 limited to 2.5mA" "No effect,Clear" bitfld.long 0x28 13. " VDAC_DUMP_CTRL ,Dumps extra Video DAC current into the VDDD supply" "No effect,Clear" textline " " bitfld.long 0x28 12. " PWD_BO ,Powers down supply brownout comparators" "No effect,Clear" bitfld.long 0x28 11. " USE_VDDXTAL_VBG ,Change the reference used in the dcdc converter to a low power, less accurate reference" "No effect,Clear" textline " " bitfld.long 0x28 10. " PWD_ANA_CMPS ,Powers down analog comparators used in the power module" "No effect,Clear" bitfld.long 0x28 9. " ENABLE_OSC ,Enables the internal oscillator" "No effect,Clear" textline " " bitfld.long 0x28 8. " SELECT_OSC ,Switch internal 24mhz clock reference to the less accurate internal oscillator" "No effect,Clear" bitfld.long 0x28 7. " VBG_OFF ,Powers down the bandgap reference" "No effect,Clear" textline " " bitfld.long 0x28 6. " DOUBLE_FETS ,Approximately doubles the size of power transistors in DC-DC converter" "No effect,Clear" bitfld.long 0x28 5. " HALF_FETS ,Disable half the power transistors in DC-DC converter" "No effect,Clear" textline " " bitfld.long 0x28 4. " LESSANA_I ,Reduce DC-DC analog bias current 20%" "No effect,Clear" bitfld.long 0x28 3. " PWD_XTAL24 ,Powers down the 24mhz oscillator" "No effect,Clear" textline " " bitfld.long 0x28 2. " DC_STOPCLK ,Stop the clock to internal logic of switching DC-DC converter" "No effect,Clear" bitfld.long 0x28 1. " EN_DC_PFM ,Forces DC-DC to operate in a Pulse Frequency Modulation mode" "No effect,Clear" textline " " bitfld.long 0x28 0. " DC_HALFCLK ,Slow down DC-DC clock from 1.5 MHz to 750 kHz" "No effect,Clear" line.long 0x2c "HW_POWER_MINPWR_TOG,DC-DC Minimum Power and Miscellaneous Control Toggle Register" bitfld.long 0x2c 14. " LOWPWR_4P2 ,Enable low power regulation of DCDC_4P2 limited to 2.5mA" "Not toggle,Toggle" bitfld.long 0x2c 13. " VDAC_DUMP_CTRL ,Dumps extra Video DAC current into the VDDD supply" "Not toggle,Toggle" textline " " bitfld.long 0x2c 12. " PWD_BO ,Powers down supply brownout comparators" "Not toggle,Toggle" bitfld.long 0x2c 11. " USE_VDDXTAL_VBG ,Change the reference used in the dcdc converter to a low power, less accurate reference" "Not toggle,Toggle" textline " " bitfld.long 0x2c 10. " PWD_ANA_CMPS ,Powers down analog comparators used in the power module" "Not toggle,Toggle" bitfld.long 0x2c 9. " ENABLE_OSC ,Enables the internal oscillator" "Not toggle,Toggle" textline " " bitfld.long 0x2c 8. " SELECT_OSC ,Switch internal 24mhz clock reference to the less accurate internal oscillator" "Not toggle,Toggle" bitfld.long 0x2c 7. " VBG_OFF ,Powers down the bandgap reference" "Not toggle,Toggle" textline " " bitfld.long 0x2c 6. " DOUBLE_FETS ,Approximately doubles the size of power transistors in DC-DC converter" "Not toggle,Toggle" bitfld.long 0x2c 5. " HALF_FETS ,Disable half the power transistors in DC-DC converter" "Not toggle,Toggle" textline " " bitfld.long 0x2c 4. " LESSANA_I ,Reduce DC-DC analog bias current 20%" "Not toggle,Toggle" bitfld.long 0x2c 3. " PWD_XTAL24 ,Powers down the 24mhz oscillator" "Not toggle,Toggle" textline " " bitfld.long 0x2c 2. " DC_STOPCLK ,Stop the clock to internal logic of switching DC-DC converter" "Not toggle,Toggle" bitfld.long 0x2c 1. " EN_DC_PFM ,Forces DC-DC to operate in a Pulse Frequency Modulation mode" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " DC_HALFCLK ,Slow down DC-DC clock from 1.5 MHz to 750 kHz" "Not toggle,Toggle" line.long 0x30 "HW_POWER_CHARGE,Battery Charge Control Register" bitfld.long 0x30 24.--26. " ADJ_VOLT ,Adjustments to the final LiIon final voltage" "No change,-0.25%,+0.50%,-0.75%,+0.25%,-0.50%,+0.75%,-1.00%" bitfld.long 0x30 22. " EN_LOAD ,Enable 100ohm load on the regulated 4.2V output" "Disabled,Enabled" textline " " bitfld.long 0x30 21. " EN_CHARGER_RESISTORS ,Enable 125k pullup on USB_DP and 375k on USB_DN to provice USB_CHARGER functionality" "Disabled,Enabled" bitfld.long 0x30 20. " EN_FAULT_DETECT ,Enable fault detection in the battery charger" "Disabled,Enabled" textline " " bitfld.long 0x30 19. " CHRG_STS_OFF ,Disable the CHRGSTS status bit" "No,Yes" bitfld.long 0x30 16. " PWD_BATTCHRG ,Power-down the battery charge circuitry" "Powered up,Powered down" textline " " bitfld.long 0x30 8.--11. " STOP_ILIMIT ,Current threshold at which the Li-Ion battery charger signals to stop charging" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA" bitfld.long 0x30 0.--5. " BATTCHRG_I ,Magnitude of the battery charge current" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" line.long 0x34 "HW_POWER_CHARGE_SET,Battery Charge Control Set Register" bitfld.long 0x34 24.--26. " ADJ_VOLT ,Adjustments to the final LiIon final voltage" "No change,-0.25%,+0.50%,-0.75%,+0.25%,-0.50%,+0.75%,-1.00%" bitfld.long 0x34 22. " EN_LOAD ,Enable 100ohm load on the regulated 4.2V output" "No effect,Set" textline " " bitfld.long 0x34 21. " EN_CHARGER_RESISTORS ,Enable 125k pullup on USB_DP and 375k on USB_DN to provice USB_CHARGER functionality" "No effect,Set" bitfld.long 0x34 20. " EN_FAULT_DETECT ,Enable fault detection in the battery charger" "No effect,Set" textline " " bitfld.long 0x34 19. " CHRG_STS_OFF ,Disable the CHRGSTS status bit" "No effect,Set" bitfld.long 0x34 16. " PWD_BATTCHRG ,Power-down the battery charge circuitry" "No effect,Set" textline " " bitfld.long 0x34 8.--11. " STOP_ILIMIT ,Current threshold at which the Li-Ion battery charger signals to stop charging" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA" bitfld.long 0x34 0.--5. " BATTCHRG_I ,Magnitude of the battery charge current" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" line.long 0x38 "HW_POWER_CHARGE_CLR,Battery Charge Control Clear Register" bitfld.long 0x38 24.--26. " ADJ_VOLT ,Adjustments to the final LiIon final voltage" "No change,-0.25%,+0.50%,-0.75%,+0.25%,-0.50%,+0.75%,-1.00%" bitfld.long 0x38 22. " EN_LOAD ,Enable 100ohm load on the regulated 4.2V output" "No effect,Clear" textline " " bitfld.long 0x38 21. " EN_CHARGER_RESISTORS ,Enable 125k pullup on USB_DP and 375k on USB_DN to provice USB_CHARGER functionality" "No effect,Clear" bitfld.long 0x38 20. " EN_FAULT_DETECT ,Enable fault detection in the battery charger" "No effect,Clear" textline " " bitfld.long 0x38 19. " CHRG_STS_OFF ,Disable the CHRGSTS status bit" "No effect,Clear" bitfld.long 0x38 16. " PWD_BATTCHRG ,Power-down the battery charge circuitry" "No effect,Clear" textline " " bitfld.long 0x38 8.--11. " STOP_ILIMIT ,Current threshold at which the Li-Ion battery charger signals to stop charging" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA" bitfld.long 0x38 0.--5. " BATTCHRG_I ,Magnitude of the battery charge current" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" line.long 0x3c "HW_POWER_CHARGE_TOG,Battery Charge Control Toggle Register" bitfld.long 0x3c 24.--26. " ADJ_VOLT ,Adjustments to the final LiIon final voltage" "No change,-0.25%,+0.50%,-0.75%,+0.25%,-0.50%,+0.75%,-1.00%" bitfld.long 0x3c 22. " EN_LOAD ,Enable 100ohm load on the regulated 4.2V output" "Not toggle,Toggle" textline " " bitfld.long 0x3c 21. " EN_CHARGER_RESISTORS ,Enable 125k pullup on USB_DP and 375k on USB_DN to provice USB_CHARGER functionality" "Not toggle,Toggle" bitfld.long 0x3c 20. " EN_FAULT_DETECT ,Enable fault detection in the battery charger" "Not toggle,Toggle" textline " " bitfld.long 0x3c 19. " CHRG_STS_OFF ,Disable the CHRGSTS status bit" "Not toggle,Toggle" bitfld.long 0x3c 16. " PWD_BATTCHRG ,Power-down the battery charge circuitry" "Not toggle,Toggle" textline " " bitfld.long 0x3c 8.--11. " STOP_ILIMIT ,Current threshold at which the Li-Ion battery charger signals to stop charging" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA" bitfld.long 0x3c 0.--5. " BATTCHRG_I ,Magnitude of the battery charge current" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" group.long 0x40++0x03 line.long 0x00 "HW_POWER_VDDDCTRL,VDDD Supply Targets and Brownouts Control Register" bitfld.long 0x00 28.--31. " ADJTN ,Two complement number that can be used to adjust the duty cycle of VDDD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 23. " PWDN_BRNOUT ,Powers down the device after the DC-DC converter completes startup if a VDDD brownout occurs" "Powered up,Powered down" textline " " bitfld.long 0x00 22. " DIS_STEPPING ,Disables the default behavior of the voltage stepping algorithm" "No,Yes" bitfld.long 0x00 21. " EN_LINREG ,Enables the VDDD linear regulator converter when the switching converter is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " DIS_FET ,Disable the VDDD switching converter output" "No,Yes" bitfld.long 0x00 16.--17. " LINREG_OFFSET ,Number of 25mV steps between linear regulator output voltage and switching converter target" "0 steps,1 step above,1 step below,1 step below" textline " " bitfld.long 0x00 8.--10. " BO_OFFSET ,Brownout voltage offset in 25mV steps below the TRG value" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x00 0.--4. " TRG ,Voltage level of the VDDD supply" "0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1.0V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,1.475V,1.5V,1.525V,1.55V,1.575V" group.long 0x50++0x03 line.long 0x00 "HW_POWER_VDDACTRL,VDDA Supply Targets and Brownouts Control Register" bitfld.long 0x00 19. " PWDN_BRNOUT ,Powers down the device after the DC-DC converter completes startup if a VDDA brownout occurs" "Powered up,Powered down" bitfld.long 0x00 18. " DIS_STEPPING ,Disables the default behavior of the voltage stepping algorithm when the TRG field is updated" "No,Yes" textline " " bitfld.long 0x00 17. " EN_LINREG ,Enables the VDDA linear regulator converter when the switching converter is active" "Disabled,Enabled" bitfld.long 0x00 16. " DIS_FET ,Disable the VDDA switching converter output" "No,Yes" textline " " bitfld.long 0x00 12.--13. " LINREG_OFFSET ,Number of 25mV steps between linear regulator output voltage and switching converter target" "0 steps,1 step above,1 step below,1 step below" bitfld.long 0x00 8.--10. " BO_OFFSET ,Brownout voltage offset in 25mV steps below the TRG value" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" textline " " bitfld.long 0x00 0.--4. " TRG ,Voltage level of the VDDD supply" "1.5V,1.525V,1.55V,1.575V,1.6V,1.625V,1.65V,1.675V,1.7V,1.725V,1.75V,1.775V,1.8V,1.825V,1.85V,1.875V,1.9V,1.925V,1.95V,1.975V,2.0V,2.025V,2.05V,2.075V,2.1V,2.125V,2.15V,2.175V,2.2V,2.225V,2.25V,2.275V" group.long 0x60++0x03 line.long 0x00 "HW_POWER_VDDIOCTRL,VDDIO Supply Targets and Brownouts Control Register" bitfld.long 0x00 20.--23. " ADJTN ,Two complement number that can be used to adjust the duty cycle of VDDD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18. " PWDN_BRNOUT ,Powers down the device after the DC-DC converter completes startup if a VDDD brownout occurs" "Powered up,Powered down" textline " " bitfld.long 0x00 17. " DIS_STEPPING ,Disables the default behavior of the voltage stepping algorithm" "No,Yes" bitfld.long 0x00 16. " DIS_FET ,Disable the VDDD switching converter output" "No,Yes" textline " " bitfld.long 0x00 12.--13. " LINREG_OFFSET ,Number of 25mV steps between linear regulator output voltage and switching converter target" "0 steps,1 step above,1 step below,1 step below" bitfld.long 0x00 8.--10. " BO_OFFSET ,Brownout voltage offset in 25mV steps below the TRG value" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" textline " " bitfld.long 0x00 0.--4. " TRG ,Voltage level of the VDDD supply" "2.8V,2.825V,2.85V,2.875V,2.9V,2.925V,2.95V,2.975V,3.0V,3.025V,3.05V,3.075V,3.1V,3.125V,3.15V,3.175V,3.2V,3.225V,3.25V,3.275V,3.3V,3.325V,3.35V,3.375V,3.4V,3.425V,3.45V,3.475V,3.5V,3.525V,3.55V,3.575V" group.long 0x70++0x03 line.long 0x00 "HW_POWER_VDDMEMCTRL,VDDMEM Supply Targets Control Register" bitfld.long 0x00 10. " PULLDOWN_ACTIVE ,Activates pulldown on external memory supply" "Not active,Active" bitfld.long 0x00 9. " EN_ILIMIT ,Controls the inrush limit (10mA) for the memory supply voltage" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " EN_LINREG ,Enables the regulator that creates the external memory supply voltage" "Disabled,Enabled" bitfld.long 0x00 0.--4. " TRG ,Voltage level of the VDDD supply" "1.7V,1.75V,1.8V,1.85V,1.9V,1.95V,2.0V,2.05V,2.1V,2.15V,2.2V,2.25V,2.3V,2.35V,2.4V,2.45V,2.5V,3.55V,2.6V,2.65V,2.7V,2.75V,2.8V,2.85V,2.9V,2.95V,3.0V,3.05V,3.1V,3.15V,3.2V,3.25V" width 23. group.long 0x80++0x03 line.long 0x00 "HW_POWER_DCDC4P2,DC-DC Converter 4.2V Control Register" bitfld.long 0x00 28.--31. " DROPOUT_CTRL ,Adjusts the behavior of the dcdc converter and 4.2V regulation circuit" "25mV DCDC_4P2 regardless of Battery voltage,25mV DCDC_4P2 or DCDC_BATT,25mV VDD4P2 or BATTERY,25mV VDD4P2 or BATTERY,50mV DCDC_4P2 regardless of Battery voltage,50mV DCDC_4P2 or DCDC_BATT,50mV VDD4P2 or BATTERY,50mV VDD4P2 or BATTERY,100mV DCDC_4P2 regardless of Battery voltage,100mV DCDC_4P2 or DCDC_BATT,100mV VDD4P2 or BATTERY,100mV VDD4P2 or BATTERY,200mV DCDC_4P2 regardless of Battery voltage,200mV DCDC_4P2 or DCDC_BATT,200mV VDD4P2 or BATTERY,200mV VDD4P2 or BATTERY" textline " " bitfld.long 0x00 24.--25. " ISTEAL_THRESH ,ISTEAL_THRESH" "0,1,2,3" bitfld.long 0x00 23. " ENABLE_4P2 ,Enables the DCDC_4P2 regulation circuitry" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " ENABLE_DCDC ,Enable the dcdc converter to use the DCDC_4P2 pin as a power source" "Disabled,Enabled" bitfld.long 0x00 21. " HYST_DIR ,Enable hysteresis in analog comparator" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " HYST_THRESH ,Increase the threshold detection for DCDC_4P2/BATTERY analog comparator" "Not increased,Increased" bitfld.long 0x00 16.--18. " TRG ,Regulation voltage of the DCDC_4P2 pin" "4.2V,4.1V,4.0V,3.9V,Battery,Battery,Battery,Battery" textline " " bitfld.long 0x00 8.--12. " BO ,rownout voltage in 25mV steps for the DCDC_4P2 pin" "3.6V,3.625V,3.65V,3.675V,3.7V,3.725V,3.75V,3.775V,3.8V,3.825V,3.85V,3.875V,3.9V,3.925V,3.95V,3.975V,4.0V,4.025V,4.05V,4.075V,4.1V,4.125V,4.15V,4.175V,4.2V,4.225V,4.25V,4.275V,4.3V,4.325V,4.35V,4.375V" textline " " bitfld.long 0x00 0.--4. " CMPTRIP ,Sets the trip point for the comparison between the DCDC_4P2 and BATTERY pin" "DCDC_4P2 pin >= 0.85 * BATTERY pin,DCDC_4P2 pin >= 0.86 * BATTERY pin,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DCDC_4P2 pin >= BATTERY pin,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DCDC_4P2 pin >= 1.05 * BATTERY pin" width 23. group.long 0x90++0x03 line.long 0x00 "HW_POWER_MISC,DC-DC Miscellaneous Register" bitfld.long 0x00 4.--6. " FREQSEL ,This register will select the PLL-based frequency that the dcdc uses when SEL_PLLCLK is set high" "Reserved,20MHz,24MHz,19.2MHz,14.4MHz,18MHz,21.6MHz,17.28MHz" bitfld.long 0x00 2. " DELAY_TIMING ,This bit delays the timing of the output fets in the switching dcdc converter" "Not delayed,Delayed" textline " " bitfld.long 0x00 0. " SEL_PLLCLK ,This bit selects the source of the clock used for the DC-DC converter" "24MHz clock,PLL clock" group.long 0xa0++0x03 line.long 0x00 "HW_POWER_DCLIMITS,DC-DC Duty Cycle Limits Control Register" hexmask.long.byte 0x00 8.--14. 1. " POSLIMIT_BUCK ,Upper limit duty cycle limit in DC-DC converter" hexmask.long.byte 0x00 0.--6. 1. " NEGLIMIT ,Negative duty cycle limit of DC-DC converter" group.long 0xb0++0x0f line.long 0x00 "HW_POWER_LOOPCTRL,Converter Loop Behavior Control Register" bitfld.long 0x00 20. " TOGGLE_DIF ,Enable supply stepping to change only after the differential control loop has toggled as well" "Disabled,Enabled" bitfld.long 0x00 19. " HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "Not inverted,Inverted" textline " " bitfld.long 0x00 18. " EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparator" "Disabled,Enabled" bitfld.long 0x00 17. " EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " CM_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "Not increased,Increased" bitfld.long 0x00 15. " DF_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "Not increased,Increased" textline " " bitfld.long 0x00 14. " RCSCALE_THRESH ,Increase the threshold detection for RC scale circuit" "Not increased,Increased" bitfld.long 0x00 12.--13. " EN_RCSCALE ,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "Disabled,2x increase,4x increase,8x increase" textline " " bitfld.long 0x00 8.--10. " DC_FF ,Two complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--7. " DC_R ,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--1. " DC_C ,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter" "Maximum,Decrease ratio 2x,Decrease ratio 4x,Lowest ratio" line.long 0x04 "HW_POWER_LOOPCTRL_SET,Converter Loop Behavior Control Set Register" bitfld.long 0x04 20. " TOGGLE_DIF ,Enable supply stepping to change only after the differential control loop has toggled as well" "No effect,Set" bitfld.long 0x04 19. " HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "No effect,Set" textline " " bitfld.long 0x04 18. " EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparator" "No effect,Set" bitfld.long 0x04 17. " EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "No effect,Set" textline " " bitfld.long 0x04 16. " CM_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "No effect,Set" bitfld.long 0x04 15. " DF_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "No effect,Set" textline " " bitfld.long 0x04 14. " RCSCALE_THRESH ,Increase the threshold detection for RC scale circuit" "No effect,Set" bitfld.long 0x04 12.--13. " EN_RCSCALE ,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "Disabled,2x increase,4x increase,8x increase" textline " " bitfld.long 0x04 8.--10. " DC_FF ,Two complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--7. " DC_R ,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 0.--1. " DC_C ,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter" "Maximum,Decrease ratio 2x,Decrease ratio 4x,Lowest ratio" line.long 0x08 "HW_POWER_LOOPCTRL_CLR,Converter Loop Behavior Control Clear Register" bitfld.long 0x08 20. " TOGGLE_DIF ,Enable supply stepping to change only after the differential control loop has toggled as well" "No effect,Clear" bitfld.long 0x08 19. " HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "No effect,Clear" textline " " bitfld.long 0x08 18. " EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparator" "No effect,Clear" bitfld.long 0x08 17. " EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "No effect,Clear" textline " " bitfld.long 0x08 16. " CM_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "No effect,Clear" bitfld.long 0x08 15. " DF_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "No effect,Clear" textline " " bitfld.long 0x08 14. " RCSCALE_THRESH ,Increase the threshold detection for RC scale circuit" "No effect,Clear" bitfld.long 0x08 12.--13. " EN_RCSCALE ,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "Disabled,2x increase,4x increase,8x increase" textline " " bitfld.long 0x08 8.--10. " DC_FF ,Two complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--7. " DC_R ,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 0.--1. " DC_C ,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter" "Maximum,Decrease ratio 2x,Decrease ratio 4x,Lowest ratio" line.long 0x0c "HW_POWER_LOOPCTRL_TOG,Converter Loop Behavior Control Toggle Register" bitfld.long 0x0c 20. " TOGGLE_DIF ,Enable supply stepping to change only after the differential control loop has toggled as well" "Not toggle,Toggle" bitfld.long 0x0c 19. " HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparator" "Not toggle,Toggle" bitfld.long 0x0c 17. " EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " CM_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "Not toggle,Toggle" bitfld.long 0x0c 15. " DF_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " RCSCALE_THRESH ,Increase the threshold detection for RC scale circuit" "Not toggle,Toggle" bitfld.long 0x0c 12.--13. " EN_RCSCALE ,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "Disabled,2x increase,4x increase,8x increase" textline " " bitfld.long 0x0c 8.--10. " DC_FF ,Two complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 4.--7. " DC_R ,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0c 0.--1. " DC_C ,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter" "Maximum,Decrease ratio 2x,Decrease ratio 4x,Lowest ratio" group.long 0xc0++0x03 line.long 0x00 "HW_POWER_STS,Power Subsystem Status Register" bitfld.long 0x00 29. " PWRUP_SOURCE3 ,Determine if five volts was active when the dcdc converter powerup sequence was complete" "Not active,Active" bitfld.long 0x00 28. " PWRUP_SOURCE2 ,Determine if rtc wakeup was active when the dcdc converter powerup sequence was complete" "Not active,Active" textline " " bitfld.long 0x00 25. " PWRUP_SOURCE1 ,Determine if high level pswitch voltage was active when the dcdc converter powerup sequence was complete" "Not active,Active" bitfld.long 0x00 24. " PWRUP_SOURCE0 ,Determine if midlevel pswitch voltage was active when the dcdc converter powerup sequence was complete" "Not active,Active" textline " " bitfld.long 0x00 21. " PSWITCH1 ,PSWITCH pin is above 1.75V" "Below,Above" bitfld.long 0x00 20. " PSWITCH0 ,PSWITCH pin is above 0.8V" "Below,Above" textline " " bitfld.long 0x00 17. " AVALID_STATUS ,Indicates VBus is valid for a A-peripheral" "Not valid,Valid" bitfld.long 0x00 16. " BVALID_STATUS ,Indicates VBus is valid for a B-peripheral" "Not valid,Valid" textline " " bitfld.long 0x00 15. " VBUSVALID_STATUS ,VBus valid for USB OTG" "Not valid,Valid" bitfld.long 0x00 14. " SESSEND_STATUS ,Session End for USB OTG" "Not ended,Ended" textline " " bitfld.long 0x00 13. " BATT_BO ,Output of battery brownout comparator" "0,1" bitfld.long 0x00 12. " VDD5V_FAULT ,Battery charging fault status" "Not fault,Fault" textline " " bitfld.long 0x00 11. " CHRGSTS ,Battery charging status" "Not charging,Charging" bitfld.long 0x00 10. " DCDC_4P2_BO ,Output of the brownout comparator on the DCDC_4P2 pin" "0,1" textline " " bitfld.long 0x00 8. " VDDIO_BO ,Output of VDDIO brownout comparator" "Not detected,Detected" bitfld.long 0x00 7. " VDDA_BO ,Output of VDDA brownout comparator" "Not detected,Detected" textline " " bitfld.long 0x00 6. " VDDD_BO ,Output of VDDD brownout comparator" "Not detected,Detected" bitfld.long 0x00 5. " VDD5V_GT_VDDIO ,Indicates the voltage on the VDD5V pin is higher than VDDIO by a Vt voltage" "Not higher,Higher" textline " " bitfld.long 0x00 4. " VDD5V_DROOP ,Indicates the voltage on the VDD5V pin is below the VBUSDROOP_TRSH defined in the 5VCTRL register" "Not below,Below" bitfld.long 0x00 3. " AVALID ,Indicates VBus is above the VA_SESS_VLD threshold" "Not above,Above" textline " " bitfld.long 0x00 2. " BVALID ,Indicates VBus is above the VB_SESS_VLD threshold" "Not above,Above" bitfld.long 0x00 1. " VBUSVALID ,Accurate detection of the presence of 5v power" "Not present,Present" textline " " bitfld.long 0x00 0. " SESSEND ,Indicates VBus is below the VB_SESS_END threshold" "Not below,Below" group.long 0xd0++0x0f line.long 0x00 "HW_POWER_SPEED,Transistor Speed Control and Status Register" hexmask.long.byte 0x00 16.--23. 1. " STATUS ,Result from the speed sensor" bitfld.long 0x00 0.--1. " CTRL ,Speed Control bits" "Sensor off,Enabled,Reserved,Measurement enabled" line.long 0x04 "HW_POWER_SPEED_SET,Transistor Speed Control and Status Set Register" hexmask.long.byte 0x04 16.--23. 1. " STATUS ,Result from the speed sensor" bitfld.long 0x04 0.--1. " CTRL ,Speed Control bits" "Sensor off,Enabled,Reserved,Measurement enabled" line.long 0x08 "HW_POWER_SPEED_CLR,Transistor Speed Control and Status Clear Register" hexmask.long.byte 0x08 16.--23. 1. " STATUS ,Result from the speed sensor" bitfld.long 0x08 0.--1. " CTRL ,Speed Control bits" "Sensor off,Enabled,Reserved,Measurement enabled" line.long 0x0c "HW_POWER_SPEED_TOG,Transistor Speed Control and Status Toggle Register" hexmask.long.byte 0x0c 16.--23. 1. " STATUS ,Result from the speed sensor" bitfld.long 0x0c 0.--1. " CTRL ,Speed Control bits" "Sensor off,Enabled,Reserved,Measurement enabled" group.long 0xe0++0x03 line.long 0x00 "HW_POWER_BATTMONITOR,Battery Level Monitor Register" hexmask.long.word 0x00 16.--25. 1. " BATT_VAL ,Battery voltage" bitfld.long 0x00 10. " EN_BATADJ ,Enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " PWDN_BATTBRNOUT ,Powers down the device after the DC-DC converter completes startup if a battery brownout occurs" "Powered up,Powered down" bitfld.long 0x00 8. " BRWNOUT_PWD ,Power-down circuitry for battery brownout detection" "Powered up,Powered down" textline " " bitfld.long 0x00 0.--4. " BRWNOUT_LVL ,BRWNOUT_LVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x2f line.long 0x00 "HW_POWER_RESET,Power Module Reset Register" hexmask.long.word 0x00 16.--31. 1. " UNLOCK ,Write 0x3E77 to unlock this register and allow other bits to be changed" bitfld.long 0x00 1. " PWD_OFF ,Disable all paths to power off the chip except the watchdog timer" "No,Yes" textline " " bitfld.long 0x00 0. " PWD ,Powers down the chip" "Powered up,Powered down" line.long 0x04 "HW_POWER_RESET_SET,Power Module Reset Set Register" hexmask.long.word 0x04 16.--31. 1. " UNLOCK ,Write 0x3E77 to unlock this register and allow other bits to be changed" bitfld.long 0x04 1. " PWD_OFF ,Disable all paths to power off the chip except the watchdog timer" "No effect,Set" textline " " bitfld.long 0x04 0. " PWD ,Powers down the chip" "No effect,Set" line.long 0x08 "HW_POWER_RESET_CLR,Power Module Reset Clear Register" hexmask.long.word 0x08 16.--31. 1. " UNLOCK ,Write 0x3E77 to unlock this register and allow other bits to be changed" bitfld.long 0x08 1. " PWD_OFF ,Disable all paths to power off the chip except the watchdog timer" "No effect,Clear" textline " " bitfld.long 0x08 0. " PWD ,Powers down the chip" "No effect,Clear" line.long 0x0c "HW_POWER_RESET_TOG,Power Module Reset Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " UNLOCK ,Write 0x3E77 to unlock this register and allow other bits to be changed" bitfld.long 0x0c 1. " PWD_OFF ,Disable all paths to power off the chip except the watchdog timer" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " PWD ,Powers down the chip" "Not toggle,Toggle" line.long 0x10 "HW_POWER_DEBUG,Power Module Debug Register" bitfld.long 0x10 3. " VBUSVALIDPIOLOCK ,VBUSVALIDPIOLOCK" "0,1" bitfld.long 0x10 2. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "0,1" textline " " bitfld.long 0x10 1. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "0,1" bitfld.long 0x10 0. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "0,1" line.long 0x14 "HW_POWER_DEBUG_SET,Power Module Debug Set Register" bitfld.long 0x14 3. " VBUSVALIDPIOLOCK ,VBUSVALIDPIOLOCK" "No effect,Set" bitfld.long 0x14 2. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Set" textline " " bitfld.long 0x14 1. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Set" bitfld.long 0x14 0. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Set" line.long 0x18 "HW_POWER_DEBUG_CLR,Power Module Debug Clear Register" bitfld.long 0x18 3. " VBUSVALIDPIOLOCK ,VBUSVALIDPIOLOCK" "No effect,Clear" bitfld.long 0x18 2. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Clear" textline " " bitfld.long 0x18 1. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Clear" bitfld.long 0x18 0. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Clear" line.long 0x1c "HW_POWER_DEBUG_TOG,Power Module Debug Toggle Register" bitfld.long 0x1c 3. " VBUSVALIDPIOLOCK ,VBUSVALIDPIOLOCK" "Not toggle,Toggle" bitfld.long 0x1c 2. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "Not toggle,Toggle" bitfld.long 0x1c 0. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "Not toggle,Toggle" line.long 0x20 "HW_POWER_SPECIAL,Power Module Special Register" line.long 0x24 "HW_POWER_SPECIAL_SET,Power Module Special Set Register" line.long 0x28 "HW_POWER_SPECIAL_CLR,Power Module Special Clear Register" line.long 0x2c "HW_POWER_SPECIAL_TOG,Power Module Special Toggle Register" rgroup.long 0x130++0x03 line.long 0x00 "HW_POWER_VERSION,Power Module Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the STEP field of the RTL version" width 0x0b tree.end tree "LRADC (Low-Resolution ADC and Touch-Screen Interface)" base asd:0x80050000 width 21. group.long 0x00++0x2f line.long 0x00 "HW_LRADC_CTRL0,LRADC Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset the entire LRADC block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clock to block" "Normal,Gated off" textline " " bitfld.long 0x00 21. " ONCHIP_GROUNDREF ,Enable use the on-chip ground as reference for conversions" "Disabled,Enabled" bitfld.long 0x00 20. " TOUCH_DET_EN ,Enable touch panel touch detector" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " YMINUS_EN ,Enable yminus pull down on the LRADC5 pin" "Disabled,Enabled" bitfld.long 0x00 18. " XMINUS_EN ,Enable xminus pull down on the LRADC5 pin" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " YPLUS_EN ,Enable yplus pull up on the LRADC3 pin" "Disabled,Enabled" bitfld.long 0x00 16. " XPLUS_EN ,Enable xplus pull up on the LRADC3 pin" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SCHEDULE7 ,Schedules the corresponding LRADC channel 7 to be converted" "Not converted,Converted" bitfld.long 0x00 6. " SCHEDULE6 ,Schedules the corresponding LRADC channel 6 to be converted" "Not converted,Converted" textline " " bitfld.long 0x00 5. " SCHEDULE5 ,Schedules the corresponding LRADC channel 5 to be converted" "Not converted,Converted" bitfld.long 0x00 4. " SCHEDULE4 ,Schedules the corresponding LRADC channel 4 to be converted" "Not converted,Converted" textline " " bitfld.long 0x00 3. " SCHEDULE3 ,Schedules the corresponding LRADC channel 3 to be converted" "Not converted,Converted" bitfld.long 0x00 2. " SCHEDULE2 ,Schedules the corresponding LRADC channel 2 to be converted" "Not converted,Converted" textline " " bitfld.long 0x00 1. " SCHEDULE1 ,Schedules the corresponding LRADC channel 1 to be converted" "Not converted,Converted" bitfld.long 0x00 0. " SCHEDULE0 ,Schedules the corresponding LRADC channel 0 to be converted" "Not converted,Converted" line.long 0x04 "HW_LRADC_CTRL0_SET,LRADC Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset the entire LRADC block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate off the clock to block" "No effect,Set" textline " " bitfld.long 0x04 21. " ONCHIP_GROUNDREF ,Enable use the on-chip ground as reference for conversions" "No effect,Set" bitfld.long 0x04 20. " TOUCH_DET_EN ,Enable touch panel touch detector" "No effect,Set" textline " " bitfld.long 0x04 19. " YMINUS_EN ,Enable yminus pull down on the LRADC5 pin" "No effect,Set" bitfld.long 0x04 18. " XMINUS_EN ,Enable xminus pull down on the LRADC5 pin" "No effect,Set" textline " " bitfld.long 0x04 17. " YPLUS_EN ,Enable yplus pull up on the LRADC3 pin" "No effect,Set" bitfld.long 0x04 16. " XPLUS_EN ,Enable xplus pull up on the LRADC3 pin" "No effect,Set" textline " " bitfld.long 0x04 7. " SCHEDULE7 ,Schedules the corresponding LRADC channel 7 to be converted" "No effect,Set" bitfld.long 0x04 6. " SCHEDULE6 ,Schedules the corresponding LRADC channel 6 to be converted" "No effect,Set" textline " " bitfld.long 0x04 5. " SCHEDULE5 ,Schedules the corresponding LRADC channel 5 to be converted" "No effect,Set" bitfld.long 0x04 4. " SCHEDULE4 ,Schedules the corresponding LRADC channel 4 to be converted" "No effect,Set" textline " " bitfld.long 0x04 3. " SCHEDULE3 ,Schedules the corresponding LRADC channel 3 to be converted" "No effect,Set" bitfld.long 0x04 2. " SCHEDULE2 ,Schedules the corresponding LRADC channel 2 to be converted" "No effect,Set" textline " " bitfld.long 0x04 1. " SCHEDULE1 ,Schedules the corresponding LRADC channel 1 to be converted" "No effect,Set" bitfld.long 0x04 0. " SCHEDULE0 ,Schedules the corresponding LRADC channel 0 to be converted" "No effect,Set" line.long 0x08 "HW_LRADC_CTRL0_CLR,LRADC Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset the entire LRADC block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate off the clock to block" "No effect,Clear" textline " " bitfld.long 0x08 21. " ONCHIP_GROUNDREF ,Enable use the on-chip ground as reference for conversions" "No effect,Clear" bitfld.long 0x08 20. " TOUCH_DET_EN ,Enable touch panel touch detector" "No effect,Clear" textline " " bitfld.long 0x08 19. " YMINUS_EN ,Enable yminus pull down on the LRADC5 pin" "No effect,Clear" bitfld.long 0x08 18. " XMINUS_EN ,Enable xminus pull down on the LRADC5 pin" "No effect,Clear" textline " " bitfld.long 0x08 17. " YPLUS_EN ,Enable yplus pull up on the LRADC3 pin" "No effect,Clear" bitfld.long 0x08 16. " XPLUS_EN ,Enable xplus pull up on the LRADC3 pin" "No effect,Clear" textline " " bitfld.long 0x08 7. " SCHEDULE7 ,Schedules the corresponding LRADC channel 7 to be converted" "No effect,Clear" bitfld.long 0x08 6. " SCHEDULE6 ,Schedules the corresponding LRADC channel 6 to be converted" "No effect,Clear" textline " " bitfld.long 0x08 5. " SCHEDULE5 ,Schedules the corresponding LRADC channel 5 to be converted" "No effect,Clear" bitfld.long 0x08 4. " SCHEDULE4 ,Schedules the corresponding LRADC channel 4 to be converted" "No effect,Clear" textline " " bitfld.long 0x08 3. " SCHEDULE3 ,Schedules the corresponding LRADC channel 3 to be converted" "No effect,Clear" bitfld.long 0x08 2. " SCHEDULE2 ,Schedules the corresponding LRADC channel 2 to be converted" "No effect,Clear" textline " " bitfld.long 0x08 1. " SCHEDULE1 ,Schedules the corresponding LRADC channel 1 to be converted" "No effect,Clear" bitfld.long 0x08 0. " SCHEDULE0 ,Schedules the corresponding LRADC channel 0 to be converted" "No effect,Clear" line.long 0x0c "HW_LRADC_CTRL0_TOG,LRADC Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset the entire LRADC block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate off the clock to block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " ONCHIP_GROUNDREF ,Enable use the on-chip ground as reference for conversions" "Not toggle,Toggle" bitfld.long 0x0c 20. " TOUCH_DET_EN ,Enable touch panel touch detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " YMINUS_EN ,Enable yminus pull down on the LRADC5 pin" "Not toggle,Toggle" bitfld.long 0x0c 18. " XMINUS_EN ,Enable xminus pull down on the LRADC5 pin" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " YPLUS_EN ,Enable yplus pull up on the LRADC3 pin" "Not toggle,Toggle" bitfld.long 0x0c 16. " XPLUS_EN ,Enable xplus pull up on the LRADC3 pin" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " SCHEDULE7 ,Schedules the corresponding LRADC channel 7 to be converted" "Not toggle,Toggle" bitfld.long 0x0c 6. " SCHEDULE6 ,Schedules the corresponding LRADC channel 6 to be converted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " SCHEDULE5 ,Schedules the corresponding LRADC channel 5 to be converted" "Not toggle,Toggle" bitfld.long 0x0c 4. " SCHEDULE4 ,Schedules the corresponding LRADC channel 4 to be converted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " SCHEDULE3 ,Schedules the corresponding LRADC channel 3 to be converted" "Not toggle,Toggle" bitfld.long 0x0c 2. " SCHEDULE2 ,Schedules the corresponding LRADC channel 2 to be converted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " SCHEDULE1 ,Schedules the corresponding LRADC channel 1 to be converted" "Not toggle,Toggle" bitfld.long 0x0c 0. " SCHEDULE0 ,Schedules the corresponding LRADC channel 0 to be converted" "Not toggle,Toggle" line.long 0x10 "HW_LRADC_CTRL1,LRADC Control Register 1" bitfld.long 0x10 24. " TOUCH_DET_IRQ_EN ,Enable an interrupt for the touch detector comparator" "Disabled,Enabled" bitfld.long 0x10 23. " LRADC7_IRQ_EN ,Enable an interrupt for channel 7 (BATT) conversions" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " LRADC6_IRQ_EN ,Enable an interrupt for channel 6 (VddIO) conversions" "Disabled,Enabled" bitfld.long 0x10 21. " LRADC5_IRQ_EN ,Enable an interrupt for channel 5 conversions" "Disabled,Enabled" textline " " bitfld.long 0x10 20. " LRADC4_IRQ_EN ,Enable an interrupt for channel 4 conversions" "Disabled,Enabled" bitfld.long 0x10 19. " LRADC3_IRQ_EN ,Enable an interrupt for channel 3 conversions" "Disabled,Enabled" textline " " bitfld.long 0x10 18. " LRADC2_IRQ_EN ,Enable an interrupt for channel 2 conversions" "Disabled,Enabled" bitfld.long 0x10 17. " LRADC1_IRQ_EN ,Enable an interrupt for channel 1 conversions" "Disabled,Enabled" textline " " bitfld.long 0x10 16. " LRADC0_IRQ_EN ,Enable an interrupt for channel 0 conversions" "Disabled,Enabled" bitfld.long 0x10 8. " TOUCH_DET_IRQ ,Detection of a touch condition in the touch panel attached to LRADC2-LRADC5" "Cleared,Pending" textline " " bitfld.long 0x10 7. " LRADC7_IRQ ,Completion of a scheduled conversion for channel 7(BATT)" "Cleared,Pending" bitfld.long 0x10 6. " LRADC6_IRQ ,Completion of a scheduled conversion for channel 6(VDDIO)" "Cleared,Pending" textline " " bitfld.long 0x10 5. " LRADC5_IRQ ,Completion of a scheduled conversion for channel 5" "Cleared,Pending" bitfld.long 0x10 4. " LRADC4_IRQ ,Completion of a scheduled conversion for channel 4" "Cleared,Pending" textline " " bitfld.long 0x10 3. " LRADC3_IRQ ,Completion of a scheduled conversion for channel 3" "Cleared,Pending" bitfld.long 0x10 2. " LRADC2_IRQ ,Completion of a scheduled conversion for channel 2" "Cleared,Pending" textline " " bitfld.long 0x10 1. " LRADC1_IRQ ,Completion of a scheduled conversion for channel 1" "Cleared,Pending" bitfld.long 0x10 0. " LRADC0_IRQ ,Completion of a scheduled conversion for channel 0" "Cleared,Pending" line.long 0x14 "HW_LRADC_CTRL1_SET,LRADC Control Set Register 1" bitfld.long 0x14 24. " TOUCH_DET_IRQ_EN ,Enable an interrupt for the touch detector comparator" "No effect,Set" bitfld.long 0x14 23. " LRADC7_IRQ_EN ,Enable an interrupt for channel 7 (BATT) conversions" "No effect,Set" textline " " bitfld.long 0x14 22. " LRADC6_IRQ_EN ,Enable an interrupt for channel 6 (VddIO) conversions" "No effect,Set" bitfld.long 0x14 21. " LRADC5_IRQ_EN ,Enable an interrupt for channel 5 conversions" "No effect,Set" textline " " bitfld.long 0x14 20. " LRADC4_IRQ_EN ,Enable an interrupt for channel 4 conversions" "No effect,Set" bitfld.long 0x14 19. " LRADC3_IRQ_EN ,Enable an interrupt for channel 3 conversions" "No effect,Set" textline " " bitfld.long 0x14 18. " LRADC2_IRQ_EN ,Enable an interrupt for channel 2 conversions" "No effect,Set" bitfld.long 0x14 17. " LRADC1_IRQ_EN ,Enable an interrupt for channel 1 conversions" "No effect,Set" textline " " bitfld.long 0x14 16. " LRADC0_IRQ_EN ,Enable an interrupt for channel 0 conversions" "No effect,Set" bitfld.long 0x14 8. " TOUCH_DET_IRQ ,Detection of a touch condition in the touch panel attached to LRADC2-LRADC5" "No effect,Set" textline " " bitfld.long 0x14 7. " LRADC7_IRQ ,Completion of a scheduled conversion for channel 7(BATT)" "No effect,Set" bitfld.long 0x14 6. " LRADC6_IRQ ,Completion of a scheduled conversion for channel 6(VDDIO)" "No effect,Set" textline " " bitfld.long 0x14 5. " LRADC5_IRQ ,Completion of a scheduled conversion for channel 5" "No effect,Set" bitfld.long 0x14 4. " LRADC4_IRQ ,Completion of a scheduled conversion for channel 4" "No effect,Set" textline " " bitfld.long 0x14 3. " LRADC3_IRQ ,Completion of a scheduled conversion for channel 3" "No effect,Set" bitfld.long 0x14 2. " LRADC2_IRQ ,Completion of a scheduled conversion for channel 2" "No effect,Set" textline " " bitfld.long 0x14 1. " LRADC1_IRQ ,Completion of a scheduled conversion for channel 1" "No effect,Set" bitfld.long 0x14 0. " LRADC0_IRQ ,Completion of a scheduled conversion for channel 0" "No effect,Set" line.long 0x18 "HW_LRADC_CTRL1_CLR,LRADC Control Clear Register 1" bitfld.long 0x18 24. " TOUCH_DET_IRQ_EN ,Enable an interrupt for the touch detector comparator" "No effect,Clear" bitfld.long 0x18 23. " LRADC7_IRQ_EN ,Enable an interrupt for channel 7 (BATT) conversions" "No effect,Clear" textline " " bitfld.long 0x18 22. " LRADC6_IRQ_EN ,Enable an interrupt for channel 6 (VddIO) conversions" "No effect,Clear" bitfld.long 0x18 21. " LRADC5_IRQ_EN ,Enable an interrupt for channel 5 conversions" "No effect,Clear" textline " " bitfld.long 0x18 20. " LRADC4_IRQ_EN ,Enable an interrupt for channel 4 conversions" "No effect,Clear" bitfld.long 0x18 19. " LRADC3_IRQ_EN ,Enable an interrupt for channel 3 conversions" "No effect,Clear" textline " " bitfld.long 0x18 18. " LRADC2_IRQ_EN ,Enable an interrupt for channel 2 conversions" "No effect,Clear" bitfld.long 0x18 17. " LRADC1_IRQ_EN ,Enable an interrupt for channel 1 conversions" "No effect,Clear" textline " " bitfld.long 0x18 16. " LRADC0_IRQ_EN ,Enable an interrupt for channel 0 conversions" "No effect,Clear" bitfld.long 0x18 8. " TOUCH_DET_IRQ ,Detection of a touch condition in the touch panel attached to LRADC2-LRADC5" "No effect,Clear" textline " " bitfld.long 0x18 7. " LRADC7_IRQ ,Completion of a scheduled conversion for channel 7(BATT)" "No effect,Clear" bitfld.long 0x18 6. " LRADC6_IRQ ,Completion of a scheduled conversion for channel 6(VDDIO)" "No effect,Clear" textline " " bitfld.long 0x18 5. " LRADC5_IRQ ,Completion of a scheduled conversion for channel 5" "No effect,Clear" bitfld.long 0x18 4. " LRADC4_IRQ ,Completion of a scheduled conversion for channel 4" "No effect,Clear" textline " " bitfld.long 0x18 3. " LRADC3_IRQ ,Completion of a scheduled conversion for channel 3" "No effect,Clear" bitfld.long 0x18 2. " LRADC2_IRQ ,Completion of a scheduled conversion for channel 2" "No effect,Clear" textline " " bitfld.long 0x18 1. " LRADC1_IRQ ,Completion of a scheduled conversion for channel 1" "No effect,Clear" bitfld.long 0x18 0. " LRADC0_IRQ ,Completion of a scheduled conversion for channel 0" "No effect,Clear" line.long 0x1c "HW_LRADC_CTRL1_TOG,LRADC Control Toggle Register 1" bitfld.long 0x1c 24. " TOUCH_DET_IRQ_EN ,Enable an interrupt for the touch detector comparator" "Not toggle,Toggle" bitfld.long 0x1c 23. " LRADC7_IRQ_EN ,Enable an interrupt for channel 7 (BATT) conversions" "Not toggle,Toggle" textline " " bitfld.long 0x1c 22. " LRADC6_IRQ_EN ,Enable an interrupt for channel 6 (VddIO) conversions" "Not toggle,Toggle" bitfld.long 0x1c 21. " LRADC5_IRQ_EN ,Enable an interrupt for channel 5 conversions" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20. " LRADC4_IRQ_EN ,Enable an interrupt for channel 4 conversions" "Not toggle,Toggle" bitfld.long 0x1c 19. " LRADC3_IRQ_EN ,Enable an interrupt for channel 3 conversions" "Not toggle,Toggle" textline " " bitfld.long 0x1c 18. " LRADC2_IRQ_EN ,Enable an interrupt for channel 2 conversions" "Not toggle,Toggle" bitfld.long 0x1c 17. " LRADC1_IRQ_EN ,Enable an interrupt for channel 1 conversions" "Not toggle,Toggle" textline " " bitfld.long 0x1c 16. " LRADC0_IRQ_EN ,Enable an interrupt for channel 0 conversions" "Not toggle,Toggle" bitfld.long 0x1c 8. " TOUCH_DET_IRQ ,Detection of a touch condition in the touch panel attached to LRADC2-LRADC5" "Not toggle,Toggle" textline " " bitfld.long 0x1c 7. " LRADC7_IRQ ,Completion of a scheduled conversion for channel 7(BATT)" "Not toggle,Toggle" bitfld.long 0x1c 6. " LRADC6_IRQ ,Completion of a scheduled conversion for channel 6(VDDIO)" "Not toggle,Toggle" textline " " bitfld.long 0x1c 5. " LRADC5_IRQ ,Completion of a scheduled conversion for channel 5" "Not toggle,Toggle" bitfld.long 0x1c 4. " LRADC4_IRQ ,Completion of a scheduled conversion for channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " LRADC3_IRQ ,Completion of a scheduled conversion for channel 3" "Not toggle,Toggle" bitfld.long 0x1c 2. " LRADC2_IRQ ,Completion of a scheduled conversion for channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " LRADC1_IRQ ,Completion of a scheduled conversion for channel 1" "Not toggle,Toggle" bitfld.long 0x1c 0. " LRADC0_IRQ ,Completion of a scheduled conversion for channel 0" "Not toggle,Toggle" line.long 0x20 "HW_LRADC_CTRL2,LRADC Control Register 2" bitfld.long 0x20 31. " DIV_BY_TWO7 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" bitfld.long 0x20 30. " DIV_BY_TWO6 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" textline " " bitfld.long 0x20 29. " DIV_BY_TWO5 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" bitfld.long 0x20 28. " DIV_BY_TWO4 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" textline " " bitfld.long 0x20 27. " DIV_BY_TWO3 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" bitfld.long 0x20 26. " DIV_BY_TWO2 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " DIV_BY_TWO1 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" bitfld.long 0x20 24. " DIV_BY_TWO0 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" textline " " bitfld.long 0x20 23. " BL_AMP_BYPASS ,The feedback control signal bypasses the gain of 4 stage" "No bypassed,Bypassed" bitfld.long 0x20 22. " BL_EN ,Enables the back light" "Disabled,Enabled" textline " " bitfld.long 0x20 21. " BL_MUX_SEL ,Pin for feedback control" "LRADC4,LRADC1" bitfld.long 0x20 16.--20. " BL_BRIGHTNESS ,Sets the voltage comparison level for the analog feedback control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x20 15. " TEMPSENSE_PWD ,PWD the tempsense block" "Enabled,Disabled" bitfld.long 0x20 12. " EXT_EN0 ,The mux amp is bypassed" "Bypassed,Not bypassed" textline " " bitfld.long 0x20 9. " TEMP_SENSOR_IEN1 ,Enable the current source onto LRADC1" "Disabled,Enabled" bitfld.long 0x20 8. " TEMP_SENSOR_IEN0 ,Enable the current source onto LRADC0" "Disabled,Enabled" textline " " bitfld.long 0x20 4.--7. " TEMP_ISRC1 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC1" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" bitfld.long 0x20 0.--3. " TEMP_ISRC0 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC0" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" line.long 0x24 "HW_LRADC_CTRL2_SET,LRADC Control Set Register 2" bitfld.long 0x24 31. " DIV_BY_TWO7 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" bitfld.long 0x24 30. " DIV_BY_TWO6 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" textline " " bitfld.long 0x24 29. " DIV_BY_TWO5 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" bitfld.long 0x24 28. " DIV_BY_TWO4 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" textline " " bitfld.long 0x24 27. " DIV_BY_TWO3 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" bitfld.long 0x24 26. " DIV_BY_TWO2 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" textline " " bitfld.long 0x24 25. " DIV_BY_TWO1 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" bitfld.long 0x24 24. " DIV_BY_TWO0 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" textline " " bitfld.long 0x24 23. " BL_AMP_BYPASS ,The feedback control signal bypasses the gain of 4 stage" "No effect,Set" bitfld.long 0x24 22. " BL_EN ,Enables the back light" "No effect,Set" textline " " bitfld.long 0x24 21. " BL_MUX_SEL ,Pin for feedback control" "No effect,Set" bitfld.long 0x24 16.--20. " BL_BRIGHTNESS ,Sets the voltage comparison level for the analog feedback control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x24 15. " TEMPSENSE_PWD ,PWD the tempsense block" "No effect,Set" bitfld.long 0x24 12. " EXT_EN0 ,The mux amp is bypassed" "No effect,Set" textline " " bitfld.long 0x24 9. " TEMP_SENSOR_IEN1 ,Enable the current source onto LRADC1" "No effect,Set" bitfld.long 0x24 8. " TEMP_SENSOR_IEN0 ,Enable the current source onto LRADC0" "No effect,Set" textline " " bitfld.long 0x24 4.--7. " TEMP_ISRC1 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC1" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" bitfld.long 0x24 0.--3. " TEMP_ISRC0 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC0" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" line.long 0x28 "HW_LRADC_CTRL2_CLR,LRADC Control Clear Register 2" bitfld.long 0x28 31. " DIV_BY_TWO7 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" bitfld.long 0x28 30. " DIV_BY_TWO6 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" textline " " bitfld.long 0x28 29. " DIV_BY_TWO5 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" bitfld.long 0x28 28. " DIV_BY_TWO4 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" textline " " bitfld.long 0x28 27. " DIV_BY_TWO3 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" bitfld.long 0x28 26. " DIV_BY_TWO2 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" textline " " bitfld.long 0x28 25. " DIV_BY_TWO1 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" bitfld.long 0x28 24. " DIV_BY_TWO0 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" textline " " bitfld.long 0x28 23. " BL_AMP_BYPASS ,The feedback control signal bypasses the gain of 4 stage" "No effect,Clear" bitfld.long 0x28 22. " BL_EN ,Enables the back light" "No effect,Clear" textline " " bitfld.long 0x28 21. " BL_MUX_SEL ,Pin for feedback control" "No effect,Clear" bitfld.long 0x28 16.--20. " BL_BRIGHTNESS ,Sets the voltage comparison level for the analog feedback control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x28 15. " TEMPSENSE_PWD ,PWD the tempsense block" "No effect,Clear" bitfld.long 0x28 12. " EXT_EN0 ,The mux amp is bypassed" "No effect,Clear" textline " " bitfld.long 0x28 9. " TEMP_SENSOR_IEN1 ,Enable the current source onto LRADC1" "No effect,Clear" bitfld.long 0x28 8. " TEMP_SENSOR_IEN0 ,Enable the current source onto LRADC0" "No effect,Clear" textline " " bitfld.long 0x28 4.--7. " TEMP_ISRC1 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC1" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" bitfld.long 0x28 0.--3. " TEMP_ISRC0 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC0" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" line.long 0x2c "HW_LRADC_CTRL2_TOG,LRADC Control Toggle Register 2" bitfld.long 0x2c 31. " DIV_BY_TWO7 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" bitfld.long 0x2c 30. " DIV_BY_TWO6 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " DIV_BY_TWO5 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" bitfld.long 0x2c 28. " DIV_BY_TWO4 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " DIV_BY_TWO3 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" bitfld.long 0x2c 26. " DIV_BY_TWO2 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " DIV_BY_TWO1 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" bitfld.long 0x2c 24. " DIV_BY_TWO0 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" textline " " bitfld.long 0x2c 23. " BL_AMP_BYPASS ,The feedback control signal bypasses the gain of 4 stage" "Not toggle,Toggle" bitfld.long 0x2c 22. " BL_EN ,Enables the back light" "Not toggle,Toggle" textline " " bitfld.long 0x2c 21. " BL_MUX_SEL ,Pin for feedback control" "Not toggle,Toggle" bitfld.long 0x2c 16.--20. " BL_BRIGHTNESS ,Sets the voltage comparison level for the analog feedback control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x2c 15. " TEMPSENSE_PWD ,PWD the tempsense block" "Not toggle,Toggle" bitfld.long 0x2c 12. " EXT_EN0 ,The mux amp is bypassed" "Not toggle,Toggle" textline " " bitfld.long 0x2c 9. " TEMP_SENSOR_IEN1 ,Enable the current source onto LRADC1" "Not toggle,Toggle" bitfld.long 0x2c 8. " TEMP_SENSOR_IEN0 ,Enable the current source onto LRADC0" "Not toggle,Toggle" textline " " bitfld.long 0x2c 4.--7. " TEMP_ISRC1 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC1" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" bitfld.long 0x2c 0.--3. " TEMP_ISRC0 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC0" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" if (((d.l(asd:(0x80050000+0x30)))&0x300)==0x0) ;CYCLE_TIME=00; group.long 0x30++0x0f line.long 0x00 "HW_LRADC_CTRL3,LRADC Control Register 3" bitfld.long 0x00 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x00 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not forced,Forced" textline " " bitfld.long 0x00 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not forced,Forced" bitfld.long 0x00 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x00 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,?..." bitfld.long 0x00 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No delay,Delayed" textline " " bitfld.long 0x00 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not inverted,Inverted" line.long 0x04 "HW_LRADC_CTRL3_SET,LRADC Control Set Register 3" bitfld.long 0x04 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x04 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Set" textline " " bitfld.long 0x04 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Set" bitfld.long 0x04 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x04 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,?..." bitfld.long 0x04 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Set" textline " " bitfld.long 0x04 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Set" line.long 0x08 "HW_LRADC_CTRL3_CLR,LRADC Control Clear Register 3" bitfld.long 0x08 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x08 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Clear" textline " " bitfld.long 0x08 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Clear" bitfld.long 0x08 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x08 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,?..." bitfld.long 0x08 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Clear" textline " " bitfld.long 0x08 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Clear" line.long 0x0c "HW_LRADC_CTRL3_TOG,LRADC Control Toggle Register 3" bitfld.long 0x0c 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x0c 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not toggle,Toggle" bitfld.long 0x0c 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x0c 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,?..." bitfld.long 0x0c 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not toggle,Toggle" elif (((d.l(asd:(0x80050000+0x30)))&0x300)==0x100) ;CYCLE_TIME=01; group.long 0x30++0x0f line.long 0x00 "HW_LRADC_CTRL3,LRADC Control Register 3" bitfld.long 0x00 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x00 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not forced,Forced" textline " " bitfld.long 0x00 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not forced,Forced" bitfld.long 0x00 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x00 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,?..." bitfld.long 0x00 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No delay,Delayed" textline " " bitfld.long 0x00 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not inverted,Inverted" line.long 0x04 "HW_LRADC_CTRL3_SET,LRADC Control Set Register 3" bitfld.long 0x04 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x04 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Set" textline " " bitfld.long 0x04 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Set" bitfld.long 0x04 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x04 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,?..." bitfld.long 0x04 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Set" textline " " bitfld.long 0x04 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Set" line.long 0x08 "HW_LRADC_CTRL3_CLR,LRADC Control Clear Register 3" bitfld.long 0x08 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x08 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Clear" textline " " bitfld.long 0x08 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Clear" bitfld.long 0x08 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x08 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,?..." bitfld.long 0x08 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Clear" textline " " bitfld.long 0x08 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Clear" line.long 0x0c "HW_LRADC_CTRL3_TOG,LRADC Control Toggle Register 3" bitfld.long 0x0c 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x0c 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not toggle,Toggle" bitfld.long 0x0c 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x0c 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,?..." bitfld.long 0x0c 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not toggle,Toggle" else group.long 0x30++0x0f line.long 0x00 "HW_LRADC_CTRL3,LRADC Control Register 3" bitfld.long 0x00 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x00 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not forced,Forced" textline " " bitfld.long 0x00 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not forced,Forced" bitfld.long 0x00 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x00 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,250ns" bitfld.long 0x00 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No delay,Delayed" textline " " bitfld.long 0x00 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not inverted,Inverted" line.long 0x04 "HW_LRADC_CTRL3_SET,LRADC Control Set Register 3" bitfld.long 0x04 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x04 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Set" textline " " bitfld.long 0x04 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Set" bitfld.long 0x04 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x04 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,250ns" bitfld.long 0x04 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Set" textline " " bitfld.long 0x04 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Set" line.long 0x08 "HW_LRADC_CTRL3_CLR,LRADC Control Clear Register 3" bitfld.long 0x08 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x08 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Clear" textline " " bitfld.long 0x08 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Clear" bitfld.long 0x08 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x08 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,250ns" bitfld.long 0x08 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Clear" textline " " bitfld.long 0x08 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Clear" line.long 0x0c "HW_LRADC_CTRL3_TOG,LRADC Control Toggle Register 3" bitfld.long 0x0c 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x0c 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not toggle,Toggle" bitfld.long 0x0c 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x0c 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,250ns" bitfld.long 0x0c 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not toggle,Toggle" endif rgroup.long 0x40++0x03 line.long 0x00 "HW_LRADC_STATUS,LRADC Status Register" bitfld.long 0x00 26. " TEMP1_PRESENT ,Temperature sensor 1 current source is present on the chip" "Not present,Present" bitfld.long 0x00 25. " TEMP0_PRESENT ,Temperature sensor 0 current source is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 24. " TOUCH_PANEL_PRESENT ,Touch panel controller function is present on the chip" "Not present,Present" bitfld.long 0x00 23. " CHANNEL7_PRESENT ,LRADC channel 7 converter function is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 22. " CHANNEL6_PRESENT ,LRADC channel 6 converter function is present on the chip" "Not present,Present" bitfld.long 0x00 21. " CHANNEL5_PRESENT ,LRADC channel 5 converter function is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 20. " CHANNEL4_PRESENT ,LRADC channel 4 converter function is present on the chip" "Not present,Present" bitfld.long 0x00 19. " CHANNEL3_PRESENT ,LRADC channel 3 converter function is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 18. " CHANNEL2_PRESENT ,LRADC channel 2 converter function is present on the chip" "Not present,Present" bitfld.long 0x00 17. " CHANNEL1_PRESENT ,LRADC channel 1 converter function is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 16. " CHANNEL0_PRESENT ,LRADC channel 0 converter function is present on the chip" "Not present,Present" bitfld.long 0x00 0. " TOUCH_DETECT_RAW ,Shows the status of the Touch Detect Comparator in the analog section" "Open,Hit" group.long 0x44++0x0b line.long 0x00 "HW_LRADC_STATUS_SET,LRADC Status Set Register" bitfld.long 0x00 26. " TEMP1_PRESENT ,Temperature sensor 1 current source is present on the chip" "No effect,Set" bitfld.long 0x00 25. " TEMP0_PRESENT ,Temperature sensor 0 current source is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 24. " TOUCH_PANEL_PRESENT ,Touch panel controller function is present on the chip" "No effect,Set" bitfld.long 0x00 23. " CHANNEL7_PRESENT ,LRADC channel 7 converter function is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 22. " CHANNEL6_PRESENT ,LRADC channel 6 converter function is present on the chip" "No effect,Set" bitfld.long 0x00 21. " CHANNEL5_PRESENT ,LRADC channel 5 converter function is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 20. " CHANNEL4_PRESENT ,LRADC channel 4 converter function is present on the chip" "No effect,Set" bitfld.long 0x00 19. " CHANNEL3_PRESENT ,LRADC channel 3 converter function is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 18. " CHANNEL2_PRESENT ,LRADC channel 2 converter function is present on the chip" "No effect,Set" bitfld.long 0x00 17. " CHANNEL1_PRESENT ,LRADC channel 1 converter function is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 16. " CHANNEL0_PRESENT ,LRADC channel 0 converter function is present on the chip" "No effect,Set" bitfld.long 0x00 0. " TOUCH_DETECT_RAW ,Shows the status of the Touch Detect Comparator in the analog section" "No effect,Set" line.long 0x04 "HW_LRADC_STATUS_CLR,LRADC Status Clear Register" bitfld.long 0x04 26. " TEMP1_PRESENT ,Temperature sensor 1 current source is present on the chip" "No effect,Clear" bitfld.long 0x04 25. " TEMP0_PRESENT ,Temperature sensor 0 current source is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 24. " TOUCH_PANEL_PRESENT ,Touch panel controller function is present on the chip" "No effect,Clear" bitfld.long 0x04 23. " CHANNEL7_PRESENT ,LRADC channel 7 converter function is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 22. " CHANNEL6_PRESENT ,LRADC channel 6 converter function is present on the chip" "No effect,Clear" bitfld.long 0x04 21. " CHANNEL5_PRESENT ,LRADC channel 5 converter function is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 20. " CHANNEL4_PRESENT ,LRADC channel 4 converter function is present on the chip" "No effect,Clear" bitfld.long 0x04 19. " CHANNEL3_PRESENT ,LRADC channel 3 converter function is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 18. " CHANNEL2_PRESENT ,LRADC channel 2 converter function is present on the chip" "No effect,Clear" bitfld.long 0x04 17. " CHANNEL1_PRESENT ,LRADC channel 1 converter function is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 16. " CHANNEL0_PRESENT ,LRADC channel 0 converter function is present on the chip" "No effect,Clear" bitfld.long 0x04 0. " TOUCH_DETECT_RAW ,Shows the status of the Touch Detect Comparator in the analog section" "No effect,Clear" line.long 0x08 "HW_LRADC_STATUS_TOG,LRADC Status Toggle Register" bitfld.long 0x08 26. " TEMP1_PRESENT ,Temperature sensor 1 current source is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 25. " TEMP0_PRESENT ,Temperature sensor 0 current source is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 24. " TOUCH_PANEL_PRESENT ,Touch panel controller function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 23. " CHANNEL7_PRESENT ,LRADC channel 7 converter function is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 22. " CHANNEL6_PRESENT ,LRADC channel 6 converter function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 21. " CHANNEL5_PRESENT ,LRADC channel 5 converter function is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 20. " CHANNEL4_PRESENT ,LRADC channel 4 converter function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 19. " CHANNEL3_PRESENT ,LRADC channel 3 converter function is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 18. " CHANNEL2_PRESENT ,LRADC channel 2 converter function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 17. " CHANNEL1_PRESENT ,LRADC channel 1 converter function is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 16. " CHANNEL0_PRESENT ,LRADC channel 0 converter function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 0. " TOUCH_DETECT_RAW ,Shows the status of the Touch Detect Comparator in the analog section" "Not toggle,Toggle" group.long 0x50++0x7f line.long 0x0 "HW_LRADC_CH0,LRADC 0 Result Register" bitfld.long 0x0 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x0 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x0 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x0 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x0+0x04) "HW_LRADC_CH0_SET,LRADC 0 Result Set Register" bitfld.long (0x0+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x0+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x0+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x0+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x0+0x08) "HW_LRADC_CH0_CLR,LRADC 0 Result Clear Register" bitfld.long (0x0+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x0+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x0+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x0+0x0c) "HW_LRADC_CH0_TOG,LRADC 0 Result Toggle Register" bitfld.long (0x0+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x0+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x10 "HW_LRADC_CH1,LRADC 1 Result Register" bitfld.long 0x10 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x10 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x10 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x10 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x10+0x04) "HW_LRADC_CH1_SET,LRADC 1 Result Set Register" bitfld.long (0x10+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x10+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x10+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x10+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x10+0x08) "HW_LRADC_CH1_CLR,LRADC 1 Result Clear Register" bitfld.long (0x10+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x10+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x10+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x10+0x0c) "HW_LRADC_CH1_TOG,LRADC 1 Result Toggle Register" bitfld.long (0x10+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x10+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x20 "HW_LRADC_CH2,LRADC 2 Result Register" bitfld.long 0x20 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x20 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x20 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x20 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x20+0x04) "HW_LRADC_CH2_SET,LRADC 2 Result Set Register" bitfld.long (0x20+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x20+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x20+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x20+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x20+0x08) "HW_LRADC_CH2_CLR,LRADC 2 Result Clear Register" bitfld.long (0x20+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x20+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x20+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x20+0x0c) "HW_LRADC_CH2_TOG,LRADC 2 Result Toggle Register" bitfld.long (0x20+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x20+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x30 "HW_LRADC_CH3,LRADC 3 Result Register" bitfld.long 0x30 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x30 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x30 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x30 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x30+0x04) "HW_LRADC_CH3_SET,LRADC 3 Result Set Register" bitfld.long (0x30+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x30+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x30+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x30+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x30+0x08) "HW_LRADC_CH3_CLR,LRADC 3 Result Clear Register" bitfld.long (0x30+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x30+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x30+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x30+0x0c) "HW_LRADC_CH3_TOG,LRADC 3 Result Toggle Register" bitfld.long (0x30+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x30+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x40 "HW_LRADC_CH4,LRADC 4 Result Register" bitfld.long 0x40 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x40 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x40 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x40 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x40+0x04) "HW_LRADC_CH4_SET,LRADC 4 Result Set Register" bitfld.long (0x40+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x40+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x40+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x40+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x40+0x08) "HW_LRADC_CH4_CLR,LRADC 4 Result Clear Register" bitfld.long (0x40+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x40+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x40+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x40+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x40+0x0c) "HW_LRADC_CH4_TOG,LRADC 4 Result Toggle Register" bitfld.long (0x40+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x40+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x40+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x40+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x50 "HW_LRADC_CH5,LRADC 5 Result Register" bitfld.long 0x50 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x50 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x50 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x50 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x50+0x04) "HW_LRADC_CH5_SET,LRADC 5 Result Set Register" bitfld.long (0x50+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x50+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x50+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x50+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x50+0x08) "HW_LRADC_CH5_CLR,LRADC 5 Result Clear Register" bitfld.long (0x50+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x50+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x50+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x50+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x50+0x0c) "HW_LRADC_CH5_TOG,LRADC 5 Result Toggle Register" bitfld.long (0x50+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x50+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x50+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x50+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x60 "HW_LRADC_CH6,LRADC 6 (VddIO) Result Register" bitfld.long 0x60 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x60 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x60 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x60 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x60+0x04) "HW_LRADC_CH6_SET,LRADC 6 (VddIO) Result Set Register" bitfld.long (0x60+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x60+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x60+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x60+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x60+0x08) "HW_LRADC_CH6_CLR,LRADC 6 (VddIO) Result Clear Register" bitfld.long (0x60+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x60+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x60+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x60+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x60+0x0c) "HW_LRADC_CH6_TOG,LRADC 6 (VddIO) Result Toggle Register" bitfld.long (0x60+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x60+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x60+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x60+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x70 "HW_LRADC_CH7,LRADC 7 (BATT) Result Register" bitfld.long 0x70 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x70 30. " TESTMODE_TOGGLE ,Toggles at every completed conversion of interest in test mode" "Not toggle,Toggle" textline " " bitfld.long 0x70 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" bitfld.long 0x70 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x70 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x70+0x04) "HW_LRADC_CH7_SET,LRADC 7 (BATT) Result Set Register" bitfld.long (0x70+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x70+0x04) 30. " TESTMODE_TOGGLE ,Toggles at every completed conversion of interest in test mode" "No effect,Set" textline " " bitfld.long (0x70+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" bitfld.long (0x70+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte (0x70+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x70+0x08) "HW_LRADC_CH7_CLR,LRADC 7 (BATT) Result Clear Register" bitfld.long (0x70+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x70+0x08) 30. " TESTMODE_TOGGLE ,Toggles at every completed conversion of interest in test mode" "No effect,Clear" textline " " bitfld.long (0x70+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" bitfld.long (0x70+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte (0x70+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x70+0x0c) "HW_LRADC_CH7_TOG,LRADC 7 (BATT) Result Toggle Register" bitfld.long (0x70+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x70+0x0c) 30. " TESTMODE_TOGGLE ,Toggles at every completed conversion of interest in test mode" "Not toggle,Toggle" textline " " bitfld.long (0x70+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" bitfld.long (0x70+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte (0x70+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" group.long 0xd0++0x3f line.long 0x0 "HW_LRADC_DELAY0,LRADC Scheduling Delay 0" bitfld.long 0x0 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Triggered" bitfld.long 0x0 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Triggered" textline " " bitfld.long 0x0 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Triggered" bitfld.long 0x0 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Triggered" textline " " bitfld.long 0x0 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Triggered" bitfld.long 0x0 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Triggered" textline " " bitfld.long 0x0 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Triggered" bitfld.long 0x0 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Triggered" textline " " bitfld.long 0x0 20. " KICK ,Setting this bit to one initiates a delay cycle" "No delay,Delayed" bitfld.long 0x0 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Triggered" textline " " bitfld.long 0x0 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Triggered" bitfld.long 0x0 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Triggered" textline " " bitfld.long 0x0 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Triggered" bitfld.long 0x0 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x0+0x04) "HW_LRADC_DELAY0_SET,LRADC Scheduling Delay 0 Set" bitfld.long (0x0+0x04) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Set" bitfld.long (0x0+0x04) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Set" textline " " bitfld.long (0x0+0x04) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Set" bitfld.long (0x0+0x04) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Set" textline " " bitfld.long (0x0+0x04) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Set" bitfld.long (0x0+0x04) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Set" bitfld.long (0x0+0x04) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Set" textline " " bitfld.long (0x0+0x04) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Set" bitfld.long (0x0+0x04) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Set" textline " " bitfld.long (0x0+0x04) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Set" bitfld.long (0x0+0x04) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Set" bitfld.long (0x0+0x04) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x0+0x04) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x0+0x08) "HW_LRADC_DELAY0_CLR,LRADC Scheduling Delay 0 Clear" bitfld.long (0x0+0x08) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Clear" bitfld.long (0x0+0x08) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Clear" bitfld.long (0x0+0x08) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Clear" bitfld.long (0x0+0x08) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Clear" bitfld.long (0x0+0x08) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Clear" bitfld.long (0x0+0x08) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Clear" bitfld.long (0x0+0x08) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Clear" bitfld.long (0x0+0x08) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x0+0x08) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x0+0x0c) "HW_LRADC_DELAY0_TOG,LRADC Scheduling Delay 0 Toggle" bitfld.long (0x0+0x0c) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 20. " KICK ,Setting this bit to one initiates a delay cycle" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x0+0x0c) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long 0x10 "HW_LRADC_DELAY1,LRADC Scheduling Delay 1" bitfld.long 0x10 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Triggered" bitfld.long 0x10 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Triggered" textline " " bitfld.long 0x10 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Triggered" bitfld.long 0x10 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Triggered" textline " " bitfld.long 0x10 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Triggered" bitfld.long 0x10 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Triggered" textline " " bitfld.long 0x10 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Triggered" bitfld.long 0x10 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Triggered" textline " " bitfld.long 0x10 20. " KICK ,Setting this bit to one initiates a delay cycle" "No delay,Delayed" bitfld.long 0x10 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Triggered" textline " " bitfld.long 0x10 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Triggered" bitfld.long 0x10 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Triggered" textline " " bitfld.long 0x10 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Triggered" bitfld.long 0x10 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x10 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x10+0x04) "HW_LRADC_DELAY1_SET,LRADC Scheduling Delay 1 Set" bitfld.long (0x10+0x04) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Set" bitfld.long (0x10+0x04) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Set" textline " " bitfld.long (0x10+0x04) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Set" bitfld.long (0x10+0x04) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Set" textline " " bitfld.long (0x10+0x04) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Set" bitfld.long (0x10+0x04) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Set" bitfld.long (0x10+0x04) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Set" textline " " bitfld.long (0x10+0x04) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Set" bitfld.long (0x10+0x04) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Set" textline " " bitfld.long (0x10+0x04) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Set" bitfld.long (0x10+0x04) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Set" bitfld.long (0x10+0x04) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x10+0x04) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x10+0x08) "HW_LRADC_DELAY1_CLR,LRADC Scheduling Delay 1 Clear" bitfld.long (0x10+0x08) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Clear" bitfld.long (0x10+0x08) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Clear" bitfld.long (0x10+0x08) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Clear" bitfld.long (0x10+0x08) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Clear" bitfld.long (0x10+0x08) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Clear" bitfld.long (0x10+0x08) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Clear" bitfld.long (0x10+0x08) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Clear" bitfld.long (0x10+0x08) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x10+0x08) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x10+0x0c) "HW_LRADC_DELAY1_TOG,LRADC Scheduling Delay 1 Toggle" bitfld.long (0x10+0x0c) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 20. " KICK ,Setting this bit to one initiates a delay cycle" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x10+0x0c) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long 0x20 "HW_LRADC_DELAY2,LRADC Scheduling Delay 2" bitfld.long 0x20 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Triggered" bitfld.long 0x20 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Triggered" textline " " bitfld.long 0x20 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Triggered" bitfld.long 0x20 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Triggered" textline " " bitfld.long 0x20 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Triggered" bitfld.long 0x20 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Triggered" textline " " bitfld.long 0x20 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Triggered" bitfld.long 0x20 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Triggered" textline " " bitfld.long 0x20 20. " KICK ,Setting this bit to one initiates a delay cycle" "No delay,Delayed" bitfld.long 0x20 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Triggered" textline " " bitfld.long 0x20 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Triggered" bitfld.long 0x20 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Triggered" textline " " bitfld.long 0x20 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Triggered" bitfld.long 0x20 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x20 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x20+0x04) "HW_LRADC_DELAY2_SET,LRADC Scheduling Delay 2 Set" bitfld.long (0x20+0x04) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Set" bitfld.long (0x20+0x04) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Set" textline " " bitfld.long (0x20+0x04) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Set" bitfld.long (0x20+0x04) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Set" textline " " bitfld.long (0x20+0x04) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Set" bitfld.long (0x20+0x04) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Set" bitfld.long (0x20+0x04) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Set" textline " " bitfld.long (0x20+0x04) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Set" bitfld.long (0x20+0x04) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Set" textline " " bitfld.long (0x20+0x04) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Set" bitfld.long (0x20+0x04) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Set" bitfld.long (0x20+0x04) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x20+0x04) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x20+0x08) "HW_LRADC_DELAY2_CLR,LRADC Scheduling Delay 2 Clear" bitfld.long (0x20+0x08) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Clear" bitfld.long (0x20+0x08) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Clear" bitfld.long (0x20+0x08) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Clear" bitfld.long (0x20+0x08) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Clear" bitfld.long (0x20+0x08) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Clear" bitfld.long (0x20+0x08) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Clear" bitfld.long (0x20+0x08) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Clear" bitfld.long (0x20+0x08) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x20+0x08) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x20+0x0c) "HW_LRADC_DELAY2_TOG,LRADC Scheduling Delay 2 Toggle" bitfld.long (0x20+0x0c) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 20. " KICK ,Setting this bit to one initiates a delay cycle" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x20+0x0c) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long 0x30 "HW_LRADC_DELAY3,LRADC Scheduling Delay 3" bitfld.long 0x30 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Triggered" bitfld.long 0x30 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Triggered" textline " " bitfld.long 0x30 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Triggered" bitfld.long 0x30 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Triggered" textline " " bitfld.long 0x30 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Triggered" bitfld.long 0x30 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Triggered" textline " " bitfld.long 0x30 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Triggered" bitfld.long 0x30 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Triggered" textline " " bitfld.long 0x30 20. " KICK ,Setting this bit to one initiates a delay cycle" "No delay,Delayed" bitfld.long 0x30 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Triggered" textline " " bitfld.long 0x30 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Triggered" bitfld.long 0x30 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Triggered" textline " " bitfld.long 0x30 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Triggered" bitfld.long 0x30 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x30 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x30+0x04) "HW_LRADC_DELAY3_SET,LRADC Scheduling Delay 3 Set" bitfld.long (0x30+0x04) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Set" bitfld.long (0x30+0x04) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Set" textline " " bitfld.long (0x30+0x04) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Set" bitfld.long (0x30+0x04) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Set" textline " " bitfld.long (0x30+0x04) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Set" bitfld.long (0x30+0x04) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Set" textline " " bitfld.long (0x30+0x04) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Set" bitfld.long (0x30+0x04) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Set" textline " " bitfld.long (0x30+0x04) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Set" bitfld.long (0x30+0x04) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Set" textline " " bitfld.long (0x30+0x04) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Set" bitfld.long (0x30+0x04) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Set" textline " " bitfld.long (0x30+0x04) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Set" bitfld.long (0x30+0x04) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x30+0x04) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x30+0x08) "HW_LRADC_DELAY3_CLR,LRADC Scheduling Delay 3 Clear" bitfld.long (0x30+0x08) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Clear" bitfld.long (0x30+0x08) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Clear" bitfld.long (0x30+0x08) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Clear" bitfld.long (0x30+0x08) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Clear" bitfld.long (0x30+0x08) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Clear" bitfld.long (0x30+0x08) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Clear" bitfld.long (0x30+0x08) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Clear" bitfld.long (0x30+0x08) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x30+0x08) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x30+0x0c) "HW_LRADC_DELAY3_TOG,LRADC Scheduling Delay 3 Toggle" bitfld.long (0x30+0x0c) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 20. " KICK ,Setting this bit to one initiates a delay cycle" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x30+0x0c) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" rgroup.long 0x110++0x03 line.long 0x00 "HW_LRADC_DEBUG0,LRADC Debug Register 0" hexmask.long.word 0x00 16.--31. 1. " READONLY ,LRADC internal state machine current state" hexmask.long.word 0x00 0.--11. 1. " STATE ,LRADC internal state machine current state" group.long 0x114++0x0b line.long 0x00 "HW_LRADC_DEBUG0_SET,LRADC Debug Set Register 0" hexmask.long.word 0x00 16.--31. 1. " READONLY ,LRADC internal state machine current state" hexmask.long.word 0x00 0.--11. 1. " STATE ,LRADC internal state machine current state" line.long 0x04 "HW_LRADC_DEBUG0_CLR,LRADC Debug Clear Register 0" hexmask.long.word 0x04 16.--31. 1. " READONLY ,LRADC internal state machine current state" hexmask.long.word 0x04 0.--11. 1. " STATE ,LRADC internal state machine current state" line.long 0x08 "HW_LRADC_DEBUG0_TOG,LRADC Debug Toggle Register 0" hexmask.long.word 0x08 16.--31. 1. " READONLY ,LRADC internal state machine current state" hexmask.long.word 0x08 0.--11. 1. " STATE ,LRADC internal state machine current state" group.long 0x120++0x2f line.long 0x00 "HW_LRADC_DEBUG1,LRADC Debug Register 1" hexmask.long.byte 0x00 16.--23. 1. " REQUEST ,LRADC internal request register" bitfld.long 0x00 8.--12. " TESTMODE_COUNT ,In test mode value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 2. " TESTMODE6 ,Force dummy conversion cycles on channel 6 during test mode" "Normal,Test mode" bitfld.long 0x00 1. " TESTMODE5 ,Force dummy conversion cycles on channel 5 during test mode" "Normal,Test mode" textline " " bitfld.long 0x00 0. " TESTMODE ,Place the LRADC in a special test mode in which the analog section is free-running at its clock rate" "Normal,Test mode" line.long 0x04 "HW_LRADC_DEBUG1_SET,LRADC Debug Set Register 1" hexmask.long.byte 0x04 16.--23. 1. " REQUEST ,LRADC internal request register" bitfld.long 0x04 8.--12. " TESTMODE_COUNT ,In test mode value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 2. " TESTMODE6 ,Force dummy conversion cycles on channel 6 during test mode" "No effect,Set" bitfld.long 0x04 1. " TESTMODE5 ,Force dummy conversion cycles on channel 5 during test mode" "No effect,Set" textline " " bitfld.long 0x04 0. " TESTMODE ,Place the LRADC in a special test mode in which the analog section is free-running at its clock rate" "No effect,Set" line.long 0x08 "HW_LRADC_DEBUG1_CLR,LRADC Debug Clear Register 1" hexmask.long.byte 0x08 16.--23. 1. " REQUEST ,LRADC internal request register" bitfld.long 0x08 8.--12. " TESTMODE_COUNT ,In test mode value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x08 2. " TESTMODE6 ,Force dummy conversion cycles on channel 6 during test mode" "No effect,Clear" bitfld.long 0x08 1. " TESTMODE5 ,Force dummy conversion cycles on channel 5 during test mode" "No effect,Clear" textline " " bitfld.long 0x08 0. " TESTMODE ,Place the LRADC in a special test mode in which the analog section is free-running at its clock rate" "No effect,Clear" line.long 0x0c "HW_LRADC_DEBUG1_TOG,LRADC Debug Toggle Register 1" hexmask.long.byte 0x0c 16.--23. 1. " REQUEST ,LRADC internal request register" bitfld.long 0x0c 8.--12. " TESTMODE_COUNT ,In test mode value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0c 2. " TESTMODE6 ,Force dummy conversion cycles on channel 6 during test mode" "Not toggle,Toggle" bitfld.long 0x0c 1. " TESTMODE5 ,Force dummy conversion cycles on channel 5 during test mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " TESTMODE ,Place the LRADC in a special test mode in which the analog section is free-running at its clock rate" "Not toggle,Toggle" line.long 0x10 "HW_LRADC_CONV,LRADC Battery Conversion Register" bitfld.long 0x10 20. " AUTOMATIC ,Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place" "Disabled,Enabled" bitfld.long 0x10 16.--17. " SCALE_FACTOR ,Scale factors of 29/512, 29/256 or 29/128 are selected here" "NIMH,Dual NIMH,LI-ION,Alt LI-ION" textline " " hexmask.long.word 0x10 0.--9. 1. " SCALED_BATT_VOLTAGE ,LRADC Battery Voltage Divided by approximately 17.708" line.long 0x14 "HW_LRADC_CONV_SET,LRADC Battery Conversion Set Register" bitfld.long 0x14 20. " AUTOMATIC ,Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place" "No effect,Set" bitfld.long 0x14 16.--17. " SCALE_FACTOR ,Scale factors of 29/512, 29/256 or 29/128 are selected here" "NIMH,Dual NIMH,LI-ION,Alt LI-ION" textline " " hexmask.long.word 0x14 0.--9. 1. " SCALED_BATT_VOLTAGE ,LRADC Battery Voltage Divided by approximately 17.708" line.long 0x18 "HW_LRADC_CONV_CLR,LRADC Battery Conversion Clear Register" bitfld.long 0x18 20. " AUTOMATIC ,Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place" "No effect,Clear" bitfld.long 0x18 16.--17. " SCALE_FACTOR ,Scale factors of 29/512, 29/256 or 29/128 are selected here" "NIMH,Dual NIMH,LI-ION,Alt LI-ION" textline " " hexmask.long.word 0x18 0.--9. 1. " SCALED_BATT_VOLTAGE ,LRADC Battery Voltage Divided by approximately 17.708" line.long 0x1c "HW_LRADC_CONV_TOG,LRADC Battery Conversion Toggle Register" bitfld.long 0x1c 20. " AUTOMATIC ,Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place" "Not toggle,Toggle" bitfld.long 0x1c 16.--17. " SCALE_FACTOR ,Scale factors of 29/512, 29/256 or 29/128 are selected here" "NIMH,Dual NIMH,LI-ION,Alt LI-ION" textline " " hexmask.long.word 0x1c 0.--9. 1. " SCALED_BATT_VOLTAGE ,LRADC Battery Voltage Divided by approximately 17.708" width 21. line.long 0x20 "HW_LRADC_CTRL4,LRADC Control Register 4" bitfld.long 0x20 28.--31. " LRADC7SELECT ,Selects which analog mux input is used for conversion on LRADC channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x20 24.--27. " LRADC6SELECT ,Selects which analog mux input is used for conversion on LRADC channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x20 20.--23. " LRADC5SELECT ,Selects which analog mux input is used for conversion on LRADC channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x20 16.--19. " LRADC4SELECT ,Selects which analog mux input is used for conversion on LRADC channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x20 12.--15. " LRADC3SELECT ,Selects which analog mux input is used for conversion on LRADC channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x20 8.--11. " LRADC2SELECT ,Selects which analog mux input is used for conversion on LRADC channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x20 4.--7. " LRADC1SELECT ,Selects which analog mux input is used for conversion on LRADC channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x20 0.--3. " LRADC0SELECT ,Selects which analog mux input is used for conversion on LRADC channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" line.long 0x24 "HW_LRADC_CTRL4_SET,LRADC Control Set Register 4" bitfld.long 0x24 28.--31. " LRADC7SELECT ,Selects which analog mux input is used for conversion on LRADC channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x24 24.--27. " LRADC6SELECT ,Selects which analog mux input is used for conversion on LRADC channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x24 20.--23. " LRADC5SELECT ,Selects which analog mux input is used for conversion on LRADC channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x24 16.--19. " LRADC4SELECT ,Selects which analog mux input is used for conversion on LRADC channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x24 12.--15. " LRADC3SELECT ,Selects which analog mux input is used for conversion on LRADC channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x24 8.--11. " LRADC2SELECT ,Selects which analog mux input is used for conversion on LRADC channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x24 4.--7. " LRADC1SELECT ,Selects which analog mux input is used for conversion on LRADC channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x24 0.--3. " LRADC0SELECT ,Selects which analog mux input is used for conversion on LRADC channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" line.long 0x28 "HW_LRADC_CTRL4_CLR,LRADC Control Clear Register 4" bitfld.long 0x28 28.--31. " LRADC7SELECT ,Selects which analog mux input is used for conversion on LRADC channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x28 24.--27. " LRADC6SELECT ,Selects which analog mux input is used for conversion on LRADC channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x28 20.--23. " LRADC5SELECT ,Selects which analog mux input is used for conversion on LRADC channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x28 16.--19. " LRADC4SELECT ,Selects which analog mux input is used for conversion on LRADC channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x28 12.--15. " LRADC3SELECT ,Selects which analog mux input is used for conversion on LRADC channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x28 8.--11. " LRADC2SELECT ,Selects which analog mux input is used for conversion on LRADC channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x28 4.--7. " LRADC1SELECT ,Selects which analog mux input is used for conversion on LRADC channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x28 0.--3. " LRADC0SELECT ,Selects which analog mux input is used for conversion on LRADC channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" line.long 0x2c "HW_LRADC_CTRL4_TOG,LRADC Control Toggle Register 4" bitfld.long 0x2c 28.--31. " LRADC7SELECT ,Selects which analog mux input is used for conversion on LRADC channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x2c 24.--27. " LRADC6SELECT ,Selects which analog mux input is used for conversion on LRADC channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x2c 20.--23. " LRADC5SELECT ,Selects which analog mux input is used for conversion on LRADC channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x2c 16.--19. " LRADC4SELECT ,Selects which analog mux input is used for conversion on LRADC channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x2c 12.--15. " LRADC3SELECT ,Selects which analog mux input is used for conversion on LRADC channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x2c 8.--11. " LRADC2SELECT ,Selects which analog mux input is used for conversion on LRADC channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x2c 4.--7. " LRADC1SELECT ,Selects which analog mux input is used for conversion on LRADC channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x2c 0.--3. " LRADC0SELECT ,Selects which analog mux input is used for conversion on LRADC channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6 (VDDIO),Channel 7 (BATTERY),Channel 8 (PMOS THIN),Channel 9 (NMOS THIN),Channel 10 (NMOS THICK),Channel 11 (PMOS THICK),Channel 12 (USB_DP),Channel 13 (USB_DN),Channel 14 (VBG),Channel 15 (5V Input)" rgroup.long 0x150++0x03 line.long 0x00 "HW_LRADC_VERSION,LRADC Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "GPIO (Pin Control and GPIO)" base asd:0x80018000 tree "Control Registers" width 23. group.long 0x00++0x0f line.long 0x00 "HW_PINCTRL_CTRL,Pin Control Register" bitfld.long 0x00 31. " SFTRST ,When set to one, it forces a block-level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Disable the block clock" "No,Yes" bitfld.long 0x00 27. " PRESENT3 ,GPIO functionality for Pin Control Bank 3" "Not present,Present" textline " " bitfld.long 0x00 26. " PRESENT2 ,GPIO functionality for Pin Control Bank 2" "Not present,Present" bitfld.long 0x00 25. " PRESENT1 ,GPIO functionality for Pin Control Bank 1" "Not present,Present" bitfld.long 0x00 24. " PRESENT0 ,GPIO functionality for Pin Control Bank 0" "Not present,Present" textline " " bitfld.long 0x00 2. " IRQOUT2 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2" "0,1" bitfld.long 0x00 1. " IRQOUT1 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 1" "0,1" bitfld.long 0x00 0. " IRQOUT0 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 0" "0,1" line.long 0x04 "HW_PINCTRL_CTRL_SET,Pin Control Set Register" bitfld.long 0x04 31. " SFTRST ,When set to one, it forces a block-level reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Disable the block clock" "No effect,Set" bitfld.long 0x04 27. " PRESENT3 ,GPIO functionality for Pin Control Bank 3" "No effect,Set" textline " " bitfld.long 0x04 26. " PRESENT2 ,GPIO functionality for Pin Control Bank 2" "No effect,Set" bitfld.long 0x04 25. " PRESENT1 ,GPIO functionality for Pin Control Bank 1" "No effect,Set" bitfld.long 0x04 24. " PRESENT0 ,GPIO functionality for Pin Control Bank 0" "No effect,Set" textline " " bitfld.long 0x04 2. " IRQOUT2 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2" "No effect,Set" bitfld.long 0x04 1. " IRQOUT1 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 1" "No effect,Set" bitfld.long 0x04 0. " IRQOUT0 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 0" "No effect,Set" line.long 0x08 "HW_PINCTRL_CTRL_CLR,Pin Control Set Register" bitfld.long 0x08 31. " SFTRST ,When set to one, it forces a block-level reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Disable the block clock" "No effect,Clear" bitfld.long 0x08 27. " PRESENT3 ,GPIO functionality for Pin Control Bank 3" "No effect,Clear" textline " " bitfld.long 0x08 26. " PRESENT2 ,GPIO functionality for Pin Control Bank 2" "No effect,Clear" bitfld.long 0x08 25. " PRESENT1 ,GPIO functionality for Pin Control Bank 1" "No effect,Clear" bitfld.long 0x08 24. " PRESENT0 ,GPIO functionality for Pin Control Bank 0" "No effect,Clear" textline " " bitfld.long 0x08 2. " IRQOUT2 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2" "No effect,Clear" bitfld.long 0x08 1. " IRQOUT1 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 1" "No effect,Clear" bitfld.long 0x08 0. " IRQOUT0 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 0" "No effect,Clear" line.long 0x0c "HW_PINCTRL_CTRL_TOG,Pin Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,When set to one, it forces a block-level reset" "Not Toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Disable the block clock" "Not Toggle,Toggle" bitfld.long 0x0c 27. " PRESENT3 ,GPIO functionality for Pin Control Bank 3" "Not Toggle,Toggle" textline " " bitfld.long 0x0c 26. " PRESENT2 ,GPIO functionality for Pin Control Bank 2" "Not Toggle,Toggle" bitfld.long 0x0c 25. " PRESENT1 ,GPIO functionality for Pin Control Bank 1" "Not Toggle,Toggle" bitfld.long 0x0c 24. " PRESENT0 ,GPIO functionality for Pin Control Bank 0" "Not Toggle,Toggle" textline " " bitfld.long 0x0c 2. " IRQOUT2 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2" "Not Toggle,Toggle" bitfld.long 0x0c 1. " IRQOUT1 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 1" "Not Toggle,Toggle" bitfld.long 0x0c 0. " IRQOUT0 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 0" "Not Toggle,Toggle" tree.end tree "Mux Select Registers" width 24. group.long 0x100++0x7f line.long 0x00 "HW_PINCTRL_MUXSEL0,Pin Mux Select Register 0" bitfld.long 0x00 30.--31. " BANK0_PIN15 ,Pin 59, GPMI_D15 pin function selection" "gpmi_data15,auart2_tx,gpmi_ce3n,GPIO" bitfld.long 0x00 28.--29. " BANK0_PIN14 ,Pin 58, GPMI_D14 pin function selection" "gpmi_data14,auart2_rx,Reserved,GPIO" bitfld.long 0x00 26.--27. " BANK0_PIN13 ,Pin 57, GPMI_D13 pin function selection" "gpmi_data13,lcd_d23,Reserved,GPIO" textline " " bitfld.long 0x00 24.--25. " BANK0_PIN12 ,Pin 56, GPMI_D12 pin function selection" "gpmi_data12,lcd_d22,Reserved,GPIO" bitfld.long 0x00 22.--23. " BANK0_PIN11 ,Pin 55, GPMI_D11 pin function selection" "gpmi_data11,lcd_d21,ssp1_d7,GPIO" bitfld.long 0x00 20.--21. " BANK0_PIN10 ,Pin 54, GPMI_D10 pin function selection" "gpmi_data10,lcd_d20,ssp1_d6,GPIO" textline " " bitfld.long 0x00 18.--19. " BANK0_PIN09 ,Pin 53, GPMI_D09 pin function selection" "gpmi_data09,lcd_d19,ssp1_d5,GPIO" bitfld.long 0x00 16.--17. " BANK0_PIN08 ,Pin 52, GPMI_D08 pin function selection" "gpmi_data08,lcd_d18,ssp1_d4,GPIO" bitfld.long 0x00 14.--15. " BANK0_PIN07 ,Pin 51, GPMI_D07 pin function selection" "gpmi_data07,lcd_d15,ssp2_d7,GPIO" textline " " bitfld.long 0x00 12.--13. " BANK0_PIN06 ,Pin 50, GPMI_D06 pin function selection" "gpmi_data06,lcd_d14,ssp2_d6,GPIO" bitfld.long 0x00 10.--11. " BANK0_PIN05 ,Pin 49, GPMI_D05 pin function selection" "gpmi_data05,lcd_d13,ssp2_d5,GPIO" bitfld.long 0x00 8.--9. " BANK0_PIN04 ,Pin 48, GPMI_D04 pin function selection" "gpmi_data04,lcd_d12,ssp2_d4,GPIO" textline " " bitfld.long 0x00 6.--7. " BANK0_PIN03 ,Pin 47, GPMI_D03 pin function selection" "gpmi_data03,lcd_d11,ssp2_d3,GPIO" bitfld.long 0x00 4.--5. " BANK0_PIN02 ,Pin 46, GPMI_D02 pin function selection" "gpmi_data02,lcd_d10,ssp2_d2,GPIO" bitfld.long 0x00 2.--3. " BANK0_PIN01 ,Pin 45, GPMI_D01 pin function selection" "gpmi_data01,lcd_d9,ssp2_d1,GPIO" textline " " bitfld.long 0x00 0.--1. " BANK0_PIN00 ,Pin 44, GPMI_D00 pin function selection" "gpmi_data00,lcd_d8,ssp2_d0,GPIO" line.long 0x04 "HW_PINCTRL_MUXSEL0_SET,Pin Mux Select Set Register 0" bitfld.long 0x04 30.--31. " BANK0_PIN15 ,Pin 59, GPMI_D15 pin function selection" "gpmi_data15,auart2_tx,gpmi_ce3n,GPIO" bitfld.long 0x04 28.--29. " BANK0_PIN14 ,Pin 58, GPMI_D14 pin function selection" "gpmi_data14,auart2_rx,Reserved,GPIO" bitfld.long 0x04 26.--27. " BANK0_PIN13 ,Pin 57, GPMI_D13 pin function selection" "gpmi_data13,lcd_d23,Reserved,GPIO" textline " " bitfld.long 0x04 24.--25. " BANK0_PIN12 ,Pin 56, GPMI_D12 pin function selection" "gpmi_data12,lcd_d22,Reserved,GPIO" bitfld.long 0x04 22.--23. " BANK0_PIN11 ,Pin 55, GPMI_D11 pin function selection" "gpmi_data11,lcd_d21,ssp1_d7,GPIO" bitfld.long 0x04 20.--21. " BANK0_PIN10 ,Pin 54, GPMI_D10 pin function selection" "gpmi_data10,lcd_d20,ssp1_d6,GPIO" textline " " bitfld.long 0x04 18.--19. " BANK0_PIN09 ,Pin 53, GPMI_D09 pin function selection" "gpmi_data09,lcd_d19,ssp1_d5,GPIO" bitfld.long 0x04 16.--17. " BANK0_PIN08 ,Pin 52, GPMI_D08 pin function selection" "gpmi_data08,lcd_d18,ssp1_d4,GPIO" bitfld.long 0x04 14.--15. " BANK0_PIN07 ,Pin 51, GPMI_D07 pin function selection" "gpmi_data07,lcd_d15,ssp2_d7,GPIO" textline " " bitfld.long 0x04 12.--13. " BANK0_PIN06 ,Pin 50, GPMI_D06 pin function selection" "gpmi_data06,lcd_d14,ssp2_d6,GPIO" bitfld.long 0x04 10.--11. " BANK0_PIN05 ,Pin 49, GPMI_D05 pin function selection" "gpmi_data05,lcd_d13,ssp2_d5,GPIO" bitfld.long 0x04 8.--9. " BANK0_PIN04 ,Pin 48, GPMI_D04 pin function selection" "gpmi_data04,lcd_d12,ssp2_d4,GPIO" textline " " bitfld.long 0x04 6.--7. " BANK0_PIN03 ,Pin 47, GPMI_D03 pin function selection" "gpmi_data03,lcd_d11,ssp2_d3,GPIO" bitfld.long 0x04 4.--5. " BANK0_PIN02 ,Pin 46, GPMI_D02 pin function selection" "gpmi_data02,lcd_d10,ssp2_d2,GPIO" bitfld.long 0x04 2.--3. " BANK0_PIN01 ,Pin 45, GPMI_D01 pin function selection" "gpmi_data01,lcd_d9,ssp2_d1,GPIO" textline " " bitfld.long 0x04 0.--1. " BANK0_PIN00 ,Pin 44, GPMI_D00 pin function selection" "gpmi_data00,lcd_d8,ssp2_d0,GPIO" line.long 0x08 "HW_PINCTRL_MUXSEL0_CLR,Pin Mux Select Clear Register 0" bitfld.long 0x08 30.--31. " BANK0_PIN15 ,Pin 59, GPMI_D15 pin function selection" "gpmi_data15,auart2_tx,gpmi_ce3n,GPIO" bitfld.long 0x08 28.--29. " BANK0_PIN14 ,Pin 58, GPMI_D14 pin function selection" "gpmi_data14,auart2_rx,Reserved,GPIO" bitfld.long 0x08 26.--27. " BANK0_PIN13 ,Pin 57, GPMI_D13 pin function selection" "gpmi_data13,lcd_d23,Reserved,GPIO" textline " " bitfld.long 0x08 24.--25. " BANK0_PIN12 ,Pin 56, GPMI_D12 pin function selection" "gpmi_data12,lcd_d22,Reserved,GPIO" bitfld.long 0x08 22.--23. " BANK0_PIN11 ,Pin 55, GPMI_D11 pin function selection" "gpmi_data11,lcd_d21,ssp1_d7,GPIO" bitfld.long 0x08 20.--21. " BANK0_PIN10 ,Pin 54, GPMI_D10 pin function selection" "gpmi_data10,lcd_d20,ssp1_d6,GPIO" textline " " bitfld.long 0x08 18.--19. " BANK0_PIN09 ,Pin 53, GPMI_D09 pin function selection" "gpmi_data09,lcd_d19,ssp1_d5,GPIO" bitfld.long 0x08 16.--17. " BANK0_PIN08 ,Pin 52, GPMI_D08 pin function selection" "gpmi_data08,lcd_d18,ssp1_d4,GPIO" bitfld.long 0x08 14.--15. " BANK0_PIN07 ,Pin 51, GPMI_D07 pin function selection" "gpmi_data07,lcd_d15,ssp2_d7,GPIO" textline " " bitfld.long 0x08 12.--13. " BANK0_PIN06 ,Pin 50, GPMI_D06 pin function selection" "gpmi_data06,lcd_d14,ssp2_d6,GPIO" bitfld.long 0x08 10.--11. " BANK0_PIN05 ,Pin 49, GPMI_D05 pin function selection" "gpmi_data05,lcd_d13,ssp2_d5,GPIO" bitfld.long 0x08 8.--9. " BANK0_PIN04 ,Pin 48, GPMI_D04 pin function selection" "gpmi_data04,lcd_d12,ssp2_d4,GPIO" textline " " bitfld.long 0x08 6.--7. " BANK0_PIN03 ,Pin 47, GPMI_D03 pin function selection" "gpmi_data03,lcd_d11,ssp2_d3,GPIO" bitfld.long 0x08 4.--5. " BANK0_PIN02 ,Pin 46, GPMI_D02 pin function selection" "gpmi_data02,lcd_d10,ssp2_d2,GPIO" bitfld.long 0x08 2.--3. " BANK0_PIN01 ,Pin 45, GPMI_D01 pin function selection" "gpmi_data01,lcd_d9,ssp2_d1,GPIO" textline " " bitfld.long 0x08 0.--1. " BANK0_PIN00 ,Pin 44, GPMI_D00 pin function selection" "gpmi_data00,lcd_d8,ssp2_d0,GPIO" line.long 0x0c "HW_PINCTRL_MUXSEL0_TOG,Pin Mux Select Toggle Register 0" bitfld.long 0x0c 30.--31. " BANK0_PIN15 ,Pin 59, GPMI_D15 pin function selection" "gpmi_data15,auart2_tx,gpmi_ce3n,GPIO" bitfld.long 0x0c 28.--29. " BANK0_PIN14 ,Pin 58, GPMI_D14 pin function selection" "gpmi_data14,auart2_rx,Reserved,GPIO" bitfld.long 0x0c 26.--27. " BANK0_PIN13 ,Pin 57, GPMI_D13 pin function selection" "gpmi_data13,lcd_d23,Reserved,GPIO" textline " " bitfld.long 0x0c 24.--25. " BANK0_PIN12 ,Pin 56, GPMI_D12 pin function selection" "gpmi_data12,lcd_d22,Reserved,GPIO" bitfld.long 0x0c 22.--23. " BANK0_PIN11 ,Pin 55, GPMI_D11 pin function selection" "gpmi_data11,lcd_d21,ssp1_d7,GPIO" bitfld.long 0x0c 20.--21. " BANK0_PIN10 ,Pin 54, GPMI_D10 pin function selection" "gpmi_data10,lcd_d20,ssp1_d6,GPIO" textline " " bitfld.long 0x0c 18.--19. " BANK0_PIN09 ,Pin 53, GPMI_D09 pin function selection" "gpmi_data09,lcd_d19,ssp1_d5,GPIO" bitfld.long 0x0c 16.--17. " BANK0_PIN08 ,Pin 52, GPMI_D08 pin function selection" "gpmi_data08,lcd_d18,ssp1_d4,GPIO" bitfld.long 0x0c 14.--15. " BANK0_PIN07 ,Pin 51, GPMI_D07 pin function selection" "gpmi_data07,lcd_d15,ssp2_d7,GPIO" textline " " bitfld.long 0x0c 12.--13. " BANK0_PIN06 ,Pin 50, GPMI_D06 pin function selection" "gpmi_data06,lcd_d14,ssp2_d6,GPIO" bitfld.long 0x0c 10.--11. " BANK0_PIN05 ,Pin 49, GPMI_D05 pin function selection" "gpmi_data05,lcd_d13,ssp2_d5,GPIO" bitfld.long 0x0c 8.--9. " BANK0_PIN04 ,Pin 48, GPMI_D04 pin function selection" "gpmi_data04,lcd_d12,ssp2_d4,GPIO" textline " " bitfld.long 0x0c 6.--7. " BANK0_PIN03 ,Pin 47, GPMI_D03 pin function selection" "gpmi_data03,lcd_d11,ssp2_d3,GPIO" bitfld.long 0x0c 4.--5. " BANK0_PIN02 ,Pin 46, GPMI_D02 pin function selection" "gpmi_data02,lcd_d10,ssp2_d2,GPIO" bitfld.long 0x0c 2.--3. " BANK0_PIN01 ,Pin 45, GPMI_D01 pin function selection" "gpmi_data01,lcd_d9,ssp2_d1,GPIO" textline " " bitfld.long 0x0c 0.--1. " BANK0_PIN00 ,Pin 44, GPMI_D00 pin function selection" "gpmi_data00,lcd_d8,ssp2_d0,GPIO" line.long 0x10 "HW_PINCTRL_MUXSEL1,Pin Mux Select Register 1" bitfld.long 0x10 30.--31. " BANK0_PIN31 ,Pin 4, I2C_SDA pin function selection" "i2c_sd,gpmi_ce2n,auart1_rx,GPIO" bitfld.long 0x10 28.--29. " BANK0_PIN30 ,Pin 2, I2C_SCL pin function selection" "i2c_clk,gpmi_ready2,auart1_tx,GPIO" bitfld.long 0x10 26.--27. " BANK0_PIN29 ,Pin 69, AUART1_TX pin function selection" "auart1_tx,Reserved,ssp1_d7,GPIO" textline " " bitfld.long 0x10 24.--25. " BANK0_PIN28 ,Pin 68, AUART1_RX pin function selection" "auart1_rx,Reserved,ssp1_d6,GPIO" bitfld.long 0x10 22.--23. " BANK0_PIN27 ,Pin 67, AUART1_RTS pin function selection" "auart1_rts,Reserved,ssp1_d5,GPIO" bitfld.long 0x10 20.--21. " BANK0_PIN26 ,Pin 66, AUART1_CTS pin function selection" "auart1_cts,Reserved,ssp1_d4,GPIO" textline " " bitfld.long 0x10 18.--19. " BANK0_PIN25 ,Pin 60, GPMI_RDN pin function selection" "gpmi_rdn,Reserved,Reserved,GPIO" bitfld.long 0x10 16.--17. " BANK0_PIN24 ,Pin 65, GPMI_WRN pin function selection" "gpmi_wrn,Reserved,ssp2_sck,GPIO" bitfld.long 0x10 14.--15. " BANK0_PIN23 ,Pin 64, GPMI_WPN pin function selection" "gpmi_wpn,Reserved,Reserved,GPIO" textline " " bitfld.long 0x10 12.--13. " BANK0_PIN22 ,Pin 63, GPMI_RDY3 pin function selection" "gpmi_ready3,Reserved,Reserved,GPIO" bitfld.long 0x10 10.--11. " BANK0_PIN21 ,Pin 62, GPMI_RDY2 pin function selection" "gpmi_ready2,Reserved,Reserved,GPIO" bitfld.long 0x10 8.--9. " BANK0_PIN20 ,Pin 43, GPMI_RDY1 pin function selection" "gpmi_ready1,Reserved,ssp2_cmd,GPIO" textline " " bitfld.long 0x10 6.--7. " BANK0_PIN19 ,Pin 61, GPMI_RDY0 pin function selection" "gpmi_ready0,Reserved,ssp2_detect,GPIO" bitfld.long 0x10 4.--5. " BANK0_PIN18 ,Pin 42, GPMI_CE2N pin function selection" "gpmi_ce2n,Reserved,Reserved,GPIO" bitfld.long 0x10 2.--3. " BANK0_PIN17 ,Pin 41, GPMI_ALE pin function selection" "gpmi_ale,lcd_d17,Reserved,GPIO" textline " " bitfld.long 0x10 0.--1. " BANK0_PIN16 ,Pin 40, GPMI_CLE pin function selection" "gpmi_cle,lcd_d16,Reserved,GPIO" line.long 0x14 "HW_PINCTRL_MUXSEL1_SET,Pin Mux Select Set Register 1" bitfld.long 0x14 30.--31. " BANK0_PIN31 ,Pin 4, I2C_SDA pin function selection" "i2c_sd,gpmi_ce2n,auart1_rx,GPIO" bitfld.long 0x14 28.--29. " BANK0_PIN30 ,Pin 2, I2C_SCL pin function selection" "i2c_clk,gpmi_ready2,auart1_tx,GPIO" bitfld.long 0x14 26.--27. " BANK0_PIN29 ,Pin 69, AUART1_TX pin function selection" "auart1_tx,Reserved,ssp1_d7,GPIO" textline " " bitfld.long 0x14 24.--25. " BANK0_PIN28 ,Pin 68, AUART1_RX pin function selection" "auart1_rx,Reserved,ssp1_d6,GPIO" bitfld.long 0x14 22.--23. " BANK0_PIN27 ,Pin 67, AUART1_RTS pin function selection" "auart1_rts,Reserved,ssp1_d5,GPIO" bitfld.long 0x14 20.--21. " BANK0_PIN26 ,Pin 66, AUART1_CTS pin function selection" "auart1_cts,Reserved,ssp1_d4,GPIO" textline " " bitfld.long 0x14 18.--19. " BANK0_PIN25 ,Pin 60, GPMI_RDN pin function selection" "gpmi_rdn,Reserved,Reserved,GPIO" bitfld.long 0x14 16.--17. " BANK0_PIN24 ,Pin 65, GPMI_WRN pin function selection" "gpmi_wrn,Reserved,ssp2_sck,GPIO" bitfld.long 0x14 14.--15. " BANK0_PIN23 ,Pin 64, GPMI_WPN pin function selection" "gpmi_wpn,Reserved,Reserved,GPIO" textline " " bitfld.long 0x14 12.--13. " BANK0_PIN22 ,Pin 63, GPMI_RDY3 pin function selection" "gpmi_ready3,Reserved,Reserved,GPIO" bitfld.long 0x14 10.--11. " BANK0_PIN21 ,Pin 62, GPMI_RDY2 pin function selection" "gpmi_ready2,Reserved,Reserved,GPIO" bitfld.long 0x14 8.--9. " BANK0_PIN20 ,Pin 43, GPMI_RDY1 pin function selection" "gpmi_ready1,Reserved,ssp2_cmd,GPIO" textline " " bitfld.long 0x14 6.--7. " BANK0_PIN19 ,Pin 61, GPMI_RDY0 pin function selection" "gpmi_ready0,Reserved,ssp2_detect,GPIO" bitfld.long 0x14 4.--5. " BANK0_PIN18 ,Pin 42, GPMI_CE2N pin function selection" "gpmi_ce2n,Reserved,Reserved,GPIO" bitfld.long 0x14 2.--3. " BANK0_PIN17 ,Pin 41, GPMI_ALE pin function selection" "gpmi_ale,lcd_d17,Reserved,GPIO" textline " " bitfld.long 0x14 0.--1. " BANK0_PIN16 ,Pin 40, GPMI_CLE pin function selection" "gpmi_cle,lcd_d16,Reserved,GPIO" line.long 0x18 "HW_PINCTRL_MUXSEL1_CLR,Pin Mux Select Clear Register 1" bitfld.long 0x18 30.--31. " BANK0_PIN31 ,Pin 4, I2C_SDA pin function selection" "i2c_sd,gpmi_ce2n,auart1_rx,GPIO" bitfld.long 0x18 28.--29. " BANK0_PIN30 ,Pin 2, I2C_SCL pin function selection" "i2c_clk,gpmi_ready2,auart1_tx,GPIO" bitfld.long 0x18 26.--27. " BANK0_PIN29 ,Pin 69, AUART1_TX pin function selection" "auart1_tx,Reserved,ssp1_d7,GPIO" textline " " bitfld.long 0x18 24.--25. " BANK0_PIN28 ,Pin 68, AUART1_RX pin function selection" "auart1_rx,Reserved,ssp1_d6,GPIO" bitfld.long 0x18 22.--23. " BANK0_PIN27 ,Pin 67, AUART1_RTS pin function selection" "auart1_rts,Reserved,ssp1_d5,GPIO" bitfld.long 0x18 20.--21. " BANK0_PIN26 ,Pin 66, AUART1_CTS pin function selection" "auart1_cts,Reserved,ssp1_d4,GPIO" textline " " bitfld.long 0x18 18.--19. " BANK0_PIN25 ,Pin 60, GPMI_RDN pin function selection" "gpmi_rdn,Reserved,Reserved,GPIO" bitfld.long 0x18 16.--17. " BANK0_PIN24 ,Pin 65, GPMI_WRN pin function selection" "gpmi_wrn,Reserved,ssp2_sck,GPIO" bitfld.long 0x18 14.--15. " BANK0_PIN23 ,Pin 64, GPMI_WPN pin function selection" "gpmi_wpn,Reserved,Reserved,GPIO" textline " " bitfld.long 0x18 12.--13. " BANK0_PIN22 ,Pin 63, GPMI_RDY3 pin function selection" "gpmi_ready3,Reserved,Reserved,GPIO" bitfld.long 0x18 10.--11. " BANK0_PIN21 ,Pin 62, GPMI_RDY2 pin function selection" "gpmi_ready2,Reserved,Reserved,GPIO" bitfld.long 0x18 8.--9. " BANK0_PIN20 ,Pin 43, GPMI_RDY1 pin function selection" "gpmi_ready1,Reserved,ssp2_cmd,GPIO" textline " " bitfld.long 0x18 6.--7. " BANK0_PIN19 ,Pin 61, GPMI_RDY0 pin function selection" "gpmi_ready0,Reserved,ssp2_detect,GPIO" bitfld.long 0x18 4.--5. " BANK0_PIN18 ,Pin 42, GPMI_CE2N pin function selection" "gpmi_ce2n,Reserved,Reserved,GPIO" bitfld.long 0x18 2.--3. " BANK0_PIN17 ,Pin 41, GPMI_ALE pin function selection" "gpmi_ale,lcd_d17,Reserved,GPIO" textline " " bitfld.long 0x18 0.--1. " BANK0_PIN16 ,Pin 40, GPMI_CLE pin function selection" "gpmi_cle,lcd_d16,Reserved,GPIO" line.long 0x1c "HW_PINCTRL_MUXSEL1_TOG,Pin Mux Select Toggle Register 1" bitfld.long 0x1c 30.--31. " BANK0_PIN31 ,Pin 4, I2C_SDA pin function selection" "i2c_sd,gpmi_ce2n,auart1_rx,GPIO" bitfld.long 0x1c 28.--29. " BANK0_PIN30 ,Pin 2, I2C_SCL pin function selection" "i2c_clk,gpmi_ready2,auart1_tx,GPIO" bitfld.long 0x1c 26.--27. " BANK0_PIN29 ,Pin 69, AUART1_TX pin function selection" "auart1_tx,Reserved,ssp1_d7,GPIO" textline " " bitfld.long 0x1c 24.--25. " BANK0_PIN28 ,Pin 68, AUART1_RX pin function selection" "auart1_rx,Reserved,ssp1_d6,GPIO" bitfld.long 0x1c 22.--23. " BANK0_PIN27 ,Pin 67, AUART1_RTS pin function selection" "auart1_rts,Reserved,ssp1_d5,GPIO" bitfld.long 0x1c 20.--21. " BANK0_PIN26 ,Pin 66, AUART1_CTS pin function selection" "auart1_cts,Reserved,ssp1_d4,GPIO" textline " " bitfld.long 0x1c 18.--19. " BANK0_PIN25 ,Pin 60, GPMI_RDN pin function selection" "gpmi_rdn,Reserved,Reserved,GPIO" bitfld.long 0x1c 16.--17. " BANK0_PIN24 ,Pin 65, GPMI_WRN pin function selection" "gpmi_wrn,Reserved,ssp2_sck,GPIO" bitfld.long 0x1c 14.--15. " BANK0_PIN23 ,Pin 64, GPMI_WPN pin function selection" "gpmi_wpn,Reserved,Reserved,GPIO" textline " " bitfld.long 0x1c 12.--13. " BANK0_PIN22 ,Pin 63, GPMI_RDY3 pin function selection" "gpmi_ready3,Reserved,Reserved,GPIO" bitfld.long 0x1c 10.--11. " BANK0_PIN21 ,Pin 62, GPMI_RDY2 pin function selection" "gpmi_ready2,Reserved,Reserved,GPIO" bitfld.long 0x1c 8.--9. " BANK0_PIN20 ,Pin 43, GPMI_RDY1 pin function selection" "gpmi_ready1,Reserved,ssp2_cmd,GPIO" textline " " bitfld.long 0x1c 6.--7. " BANK0_PIN19 ,Pin 61, GPMI_RDY0 pin function selection" "gpmi_ready0,Reserved,ssp2_detect,GPIO" bitfld.long 0x1c 4.--5. " BANK0_PIN18 ,Pin 42, GPMI_CE2N pin function selection" "gpmi_ce2n,Reserved,Reserved,GPIO" bitfld.long 0x1c 2.--3. " BANK0_PIN17 ,Pin 41, GPMI_ALE pin function selection" "gpmi_ale,lcd_d17,Reserved,GPIO" textline " " bitfld.long 0x1c 0.--1. " BANK0_PIN16 ,Pin 40, GPMI_CLE pin function selection" "gpmi_cle,lcd_d16,Reserved,GPIO" line.long 0x20 "HW_PINCTRL_MUXSEL2,Pin Mux Select Register 2" bitfld.long 0x20 30.--31. " BANK1_PIN15 ,Pin 15, LCD_D15 pin function selection" "lcd_d15,etm_da7,saif1_sdata1,GPIO" bitfld.long 0x20 28.--29. " BANK1_PIN14 ,Pin 17, LCD_D14 pin function selection" "lcd_d14,etm_da6,saif1_sdata2,GPIO" bitfld.long 0x20 26.--27. " BANK1_PIN13 ,Pin 19, LCD_D13 pin function selection" "lcd_d13,etm_da5,saif2_sdata2,GPIO" textline " " bitfld.long 0x20 24.--25. " BANK1_PIN12 ,Pin 22, LCD_D12 pin function selection" "lcd_d12,etm_da4,saif2_sdata1,GPIO" bitfld.long 0x20 22.--23. " BANK1_PIN11 ,Pin 24, LCD_D11 pin function selection" "icd_d11,etm_da3,saif_Irclk,GPIO" bitfld.long 0x20 20.--21. " BANK1_PIN10 ,Pin 26, LCD_D10 pin function selection" "lcd_d10,etm_da2,saif_bitclk,GPIO" textline " " bitfld.long 0x20 18.--19. " BANK1_PIN09 ,Pin 28, LCD_D09 pin function selection" "lcd_d9,etm_da1,saif1_sdata0,GPIO" bitfld.long 0x20 16.--17. " BANK1_PIN08 ,Pin 27, LCD_D08 pin function selection" "lcd_d8,etm_da0,saif2_sdata0,GPIO" bitfld.long 0x20 14.--15. " BANK1_PIN07 ,Pin 25, LCD_D07 pin function selection" "lcd_d7,etm_da15,Reserved,GPIO" textline " " bitfld.long 0x20 12.--13. " BANK1_PIN06 ,Pin 23, LCD_D06 pin function selection" "lcd_d6,etm_da14,Reserved,GPIO" bitfld.long 0x20 10.--11. " BANK1_PIN05 ,Pin 21, LCD_D05 pin function selection" "lcd_d5,etm_da13,Reserved,GPIO" bitfld.long 0x20 8.--9. " BANK1_PIN04 ,Pin 18, LCD_D04 pin function selection" "lcd_d4,etm_da12,Reserved,GPIO" textline " " bitfld.long 0x20 6.--7. " BANK1_PIN03 ,Pin 16, LCD_D03 pin function selection" "lcd_d3,etm_da11,Reserved,GPIO" bitfld.long 0x20 4.--5. " BANK1_PIN02 ,Pin 14, LCD_D02 pin function selection" "lcd_d2,etm_da10,Reserved,GPIO" bitfld.long 0x20 2.--3. " BANK1_PIN01 ,Pin 12, LCD_D01 pin function selection" "lcd_d1,etm_da9,Reserved,GPIO" textline " " bitfld.long 0x20 0.--1. " BANK1_PIN00 ,Pin 10, LCD_D00 pin function selection" "lcd_d0,etm_da8,Reserved,GPIO" line.long 0x24 "HW_PINCTRL_MUXSEL2_SET,Pin Mux Select Set Register 2" bitfld.long 0x24 30.--31. " BANK1_PIN15 ,Pin 15, LCD_D15 pin function selection" "lcd_d15,etm_da7,saif1_sdata1,GPIO" bitfld.long 0x24 28.--29. " BANK1_PIN14 ,Pin 17, LCD_D14 pin function selection" "lcd_d14,etm_da6,saif1_sdata2,GPIO" bitfld.long 0x24 26.--27. " BANK1_PIN13 ,Pin 19, LCD_D13 pin function selection" "lcd_d13,etm_da5,saif2_sdata2,GPIO" textline " " bitfld.long 0x24 24.--25. " BANK1_PIN12 ,Pin 22, LCD_D12 pin function selection" "lcd_d12,etm_da4,saif2_sdata1,GPIO" bitfld.long 0x24 22.--23. " BANK1_PIN11 ,Pin 24, LCD_D11 pin function selection" "icd_d11,etm_da3,saif_Irclk,GPIO" bitfld.long 0x24 20.--21. " BANK1_PIN10 ,Pin 26, LCD_D10 pin function selection" "lcd_d10,etm_da2,saif_bitclk,GPIO" textline " " bitfld.long 0x24 18.--19. " BANK1_PIN09 ,Pin 28, LCD_D09 pin function selection" "lcd_d9,etm_da1,saif1_sdata0,GPIO" bitfld.long 0x24 16.--17. " BANK1_PIN08 ,Pin 27, LCD_D08 pin function selection" "lcd_d8,etm_da0,saif2_sdata0,GPIO" bitfld.long 0x24 14.--15. " BANK1_PIN07 ,Pin 25, LCD_D07 pin function selection" "lcd_d7,etm_da15,Reserved,GPIO" textline " " bitfld.long 0x24 12.--13. " BANK1_PIN06 ,Pin 23, LCD_D06 pin function selection" "lcd_d6,etm_da14,Reserved,GPIO" bitfld.long 0x24 10.--11. " BANK1_PIN05 ,Pin 21, LCD_D05 pin function selection" "lcd_d5,etm_da13,Reserved,GPIO" bitfld.long 0x24 8.--9. " BANK1_PIN04 ,Pin 18, LCD_D04 pin function selection" "lcd_d4,etm_da12,Reserved,GPIO" textline " " bitfld.long 0x24 6.--7. " BANK1_PIN03 ,Pin 16, LCD_D03 pin function selection" "lcd_d3,etm_da11,Reserved,GPIO" bitfld.long 0x24 4.--5. " BANK1_PIN02 ,Pin 14, LCD_D02 pin function selection" "lcd_d2,etm_da10,Reserved,GPIO" bitfld.long 0x24 2.--3. " BANK1_PIN01 ,Pin 12, LCD_D01 pin function selection" "lcd_d1,etm_da9,Reserved,GPIO" textline " " bitfld.long 0x24 0.--1. " BANK1_PIN00 ,Pin 10, LCD_D00 pin function selection" "lcd_d0,etm_da8,Reserved,GPIO" line.long 0x28 "HW_PINCTRL_MUXSEL2_CLR,Pin Mux Select Clear Register 2" bitfld.long 0x28 30.--31. " BANK1_PIN15 ,Pin 15, LCD_D15 pin function selection" "lcd_d15,etm_da7,saif1_sdata1,GPIO" bitfld.long 0x28 28.--29. " BANK1_PIN14 ,Pin 17, LCD_D14 pin function selection" "lcd_d14,etm_da6,saif1_sdata2,GPIO" bitfld.long 0x28 26.--27. " BANK1_PIN13 ,Pin 19, LCD_D13 pin function selection" "lcd_d13,etm_da5,saif2_sdata2,GPIO" textline " " bitfld.long 0x28 24.--25. " BANK1_PIN12 ,Pin 22, LCD_D12 pin function selection" "lcd_d12,etm_da4,saif2_sdata1,GPIO" bitfld.long 0x28 22.--23. " BANK1_PIN11 ,Pin 24, LCD_D11 pin function selection" "icd_d11,etm_da3,saif_Irclk,GPIO" bitfld.long 0x28 20.--21. " BANK1_PIN10 ,Pin 26, LCD_D10 pin function selection" "lcd_d10,etm_da2,saif_bitclk,GPIO" textline " " bitfld.long 0x28 18.--19. " BANK1_PIN09 ,Pin 28, LCD_D09 pin function selection" "lcd_d9,etm_da1,saif1_sdata0,GPIO" bitfld.long 0x28 16.--17. " BANK1_PIN08 ,Pin 27, LCD_D08 pin function selection" "lcd_d8,etm_da0,saif2_sdata0,GPIO" bitfld.long 0x28 14.--15. " BANK1_PIN07 ,Pin 25, LCD_D07 pin function selection" "lcd_d7,etm_da15,Reserved,GPIO" textline " " bitfld.long 0x28 12.--13. " BANK1_PIN06 ,Pin 23, LCD_D06 pin function selection" "lcd_d6,etm_da14,Reserved,GPIO" bitfld.long 0x28 10.--11. " BANK1_PIN05 ,Pin 21, LCD_D05 pin function selection" "lcd_d5,etm_da13,Reserved,GPIO" bitfld.long 0x28 8.--9. " BANK1_PIN04 ,Pin 18, LCD_D04 pin function selection" "lcd_d4,etm_da12,Reserved,GPIO" textline " " bitfld.long 0x28 6.--7. " BANK1_PIN03 ,Pin 16, LCD_D03 pin function selection" "lcd_d3,etm_da11,Reserved,GPIO" bitfld.long 0x28 4.--5. " BANK1_PIN02 ,Pin 14, LCD_D02 pin function selection" "lcd_d2,etm_da10,Reserved,GPIO" bitfld.long 0x28 2.--3. " BANK1_PIN01 ,Pin 12, LCD_D01 pin function selection" "lcd_d1,etm_da9,Reserved,GPIO" textline " " bitfld.long 0x28 0.--1. " BANK1_PIN00 ,Pin 10, LCD_D00 pin function selection" "lcd_d0,etm_da8,Reserved,GPIO" line.long 0x2c "HW_PINCTRL_MUXSEL2_TOG,Pin Mux Select Toggle Register 2" bitfld.long 0x2c 30.--31. " BANK1_PIN15 ,Pin 15, LCD_D15 pin function selection" "lcd_d15,etm_da7,saif1_sdata1,GPIO" bitfld.long 0x2c 28.--29. " BANK1_PIN14 ,Pin 17, LCD_D14 pin function selection" "lcd_d14,etm_da6,saif1_sdata2,GPIO" bitfld.long 0x2c 26.--27. " BANK1_PIN13 ,Pin 19, LCD_D13 pin function selection" "lcd_d13,etm_da5,saif2_sdata2,GPIO" textline " " bitfld.long 0x2c 24.--25. " BANK1_PIN12 ,Pin 22, LCD_D12 pin function selection" "lcd_d12,etm_da4,saif2_sdata1,GPIO" bitfld.long 0x2c 22.--23. " BANK1_PIN11 ,Pin 24, LCD_D11 pin function selection" "icd_d11,etm_da3,saif_Irclk,GPIO" bitfld.long 0x2c 20.--21. " BANK1_PIN10 ,Pin 26, LCD_D10 pin function selection" "lcd_d10,etm_da2,saif_bitclk,GPIO" textline " " bitfld.long 0x2c 18.--19. " BANK1_PIN09 ,Pin 28, LCD_D09 pin function selection" "lcd_d9,etm_da1,saif1_sdata0,GPIO" bitfld.long 0x2c 16.--17. " BANK1_PIN08 ,Pin 27, LCD_D08 pin function selection" "lcd_d8,etm_da0,saif2_sdata0,GPIO" bitfld.long 0x2c 14.--15. " BANK1_PIN07 ,Pin 25, LCD_D07 pin function selection" "lcd_d7,etm_da15,Reserved,GPIO" textline " " bitfld.long 0x2c 12.--13. " BANK1_PIN06 ,Pin 23, LCD_D06 pin function selection" "lcd_d6,etm_da14,Reserved,GPIO" bitfld.long 0x2c 10.--11. " BANK1_PIN05 ,Pin 21, LCD_D05 pin function selection" "lcd_d5,etm_da13,Reserved,GPIO" bitfld.long 0x2c 8.--9. " BANK1_PIN04 ,Pin 18, LCD_D04 pin function selection" "lcd_d4,etm_da12,Reserved,GPIO" textline " " bitfld.long 0x2c 6.--7. " BANK1_PIN03 ,Pin 16, LCD_D03 pin function selection" "lcd_d3,etm_da11,Reserved,GPIO" bitfld.long 0x2c 4.--5. " BANK1_PIN02 ,Pin 14, LCD_D02 pin function selection" "lcd_d2,etm_da10,Reserved,GPIO" bitfld.long 0x2c 2.--3. " BANK1_PIN01 ,Pin 12, LCD_D01 pin function selection" "lcd_d1,etm_da9,Reserved,GPIO" textline " " bitfld.long 0x2c 0.--1. " BANK1_PIN00 ,Pin 10, LCD_D00 pin function selection" "lcd_d0,etm_da8,Reserved,GPIO" line.long 0x30 "HW_PINCTRL_MUXSEL3,Pin Mux Select Register 3" bitfld.long 0x30 28.--29. " BANK1_PIN30 ,Pin 131, PWM4 pin function selection" "pwm4,etm_tclk,auart1_rts,GPIO" bitfld.long 0x30 26.--27. " BANK1_PIN29 ,Pin 130, PWM3 pin function selection" "pwm3,etm_tctl,auart1_cts,GPIO" textline " " bitfld.long 0x30 24.--25. " BANK1_PIN28 ,Pin 129, PWM2 pin function selection" "pwm2,gpmi_ready3,Reserved,GPIO" bitfld.long 0x30 22.--23. " BANK1_PIN27 ,Pin 3, PWM1 pin function selection" "pwm1,timrot2,duart_tx,GPIO" bitfld.long 0x30 20.--21. " BANK1_PIN26 ,Pin 1, PWM0 pin function selection" "pwm0,timrot1,duart_rx,GPIO" textline " " bitfld.long 0x30 18.--19. " BANK1_PIN25 ,Pin 35, LCD_VSYNC pin function selection" "lcd_vsync,lcd_busy,Reserved,GPIO" bitfld.long 0x30 16.--17. " BANK1_PIN24 ,Pin 34, LCD_HSYNC pin function selection" "lcd_hsync,i2c_sd,Reserved,GPIO" bitfld.long 0x30 14.--15. " BANK1_PIN23 ,Pin 30, LCD_ENABLE pin function selection" "lcd_enable,i2c_clk,Reserved,GPIO" textline " " bitfld.long 0x30 12.--13. " BANK1_PIN22 ,Pin 36, LCD_DOTCK pin function selection" "lcd_dotck,gpmi_ready3,Reserved,GPIO" bitfld.long 0x30 10.--11. " BANK1_PIN21 ,Pin 29, LCD_CS pin function selection" "lcd_cs,Reserved,Reserved,GPIO" bitfld.long 0x30 8.--9. " BANK1_PIN20 ,Pin 32, LCD_WR pin function selection" "lcd_wr,Reserved,Reserved,GPIO" textline " " bitfld.long 0x30 6.--7. " BANK1_PIN19 ,Pin 33, LCD_RS pin function selection" "lcd_rs,etm_tclk,Reserved,GPIO" bitfld.long 0x30 4.--5. " BANK1_PIN18 ,Pin 31, LCD_RESET pin function selection" "lcd_reset,etm_tctl,gpmi_ce3n,GPIO" bitfld.long 0x30 2.--3. " BANK1_PIN17 ,Pin 11, LCD_D17 pin function selection" "lcd_d17,Reserved,Reserved,GPIO" textline " " bitfld.long 0x30 0.--1. " BANK1_PIN16 ,Pin 13, LCD_D16 pin function selection" "lcd_d16,Reserved,saif_alt_bitclk,GPIO" line.long 0x34 "HW_PINCTRL_MUXSEL3_SET,Pin Mux Select Set Register 3" bitfld.long 0x34 28.--29. " BANK1_PIN30 ,Pin 131, PWM4 pin function selection" "pwm4,etm_tclk,auart1_rts,GPIO" bitfld.long 0x34 26.--27. " BANK1_PIN29 ,Pin 130, PWM3 pin function selection" "pwm3,etm_tctl,auart1_cts,GPIO" textline " " bitfld.long 0x34 24.--25. " BANK1_PIN28 ,Pin 129, PWM2 pin function selection" "pwm2,gpmi_ready3,Reserved,GPIO" bitfld.long 0x34 22.--23. " BANK1_PIN27 ,Pin 3, PWM1 pin function selection" "pwm1,timrot2,duart_tx,GPIO" bitfld.long 0x34 20.--21. " BANK1_PIN26 ,Pin 1, PWM0 pin function selection" "pwm0,timrot1,duart_rx,GPIO" textline " " bitfld.long 0x34 18.--19. " BANK1_PIN25 ,Pin 35, LCD_VSYNC pin function selection" "lcd_vsync,lcd_busy,Reserved,GPIO" bitfld.long 0x34 16.--17. " BANK1_PIN24 ,Pin 34, LCD_HSYNC pin function selection" "lcd_hsync,i2c_sd,Reserved,GPIO" bitfld.long 0x34 14.--15. " BANK1_PIN23 ,Pin 30, LCD_ENABLE pin function selection" "lcd_enable,i2c_clk,Reserved,GPIO" textline " " bitfld.long 0x34 12.--13. " BANK1_PIN22 ,Pin 36, LCD_DOTCK pin function selection" "lcd_dotck,gpmi_ready3,Reserved,GPIO" bitfld.long 0x34 10.--11. " BANK1_PIN21 ,Pin 29, LCD_CS pin function selection" "lcd_cs,Reserved,Reserved,GPIO" bitfld.long 0x34 8.--9. " BANK1_PIN20 ,Pin 32, LCD_WR pin function selection" "lcd_wr,Reserved,Reserved,GPIO" textline " " bitfld.long 0x34 6.--7. " BANK1_PIN19 ,Pin 33, LCD_RS pin function selection" "lcd_rs,etm_tclk,Reserved,GPIO" bitfld.long 0x34 4.--5. " BANK1_PIN18 ,Pin 31, LCD_RESET pin function selection" "lcd_reset,etm_tctl,gpmi_ce3n,GPIO" bitfld.long 0x34 2.--3. " BANK1_PIN17 ,Pin 11, LCD_D17 pin function selection" "lcd_d17,Reserved,Reserved,GPIO" textline " " bitfld.long 0x34 0.--1. " BANK1_PIN16 ,Pin 13, LCD_D16 pin function selection" "lcd_d16,Reserved,saif_alt_bitclk,GPIO" line.long 0x38 "HW_PINCTRL_MUXSEL3_CLR,Pin Mux Select Clear Register 3" bitfld.long 0x38 28.--29. " BANK1_PIN30 ,Pin 131, PWM4 pin function selection" "pwm4,etm_tclk,auart1_rts,GPIO" bitfld.long 0x38 26.--27. " BANK1_PIN29 ,Pin 130, PWM3 pin function selection" "pwm3,etm_tctl,auart1_cts,GPIO" textline " " bitfld.long 0x38 24.--25. " BANK1_PIN28 ,Pin 129, PWM2 pin function selection" "pwm2,gpmi_ready3,Reserved,GPIO" bitfld.long 0x38 22.--23. " BANK1_PIN27 ,Pin 3, PWM1 pin function selection" "pwm1,timrot2,duart_tx,GPIO" bitfld.long 0x38 20.--21. " BANK1_PIN26 ,Pin 1, PWM0 pin function selection" "pwm0,timrot1,duart_rx,GPIO" textline " " bitfld.long 0x38 18.--19. " BANK1_PIN25 ,Pin 35, LCD_VSYNC pin function selection" "lcd_vsync,lcd_busy,Reserved,GPIO" bitfld.long 0x38 16.--17. " BANK1_PIN24 ,Pin 34, LCD_HSYNC pin function selection" "lcd_hsync,i2c_sd,Reserved,GPIO" bitfld.long 0x38 14.--15. " BANK1_PIN23 ,Pin 30, LCD_ENABLE pin function selection" "lcd_enable,i2c_clk,Reserved,GPIO" textline " " bitfld.long 0x38 12.--13. " BANK1_PIN22 ,Pin 36, LCD_DOTCK pin function selection" "lcd_dotck,gpmi_ready3,Reserved,GPIO" bitfld.long 0x38 10.--11. " BANK1_PIN21 ,Pin 29, LCD_CS pin function selection" "lcd_cs,Reserved,Reserved,GPIO" bitfld.long 0x38 8.--9. " BANK1_PIN20 ,Pin 32, LCD_WR pin function selection" "lcd_wr,Reserved,Reserved,GPIO" textline " " bitfld.long 0x38 6.--7. " BANK1_PIN19 ,Pin 33, LCD_RS pin function selection" "lcd_rs,etm_tclk,Reserved,GPIO" bitfld.long 0x38 4.--5. " BANK1_PIN18 ,Pin 31, LCD_RESET pin function selection" "lcd_reset,etm_tctl,gpmi_ce3n,GPIO" bitfld.long 0x38 2.--3. " BANK1_PIN17 ,Pin 11, LCD_D17 pin function selection" "lcd_d17,Reserved,Reserved,GPIO" textline " " bitfld.long 0x38 0.--1. " BANK1_PIN16 ,Pin 13, LCD_D16 pin function selection" "lcd_d16,Reserved,saif_alt_bitclk,GPIO" line.long 0x3c "HW_PINCTRL_MUXSEL3_TOG,Pin Mux Select Toggle Register 3" bitfld.long 0x3c 28.--29. " BANK1_PIN30 ,Pin 131, PWM4 pin function selection" "pwm4,etm_tclk,auart1_rts,GPIO" bitfld.long 0x3c 26.--27. " BANK1_PIN29 ,Pin 130, PWM3 pin function selection" "pwm3,etm_tctl,auart1_cts,GPIO" textline " " bitfld.long 0x3c 24.--25. " BANK1_PIN28 ,Pin 129, PWM2 pin function selection" "pwm2,gpmi_ready3,Reserved,GPIO" bitfld.long 0x3c 22.--23. " BANK1_PIN27 ,Pin 3, PWM1 pin function selection" "pwm1,timrot2,duart_tx,GPIO" bitfld.long 0x3c 20.--21. " BANK1_PIN26 ,Pin 1, PWM0 pin function selection" "pwm0,timrot1,duart_rx,GPIO" textline " " bitfld.long 0x3c 18.--19. " BANK1_PIN25 ,Pin 35, LCD_VSYNC pin function selection" "lcd_vsync,lcd_busy,Reserved,GPIO" bitfld.long 0x3c 16.--17. " BANK1_PIN24 ,Pin 34, LCD_HSYNC pin function selection" "lcd_hsync,i2c_sd,Reserved,GPIO" bitfld.long 0x3c 14.--15. " BANK1_PIN23 ,Pin 30, LCD_ENABLE pin function selection" "lcd_enable,i2c_clk,Reserved,GPIO" textline " " bitfld.long 0x3c 12.--13. " BANK1_PIN22 ,Pin 36, LCD_DOTCK pin function selection" "lcd_dotck,gpmi_ready3,Reserved,GPIO" bitfld.long 0x3c 10.--11. " BANK1_PIN21 ,Pin 29, LCD_CS pin function selection" "lcd_cs,Reserved,Reserved,GPIO" bitfld.long 0x3c 8.--9. " BANK1_PIN20 ,Pin 32, LCD_WR pin function selection" "lcd_wr,Reserved,Reserved,GPIO" textline " " bitfld.long 0x3c 6.--7. " BANK1_PIN19 ,Pin 33, LCD_RS pin function selection" "lcd_rs,etm_tclk,Reserved,GPIO" bitfld.long 0x3c 4.--5. " BANK1_PIN18 ,Pin 31, LCD_RESET pin function selection" "lcd_reset,etm_tctl,gpmi_ce3n,GPIO" bitfld.long 0x3c 2.--3. " BANK1_PIN17 ,Pin 11, LCD_D17 pin function selection" "lcd_d17,Reserved,Reserved,GPIO" textline " " bitfld.long 0x3c 0.--1. " BANK1_PIN16 ,Pin 13, LCD_D16 pin function selection" "lcd_d16,Reserved,saif_alt_bitclk,GPIO" line.long 0x40 "HW_PINCTRL_MUXSEL4,Pin Mux Select Register 4" bitfld.long 0x40 30.--31. " BANK2_PIN15 ,Pin 108, EMI_A06 pin function selection" "emi_addr06,Reserved,Reserved,GPIO" bitfld.long 0x40 28.--29. " BANK2_PIN14 ,Pin 107, EMI_A05 pin function selection" "emi_addr05,Reserved,Reserved,GPIO" bitfld.long 0x40 26.--27. " BANK2_PIN13 ,Pin 109, EMI_A04 pin function selection" "emi_addr04,Reserved,Reserved,GPIO" textline " " bitfld.long 0x40 24.--25. " BANK2_PIN12 ,Pin 110, EMI_AO3 pin function selection" "emi_addr03,Reserved,Reserved,GPIO" bitfld.long 0x40 22.--23. " BANK2_PIN11 ,Pin 111, EMI_A02 pin function selection" "emi_addr02,Reserved,Reserved,GPIO" bitfld.long 0x40 20.--21. " BANK2_PIN10 ,Pin 112, EMI_A01 pin function selection" "emi_addr01,Reserved,Reserved,GPIO" textline " " bitfld.long 0x40 18.--19. " BANK2_PIN09 ,Pin 113, EMI_A00 pin function selection" "emi_addr00,Reserved,Reserved,GPIO" bitfld.long 0x40 16.--17. " BANK2_PIN08 ,Pin 38, ROTARYB pin function selection" "timrot2,auart2_cts,gpmi_ce3n,GPIO" bitfld.long 0x40 14.--15. " BANK2_PIN07 ,Pin 37, ROTARYA pin function selection" "timrot1,auart2_rts,spdif,GPIO" textline " " bitfld.long 0x40 12.--13. " BANK2_PIN06 ,Pin 127, SSP1_SCK pin function selection" "ssp1_sck,Reserved,alt_jtag_trs_n,GPIO" bitfld.long 0x40 10.--11. " BANK2_PIN05 ,Pin 125, SSP1_DATA3 pin function selection" "ssp1_d3,Reserved,alt_jtag_tms,GPIO" bitfld.long 0x40 8.--9. " BANK2_PIN04 ,Pin 124, SSP1_DATA2 pin function selection" "ssp1_d2,i2c_sd,alt_jtag_rtck,GPIO" textline " " bitfld.long 0x40 6.--7. " BANK2_PIN03 ,Pin 123, SSP1_DATA1 pin function selection" "ssp1_d1,Reserved,alt_jtag_tck,GPIO" bitfld.long 0x40 4.--5. " BANK2_PIN02 ,Pin 122, SSP1_DATA0 pin function selection" "ssp1_d0,Reserved,alt_jtag_tdi,GPIO" bitfld.long 0x40 2.--3. " BANK2_PIN01 ,Pin 126, SSP1_DETECT pin function selection" "ssp1_detect,gpmi_ce3n,usb_id,GPIO" textline " " bitfld.long 0x40 0.--1. " BANK2_PIN00 ,Pin 121, SSP1_CMD pin function selection" "ssp1_cmd,Reserved,alt_jtag_tdo,GPIO" line.long 0x44 "HW_PINCTRL_MUXSEL4_SET,Pin Mux Select Set Register 4" bitfld.long 0x44 30.--31. " BANK2_PIN15 ,Pin 108, EMI_A06 pin function selection" "emi_addr06,Reserved,Reserved,GPIO" bitfld.long 0x44 28.--29. " BANK2_PIN14 ,Pin 107, EMI_A05 pin function selection" "emi_addr05,Reserved,Reserved,GPIO" bitfld.long 0x44 26.--27. " BANK2_PIN13 ,Pin 109, EMI_A04 pin function selection" "emi_addr04,Reserved,Reserved,GPIO" textline " " bitfld.long 0x44 24.--25. " BANK2_PIN12 ,Pin 110, EMI_AO3 pin function selection" "emi_addr03,Reserved,Reserved,GPIO" bitfld.long 0x44 22.--23. " BANK2_PIN11 ,Pin 111, EMI_A02 pin function selection" "emi_addr02,Reserved,Reserved,GPIO" bitfld.long 0x44 20.--21. " BANK2_PIN10 ,Pin 112, EMI_A01 pin function selection" "emi_addr01,Reserved,Reserved,GPIO" textline " " bitfld.long 0x44 18.--19. " BANK2_PIN09 ,Pin 113, EMI_A00 pin function selection" "emi_addr00,Reserved,Reserved,GPIO" bitfld.long 0x44 16.--17. " BANK2_PIN08 ,Pin 38, ROTARYB pin function selection" "timrot2,auart2_cts,gpmi_ce3n,GPIO" bitfld.long 0x44 14.--15. " BANK2_PIN07 ,Pin 37, ROTARYA pin function selection" "timrot1,auart2_rts,spdif,GPIO" textline " " bitfld.long 0x44 12.--13. " BANK2_PIN06 ,Pin 127, SSP1_SCK pin function selection" "ssp1_sck,Reserved,alt_jtag_trs_n,GPIO" bitfld.long 0x44 10.--11. " BANK2_PIN05 ,Pin 125, SSP1_DATA3 pin function selection" "ssp1_d3,Reserved,alt_jtag_tms,GPIO" bitfld.long 0x44 8.--9. " BANK2_PIN04 ,Pin 124, SSP1_DATA2 pin function selection" "ssp1_d2,i2c_sd,alt_jtag_rtck,GPIO" textline " " bitfld.long 0x44 6.--7. " BANK2_PIN03 ,Pin 123, SSP1_DATA1 pin function selection" "ssp1_d1,Reserved,alt_jtag_tck,GPIO" bitfld.long 0x44 4.--5. " BANK2_PIN02 ,Pin 122, SSP1_DATA0 pin function selection" "ssp1_d0,Reserved,alt_jtag_tdi,GPIO" bitfld.long 0x44 2.--3. " BANK2_PIN01 ,Pin 126, SSP1_DETECT pin function selection" "ssp1_detect,gpmi_ce3n,usb_id,GPIO" textline " " bitfld.long 0x44 0.--1. " BANK2_PIN00 ,Pin 121, SSP1_CMD pin function selection" "ssp1_cmd,Reserved,alt_jtag_tdo,GPIO" line.long 0x48 "HW_PINCTRL_MUXSEL4_CLR,Pin Mux Select Clear Register 4" bitfld.long 0x48 30.--31. " BANK2_PIN15 ,Pin 108, EMI_A06 pin function selection" "emi_addr06,Reserved,Reserved,GPIO" bitfld.long 0x48 28.--29. " BANK2_PIN14 ,Pin 107, EMI_A05 pin function selection" "emi_addr05,Reserved,Reserved,GPIO" bitfld.long 0x48 26.--27. " BANK2_PIN13 ,Pin 109, EMI_A04 pin function selection" "emi_addr04,Reserved,Reserved,GPIO" textline " " bitfld.long 0x48 24.--25. " BANK2_PIN12 ,Pin 110, EMI_AO3 pin function selection" "emi_addr03,Reserved,Reserved,GPIO" bitfld.long 0x48 22.--23. " BANK2_PIN11 ,Pin 111, EMI_A02 pin function selection" "emi_addr02,Reserved,Reserved,GPIO" bitfld.long 0x48 20.--21. " BANK2_PIN10 ,Pin 112, EMI_A01 pin function selection" "emi_addr01,Reserved,Reserved,GPIO" textline " " bitfld.long 0x48 18.--19. " BANK2_PIN09 ,Pin 113, EMI_A00 pin function selection" "emi_addr00,Reserved,Reserved,GPIO" bitfld.long 0x48 16.--17. " BANK2_PIN08 ,Pin 38, ROTARYB pin function selection" "timrot2,auart2_cts,gpmi_ce3n,GPIO" bitfld.long 0x48 14.--15. " BANK2_PIN07 ,Pin 37, ROTARYA pin function selection" "timrot1,auart2_rts,spdif,GPIO" textline " " bitfld.long 0x48 12.--13. " BANK2_PIN06 ,Pin 127, SSP1_SCK pin function selection" "ssp1_sck,Reserved,alt_jtag_trs_n,GPIO" bitfld.long 0x48 10.--11. " BANK2_PIN05 ,Pin 125, SSP1_DATA3 pin function selection" "ssp1_d3,Reserved,alt_jtag_tms,GPIO" bitfld.long 0x48 8.--9. " BANK2_PIN04 ,Pin 124, SSP1_DATA2 pin function selection" "ssp1_d2,i2c_sd,alt_jtag_rtck,GPIO" textline " " bitfld.long 0x48 6.--7. " BANK2_PIN03 ,Pin 123, SSP1_DATA1 pin function selection" "ssp1_d1,Reserved,alt_jtag_tck,GPIO" bitfld.long 0x48 4.--5. " BANK2_PIN02 ,Pin 122, SSP1_DATA0 pin function selection" "ssp1_d0,Reserved,alt_jtag_tdi,GPIO" bitfld.long 0x48 2.--3. " BANK2_PIN01 ,Pin 126, SSP1_DETECT pin function selection" "ssp1_detect,gpmi_ce3n,usb_id,GPIO" textline " " bitfld.long 0x48 0.--1. " BANK2_PIN00 ,Pin 121, SSP1_CMD pin function selection" "ssp1_cmd,Reserved,alt_jtag_tdo,GPIO" line.long 0x4c "HW_PINCTRL_MUXSEL4_TOG,Pin Mux Select Toggle Register 4" bitfld.long 0x4c 30.--31. " BANK2_PIN15 ,Pin 108, EMI_A06 pin function selection" "emi_addr06,Reserved,Reserved,GPIO" bitfld.long 0x4c 28.--29. " BANK2_PIN14 ,Pin 107, EMI_A05 pin function selection" "emi_addr05,Reserved,Reserved,GPIO" bitfld.long 0x4c 26.--27. " BANK2_PIN13 ,Pin 109, EMI_A04 pin function selection" "emi_addr04,Reserved,Reserved,GPIO" textline " " bitfld.long 0x4c 24.--25. " BANK2_PIN12 ,Pin 110, EMI_AO3 pin function selection" "emi_addr03,Reserved,Reserved,GPIO" bitfld.long 0x4c 22.--23. " BANK2_PIN11 ,Pin 111, EMI_A02 pin function selection" "emi_addr02,Reserved,Reserved,GPIO" bitfld.long 0x4c 20.--21. " BANK2_PIN10 ,Pin 112, EMI_A01 pin function selection" "emi_addr01,Reserved,Reserved,GPIO" textline " " bitfld.long 0x4c 18.--19. " BANK2_PIN09 ,Pin 113, EMI_A00 pin function selection" "emi_addr00,Reserved,Reserved,GPIO" bitfld.long 0x4c 16.--17. " BANK2_PIN08 ,Pin 38, ROTARYB pin function selection" "timrot2,auart2_cts,gpmi_ce3n,GPIO" bitfld.long 0x4c 14.--15. " BANK2_PIN07 ,Pin 37, ROTARYA pin function selection" "timrot1,auart2_rts,spdif,GPIO" textline " " bitfld.long 0x4c 12.--13. " BANK2_PIN06 ,Pin 127, SSP1_SCK pin function selection" "ssp1_sck,Reserved,alt_jtag_trs_n,GPIO" bitfld.long 0x4c 10.--11. " BANK2_PIN05 ,Pin 125, SSP1_DATA3 pin function selection" "ssp1_d3,Reserved,alt_jtag_tms,GPIO" bitfld.long 0x4c 8.--9. " BANK2_PIN04 ,Pin 124, SSP1_DATA2 pin function selection" "ssp1_d2,i2c_sd,alt_jtag_rtck,GPIO" textline " " bitfld.long 0x4c 6.--7. " BANK2_PIN03 ,Pin 123, SSP1_DATA1 pin function selection" "ssp1_d1,Reserved,alt_jtag_tck,GPIO" bitfld.long 0x4c 4.--5. " BANK2_PIN02 ,Pin 122, SSP1_DATA0 pin function selection" "ssp1_d0,Reserved,alt_jtag_tdi,GPIO" bitfld.long 0x4c 2.--3. " BANK2_PIN01 ,Pin 126, SSP1_DETECT pin function selection" "ssp1_detect,gpmi_ce3n,usb_id,GPIO" textline " " bitfld.long 0x4c 0.--1. " BANK2_PIN00 ,Pin 121, SSP1_CMD pin function selection" "ssp1_cmd,Reserved,alt_jtag_tdo,GPIO" line.long 0x50 "HW_PINCTRL_MUXSEL5,Pin Mux Select Register 5" bitfld.long 0x50 30.--31. " BANK2_PIN31 ,Pin 114, EMI_WEN pin function selection" "emi_wen,Reserved,Reserved,GPIO" bitfld.long 0x50 28.--29. " BANK2_PIN30 ,Pin 98, EMI_RASN pin function selection" "emi_rasn,Reserved,Reserved,GPIO" bitfld.long 0x50 26.--27. " BANK2_PIN29 ,Pin 115, EMI_CKE pin function selection" "emi_cke,Reserved,Reserved,GPIO" textline " " bitfld.long 0x50 24.--25. " BANK2_PIN28 ,Pin 120, GPMI_CE0N pin function selection" "emi_gpmi_ce0n,Reserved,Reserved,GPIO" bitfld.long 0x50 22.--23. " BANK2_PIN27 ,Pin 118, GPMI_CE1N pin function selection" "emi_gpmi_ce1n,Reserved,Reserved,GPIO" bitfld.long 0x50 20.--21. " BANK2_PIN26 ,Pin 99, EMI_CE1N pin function selection" "emi_ce1n,Reserved,Reserved,GPIO" textline " " bitfld.long 0x50 18.--19. " BANK2_PIN25 ,Pin 100, EMI_CE0N pin function selection" "emi_ce0n,Reserved,Reserved,GPIO" bitfld.long 0x50 16.--17. " BANK2_PIN24 ,Pin 97, EMI_CASN pin function selection" "emi_casn,Reserved,Reserved,GPIO" bitfld.long 0x50 14.--15. " BANK2_PIN23 ,Pin 117, EMI_BA1 pin function selection" "emi_ba1,Reserved,Reserved,GPIO" textline " " bitfld.long 0x50 12.--13. " BANK2_PIN22 ,Pin 116, EMI_BA0 pin function selection" "emi_ba0,Reserved,Reserved,GPIO" bitfld.long 0x50 10.--11. " BANK2_PIN21 ,Pin 101, EMI_A12 pin function selection" "emi_addr12,Reserved,Reserved,GPIO" bitfld.long 0x50 8.--9. " BANK2_PIN20 ,Pin 102, EMI_A11 pin function selection" "emi_addr11,Reserved,Reserved,GPIO" textline " " bitfld.long 0x50 6.--7. " BANK2_PIN19 ,Pin 104, EMI_A10 pin function selection" "emi_addr10,Reserved,Reserved,GPIO" bitfld.long 0x50 4.--5. " BANK2_PIN18 ,Pin 103, EMI_A09 pin function selection" "emi_addr09,Reserved,Reserved,GPIO" bitfld.long 0x50 2.--3. " BANK2_PIN17 ,Pin 106, EMI_A08 pin function selection" "emi_addr08,Reserved,Reserved,GPIO" textline " " bitfld.long 0x50 0.--1. " BANK2_PIN16 ,Pin 105, EMI_A07 pin function selection" "emi_addr07,Reserved,Reserved,GPIO" line.long 0x54 "HW_PINCTRL_MUXSEL5_SET,Pin Mux Select Set Register 5" bitfld.long 0x54 30.--31. " BANK2_PIN31 ,Pin 114, EMI_WEN pin function selection" "emi_wen,Reserved,Reserved,GPIO" bitfld.long 0x54 28.--29. " BANK2_PIN30 ,Pin 98, EMI_RASN pin function selection" "emi_rasn,Reserved,Reserved,GPIO" bitfld.long 0x54 26.--27. " BANK2_PIN29 ,Pin 115, EMI_CKE pin function selection" "emi_cke,Reserved,Reserved,GPIO" textline " " bitfld.long 0x54 24.--25. " BANK2_PIN28 ,Pin 120, GPMI_CE0N pin function selection" "emi_gpmi_ce0n,Reserved,Reserved,GPIO" bitfld.long 0x54 22.--23. " BANK2_PIN27 ,Pin 118, GPMI_CE1N pin function selection" "emi_gpmi_ce1n,Reserved,Reserved,GPIO" bitfld.long 0x54 20.--21. " BANK2_PIN26 ,Pin 99, EMI_CE1N pin function selection" "emi_ce1n,Reserved,Reserved,GPIO" textline " " bitfld.long 0x54 18.--19. " BANK2_PIN25 ,Pin 100, EMI_CE0N pin function selection" "emi_ce0n,Reserved,Reserved,GPIO" bitfld.long 0x54 16.--17. " BANK2_PIN24 ,Pin 97, EMI_CASN pin function selection" "emi_casn,Reserved,Reserved,GPIO" bitfld.long 0x54 14.--15. " BANK2_PIN23 ,Pin 117, EMI_BA1 pin function selection" "emi_ba1,Reserved,Reserved,GPIO" textline " " bitfld.long 0x54 12.--13. " BANK2_PIN22 ,Pin 116, EMI_BA0 pin function selection" "emi_ba0,Reserved,Reserved,GPIO" bitfld.long 0x54 10.--11. " BANK2_PIN21 ,Pin 101, EMI_A12 pin function selection" "emi_addr12,Reserved,Reserved,GPIO" bitfld.long 0x54 8.--9. " BANK2_PIN20 ,Pin 102, EMI_A11 pin function selection" "emi_addr11,Reserved,Reserved,GPIO" textline " " bitfld.long 0x54 6.--7. " BANK2_PIN19 ,Pin 104, EMI_A10 pin function selection" "emi_addr10,Reserved,Reserved,GPIO" bitfld.long 0x54 4.--5. " BANK2_PIN18 ,Pin 103, EMI_A09 pin function selection" "emi_addr09,Reserved,Reserved,GPIO" bitfld.long 0x54 2.--3. " BANK2_PIN17 ,Pin 106, EMI_A08 pin function selection" "emi_addr08,Reserved,Reserved,GPIO" textline " " bitfld.long 0x54 0.--1. " BANK2_PIN16 ,Pin 105, EMI_A07 pin function selection" "emi_addr07,Reserved,Reserved,GPIO" line.long 0x58 "HW_PINCTRL_MUXSEL5_CLR,Pin Mux Select Clear Register 5" bitfld.long 0x58 30.--31. " BANK2_PIN31 ,Pin 114, EMI_WEN pin function selection" "emi_wen,Reserved,Reserved,GPIO" bitfld.long 0x58 28.--29. " BANK2_PIN30 ,Pin 98, EMI_RASN pin function selection" "emi_rasn,Reserved,Reserved,GPIO" bitfld.long 0x58 26.--27. " BANK2_PIN29 ,Pin 115, EMI_CKE pin function selection" "emi_cke,Reserved,Reserved,GPIO" textline " " bitfld.long 0x58 24.--25. " BANK2_PIN28 ,Pin 120, GPMI_CE0N pin function selection" "emi_gpmi_ce0n,Reserved,Reserved,GPIO" bitfld.long 0x58 22.--23. " BANK2_PIN27 ,Pin 118, GPMI_CE1N pin function selection" "emi_gpmi_ce1n,Reserved,Reserved,GPIO" bitfld.long 0x58 20.--21. " BANK2_PIN26 ,Pin 99, EMI_CE1N pin function selection" "emi_ce1n,Reserved,Reserved,GPIO" textline " " bitfld.long 0x58 18.--19. " BANK2_PIN25 ,Pin 100, EMI_CE0N pin function selection" "emi_ce0n,Reserved,Reserved,GPIO" bitfld.long 0x58 16.--17. " BANK2_PIN24 ,Pin 97, EMI_CASN pin function selection" "emi_casn,Reserved,Reserved,GPIO" bitfld.long 0x58 14.--15. " BANK2_PIN23 ,Pin 117, EMI_BA1 pin function selection" "emi_ba1,Reserved,Reserved,GPIO" textline " " bitfld.long 0x58 12.--13. " BANK2_PIN22 ,Pin 116, EMI_BA0 pin function selection" "emi_ba0,Reserved,Reserved,GPIO" bitfld.long 0x58 10.--11. " BANK2_PIN21 ,Pin 101, EMI_A12 pin function selection" "emi_addr12,Reserved,Reserved,GPIO" bitfld.long 0x58 8.--9. " BANK2_PIN20 ,Pin 102, EMI_A11 pin function selection" "emi_addr11,Reserved,Reserved,GPIO" textline " " bitfld.long 0x58 6.--7. " BANK2_PIN19 ,Pin 104, EMI_A10 pin function selection" "emi_addr10,Reserved,Reserved,GPIO" bitfld.long 0x58 4.--5. " BANK2_PIN18 ,Pin 103, EMI_A09 pin function selection" "emi_addr09,Reserved,Reserved,GPIO" bitfld.long 0x58 2.--3. " BANK2_PIN17 ,Pin 106, EMI_A08 pin function selection" "emi_addr08,Reserved,Reserved,GPIO" textline " " bitfld.long 0x58 0.--1. " BANK2_PIN16 ,Pin 105, EMI_A07 pin function selection" "emi_addr07,Reserved,Reserved,GPIO" line.long 0x5c "HW_PINCTRL_MUXSEL5_TOG,Pin Mux Select Toggle Register 5" bitfld.long 0x5c 30.--31. " BANK2_PIN31 ,Pin 114, EMI_WEN pin function selection" "emi_wen,Reserved,Reserved,GPIO" bitfld.long 0x5c 28.--29. " BANK2_PIN30 ,Pin 98, EMI_RASN pin function selection" "emi_rasn,Reserved,Reserved,GPIO" bitfld.long 0x5c 26.--27. " BANK2_PIN29 ,Pin 115, EMI_CKE pin function selection" "emi_cke,Reserved,Reserved,GPIO" textline " " bitfld.long 0x5c 24.--25. " BANK2_PIN28 ,Pin 120, GPMI_CE0N pin function selection" "emi_gpmi_ce0n,Reserved,Reserved,GPIO" bitfld.long 0x5c 22.--23. " BANK2_PIN27 ,Pin 118, GPMI_CE1N pin function selection" "emi_gpmi_ce1n,Reserved,Reserved,GPIO" bitfld.long 0x5c 20.--21. " BANK2_PIN26 ,Pin 99, EMI_CE1N pin function selection" "emi_ce1n,Reserved,Reserved,GPIO" textline " " bitfld.long 0x5c 18.--19. " BANK2_PIN25 ,Pin 100, EMI_CE0N pin function selection" "emi_ce0n,Reserved,Reserved,GPIO" bitfld.long 0x5c 16.--17. " BANK2_PIN24 ,Pin 97, EMI_CASN pin function selection" "emi_casn,Reserved,Reserved,GPIO" bitfld.long 0x5c 14.--15. " BANK2_PIN23 ,Pin 117, EMI_BA1 pin function selection" "emi_ba1,Reserved,Reserved,GPIO" textline " " bitfld.long 0x5c 12.--13. " BANK2_PIN22 ,Pin 116, EMI_BA0 pin function selection" "emi_ba0,Reserved,Reserved,GPIO" bitfld.long 0x5c 10.--11. " BANK2_PIN21 ,Pin 101, EMI_A12 pin function selection" "emi_addr12,Reserved,Reserved,GPIO" bitfld.long 0x5c 8.--9. " BANK2_PIN20 ,Pin 102, EMI_A11 pin function selection" "emi_addr11,Reserved,Reserved,GPIO" textline " " bitfld.long 0x5c 6.--7. " BANK2_PIN19 ,Pin 104, EMI_A10 pin function selection" "emi_addr10,Reserved,Reserved,GPIO" bitfld.long 0x5c 4.--5. " BANK2_PIN18 ,Pin 103, EMI_A09 pin function selection" "emi_addr09,Reserved,Reserved,GPIO" bitfld.long 0x5c 2.--3. " BANK2_PIN17 ,Pin 106, EMI_A08 pin function selection" "emi_addr08,Reserved,Reserved,GPIO" textline " " bitfld.long 0x5c 0.--1. " BANK2_PIN16 ,Pin 105, EMI_A07 pin function selection" "emi_addr07,Reserved,Reserved,GPIO" line.long 0x60 "HW_PINCTRL_MUXSEL6,Pin Mux Select Register 6" bitfld.long 0x60 30.--31. " BANK3_PIN15 ,Pin 95, EMI_D15 pin function selection" "emi_data15,Reserved,Reserved,Disabled" bitfld.long 0x60 28.--29. " BANK3_PIN14 ,Pin 96, EMI_D14 pin function selection" "emi_data14,Reserved,Reserved,Disabled" bitfld.long 0x60 26.--27. " BANK3_PIN13 ,Pin 94, EMI_D13 pin function selection" "emi_data13,Reserved,Reserved,Disabled" textline " " bitfld.long 0x60 24.--25. " BANK3_PIN12 ,Pin 93, EMI_D12 pin function selection" "emi_data12,Reserved,Reserved,Disabled" bitfld.long 0x60 22.--23. " BANK3_PIN11 ,Pin 91, EMI_D11 pin function selection" "emi_data11,Reserved,Reserved,Disabled" bitfld.long 0x60 20.--21. " BANK3_PIN10 ,Pin 89, EMI_D10 pin function selection" "emi_data10,Reserved,Reserved,Disabled" textline " " bitfld.long 0x60 18.--19. " BANK3_PIN09 ,Pin 87, EMI_D09 pin function selection" "emi_data09,Reserved,Reserved,Disabled" bitfld.long 0x60 16.--17. " BANK3_PIN08 ,Pin 86, EMI_D08 pin function selection" "emi_data08,Reserved,Reserved,Disabled" bitfld.long 0x60 14.--15. " BANK3_PIN07 ,Pin 85, EMI_D07 pin function selection" "emi_data07,Reserved,Reserved,Disabled" textline " " bitfld.long 0x60 12.--13. " BANK3_PIN06 ,Pin 84, EMI_D06 pin function selection" "emi_data06,Reserved,Reserved,Disabled" bitfld.long 0x60 10.--11. " BANK3_PIN05 ,Pin 83, EMI_D05 pin function selection" "emi_data05,Reserved,Reserved,Disabled" bitfld.long 0x60 8.--9. " BANK3_PIN04 ,Pin 82, EMI_D04 pin function selection" "emi_data04,Reserved,Reserved,Disabled" textline " " bitfld.long 0x60 6.--7. " BANK3_PIN03 ,Pin 79, EMI_D03 pin function selection" "emi_data03,Reserved,Reserved,Disabled" bitfld.long 0x60 4.--5. " BANK3_PIN02 ,Pin 77, EMI_D02 pin function selection" "emi_data02,Reserved,Reserved,Disabled" bitfld.long 0x60 2.--3. " BANK3_PIN01 ,Pin 76, EMI_D01 pin function selection" "emi_data01,Reserved,Reserved,Disabled" textline " " bitfld.long 0x60 0.--1. " BANK3_PIN00 ,Pin 75, EMI_D00 pin function selection" "emi_data00,Reserved,Reserved,Disabled" line.long 0x64 "HW_PINCTRL_MUXSEL6_SET,Pin Mux Select Register Set 6" bitfld.long 0x64 30.--31. " BANK3_PIN15 ,Pin 95, EMI_D15 pin function selection" "emi_data15,Reserved,Reserved,Disabled" bitfld.long 0x64 28.--29. " BANK3_PIN14 ,Pin 96, EMI_D14 pin function selection" "emi_data14,Reserved,Reserved,Disabled" bitfld.long 0x64 26.--27. " BANK3_PIN13 ,Pin 94, EMI_D13 pin function selection" "emi_data13,Reserved,Reserved,Disabled" textline " " bitfld.long 0x64 24.--25. " BANK3_PIN12 ,Pin 93, EMI_D12 pin function selection" "emi_data12,Reserved,Reserved,Disabled" bitfld.long 0x64 22.--23. " BANK3_PIN11 ,Pin 91, EMI_D11 pin function selection" "emi_data11,Reserved,Reserved,Disabled" bitfld.long 0x64 20.--21. " BANK3_PIN10 ,Pin 89, EMI_D10 pin function selection" "emi_data10,Reserved,Reserved,Disabled" textline " " bitfld.long 0x64 18.--19. " BANK3_PIN09 ,Pin 87, EMI_D09 pin function selection" "emi_data09,Reserved,Reserved,Disabled" bitfld.long 0x64 16.--17. " BANK3_PIN08 ,Pin 86, EMI_D08 pin function selection" "emi_data08,Reserved,Reserved,Disabled" bitfld.long 0x64 14.--15. " BANK3_PIN07 ,Pin 85, EMI_D07 pin function selection" "emi_data07,Reserved,Reserved,Disabled" textline " " bitfld.long 0x64 12.--13. " BANK3_PIN06 ,Pin 84, EMI_D06 pin function selection" "emi_data06,Reserved,Reserved,Disabled" bitfld.long 0x64 10.--11. " BANK3_PIN05 ,Pin 83, EMI_D05 pin function selection" "emi_data05,Reserved,Reserved,Disabled" bitfld.long 0x64 8.--9. " BANK3_PIN04 ,Pin 82, EMI_D04 pin function selection" "emi_data04,Reserved,Reserved,Disabled" textline " " bitfld.long 0x64 6.--7. " BANK3_PIN03 ,Pin 79, EMI_D03 pin function selection" "emi_data03,Reserved,Reserved,Disabled" bitfld.long 0x64 4.--5. " BANK3_PIN02 ,Pin 77, EMI_D02 pin function selection" "emi_data02,Reserved,Reserved,Disabled" bitfld.long 0x64 2.--3. " BANK3_PIN01 ,Pin 76, EMI_D01 pin function selection" "emi_data01,Reserved,Reserved,Disabled" textline " " bitfld.long 0x64 0.--1. " BANK3_PIN00 ,Pin 75, EMI_D00 pin function selection" "emi_data00,Reserved,Reserved,Disabled" line.long 0x68 "HW_PINCTRL_MUXSEL6_CLR,Pin Mux Select Clear Register 6" bitfld.long 0x68 30.--31. " BANK3_PIN15 ,Pin 95, EMI_D15 pin function selection" "emi_data15,Reserved,Reserved,Disabled" bitfld.long 0x68 28.--29. " BANK3_PIN14 ,Pin 96, EMI_D14 pin function selection" "emi_data14,Reserved,Reserved,Disabled" bitfld.long 0x68 26.--27. " BANK3_PIN13 ,Pin 94, EMI_D13 pin function selection" "emi_data13,Reserved,Reserved,Disabled" textline " " bitfld.long 0x68 24.--25. " BANK3_PIN12 ,Pin 93, EMI_D12 pin function selection" "emi_data12,Reserved,Reserved,Disabled" bitfld.long 0x68 22.--23. " BANK3_PIN11 ,Pin 91, EMI_D11 pin function selection" "emi_data11,Reserved,Reserved,Disabled" bitfld.long 0x68 20.--21. " BANK3_PIN10 ,Pin 89, EMI_D10 pin function selection" "emi_data10,Reserved,Reserved,Disabled" textline " " bitfld.long 0x68 18.--19. " BANK3_PIN09 ,Pin 87, EMI_D09 pin function selection" "emi_data09,Reserved,Reserved,Disabled" bitfld.long 0x68 16.--17. " BANK3_PIN08 ,Pin 86, EMI_D08 pin function selection" "emi_data08,Reserved,Reserved,Disabled" bitfld.long 0x68 14.--15. " BANK3_PIN07 ,Pin 85, EMI_D07 pin function selection" "emi_data07,Reserved,Reserved,Disabled" textline " " bitfld.long 0x68 12.--13. " BANK3_PIN06 ,Pin 84, EMI_D06 pin function selection" "emi_data06,Reserved,Reserved,Disabled" bitfld.long 0x68 10.--11. " BANK3_PIN05 ,Pin 83, EMI_D05 pin function selection" "emi_data05,Reserved,Reserved,Disabled" bitfld.long 0x68 8.--9. " BANK3_PIN04 ,Pin 82, EMI_D04 pin function selection" "emi_data04,Reserved,Reserved,Disabled" textline " " bitfld.long 0x68 6.--7. " BANK3_PIN03 ,Pin 79, EMI_D03 pin function selection" "emi_data03,Reserved,Reserved,Disabled" bitfld.long 0x68 4.--5. " BANK3_PIN02 ,Pin 77, EMI_D02 pin function selection" "emi_data02,Reserved,Reserved,Disabled" bitfld.long 0x68 2.--3. " BANK3_PIN01 ,Pin 76, EMI_D01 pin function selection" "emi_data01,Reserved,Reserved,Disabled" textline " " bitfld.long 0x68 0.--1. " BANK3_PIN00 ,Pin 75, EMI_D00 pin function selection" "emi_data00,Reserved,Reserved,Disabled" line.long 0x6c "HW_PINCTRL_MUXSEL6_TOG,Pin Mux Select Toggle Register 6" bitfld.long 0x6c 30.--31. " BANK3_PIN15 ,Pin 95, EMI_D15 pin function selection" "emi_data15,Reserved,Reserved,Disabled" bitfld.long 0x6c 28.--29. " BANK3_PIN14 ,Pin 96, EMI_D14 pin function selection" "emi_data14,Reserved,Reserved,Disabled" bitfld.long 0x6c 26.--27. " BANK3_PIN13 ,Pin 94, EMI_D13 pin function selection" "emi_data13,Reserved,Reserved,Disabled" textline " " bitfld.long 0x6c 24.--25. " BANK3_PIN12 ,Pin 93, EMI_D12 pin function selection" "emi_data12,Reserved,Reserved,Disabled" bitfld.long 0x6c 22.--23. " BANK3_PIN11 ,Pin 91, EMI_D11 pin function selection" "emi_data11,Reserved,Reserved,Disabled" bitfld.long 0x6c 20.--21. " BANK3_PIN10 ,Pin 89, EMI_D10 pin function selection" "emi_data10,Reserved,Reserved,Disabled" textline " " bitfld.long 0x6c 18.--19. " BANK3_PIN09 ,Pin 87, EMI_D09 pin function selection" "emi_data09,Reserved,Reserved,Disabled" bitfld.long 0x6c 16.--17. " BANK3_PIN08 ,Pin 86, EMI_D08 pin function selection" "emi_data08,Reserved,Reserved,Disabled" bitfld.long 0x6c 14.--15. " BANK3_PIN07 ,Pin 85, EMI_D07 pin function selection" "emi_data07,Reserved,Reserved,Disabled" textline " " bitfld.long 0x6c 12.--13. " BANK3_PIN06 ,Pin 84, EMI_D06 pin function selection" "emi_data06,Reserved,Reserved,Disabled" bitfld.long 0x6c 10.--11. " BANK3_PIN05 ,Pin 83, EMI_D05 pin function selection" "emi_data05,Reserved,Reserved,Disabled" bitfld.long 0x6c 8.--9. " BANK3_PIN04 ,Pin 82, EMI_D04 pin function selection" "emi_data04,Reserved,Reserved,Disabled" textline " " bitfld.long 0x6c 6.--7. " BANK3_PIN03 ,Pin 79, EMI_D03 pin function selection" "emi_data03,Reserved,Reserved,Disabled" bitfld.long 0x6c 4.--5. " BANK3_PIN02 ,Pin 77, EMI_D02 pin function selection" "emi_data02,Reserved,Reserved,Disabled" bitfld.long 0x6c 2.--3. " BANK3_PIN01 ,Pin 76, EMI_D01 pin function selection" "emi_data01,Reserved,Reserved,Disabled" textline " " bitfld.long 0x6c 0.--1. " BANK3_PIN00 ,Pin 75, EMI_D00 pin function selection" "emi_data00,Reserved,Reserved,Disabled" line.long 0x70 "HW_PINCTRL_MUXSEL7,Pin Mux Select Register 7" bitfld.long 0x70 10.--11. " BANK3_PIN21 ,Pin 72, EMI_CLKN pin function selection" "emi_clkn,Reserved,Reserved,Disabled" bitfld.long 0x70 8.--9. " BANK3_PIN20 ,Pin 70, EMI_CLK pin function selection" "emi_clk,Reserved,Reserved,Disabled" bitfld.long 0x70 6.--7. " BANK3_PIN19 ,Pin 74, EMI_DQS1 pin function selection" "emi_dqs1,Reserved,Reserved,Disabled" textline " " bitfld.long 0x70 4.--5. " BANK3_PIN18 ,Pin 73, EMI_DQS0 pin function selection" "emi_dqs0,Reserved,Reserved,Disabled" bitfld.long 0x70 2.--3. " BANK3_PIN17 ,Pin 92, EMI_DQM1 pin function selection" "emi_dqm1,Reserved,Reserved,Disabled" bitfld.long 0x70 0.--1. " BANK3_PIN16 ,Pin 81, EMI_DQM0 pin function selection" "emi_dqm0,Reserved,Reserved,Disabled" line.long 0x74 "HW_PINCTRL_MUXSEL7_SET,Pin Mux Select Set Register 7" bitfld.long 0x74 10.--11. " BANK3_PIN21 ,Pin 72, EMI_CLKN pin function selection" "emi_clkn,Reserved,Reserved,Disabled" bitfld.long 0x74 8.--9. " BANK3_PIN20 ,Pin 70, EMI_CLK pin function selection" "emi_clk,Reserved,Reserved,Disabled" bitfld.long 0x74 6.--7. " BANK3_PIN19 ,Pin 74, EMI_DQS1 pin function selection" "emi_dqs1,Reserved,Reserved,Disabled" textline " " bitfld.long 0x74 4.--5. " BANK3_PIN18 ,Pin 73, EMI_DQS0 pin function selection" "emi_dqs0,Reserved,Reserved,Disabled" bitfld.long 0x74 2.--3. " BANK3_PIN17 ,Pin 92, EMI_DQM1 pin function selection" "emi_dqm1,Reserved,Reserved,Disabled" bitfld.long 0x74 0.--1. " BANK3_PIN16 ,Pin 81, EMI_DQM0 pin function selection" "emi_dqm0,Reserved,Reserved,Disabled" line.long 0x78 "HW_PINCTRL_MUXSEL7_CLR,Pin Mux Select Clear Register 7" bitfld.long 0x78 10.--11. " BANK3_PIN21 ,Pin 72, EMI_CLKN pin function selection" "emi_clkn,Reserved,Reserved,Disabled" bitfld.long 0x78 8.--9. " BANK3_PIN20 ,Pin 70, EMI_CLK pin function selection" "emi_clk,Reserved,Reserved,Disabled" bitfld.long 0x78 6.--7. " BANK3_PIN19 ,Pin 74, EMI_DQS1 pin function selection" "emi_dqs1,Reserved,Reserved,Disabled" textline " " bitfld.long 0x78 4.--5. " BANK3_PIN18 ,Pin 73, EMI_DQS0 pin function selection" "emi_dqs0,Reserved,Reserved,Disabled" bitfld.long 0x78 2.--3. " BANK3_PIN17 ,Pin 92, EMI_DQM1 pin function selection" "emi_dqm1,Reserved,Reserved,Disabled" bitfld.long 0x78 0.--1. " BANK3_PIN16 ,Pin 81, EMI_DQM0 pin function selection" "emi_dqm0,Reserved,Reserved,Disabled" line.long 0x7c "HW_PINCTRL_MUXSEL7_TOG,Pin Mux Select Toggle Register 7" bitfld.long 0x7c 10.--11. " BANK3_PIN21 ,Pin 72, EMI_CLKN pin function selection" "emi_clkn,Reserved,Reserved,Disabled" bitfld.long 0x7c 8.--9. " BANK3_PIN20 ,Pin 70, EMI_CLK pin function selection" "emi_clk,Reserved,Reserved,Disabled" bitfld.long 0x7c 6.--7. " BANK3_PIN19 ,Pin 74, EMI_DQS1 pin function selection" "emi_dqs1,Reserved,Reserved,Disabled" textline " " bitfld.long 0x7c 4.--5. " BANK3_PIN18 ,Pin 73, EMI_DQS0 pin function selection" "emi_dqs0,Reserved,Reserved,Disabled" bitfld.long 0x7c 2.--3. " BANK3_PIN17 ,Pin 92, EMI_DQM1 pin function selection" "emi_dqm1,Reserved,Reserved,Disabled" bitfld.long 0x7c 0.--1. " BANK3_PIN16 ,Pin 81, EMI_DQM0 pin function selection" "emi_dqm0,Reserved,Reserved,Disabled" tree.end tree "Drive Strength Registers" width 24. group.long 0x200++0xef line.long 0x00 "HW_PINCTRL_DRIVE0,Drive Strength and Voltage Register 0" bitfld.long 0x00 28.--29. " BANK0_PIN07_MA ,Pin 50, GPMI_D07 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x00 24.--25. " BANK0_PIN06_MA ,Pin 51, GPMI_D06 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x00 20.--21. " BANK0_PIN05_MA ,Pin 48, GPMI_D05 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x00 16.--17. " BANK0_PIN04_MA ,Pin 49, GPMI_D04 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x00 12.--13. " BANK0_PIN03_MA ,Pin 47, GPMI_D03 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x00 8.--9. " BANK0_PIN02_MA ,Pin 46, GPMI_D02 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x00 4.--5. " BANK0_PIN01_MA ,Pin 45, GPMI_D01 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x00 0.--1. " BANK0_PIN00_MA ,Pin 44, GPMI_D00 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x04 "HW_PINCTRL_DRIVE0_SET,Drive Strength and Voltage Set Register 0" bitfld.long 0x04 28.--29. " BANK0_PIN07_MA ,Pin 50, GPMI_D07 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x04 24.--25. " BANK0_PIN06_MA ,Pin 51, GPMI_D06 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x04 20.--21. " BANK0_PIN05_MA ,Pin 48, GPMI_D05 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x04 16.--17. " BANK0_PIN04_MA ,Pin 49, GPMI_D04 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x04 12.--13. " BANK0_PIN03_MA ,Pin 47, GPMI_D03 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x04 8.--9. " BANK0_PIN02_MA ,Pin 46, GPMI_D02 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x04 4.--5. " BANK0_PIN01_MA ,Pin 45, GPMI_D01 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x04 0.--1. " BANK0_PIN00_MA ,Pin 44, GPMI_D00 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x08 "HW_PINCTRL_DRIVE0_CLR,Drive Strength and Voltage Clear Register 0" bitfld.long 0x08 28.--29. " BANK0_PIN07_MA ,Pin 50, GPMI_D07 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x08 24.--25. " BANK0_PIN06_MA ,Pin 51, GPMI_D06 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x08 20.--21. " BANK0_PIN05_MA ,Pin 48, GPMI_D05 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x08 16.--17. " BANK0_PIN04_MA ,Pin 49, GPMI_D04 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x08 12.--13. " BANK0_PIN03_MA ,Pin 47, GPMI_D03 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x08 8.--9. " BANK0_PIN02_MA ,Pin 46, GPMI_D02 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x08 4.--5. " BANK0_PIN01_MA ,Pin 45, GPMI_D01 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x08 0.--1. " BANK0_PIN00_MA ,Pin 44, GPMI_D00 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x0c "HW_PINCTRL_DRIVE0_TOG,Drive Strength and Voltage Toggle Register 0" bitfld.long 0x0c 28.--29. " BANK0_PIN07_MA ,Pin 50, GPMI_D07 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x0c 24.--25. " BANK0_PIN06_MA ,Pin 51, GPMI_D06 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x0c 20.--21. " BANK0_PIN05_MA ,Pin 48, GPMI_D05 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x0c 16.--17. " BANK0_PIN04_MA ,Pin 49, GPMI_D04 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x0c 12.--13. " BANK0_PIN03_MA ,Pin 47, GPMI_D03 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x0c 8.--9. " BANK0_PIN02_MA ,Pin 46, GPMI_D02 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x0c 4.--5. " BANK0_PIN01_MA ,Pin 45, GPMI_D01 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x0c 0.--1. " BANK0_PIN00_MA ,Pin 44, GPMI_D00 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x10 "HW_PINCTRL_DRIVE1,Drive Strength and Voltage Register 1" bitfld.long 0x10 28.--29. " BANK0_PIN15_MA ,Pin 59, GPMI_D15 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x10 24.--25. " BANK0_PIN14_MA ,Pin 58, GPMI_D14 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x10 20.--21. " BANK0_PIN13_MA ,Pin 57, GPMI_D13 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x10 16.--17. " BANK0_PIN12_MA ,Pin 56, GPMI_D12 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x10 12.--13. " BANK0_PIN11_MA ,Pin 55, GPMI_D11 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x10 8.--9. " BANK0_PIN010_MA ,Pin 54, GPMI_D10 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x10 4.--5. " BANK0_PIN09_MA ,Pin 53, GPMI_D09 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x10 0.--1. " BANK0_PIN08_MA ,Pin 52, GPMI_D08 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x14 "HW_PINCTRL_DRIVE1_SET,Drive Strength and Voltage Set Register 1" bitfld.long 0x14 28.--29. " BANK0_PIN15_MA ,Pin 59, GPMI_D15 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x14 24.--25. " BANK0_PIN14_MA ,Pin 58, GPMI_D14 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x14 20.--21. " BANK0_PIN13_MA ,Pin 57, GPMI_D13 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x14 16.--17. " BANK0_PIN12_MA ,Pin 56, GPMI_D12 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x14 12.--13. " BANK0_PIN11_MA ,Pin 55, GPMI_D11 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x14 8.--9. " BANK0_PIN010_MA ,Pin 54, GPMI_D10 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x14 4.--5. " BANK0_PIN09_MA ,Pin 53, GPMI_D09 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x14 0.--1. " BANK0_PIN08_MA ,Pin 52, GPMI_D08 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x18 "HW_PINCTRL_DRIVE1_CR,Drive Strength and Voltage Clear Register 1" bitfld.long 0x18 28.--29. " BANK0_PIN15_MA ,Pin 59, GPMI_D15 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x18 24.--25. " BANK0_PIN14_MA ,Pin 58, GPMI_D14 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x18 20.--21. " BANK0_PIN13_MA ,Pin 57, GPMI_D13 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x18 16.--17. " BANK0_PIN12_MA ,Pin 56, GPMI_D12 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x18 12.--13. " BANK0_PIN11_MA ,Pin 55, GPMI_D11 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x18 8.--9. " BANK0_PIN010_MA ,Pin 54, GPMI_D10 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x18 4.--5. " BANK0_PIN09_MA ,Pin 53, GPMI_D09 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x18 0.--1. " BANK0_PIN08_MA ,Pin 52, GPMI_D08 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x1c "HW_PINCTRL_DRIVE1_TOG,Drive Strength and Voltage Toggle Register 1" bitfld.long 0x1c 28.--29. " BANK0_PIN15_MA ,Pin 59, GPMI_D15 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x1c 24.--25. " BANK0_PIN14_MA ,Pin 58, GPMI_D14 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x1c 20.--21. " BANK0_PIN13_MA ,Pin 57, GPMI_D13 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x1c 16.--17. " BANK0_PIN12_MA ,Pin 56, GPMI_D12 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x1c 12.--13. " BANK0_PIN11_MA ,Pin 55, GPMI_D11 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x1c 8.--9. " BANK0_PIN010_MA ,Pin 54, GPMI_D10 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x1c 4.--5. " BANK0_PIN09_MA ,Pin 53, GPMI_D09 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x1c 0.--1. " BANK0_PIN08_MA ,Pin 52, GPMI_D08 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x20 "HW_PINCTRL_DRIVE2,Drive Strength and Voltage Register 2" bitfld.long 0x20 28.--29. " BANK0_PIN23_MA ,Pin 64, GPMI_WPN pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x20 24.--25. " BANK0_PIN22_MA ,Pin 63, GPMI_RDY3 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x20 20.--21. " BANK0_PIN21_MA ,Pin 62, GPMI_RDY2 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x20 16.--17. " BANK0_PIN20_MA ,Pin 43, GPMI_RDY1 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x20 12.--13. " BANK0_PIN19_MA ,Pin 61, GPMI_RDY0 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x20 8.--9. " BANK0_PIN18_MA ,Pin 42, GPMI_CE2N pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x20 4.--5. " BANK0_PIN17_MA ,Pin 41, GPMI_ALE pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x20 0.--1. " BANK0_PIN16_MA ,Pin 40, GPMI_CLE pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x24 "HW_PINCTRL_DRIVE2_SET,Drive Strength and Voltage Set Register 2" bitfld.long 0x24 28.--29. " BANK0_PIN23_MA ,Pin 64, GPMI_WPN pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x24 24.--25. " BANK0_PIN22_MA ,Pin 63, GPMI_RDY3 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x24 20.--21. " BANK0_PIN21_MA ,Pin 62, GPMI_RDY2 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x24 16.--17. " BANK0_PIN20_MA ,Pin 43, GPMI_RDY1 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x24 12.--13. " BANK0_PIN19_MA ,Pin 61, GPMI_RDY0 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x24 8.--9. " BANK0_PIN18_MA ,Pin 42, GPMI_CE2N pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x24 4.--5. " BANK0_PIN17_MA ,Pin 41, GPMI_ALE pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x24 0.--1. " BANK0_PIN16_MA ,Pin 40, GPMI_CLE pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x28 "HW_PINCTRL_DRIVE2_CLR,Drive Strength and Voltage Clear Register 2" bitfld.long 0x28 28.--29. " BANK0_PIN23_MA ,Pin 64, GPMI_WPN pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x28 24.--25. " BANK0_PIN22_MA ,Pin 63, GPMI_RDY3 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x28 20.--21. " BANK0_PIN21_MA ,Pin 62, GPMI_RDY2 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x28 16.--17. " BANK0_PIN20_MA ,Pin 43, GPMI_RDY1 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x28 12.--13. " BANK0_PIN19_MA ,Pin 61, GPMI_RDY0 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x28 8.--9. " BANK0_PIN18_MA ,Pin 42, GPMI_CE2N pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x28 4.--5. " BANK0_PIN17_MA ,Pin 41, GPMI_ALE pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x28 0.--1. " BANK0_PIN16_MA ,Pin 40, GPMI_CLE pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x2c "HW_PINCTRL_DRIVE2_TOG,Drive Strength and Voltage Toggle Register 2" bitfld.long 0x2c 28.--29. " BANK0_PIN23_MA ,Pin 64, GPMI_WPN pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x2c 24.--25. " BANK0_PIN22_MA ,Pin 63, GPMI_RDY3 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x2c 20.--21. " BANK0_PIN21_MA ,Pin 62, GPMI_RDY2 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x2c 16.--17. " BANK0_PIN20_MA ,Pin 43, GPMI_RDY1 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x2c 12.--13. " BANK0_PIN19_MA ,Pin 61, GPMI_RDY0 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x2c 8.--9. " BANK0_PIN18_MA ,Pin 42, GPMI_CE2N pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x2c 4.--5. " BANK0_PIN17_MA ,Pin 41, GPMI_ALE pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x2c 0.--1. " BANK0_PIN16_MA ,Pin 40, GPMI_CLE pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x30 "HW_PINCTRL_DRIVE3,Drive Strength and Voltage Register 3" bitfld.long 0x30 28.--29. " BANK0_PIN31_MA ,Pin 4, I2C_SDA pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x30 24.--25. " BANK0_PIN30_MA ,Pin 2, I2C_SCL pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x30 20.--21. " BANK0_PIN29_MA ,Pin 69, AUART1_TX pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x30 16.--17. " BANK0_PIN28_MA ,Pin 68, AUART1_RX pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x30 12.--13. " BANK0_PIN27_MA ,Pin 67, AUART1_RTS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x30 8.--9. " BANK0_PIN26_MA ,Pin 66, AUART1_CTS pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x30 4.--5. " BANK0_PIN25_MA ,Pin 60, GPMI_RDN pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x30 0.--1. " BANK0_PIN24_MA ,Pin 65, GPMI_WRN pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x34 "HW_PINCTRL_DRIVE3_SET,Drive Strength and Voltage Set Register 3" bitfld.long 0x34 28.--29. " BANK0_PIN31_MA ,Pin 4, I2C_SDA pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x34 24.--25. " BANK0_PIN30_MA ,Pin 2, I2C_SCL pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x34 20.--21. " BANK0_PIN29_MA ,Pin 69, AUART1_TX pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x34 16.--17. " BANK0_PIN28_MA ,Pin 68, AUART1_RX pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x34 12.--13. " BANK0_PIN27_MA ,Pin 67, AUART1_RTS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x34 8.--9. " BANK0_PIN26_MA ,Pin 66, AUART1_CTS pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x34 4.--5. " BANK0_PIN25_MA ,Pin 60, GPMI_RDN pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x34 0.--1. " BANK0_PIN24_MA ,Pin 65, GPMI_WRN pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x38 "HW_PINCTRL_DRIVE3_CLR,Drive Strength and Voltage Clear Register 3" bitfld.long 0x38 28.--29. " BANK0_PIN31_MA ,Pin 4, I2C_SDA pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x38 24.--25. " BANK0_PIN30_MA ,Pin 2, I2C_SCL pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x38 20.--21. " BANK0_PIN29_MA ,Pin 69, AUART1_TX pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x38 16.--17. " BANK0_PIN28_MA ,Pin 68, AUART1_RX pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x38 12.--13. " BANK0_PIN27_MA ,Pin 67, AUART1_RTS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x38 8.--9. " BANK0_PIN26_MA ,Pin 66, AUART1_CTS pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x38 4.--5. " BANK0_PIN25_MA ,Pin 60, GPMI_RDN pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x38 0.--1. " BANK0_PIN24_MA ,Pin 65, GPMI_WRN pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x3c "HW_PINCTRL_DRIVE3_TOG,Drive Strength and Voltage Toggle Register 3" bitfld.long 0x3c 28.--29. " BANK0_PIN31_MA ,Pin 4, I2C_SDA pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x3c 24.--25. " BANK0_PIN30_MA ,Pin 2, I2C_SCL pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x3c 20.--21. " BANK0_PIN29_MA ,Pin 69, AUART1_TX pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x3c 16.--17. " BANK0_PIN28_MA ,Pin 68, AUART1_RX pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x3c 12.--13. " BANK0_PIN27_MA ,Pin 67, AUART1_RTS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x3c 8.--9. " BANK0_PIN26_MA ,Pin 66, AUART1_CTS pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x3c 4.--5. " BANK0_PIN25_MA ,Pin 60, GPMI_RDN pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x3c 0.--1. " BANK0_PIN24_MA ,Pin 65, GPMI_WRN pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x40 "HW_PINCTRL_DRIVE4,Drive Strength and Voltage Register 4" bitfld.long 0x40 28.--29. " BANK1_PIN07_MA ,Pin 25, LCD_D07 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x40 24.--25. " BANK1_PIN06_MA ,Pin 23, LCD_D06 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x40 20.--21. " BANK1_PIN05_MA ,Pin 21, LCD_D05 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x40 16.--17. " BANK1_PIN04_MA ,Pin 18, LCD_D04 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x40 12.--13. " BANK1_PIN03_MA ,Pin 16, LCD_D03 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x40 8.--9. " BANK1_PIN02_MA ,Pin 14, LCD_D02 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x40 4.--5. " BANK1_PIN01_MA ,Pin 12, LCD_D01 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x40 0.--1. " BANK1_PIN00_MA ,Pin 10, LCD_D00 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x44 "HW_PINCTRL_DRIVE4_SET,Drive Strength and Voltage Set Register 4" bitfld.long 0x44 28.--29. " BANK1_PIN07_MA ,Pin 25, LCD_D07 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x44 24.--25. " BANK1_PIN06_MA ,Pin 23, LCD_D06 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x44 20.--21. " BANK1_PIN05_MA ,Pin 21, LCD_D05 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x44 16.--17. " BANK1_PIN04_MA ,Pin 18, LCD_D04 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x44 12.--13. " BANK1_PIN03_MA ,Pin 16, LCD_D03 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x44 8.--9. " BANK1_PIN02_MA ,Pin 14, LCD_D02 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x44 4.--5. " BANK1_PIN01_MA ,Pin 12, LCD_D01 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x44 0.--1. " BANK1_PIN00_MA ,Pin 10, LCD_D00 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x48 "HW_PINCTRL_DRIVE4_CLR,Drive Strength and Voltage Clear Register 4" bitfld.long 0x48 28.--29. " BANK1_PIN07_MA ,Pin 25, LCD_D07 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x48 24.--25. " BANK1_PIN06_MA ,Pin 23, LCD_D06 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x48 20.--21. " BANK1_PIN05_MA ,Pin 21, LCD_D05 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x48 16.--17. " BANK1_PIN04_MA ,Pin 18, LCD_D04 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x48 12.--13. " BANK1_PIN03_MA ,Pin 16, LCD_D03 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x48 8.--9. " BANK1_PIN02_MA ,Pin 14, LCD_D02 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x48 4.--5. " BANK1_PIN01_MA ,Pin 12, LCD_D01 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x48 0.--1. " BANK1_PIN00_MA ,Pin 10, LCD_D00 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x4c "HW_PINCTRL_DRIVE4_TOG,Drive Strength and Voltage Toggle Register 4" bitfld.long 0x4c 28.--29. " BANK1_PIN07_MA ,Pin 25, LCD_D07 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x4c 24.--25. " BANK1_PIN06_MA ,Pin 23, LCD_D06 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x4c 20.--21. " BANK1_PIN05_MA ,Pin 21, LCD_D05 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x4c 16.--17. " BANK1_PIN04_MA ,Pin 18, LCD_D04 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x4c 12.--13. " BANK1_PIN03_MA ,Pin 16, LCD_D03 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x4c 8.--9. " BANK1_PIN02_MA ,Pin 14, LCD_D02 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x4c 4.--5. " BANK1_PIN01_MA ,Pin 12, LCD_D01 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x4c 0.--1. " BANK1_PIN00_MA ,Pin 10, LCD_D00 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x50 "HW_PINCTRL_DRIVE5,Drive Strength and Voltage Register 5" bitfld.long 0x50 28.--29. " BANK1_PIN15_MA ,Pin 15, LCD_D15 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x50 24.--25. " BANK1_PIN14_MA ,Pin 17, LCD_D14 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x50 20.--21. " BANK1_PIN13_MA ,Pin 19, LCD_D13 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x50 16.--17. " BANK1_PIN12_MA ,Pin 22, LCD_D12 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x50 12.--13. " BANK1_PIN11_MA ,Pin 24, LCD_D11 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x50 8.--9. " BANK1_PIN10_MA ,Pin 26, LCD_D10 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x50 4.--5. " BANK1_PIN09_MA ,Pin 28, LCD_D09 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x50 0.--1. " BANK1_PIN08_MA ,Pin 27, LCD_D08 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x54 "HW_PINCTRL_DRIVE5_SET,Drive Strength and Voltage Set Register 5" bitfld.long 0x54 28.--29. " BANK1_PIN15_MA ,Pin 15, LCD_D15 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x54 24.--25. " BANK1_PIN14_MA ,Pin 17, LCD_D14 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x54 20.--21. " BANK1_PIN13_MA ,Pin 19, LCD_D13 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x54 16.--17. " BANK1_PIN12_MA ,Pin 22, LCD_D12 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x54 12.--13. " BANK1_PIN11_MA ,Pin 24, LCD_D11 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x54 8.--9. " BANK1_PIN10_MA ,Pin 26, LCD_D10 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x54 4.--5. " BANK1_PIN09_MA ,Pin 28, LCD_D09 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x54 0.--1. " BANK1_PIN08_MA ,Pin 27, LCD_D08 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x58 "HW_PINCTRL_DRIVE5_CLR,Drive Strength and Voltage Clear Register 5" bitfld.long 0x58 28.--29. " BANK1_PIN15_MA ,Pin 15, LCD_D15 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x58 24.--25. " BANK1_PIN14_MA ,Pin 17, LCD_D14 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x58 20.--21. " BANK1_PIN13_MA ,Pin 19, LCD_D13 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x58 16.--17. " BANK1_PIN12_MA ,Pin 22, LCD_D12 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x58 12.--13. " BANK1_PIN11_MA ,Pin 24, LCD_D11 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x58 8.--9. " BANK1_PIN10_MA ,Pin 26, LCD_D10 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x58 4.--5. " BANK1_PIN09_MA ,Pin 28, LCD_D09 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x58 0.--1. " BANK1_PIN08_MA ,Pin 27, LCD_D08 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x5c "HW_PINCTRL_DRIVE5_TOG,Drive Strength and Voltage Toggle Register 5" bitfld.long 0x5c 28.--29. " BANK1_PIN15_MA ,Pin 15, LCD_D15 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x5c 24.--25. " BANK1_PIN14_MA ,Pin 17, LCD_D14 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x5c 20.--21. " BANK1_PIN13_MA ,Pin 19, LCD_D13 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x5c 16.--17. " BANK1_PIN12_MA ,Pin 22, LCD_D12 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x5c 12.--13. " BANK1_PIN11_MA ,Pin 24, LCD_D11 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x5c 8.--9. " BANK1_PIN10_MA ,Pin 26, LCD_D10 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x5c 4.--5. " BANK1_PIN09_MA ,Pin 28, LCD_D09 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x5c 0.--1. " BANK1_PIN08_MA ,Pin 27, LCD_D08 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x60 "HW_PINCTRL_DRIVE6,Drive Strength and Voltage Register 6" bitfld.long 0x60 28.--29. " BANK1_PIN23_MA ,Pin 30, LCD_ENABLE pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x60 24.--25. " BANK1_PIN22_MA ,Pin 36, LCD_DOTCK pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x60 20.--21. " BANK1_PIN21_MA ,Pin 29, LCD_CS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x60 16.--17. " BANK1_PIN20_MA ,Pin 32, LCD_WR pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x60 12.--13. " BANK1_PIN19_MA ,Pin 33, LCD_RS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x60 8.--9. " BANK1_PIN18_MA ,Pin 31, LCD_RESET pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x60 4.--5. " BANK1_PIN17_MA ,Pin 11, LCD_D17 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x60 0.--1. " BANK1_PIN16_MA ,Pin 13, LCD_D16 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x64 "HW_PINCTRL_DRIVE6_SET,Drive Strength and Voltage Set Register 6" bitfld.long 0x64 28.--29. " BANK1_PIN23_MA ,Pin 30, LCD_ENABLE pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x64 24.--25. " BANK1_PIN22_MA ,Pin 36, LCD_DOTCK pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x64 20.--21. " BANK1_PIN21_MA ,Pin 29, LCD_CS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x64 16.--17. " BANK1_PIN20_MA ,Pin 32, LCD_WR pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x64 12.--13. " BANK1_PIN19_MA ,Pin 33, LCD_RS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x64 8.--9. " BANK1_PIN18_MA ,Pin 31, LCD_RESET pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x64 4.--5. " BANK1_PIN17_MA ,Pin 11, LCD_D17 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x64 0.--1. " BANK1_PIN16_MA ,Pin 13, LCD_D16 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x68 "HW_PINCTRL_DRIVE6_CLR,Drive Strength and Voltage Clear Register 6" bitfld.long 0x68 28.--29. " BANK1_PIN23_MA ,Pin 30, LCD_ENABLE pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x68 24.--25. " BANK1_PIN22_MA ,Pin 36, LCD_DOTCK pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x68 20.--21. " BANK1_PIN21_MA ,Pin 29, LCD_CS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x68 16.--17. " BANK1_PIN20_MA ,Pin 32, LCD_WR pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x68 12.--13. " BANK1_PIN19_MA ,Pin 33, LCD_RS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x68 8.--9. " BANK1_PIN18_MA ,Pin 31, LCD_RESET pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x68 4.--5. " BANK1_PIN17_MA ,Pin 11, LCD_D17 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x68 0.--1. " BANK1_PIN16_MA ,Pin 13, LCD_D16 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x6c "HW_PINCTRL_DRIVE6_TOG,Drive Strength and Voltage Toggle Register 6" bitfld.long 0x6c 28.--29. " BANK1_PIN23_MA ,Pin 30, LCD_ENABLE pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x6c 24.--25. " BANK1_PIN22_MA ,Pin 36, LCD_DOTCK pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x6c 20.--21. " BANK1_PIN21_MA ,Pin 29, LCD_CS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x6c 16.--17. " BANK1_PIN20_MA ,Pin 32, LCD_WR pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x6c 12.--13. " BANK1_PIN19_MA ,Pin 33, LCD_RS pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x6c 8.--9. " BANK1_PIN18_MA ,Pin 31, LCD_RESET pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x6c 4.--5. " BANK1_PIN17_MA ,Pin 11, LCD_D17 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x6c 0.--1. " BANK1_PIN16_MA ,Pin 13, LCD_D16 pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x70 "HW_PINCTRL_DRIVE7,Drive Strength and Voltage Register 7" bitfld.long 0x70 24.--25. " BANK1_PIN30_MA ,Pin 131, PWM4 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x70 20.--21. " BANK1_PIN29_MA ,Pin 130, PWM3 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x70 16.--17. " BANK1_PIN28_MA ,Pin 129, PWM2 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x70 12.--13. " BANK1_PIN27_MA ,Pin 3, PWM1 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x70 8.--9. " BANK1_PIN26_MA ,Pin 1, PWM0 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x70 4.--5. " BANK1_PIN25_MA ,Pin 35, LCD_VSYNC pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x70 0.--1. " BANK1_PIN24_MA ,Pin 34, LCD_HSYNC pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x74 "HW_PINCTRL_DRIVE7_SET,Drive Strength and Voltage Set Register 7" bitfld.long 0x74 24.--25. " BANK1_PIN30_MA ,Pin 131, PWM4 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x74 20.--21. " BANK1_PIN29_MA ,Pin 130, PWM3 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x74 16.--17. " BANK1_PIN28_MA ,Pin 129, PWM2 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x74 12.--13. " BANK1_PIN27_MA ,Pin 3, PWM1 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x74 8.--9. " BANK1_PIN26_MA ,Pin 1, PWM0 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x74 4.--5. " BANK1_PIN25_MA ,Pin 35, LCD_VSYNC pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x74 0.--1. " BANK1_PIN24_MA ,Pin 34, LCD_HSYNC pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x78 "HW_PINCTRL_DRIVE7_CLR,Drive Strength and Voltage Clear Register 7" bitfld.long 0x78 24.--25. " BANK1_PIN30_MA ,Pin 131, PWM4 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x78 20.--21. " BANK1_PIN29_MA ,Pin 130, PWM3 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x78 16.--17. " BANK1_PIN28_MA ,Pin 129, PWM2 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x78 12.--13. " BANK1_PIN27_MA ,Pin 3, PWM1 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x78 8.--9. " BANK1_PIN26_MA ,Pin 1, PWM0 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x78 4.--5. " BANK1_PIN25_MA ,Pin 35, LCD_VSYNC pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x78 0.--1. " BANK1_PIN24_MA ,Pin 34, LCD_HSYNC pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x7c "HW_PINCTRL_DRIVE7_TOG,Drive Strength and Voltage Toggle Register 7" bitfld.long 0x7c 24.--25. " BANK1_PIN30_MA ,Pin 131, PWM4 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x7c 20.--21. " BANK1_PIN29_MA ,Pin 130, PWM3 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x7c 16.--17. " BANK1_PIN28_MA ,Pin 129, PWM2 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x7c 12.--13. " BANK1_PIN27_MA ,Pin 3, PWM1 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x7c 8.--9. " BANK1_PIN26_MA ,Pin 1, PWM0 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x7c 4.--5. " BANK1_PIN25_MA ,Pin 35, LCD_VSYNC pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x7c 0.--1. " BANK1_PIN24_MA ,Pin 34, LCD_HSYNC pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x80 "HW_PINCTRL_DRIVE8,Drive Strength and Voltage Register 8" bitfld.long 0x80 28.--29. " BANK2_PIN07_MA ,Pin 37, ROTARYA pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x80 24.--25. " BANK2_PIN06_MA ,Pin 127, SSP1_SCK pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x80 20.--21. " BANK2_PIN05_MA ,Pin 125, SSP1_DATA3 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x80 16.--17. " BANK2_PIN04_MA ,Pin 124, SSP1_DATA2 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x80 12.--13. " BANK2_PIN03_MA ,Pin 123, SSP1_DATA1 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x80 8.--9. " BANK2_PIN02_MA ,Pin 122, SSP1_DATA0 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x80 4.--5. " BANK2_PIN01_MA ,Pin 126, SSP1_DETECT pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x80 0.--1. " BANK2_PIN00_MA ,Pin 121, SSP1_CMD pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x84 "HW_PINCTRL_DRIVE8_SET,Drive Strength and Voltage Set Register 8" bitfld.long 0x84 28.--29. " BANK2_PIN07_MA ,Pin 37, ROTARYA pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x84 24.--25. " BANK2_PIN06_MA ,Pin 127, SSP1_SCK pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x84 20.--21. " BANK2_PIN05_MA ,Pin 125, SSP1_DATA3 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x84 16.--17. " BANK2_PIN04_MA ,Pin 124, SSP1_DATA2 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x84 12.--13. " BANK2_PIN03_MA ,Pin 123, SSP1_DATA1 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x84 8.--9. " BANK2_PIN02_MA ,Pin 122, SSP1_DATA0 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x84 4.--5. " BANK2_PIN01_MA ,Pin 126, SSP1_DETECT pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x84 0.--1. " BANK2_PIN00_MA ,Pin 121, SSP1_CMD pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x88 "HW_PINCTRL_DRIVE8_CLR,Drive Strength and Voltage Clear Register 8" bitfld.long 0x88 28.--29. " BANK2_PIN07_MA ,Pin 37, ROTARYA pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x88 24.--25. " BANK2_PIN06_MA ,Pin 127, SSP1_SCK pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x88 20.--21. " BANK2_PIN05_MA ,Pin 125, SSP1_DATA3 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x88 16.--17. " BANK2_PIN04_MA ,Pin 124, SSP1_DATA2 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x88 12.--13. " BANK2_PIN03_MA ,Pin 123, SSP1_DATA1 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x88 8.--9. " BANK2_PIN02_MA ,Pin 122, SSP1_DATA0 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x88 4.--5. " BANK2_PIN01_MA ,Pin 126, SSP1_DETECT pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x88 0.--1. " BANK2_PIN00_MA ,Pin 121, SSP1_CMD pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x8c "HW_PINCTRL_DRIVE8_TOG,Drive Strength and Voltage Toggle Register 8" bitfld.long 0x8c 28.--29. " BANK2_PIN07_MA ,Pin 37, ROTARYA pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x8c 24.--25. " BANK2_PIN06_MA ,Pin 127, SSP1_SCK pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x8c 20.--21. " BANK2_PIN05_MA ,Pin 125, SSP1_DATA3 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x8c 16.--17. " BANK2_PIN04_MA ,Pin 124, SSP1_DATA2 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x8c 12.--13. " BANK2_PIN03_MA ,Pin 123, SSP1_DATA1 pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x8c 8.--9. " BANK2_PIN02_MA ,Pin 122, SSP1_DATA0 pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0x8c 4.--5. " BANK2_PIN01_MA ,Pin 126, SSP1_DETECT pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0x8c 0.--1. " BANK2_PIN00_MA ,Pin 121, SSP1_CMD pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x90 "HW_PINCTRL_DRIVE9,Drive Strength and Voltage Register 9" bitfld.long 0x90 30. " BANK2_PIN15_V ,Pin 108, EMI_A06 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0x90 28.--29. " BANK2_PIN15_MA ,Pin 108, EMI_A06 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x90 26. " BANK2_PIN14_V ,Pin 107, EMI_A05 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0x90 24.--25. " BANK2_PIN14_MA ,Pin 107, EMI_A05 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x90 22. " BANK2_PIN13_V ,Pin 109, EMI_A04 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0x90 20.--21. " BANK2_PIN13_MA ,Pin 109, EMI_A04 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x90 18. " BANK2_PIN12_V ,Pin 110, EMI_A03 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0x90 16.--17. " BANK2_PIN12_MA ,Pin 110, EMI_A03 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x90 14. " BANK2_PIN11_V ,Pin 111, EMI_A02 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0x90 12.--13. " BANK2_PIN11_MA ,Pin 111, EMI_A02 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x90 10. " BANK2_PIN10_V ,Pin 112, EMI_A01 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0x90 8.--9. " BANK2_PIN10_MA ,Pin 112, EMI_A01 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x90 6. " BANK2_PIN09_V ,Pin 113, EMI_A00 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0x90 4.--5. " BANK2_PIN09_MA ,Pin 113, EMI_A00 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x90 0.--1. " BANK2_PIN08_MA ,Pin 38, ROTARYB pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x94 "HW_PINCTRL_DRIVE9_SET,Drive Strength and Voltage Set Register 9" bitfld.long 0x94 30. " BANK2_PIN15_V ,Pin 108, EMI_A06 pin voltage selection" "No effect,Set" bitfld.long 0x94 28.--29. " BANK2_PIN15_MA ,Pin 108, EMI_A06 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x94 26. " BANK2_PIN14_V ,Pin 107, EMI_A05 pin voltage selection" "No effect,Set" bitfld.long 0x94 24.--25. " BANK2_PIN14_MA ,Pin 107, EMI_A05 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x94 22. " BANK2_PIN13_V ,Pin 109, EMI_A04 pin voltage selection" "No effect,Set" bitfld.long 0x94 20.--21. " BANK2_PIN13_MA ,Pin 109, EMI_A04 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x94 18. " BANK2_PIN12_V ,Pin 110, EMI_A03 pin voltage selection" "No effect,Set" bitfld.long 0x94 16.--17. " BANK2_PIN12_MA ,Pin 110, EMI_A03 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x94 14. " BANK2_PIN11_V ,Pin 111, EMI_A02 pin voltage selection" "No effect,Set" bitfld.long 0x94 12.--13. " BANK2_PIN11_MA ,Pin 111, EMI_A02 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x94 10. " BANK2_PIN10_V ,Pin 112, EMI_A01 pin voltage selection" "No effect,Set" bitfld.long 0x94 8.--9. " BANK2_PIN10_MA ,Pin 112, EMI_A01 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x94 6. " BANK2_PIN09_V ,Pin 113, EMI_A00 pin voltage selection" "No effect,Set" bitfld.long 0x94 4.--5. " BANK2_PIN09_MA ,Pin 113, EMI_A00 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x94 0.--1. " BANK2_PIN08_MA ,Pin 38, ROTARYB pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x98 "HW_PINCTRL_DRIVE9_CLR,Drive Strength and Voltage Clear Register 9" bitfld.long 0x98 30. " BANK2_PIN15_V ,Pin 108, EMI_A06 pin voltage selection" "No effect,Clear" bitfld.long 0x98 28.--29. " BANK2_PIN15_MA ,Pin 108, EMI_A06 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x98 26. " BANK2_PIN14_V ,Pin 107, EMI_A05 pin voltage selection" "No effect,Clear" bitfld.long 0x98 24.--25. " BANK2_PIN14_MA ,Pin 107, EMI_A05 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x98 22. " BANK2_PIN13_V ,Pin 109, EMI_A04 pin voltage selection" "No effect,Clear" bitfld.long 0x98 20.--21. " BANK2_PIN13_MA ,Pin 109, EMI_A04 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x98 18. " BANK2_PIN12_V ,Pin 110, EMI_A03 pin voltage selection" "No effect,Clear" bitfld.long 0x98 16.--17. " BANK2_PIN12_MA ,Pin 110, EMI_A03 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x98 14. " BANK2_PIN11_V ,Pin 111, EMI_A02 pin voltage selection" "No effect,Clear" bitfld.long 0x98 12.--13. " BANK2_PIN11_MA ,Pin 111, EMI_A02 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x98 10. " BANK2_PIN10_V ,Pin 112, EMI_A01 pin voltage selection" "No effect,Clear" bitfld.long 0x98 8.--9. " BANK2_PIN10_MA ,Pin 112, EMI_A01 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x98 6. " BANK2_PIN09_V ,Pin 113, EMI_A00 pin voltage selection" "No effect,Clear" bitfld.long 0x98 4.--5. " BANK2_PIN09_MA ,Pin 113, EMI_A00 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x98 0.--1. " BANK2_PIN08_MA ,Pin 38, ROTARYB pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0x9c "HW_PINCTRL_DRIVE9_TOG,Drive Strength and Voltage Toggle Register 9" bitfld.long 0x9c 30. " BANK2_PIN15_V ,Pin 108, EMI_A06 pin voltage selection" "Not toggle,Toggle" bitfld.long 0x9c 28.--29. " BANK2_PIN15_MA ,Pin 108, EMI_A06 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x9c 26. " BANK2_PIN14_V ,Pin 107, EMI_A05 pin voltage selection" "Not toggle,Toggle" bitfld.long 0x9c 24.--25. " BANK2_PIN14_MA ,Pin 107, EMI_A05 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x9c 22. " BANK2_PIN13_V ,Pin 109, EMI_A04 pin voltage selection" "Not toggle,Toggle" bitfld.long 0x9c 20.--21. " BANK2_PIN13_MA ,Pin 109, EMI_A04 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x9c 18. " BANK2_PIN12_V ,Pin 110, EMI_A03 pin voltage selection" "Not toggle,Toggle" bitfld.long 0x9c 16.--17. " BANK2_PIN12_MA ,Pin 110, EMI_A03 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x9c 14. " BANK2_PIN11_V ,Pin 111, EMI_A02 pin voltage selection" "Not toggle,Toggle" bitfld.long 0x9c 12.--13. " BANK2_PIN11_MA ,Pin 111, EMI_A02 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x9c 10. " BANK2_PIN10_V ,Pin 112, EMI_A01 pin voltage selection" "Not toggle,Toggle" bitfld.long 0x9c 8.--9. " BANK2_PIN10_MA ,Pin 112, EMI_A01 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x9c 6. " BANK2_PIN09_V ,Pin 113, EMI_A00 pin voltage selection" "Not toggle,Toggle" bitfld.long 0x9c 4.--5. " BANK2_PIN09_MA ,Pin 113, EMI_A00 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0x9c 0.--1. " BANK2_PIN08_MA ,Pin 38, ROTARYB pin output drive strength selection" "4mA,8mA,12mA,?..." line.long 0xa0 "HW_PINCTRL_DRIVE10,Drive Strength and Voltage Register 10" bitfld.long 0xa0 30. " BANK2_PIN23_V ,Pin 117, EMI_BA1 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xa0 28.--29. " BANK2_PIN23_MA ,Pin 117, EMI_BA1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa0 26. " BANK2_PIN22_V ,Pin 116, EMI_BA0 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xa0 24.--25. " BANK2_PIN22_MA ,Pin 116, EMI_BA0 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa0 22. " BANK2_PIN21_V ,Pin 101, EMI_A12 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xa0 20.--21. " BANK2_PIN21_MA ,Pin 101, EMI_A12 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa0 18. " BANK2_PIN20_V ,Pin 102, EMI_A11 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xa0 16.--17. " BANK2_PIN20_MA ,Pin 102, EMI_A11 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa0 14. " BANK2_PIN19_V ,Pin 104, EMI_A10 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xa0 12.--13. " BANK2_PIN19_MA ,Pin 104, EMI_A10 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa0 10. " BANK2_PIN18_V ,Pin 103, EMI_A09 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xa0 8.--9. " BANK2_PIN18_MA ,Pin 103, EMI_A09 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa0 6. " BANK2_PIN17_V ,Pin 106, EMI_A08 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xa0 4.--5. " BANK2_PIN17_MA ,Pin 106, EMI_A08 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa0 2. " BANK2_PIN16_V ,Pin 105, EMI_A07 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xa0 0.--1. " BANK2_PIN16_MA ,Pin 105, EMI_A07 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xa4 "HW_PINCTRL_DRIVE10_SET,Drive Strength and Voltage Set Register 10" bitfld.long 0xa4 30. " BANK2_PIN23_V ,Pin 117, EMI_BA1 pin voltage selection" "No effect,Set" bitfld.long 0xa4 28.--29. " BANK2_PIN23_MA ,Pin 117, EMI_BA1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa4 26. " BANK2_PIN22_V ,Pin 116, EMI_BA0 pin voltage selection" "No effect,Set" bitfld.long 0xa4 24.--25. " BANK2_PIN22_MA ,Pin 116, EMI_BA0 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa4 22. " BANK2_PIN21_V ,Pin 101, EMI_A12 pin voltage selection" "No effect,Set" bitfld.long 0xa4 20.--21. " BANK2_PIN21_MA ,Pin 101, EMI_A12 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa4 18. " BANK2_PIN20_V ,Pin 102, EMI_A11 pin voltage selection" "No effect,Set" bitfld.long 0xa4 16.--17. " BANK2_PIN20_MA ,Pin 102, EMI_A11 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa4 14. " BANK2_PIN19_V ,Pin 104, EMI_A10 pin voltage selection" "No effect,Set" bitfld.long 0xa4 12.--13. " BANK2_PIN19_MA ,Pin 104, EMI_A10 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa4 10. " BANK2_PIN18_V ,Pin 103, EMI_A09 pin voltage selection" "No effect,Set" bitfld.long 0xa4 8.--9. " BANK2_PIN18_MA ,Pin 103, EMI_A09 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa4 6. " BANK2_PIN17_V ,Pin 106, EMI_A08 pin voltage selection" "No effect,Set" bitfld.long 0xa4 4.--5. " BANK2_PIN17_MA ,Pin 106, EMI_A08 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa4 2. " BANK2_PIN16_V ,Pin 105, EMI_A07 pin voltage selection" "No effect,Set" bitfld.long 0xa4 0.--1. " BANK2_PIN16_MA ,Pin 105, EMI_A07 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xa8 "HW_PINCTRL_DRIVE10_CLR,Drive Strength and Voltage Clear Register 10" bitfld.long 0xa8 30. " BANK2_PIN23_V ,Pin 117, EMI_BA1 pin voltage selection" "No effect,Clear" bitfld.long 0xa8 28.--29. " BANK2_PIN23_MA ,Pin 117, EMI_BA1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa8 26. " BANK2_PIN22_V ,Pin 116, EMI_BA0 pin voltage selection" "No effect,Clear" bitfld.long 0xa8 24.--25. " BANK2_PIN22_MA ,Pin 116, EMI_BA0 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa8 22. " BANK2_PIN21_V ,Pin 101, EMI_A12 pin voltage selection" "No effect,Clear" bitfld.long 0xa8 20.--21. " BANK2_PIN21_MA ,Pin 101, EMI_A12 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa8 18. " BANK2_PIN20_V ,Pin 102, EMI_A11 pin voltage selection" "No effect,Clear" bitfld.long 0xa8 16.--17. " BANK2_PIN20_MA ,Pin 102, EMI_A11 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa8 14. " BANK2_PIN19_V ,Pin 104, EMI_A10 pin voltage selection" "No effect,Clear" bitfld.long 0xa8 12.--13. " BANK2_PIN19_MA ,Pin 104, EMI_A10 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa8 10. " BANK2_PIN18_V ,Pin 103, EMI_A09 pin voltage selection" "No effect,Clear" bitfld.long 0xa8 8.--9. " BANK2_PIN18_MA ,Pin 103, EMI_A09 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa8 6. " BANK2_PIN17_V ,Pin 106, EMI_A08 pin voltage selection" "No effect,Clear" bitfld.long 0xa8 4.--5. " BANK2_PIN17_MA ,Pin 106, EMI_A08 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xa8 2. " BANK2_PIN16_V ,Pin 105, EMI_A07 pin voltage selection" "No effect,Clear" bitfld.long 0xa8 0.--1. " BANK2_PIN16_MA ,Pin 105, EMI_A07 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xac "HW_PINCTRL_DRIVE10_TOG,Drive Strength and Voltage Toggle Register 10" bitfld.long 0xac 30. " BANK2_PIN23_V ,Pin 117, EMI_BA1 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xac 28.--29. " BANK2_PIN23_MA ,Pin 117, EMI_BA1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xac 26. " BANK2_PIN22_V ,Pin 116, EMI_BA0 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xac 24.--25. " BANK2_PIN22_MA ,Pin 116, EMI_BA0 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xac 22. " BANK2_PIN21_V ,Pin 101, EMI_A12 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xac 20.--21. " BANK2_PIN21_MA ,Pin 101, EMI_A12 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xac 18. " BANK2_PIN20_V ,Pin 102, EMI_A11 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xac 16.--17. " BANK2_PIN20_MA ,Pin 102, EMI_A11 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xac 14. " BANK2_PIN19_V ,Pin 104, EMI_A10 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xac 12.--13. " BANK2_PIN19_MA ,Pin 104, EMI_A10 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xac 10. " BANK2_PIN18_V ,Pin 103, EMI_A09 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xac 8.--9. " BANK2_PIN18_MA ,Pin 103, EMI_A09 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xac 6. " BANK2_PIN17_V ,Pin 106, EMI_A08 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xac 4.--5. " BANK2_PIN17_MA ,Pin 106, EMI_A08 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xac 2. " BANK2_PIN16_V ,Pin 105, EMI_A07 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xac 0.--1. " BANK2_PIN16_MA ,Pin 105, EMI_A07 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xb0 "HW_PINCTRL_DRIVE11,Drive Strength and Voltage Register 11" bitfld.long 0xb0 30. " BANK2_PIN31_V ,Pin 114, EMI_WEN pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xb0 28.--29. " BANK2_PIN31_MA ,Pin 114, EMI_WEN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb0 26. " BANK2_PIN30_V ,Pin 98, EMI_RASN pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xb0 24.--25. " BANK2_PIN30_MA ,Pin 98, EMI_RASN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb0 22. " BANK2_PIN29_V ,Pin 115, EMI_CKE pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xb0 20.--21. " BANK2_PIN29_MA ,Pin 115, EMI_CKE pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb0 16.--17. " BANK2_PIN28_MA ,Pin 120, GPMI_CE0N pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0xb0 12.--13. " BANK2_PIN27_MA ,Pin 118, GPMI_CE1N pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0xb0 10. " BANK2_PIN26_V ,Pin 99, EMI_CE1N pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xb0 8.--9. " BANK2_PIN26_MA ,Pin 99, EMI_CE1N pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb0 6. " BANK2_PIN25_V ,Pin 100, EMI_CE0N pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xb0 4.--5. " BANK2_PIN25_MA ,Pin 100, EMI_CE0N pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb0 2. " BANK2_PIN24_V ,Pin 97, EMI_CASN pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xb0 0.--1. " BANK2_PIN24_MA ,Pin 97, EMI_CASN pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xb4 "HW_PINCTRL_DRIVE11_SET,Drive Strength and Voltage Set Register 11" bitfld.long 0xb4 30. " BANK2_PIN31_V ,Pin 114, EMI_WEN pin voltage selection" "No effect,Set" bitfld.long 0xb4 28.--29. " BANK2_PIN31_MA ,Pin 114, EMI_WEN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb4 26. " BANK2_PIN30_V ,Pin 98, EMI_RASN pin voltage selection" "No effect,Set" bitfld.long 0xb4 24.--25. " BANK2_PIN30_MA ,Pin 98, EMI_RASN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb4 22. " BANK2_PIN29_V ,Pin 115, EMI_CKE pin voltage selection" "No effect,Set" bitfld.long 0xb4 20.--21. " BANK2_PIN29_MA ,Pin 115, EMI_CKE pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb4 16.--17. " BANK2_PIN28_MA ,Pin 120, GPMI_CE0N pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0xb4 12.--13. " BANK2_PIN27_MA ,Pin 118, GPMI_CE1N pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0xb4 10. " BANK2_PIN26_V ,Pin 99, EMI_CE1N pin voltage selection" "No effect,Set" bitfld.long 0xb4 8.--9. " BANK2_PIN26_MA ,Pin 99, EMI_CE1N pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb4 6. " BANK2_PIN25_V ,Pin 100, EMI_CE0N pin voltage selection" "No effect,Set" bitfld.long 0xb4 4.--5. " BANK2_PIN25_MA ,Pin 100, EMI_CE0N pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb4 2. " BANK2_PIN24_V ,Pin 97, EMI_CASN pin voltage selection" "No effect,Set" bitfld.long 0xb4 0.--1. " BANK2_PIN24_MA ,Pin 97, EMI_CASN pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xb8 "HW_PINCTRL_DRIVE11_CLR,Drive Strength and Voltage Clear Register 11" bitfld.long 0xb8 30. " BANK2_PIN31_V ,Pin 114, EMI_WEN pin voltage selection" "No effect,Clear" bitfld.long 0xb8 28.--29. " BANK2_PIN31_MA ,Pin 114, EMI_WEN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb8 26. " BANK2_PIN30_V ,Pin 98, EMI_RASN pin voltage selection" "No effect,Clear" bitfld.long 0xb8 24.--25. " BANK2_PIN30_MA ,Pin 98, EMI_RASN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb8 22. " BANK2_PIN29_V ,Pin 115, EMI_CKE pin voltage selection" "No effect,Clear" bitfld.long 0xb8 20.--21. " BANK2_PIN29_MA ,Pin 115, EMI_CKE pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb8 16.--17. " BANK2_PIN28_MA ,Pin 120, GPMI_CE0N pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0xb8 12.--13. " BANK2_PIN27_MA ,Pin 118, GPMI_CE1N pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0xb8 10. " BANK2_PIN26_V ,Pin 99, EMI_CE1N pin voltage selection" "No effect,Clear" bitfld.long 0xb8 8.--9. " BANK2_PIN26_MA ,Pin 99, EMI_CE1N pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb8 6. " BANK2_PIN25_V ,Pin 100, EMI_CE0N pin voltage selection" "No effect,Clear" bitfld.long 0xb8 4.--5. " BANK2_PIN25_MA ,Pin 100, EMI_CE0N pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xb8 2. " BANK2_PIN24_V ,Pin 97, EMI_CASN pin voltage selection" "No effect,Clear" bitfld.long 0xb8 0.--1. " BANK2_PIN24_MA ,Pin 97, EMI_CASN pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xbc "HW_PINCTRL_DRIVE11_TOG,Drive Strength and Voltage Toggle Register 11" bitfld.long 0xbc 30. " BANK2_PIN31_V ,Pin 114, EMI_WEN pin voltage selection" "Not toggle,Toggle" bitfld.long 0xbc 28.--29. " BANK2_PIN31_MA ,Pin 114, EMI_WEN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xbc 26. " BANK2_PIN30_V ,Pin 98, EMI_RASN pin voltage selection" "Not toggle,Toggle" bitfld.long 0xbc 24.--25. " BANK2_PIN30_MA ,Pin 98, EMI_RASN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xbc 22. " BANK2_PIN29_V ,Pin 115, EMI_CKE pin voltage selection" "Not toggle,Toggle" bitfld.long 0xbc 20.--21. " BANK2_PIN29_MA ,Pin 115, EMI_CKE pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xbc 16.--17. " BANK2_PIN28_MA ,Pin 120, GPMI_CE0N pin output drive strength selection" "4mA,8mA,12mA,?..." bitfld.long 0xbc 12.--13. " BANK2_PIN27_MA ,Pin 118, GPMI_CE1N pin output drive strength selection" "4mA,8mA,12mA,?..." textline " " bitfld.long 0xbc 10. " BANK2_PIN26_V ,Pin 99, EMI_CE1N pin voltage selection" "Not toggle,Toggle" bitfld.long 0xbc 8.--9. " BANK2_PIN26_MA ,Pin 99, EMI_CE1N pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xbc 6. " BANK2_PIN25_V ,Pin 100, EMI_CE0N pin voltage selection" "Not toggle,Toggle" bitfld.long 0xbc 4.--5. " BANK2_PIN25_MA ,Pin 100, EMI_CE0N pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xbc 2. " BANK2_PIN24_V ,Pin 97, EMI_CASN pin voltage selection" "Not toggle,Toggle" bitfld.long 0xbc 0.--1. " BANK2_PIN24_MA ,Pin 97, EMI_CASN pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xc0 "HW_PINCTRL_DRIVE12,Drive Strength and Voltage Register 12" bitfld.long 0xc0 30. " BANK3_PIN07_V ,Pin 85, EMI_D07 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xc0 28.--29. " BANK3_PIN07_MA ,Pin 85, EMI_D07 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc0 26. " BANK3_PIN06_V ,Pin 84, EMI_D06 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xc0 24.--25. " BANK3_PIN06_MA ,Pin 84, EMI_D06 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc0 22. " BANK3_PIN05_V ,Pin 83, EMI_D05 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xc0 20.--21. " BANK3_PIN05_MA ,Pin 83, EMI_D05 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc0 18. " BANK3_PIN04_V ,Pin 82, EMI_D04 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xc0 16.--17. " BANK3_PIN04_MA ,Pin 82, EMI_D04 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc0 14. " BANK3_PIN03_V ,Pin 79, EMI_D03 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xc0 12.--13. " BANK3_PIN03_MA ,Pin 79, EMI_D03 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc0 10. " BANK3_PIN02_V ,Pin 77, EMI_D02 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xc0 8.--9. " BANK3_PIN02_MA ,Pin 77, EMI_D02 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc0 6. " BANK3_PIN01_V ,Pin 76, EMI_D01 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xc0 4.--5. " BANK3_PIN01_MA ,Pin 76, EMI_D01 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc0 2. " BANK3_PIN00_V ,Pin 75, EMI_D00 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xc0 0.--1. " BANK3_PIN00_MA ,Pin 75, EMI_D00 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xc4 "HW_PINCTRL_DRIVE12_SET,Drive Strength and Voltage Set Register 12" bitfld.long 0xc4 30. " BANK3_PIN07_V ,Pin 85, EMI_D07 pin voltage selection" "No effect,Set" bitfld.long 0xc4 28.--29. " BANK3_PIN07_MA ,Pin 85, EMI_D07 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc4 26. " BANK3_PIN06_V ,Pin 84, EMI_D06 pin voltage selection" "No effect,Set" bitfld.long 0xc4 24.--25. " BANK3_PIN06_MA ,Pin 84, EMI_D06 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc4 22. " BANK3_PIN05_V ,Pin 83, EMI_D05 pin voltage selection" "No effect,Set" bitfld.long 0xc4 20.--21. " BANK3_PIN05_MA ,Pin 83, EMI_D05 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc4 18. " BANK3_PIN04_V ,Pin 82, EMI_D04 pin voltage selection" "No effect,Set" bitfld.long 0xc4 16.--17. " BANK3_PIN04_MA ,Pin 82, EMI_D04 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc4 14. " BANK3_PIN03_V ,Pin 79, EMI_D03 pin voltage selection" "No effect,Set" bitfld.long 0xc4 12.--13. " BANK3_PIN03_MA ,Pin 79, EMI_D03 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc4 10. " BANK3_PIN02_V ,Pin 77, EMI_D02 pin voltage selection" "No effect,Set" bitfld.long 0xc4 8.--9. " BANK3_PIN02_MA ,Pin 77, EMI_D02 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc4 6. " BANK3_PIN01_V ,Pin 76, EMI_D01 pin voltage selection" "No effect,Set" bitfld.long 0xc4 4.--5. " BANK3_PIN01_MA ,Pin 76, EMI_D01 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc4 2. " BANK3_PIN00_V ,Pin 75, EMI_D00 pin voltage selection" "No effect,Set" bitfld.long 0xc4 0.--1. " BANK3_PIN00_MA ,Pin 75, EMI_D00 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xc8 "HW_PINCTRL_DRIVE12_CLR,Drive Strength and Voltage Clear Register 12" bitfld.long 0xc8 30. " BANK3_PIN07_V ,Pin 85, EMI_D07 pin voltage selection" "No effect,Clear" bitfld.long 0xc8 28.--29. " BANK3_PIN07_MA ,Pin 85, EMI_D07 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc8 26. " BANK3_PIN06_V ,Pin 84, EMI_D06 pin voltage selection" "No effect,Clear" bitfld.long 0xc8 24.--25. " BANK3_PIN06_MA ,Pin 84, EMI_D06 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc8 22. " BANK3_PIN05_V ,Pin 83, EMI_D05 pin voltage selection" "No effect,Clear" bitfld.long 0xc8 20.--21. " BANK3_PIN05_MA ,Pin 83, EMI_D05 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc8 18. " BANK3_PIN04_V ,Pin 82, EMI_D04 pin voltage selection" "No effect,Clear" bitfld.long 0xc8 16.--17. " BANK3_PIN04_MA ,Pin 82, EMI_D04 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc8 14. " BANK3_PIN03_V ,Pin 79, EMI_D03 pin voltage selection" "No effect,Clear" bitfld.long 0xc8 12.--13. " BANK3_PIN03_MA ,Pin 79, EMI_D03 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc8 10. " BANK3_PIN02_V ,Pin 77, EMI_D02 pin voltage selection" "No effect,Clear" bitfld.long 0xc8 8.--9. " BANK3_PIN02_MA ,Pin 77, EMI_D02 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc8 6. " BANK3_PIN01_V ,Pin 76, EMI_D01 pin voltage selection" "No effect,Clear" bitfld.long 0xc8 4.--5. " BANK3_PIN01_MA ,Pin 76, EMI_D01 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xc8 2. " BANK3_PIN00_V ,Pin 75, EMI_D00 pin voltage selection" "No effect,Clear" bitfld.long 0xc8 0.--1. " BANK3_PIN00_MA ,Pin 75, EMI_D00 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xcc "HW_PINCTRL_DRIVE12_TOG,Drive Strength and Voltage Toggle Register 12" bitfld.long 0xcc 30. " BANK3_PIN07_V ,Pin 85, EMI_D07 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xcc 28.--29. " BANK3_PIN07_MA ,Pin 85, EMI_D07 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xcc 26. " BANK3_PIN06_V ,Pin 84, EMI_D06 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xcc 24.--25. " BANK3_PIN06_MA ,Pin 84, EMI_D06 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xcc 22. " BANK3_PIN05_V ,Pin 83, EMI_D05 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xcc 20.--21. " BANK3_PIN05_MA ,Pin 83, EMI_D05 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xcc 18. " BANK3_PIN04_V ,Pin 82, EMI_D04 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xcc 16.--17. " BANK3_PIN04_MA ,Pin 82, EMI_D04 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xcc 14. " BANK3_PIN03_V ,Pin 79, EMI_D03 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xcc 12.--13. " BANK3_PIN03_MA ,Pin 79, EMI_D03 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xcc 10. " BANK3_PIN02_V ,Pin 77, EMI_D02 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xcc 8.--9. " BANK3_PIN02_MA ,Pin 77, EMI_D02 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xcc 6. " BANK3_PIN01_V ,Pin 76, EMI_D01 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xcc 4.--5. " BANK3_PIN01_MA ,Pin 76, EMI_D01 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xcc 2. " BANK3_PIN00_V ,Pin 75, EMI_D00 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xcc 0.--1. " BANK3_PIN00_MA ,Pin 75, EMI_D00 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xd0 "HW_PINCTRL_DRIVE13,Drive Strength and Voltage Register 13" bitfld.long 0xd0 30. " BANK3_PIN15_V ,Pin 95, EMI_D15 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xd0 28.--29. " BANK3_PIN15_MA ,Pin 95, EMI_D15 pin voltage selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd0 26. " BANK3_PIN14_V ,Pin 96, EMI_D14 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xd0 24.--25. " BANK3_PIN14_MA ,Pin 96, EMI_D14 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd0 22. " BANK3_PIN13_V ,Pin 94, EMI_D13 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xd0 20.--21. " BANK3_PIN13_MA ,Pin 94, EMI_D13 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd0 18. " BANK3_PIN12_V ,Pin 93, EMI_D12 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xd0 16.--17. " BANK3_PIN12_MA ,Pin 93, EMI_D12 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd0 14. " BANK3_PIN11_V ,Pin 91, EMI_D11 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xd0 12.--13. " BANK3_PIN11_MA ,Pin 91, EMI_D11 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd0 10. " BANK3_PIN10_V ,Pin 89, EMI_D10 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xd0 8.--9. " BANK3_PIN10_MA ,Pin 89, EMI_D10 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd0 6. " BANK3_PIN09_V ,Pin 87, EMI_D09 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xd0 4.--5. " BANK3_PIN09_MA ,Pin 87, EMI_D09 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd0 2. " BANK3_PIN08_V ,Pin 86, EMI_D08 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xd0 0.--1. " BANK3_PIN08_MA ,Pin 86, EMI_D08 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xd4 "HW_PINCTRL_DRIVE13_SET,Drive Strength and Voltage Set Register 13" bitfld.long 0xd4 30. " BANK3_PIN15_V ,Pin 95, EMI_D15 pin voltage selection" "No effect,Set" bitfld.long 0xd4 28.--29. " BANK3_PIN15_MA ,Pin 95, EMI_D15 pin voltage selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd4 26. " BANK3_PIN14_V ,Pin 96, EMI_D14 pin voltage selection" "No effect,Set" bitfld.long 0xd4 24.--25. " BANK3_PIN14_MA ,Pin 96, EMI_D14 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd4 22. " BANK3_PIN13_V ,Pin 94, EMI_D13 pin voltage selection" "No effect,Set" bitfld.long 0xd4 20.--21. " BANK3_PIN13_MA ,Pin 94, EMI_D13 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd4 18. " BANK3_PIN12_V ,Pin 93, EMI_D12 pin voltage selection" "No effect,Set" bitfld.long 0xd4 16.--17. " BANK3_PIN12_MA ,Pin 93, EMI_D12 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd4 14. " BANK3_PIN11_V ,Pin 91, EMI_D11 pin voltage selection" "No effect,Set" bitfld.long 0xd4 12.--13. " BANK3_PIN11_MA ,Pin 91, EMI_D11 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd4 10. " BANK3_PIN10_V ,Pin 89, EMI_D10 pin voltage selection" "No effect,Set" bitfld.long 0xd4 8.--9. " BANK3_PIN10_MA ,Pin 89, EMI_D10 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd4 6. " BANK3_PIN09_V ,Pin 87, EMI_D09 pin voltage selection" "No effect,Set" bitfld.long 0xd4 4.--5. " BANK3_PIN09_MA ,Pin 87, EMI_D09 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd4 2. " BANK3_PIN08_V ,Pin 86, EMI_D08 pin voltage selection" "No effect,Set" bitfld.long 0xd4 0.--1. " BANK3_PIN08_MA ,Pin 86, EMI_D08 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xd8 "HW_PINCTRL_DRIVE13_CLR,Drive Strength and Voltage Clear Register 13" bitfld.long 0xd8 30. " BANK3_PIN15_V ,Pin 95, EMI_D15 pin voltage selection" "No effect,Clear" bitfld.long 0xd8 28.--29. " BANK3_PIN15_MA ,Pin 95, EMI_D15 pin voltage selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd8 26. " BANK3_PIN14_V ,Pin 96, EMI_D14 pin voltage selection" "No effect,Clear" bitfld.long 0xd8 24.--25. " BANK3_PIN14_MA ,Pin 96, EMI_D14 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd8 22. " BANK3_PIN13_V ,Pin 94, EMI_D13 pin voltage selection" "No effect,Clear" bitfld.long 0xd8 20.--21. " BANK3_PIN13_MA ,Pin 94, EMI_D13 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd8 18. " BANK3_PIN12_V ,Pin 93, EMI_D12 pin voltage selection" "No effect,Clear" bitfld.long 0xd8 16.--17. " BANK3_PIN12_MA ,Pin 93, EMI_D12 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd8 14. " BANK3_PIN11_V ,Pin 91, EMI_D11 pin voltage selection" "No effect,Clear" bitfld.long 0xd8 12.--13. " BANK3_PIN11_MA ,Pin 91, EMI_D11 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd8 10. " BANK3_PIN10_V ,Pin 89, EMI_D10 pin voltage selection" "No effect,Clear" bitfld.long 0xd8 8.--9. " BANK3_PIN10_MA ,Pin 89, EMI_D10 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd8 6. " BANK3_PIN09_V ,Pin 87, EMI_D09 pin voltage selection" "No effect,Clear" bitfld.long 0xd8 4.--5. " BANK3_PIN09_MA ,Pin 87, EMI_D09 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xd8 2. " BANK3_PIN08_V ,Pin 86, EMI_D08 pin voltage selection" "No effect,Clear" bitfld.long 0xd8 0.--1. " BANK3_PIN08_MA ,Pin 86, EMI_D08 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xdc "HW_PINCTRL_DRIVE13_TOG,Drive Strength and Voltage Toggle Register 13" bitfld.long 0xdc 30. " BANK3_PIN15_V ,Pin 95, EMI_D15 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xdc 28.--29. " BANK3_PIN15_MA ,Pin 95, EMI_D15 pin voltage selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xdc 26. " BANK3_PIN14_V ,Pin 96, EMI_D14 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xdc 24.--25. " BANK3_PIN14_MA ,Pin 96, EMI_D14 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xdc 22. " BANK3_PIN13_V ,Pin 94, EMI_D13 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xdc 20.--21. " BANK3_PIN13_MA ,Pin 94, EMI_D13 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xdc 18. " BANK3_PIN12_V ,Pin 93, EMI_D12 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xdc 16.--17. " BANK3_PIN12_MA ,Pin 93, EMI_D12 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xdc 14. " BANK3_PIN11_V ,Pin 91, EMI_D11 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xdc 12.--13. " BANK3_PIN11_MA ,Pin 91, EMI_D11 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xdc 10. " BANK3_PIN10_V ,Pin 89, EMI_D10 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xdc 8.--9. " BANK3_PIN10_MA ,Pin 89, EMI_D10 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xdc 6. " BANK3_PIN09_V ,Pin 87, EMI_D09 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xdc 4.--5. " BANK3_PIN09_MA ,Pin 87, EMI_D09 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xdc 2. " BANK3_PIN08_V ,Pin 86, EMI_D08 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xdc 0.--1. " BANK3_PIN08_MA ,Pin 86, EMI_D08 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xe0 "HW_PINCTRL_DRIVE14,Drive Strength and Voltage Register 14" bitfld.long 0xe0 22. " BANK3_PIN21_V ,Pin 72, EMI_CLKN pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xe0 20.--21. " BANK3_PIN21_MA ,Pin 72, EMI_CLKN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe0 18. " BANK3_PIN20_V ,Pin 70, EMI_CLK pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xe0 16.--17. " BANK3_PIN20_MA ,Pin 70, EMI_CLK pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe0 14. " BANK3_PIN19_V ,Pin 74, EMI_DQS1 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xe0 12.--13. " BANK3_PIN19_MA ,Pin 74, EMI_DQS1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe0 10. " BANK3_PIN18_V ,Pin 73, EMI_DQS0 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xe0 8.--9. " BANK3_PIN18_MA ,Pin 73, EMI_DQS0 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe0 6. " BANK3_PIN17_V ,Pin 92, EMI_DQM1 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xe0 4.--5. " BANK3_PIN17_MA ,Pin 92, EMI_DQM1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe0 2. " BANK3_PIN16_V ,Pin 81, EMI_DQM0 pin voltage selection" "1.8V or 2.5V,?..." bitfld.long 0xe0 0.--1. " BANK3_PIN16_MA ,Pin 81, EMI_DQM0 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xe4 "HW_PINCTRL_DRIVE14_SET,Drive Strength and Voltage Set Register 14" bitfld.long 0xe4 22. " BANK3_PIN21_V ,Pin 72, EMI_CLKN pin voltage selection" "No effect,Set" bitfld.long 0xe4 20.--21. " BANK3_PIN21_MA ,Pin 72, EMI_CLKN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe4 18. " BANK3_PIN20_V ,Pin 70, EMI_CLK pin voltage selection" "No effect,Set" bitfld.long 0xe4 16.--17. " BANK3_PIN20_MA ,Pin 70, EMI_CLK pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe4 14. " BANK3_PIN19_V ,Pin 74, EMI_DQS1 pin voltage selection" "No effect,Set" bitfld.long 0xe4 12.--13. " BANK3_PIN19_MA ,Pin 74, EMI_DQS1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe4 10. " BANK3_PIN18_V ,Pin 73, EMI_DQS0 pin voltage selection" "No effect,Set" bitfld.long 0xe4 8.--9. " BANK3_PIN18_MA ,Pin 73, EMI_DQS0 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe4 6. " BANK3_PIN17_V ,Pin 92, EMI_DQM1 pin voltage selection" "No effect,Set" bitfld.long 0xe4 4.--5. " BANK3_PIN17_MA ,Pin 92, EMI_DQM1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe4 2. " BANK3_PIN16_V ,Pin 81, EMI_DQM0 pin voltage selection" "No effect,Set" bitfld.long 0xe4 0.--1. " BANK3_PIN16_MA ,Pin 81, EMI_DQM0 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xe8 "HW_PINCTRL_DRIVE14_CLR,Drive Strength and Voltage Clear Register 14" bitfld.long 0xe8 22. " BANK3_PIN21_V ,Pin 72, EMI_CLKN pin voltage selection" "No effect,Clear" bitfld.long 0xe8 20.--21. " BANK3_PIN21_MA ,Pin 72, EMI_CLKN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe8 18. " BANK3_PIN20_V ,Pin 70, EMI_CLK pin voltage selection" "No effect,Clear" bitfld.long 0xe8 16.--17. " BANK3_PIN20_MA ,Pin 70, EMI_CLK pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe8 14. " BANK3_PIN19_V ,Pin 74, EMI_DQS1 pin voltage selection" "No effect,Clear" bitfld.long 0xe8 12.--13. " BANK3_PIN19_MA ,Pin 74, EMI_DQS1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe8 10. " BANK3_PIN18_V ,Pin 73, EMI_DQS0 pin voltage selection" "No effect,Clear" bitfld.long 0xe8 8.--9. " BANK3_PIN18_MA ,Pin 73, EMI_DQS0 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe8 6. " BANK3_PIN17_V ,Pin 92, EMI_DQM1 pin voltage selection" "No effect,Clear" bitfld.long 0xe8 4.--5. " BANK3_PIN17_MA ,Pin 92, EMI_DQM1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xe8 2. " BANK3_PIN16_V ,Pin 81, EMI_DQM0 pin voltage selection" "No effect,Clear" bitfld.long 0xe8 0.--1. " BANK3_PIN16_MA ,Pin 81, EMI_DQM0 pin output drive strength selection" "4mA,8mA,12mA,16mA" line.long 0xec "HW_PINCTRL_DRIVE14_TOG,Drive Strength and Voltage Toggle Register 14" bitfld.long 0xec 22. " BANK3_PIN21_V ,Pin 72, EMI_CLKN pin voltage selection" "Not toggle,Toggle" bitfld.long 0xec 20.--21. " BANK3_PIN21_MA ,Pin 72, EMI_CLKN pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xec 18. " BANK3_PIN20_V ,Pin 70, EMI_CLK pin voltage selection" "Not toggle,Toggle" bitfld.long 0xec 16.--17. " BANK3_PIN20_MA ,Pin 70, EMI_CLK pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xec 14. " BANK3_PIN19_V ,Pin 74, EMI_DQS1 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xec 12.--13. " BANK3_PIN19_MA ,Pin 74, EMI_DQS1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xec 10. " BANK3_PIN18_V ,Pin 73, EMI_DQS0 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xec 8.--9. " BANK3_PIN18_MA ,Pin 73, EMI_DQS0 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xec 6. " BANK3_PIN17_V ,Pin 92, EMI_DQM1 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xec 4.--5. " BANK3_PIN17_MA ,Pin 92, EMI_DQM1 pin output drive strength selection" "4mA,8mA,12mA,16mA" textline " " bitfld.long 0xec 2. " BANK3_PIN16_V ,Pin 81, EMI_DQM0 pin voltage selection" "Not toggle,Toggle" bitfld.long 0xec 0.--1. " BANK3_PIN16_MA ,Pin 81, EMI_DQM0 pin output drive strength selection" "4mA,8mA,12mA,16mA" tree.end tree "Pull-up Registers" width 22. group.long 0x400++0x3f line.long 0x00 "HW_PINCTRL_PULL0,Bank 0 Pull Up Resistor Enable Register" bitfld.long 0x00 31. " BANK0_PIN31 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 30. " BANK0_PIN30 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 29. " BANK0_PIN29 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BANK0_PIN28 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 27. " BANK0_PIN27 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 26. " BANK0_PIN26 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " BANK0_PIN22 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 21. " BANK0_PIN21 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 20. " BANK0_PIN20 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BANK0_PIN19 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 18. " BANK0_PIN18 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 15. " BANK0_PIN15 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " BANK0_PIN11 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 10. " BANK0_PIN10 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 9. " BANK0_PIN09 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " BANK0_PIN08 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 7. " BANK0_PIN07 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 6. " BANK0_PIN06 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " BANK0_PIN05 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 4. " BANK0_PIN04 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 3. " BANK0_PIN03 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BANK0_PIN02 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 1. " BANK0_PIN01 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 0. " BANK0_PIN00 ,Enable the internal pull up resistor" "Disabled,Enabled" line.long 0x04 "HW_PINCTRL_PULL0_SET,Bank 0 Pull Up Resistor Enable Set Register" bitfld.long 0x04 31. " BANK0_PIN31 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 30. " BANK0_PIN30 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 29. " BANK0_PIN29 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 28. " BANK0_PIN28 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 27. " BANK0_PIN27 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 26. " BANK0_PIN26 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 22. " BANK0_PIN22 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 21. " BANK0_PIN21 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 20. " BANK0_PIN20 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 19. " BANK0_PIN19 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 18. " BANK0_PIN18 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 15. " BANK0_PIN15 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 11. " BANK0_PIN11 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 10. " BANK0_PIN10 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 9. " BANK0_PIN09 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 8. " BANK0_PIN08 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 7. " BANK0_PIN07 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 6. " BANK0_PIN06 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 5. " BANK0_PIN05 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 4. " BANK0_PIN04 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 3. " BANK0_PIN03 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 2. " BANK0_PIN02 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 1. " BANK0_PIN01 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 0. " BANK0_PIN00 ,Enable the internal pull up resistor" "No effect,Set" line.long 0x08 "HW_PINCTRL_PULL0_CLR,Bank 0 Pull Up Resistor Enable Clear Register" bitfld.long 0x08 31. " BANK0_PIN31 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 30. " BANK0_PIN30 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 29. " BANK0_PIN29 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 28. " BANK0_PIN28 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 27. " BANK0_PIN27 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 26. " BANK0_PIN26 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 22. " BANK0_PIN22 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 21. " BANK0_PIN21 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 20. " BANK0_PIN20 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 19. " BANK0_PIN19 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 18. " BANK0_PIN18 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 15. " BANK0_PIN15 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 11. " BANK0_PIN11 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 10. " BANK0_PIN10 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 9. " BANK0_PIN09 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 8. " BANK0_PIN08 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 7. " BANK0_PIN07 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 6. " BANK0_PIN06 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 5. " BANK0_PIN05 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 4. " BANK0_PIN04 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 3. " BANK0_PIN03 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 2. " BANK0_PIN02 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 1. " BANK0_PIN01 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 0. " BANK0_PIN00 ,Enable the internal pull up resistor" "No effect,Clear" line.long 0x0c "HW_PINCTRL_PULL0_TOG,Bank 0 Pull Up Resistor Enable Toggle Register" bitfld.long 0x0c 31. " BANK0_PIN31 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 30. " BANK0_PIN30 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 29. " BANK0_PIN29 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0c 28. " BANK0_PIN28 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 27. " BANK0_PIN27 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 26. " BANK0_PIN26 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " BANK0_PIN22 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 21. " BANK0_PIN21 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 20. " BANK0_PIN20 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " BANK0_PIN19 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 18. " BANK0_PIN18 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 15. " BANK0_PIN15 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " BANK0_PIN11 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 10. " BANK0_PIN10 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 9. " BANK0_PIN09 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BANK0_PIN08 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 7. " BANK0_PIN07 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 6. " BANK0_PIN06 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " BANK0_PIN05 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 4. " BANK0_PIN04 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 3. " BANK0_PIN03 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " BANK0_PIN02 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 1. " BANK0_PIN01 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0c 0. " BANK0_PIN00 ,Enable the internal pull up resistor" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_PULL1,Bank 1 Pull Up Resistor Enable Register" bitfld.long 0x10 28. " BANK1_PIN28 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x10 22. " BANK1_PIN22 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x10 18. " BANK1_PIN18 ,Enable the internal pull up resistor" "Disabled,Enabled" line.long 0x14 "HW_PINCTRL_PULL1_SET,Bank 1 Pull Up Resistor Enable Set Register" bitfld.long 0x14 28. " BANK1_PIN28 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x14 22. " BANK1_PIN22 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x14 18. " BANK1_PIN18 ,Enable the internal pull up resistor" "No effect,Set" line.long 0x18 "HW_PINCTRL_PULL1_CLR,Bank 1 Pull Up Resistor Enable Clear Register" bitfld.long 0x18 28. " BANK1_PIN28 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x18 22. " BANK1_PIN22 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x18 18. " BANK1_PIN18 ,Enable the internal pull up resistor" "No effect,Clear" line.long 0x1c "HW_PINCTRL_PULL1_TOG,Bank 1 Pull Up Resistor Enable Toggle Register" bitfld.long 0x1c 28. " BANK1_PIN28 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x1c 22. " BANK1_PIN22 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x1c 18. " BANK1_PIN18 ,Enable the internal pull up resistor" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_PULL2,Bank 2 Pull Up Resistor Enable Register" bitfld.long 0x20 28. " BANK2_PIN28 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x20 27. " BANK2_PIN27 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x20 8. " BANK2_PIN08 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x20 5. " BANK2_PIN05 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x20 4. " BANK2_PIN04 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x20 3. " BANK2_PIN03 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x20 2. " BANK2_PIN02 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x20 1. " BANK2_PIN01 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x20 0. " BANK2_PIN00 ,Enable the internal pull up resistor" "Disabled,Enabled" line.long 0x24 "HW_PINCTRL_PULL2_SET,Bank 2 Pull Up Resistor Enable Set Register" bitfld.long 0x24 28. " BANK2_PIN28 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x24 27. " BANK2_PIN27 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x24 8. " BANK2_PIN08 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x24 5. " BANK2_PIN05 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x24 4. " BANK2_PIN04 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x24 3. " BANK2_PIN03 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x24 2. " BANK2_PIN02 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x24 1. " BANK2_PIN01 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x24 0. " BANK2_PIN00 ,Enable the internal pull up resistor" "No effect,Set" line.long 0x28 "HW_PINCTRL_PULL2_CLR,Bank 2 Pull Up Resistor Enable Clear Register" bitfld.long 0x28 28. " BANK2_PIN28 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x28 27. " BANK2_PIN27 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x28 8. " BANK2_PIN08 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x28 5. " BANK2_PIN05 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x28 4. " BANK2_PIN04 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x28 3. " BANK2_PIN03 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x28 2. " BANK2_PIN02 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x28 1. " BANK2_PIN01 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x28 0. " BANK2_PIN00 ,Enable the internal pull up resistor" "No effect,Clear" line.long 0x2c "HW_PINCTRL_PULL2_TOG,Bank 2 Pull Up Resistor Enable Toggle Register" bitfld.long 0x2c 28. " BANK2_PIN28 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x2c 27. " BANK2_PIN27 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x2c 8. " BANK2_PIN08 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x2c 5. " BANK2_PIN05 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x2c 4. " BANK2_PIN04 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x2c 3. " BANK2_PIN03 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x2c 2. " BANK2_PIN02 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x2c 1. " BANK2_PIN01 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x2c 0. " BANK2_PIN00 ,Enable the internal pull up resistor" "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_PULL3,Bank 3 Pad Keeper Disable Register" bitfld.long 0x30 17. " BANK3_PIN17 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 16. " BANK3_PIN16 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 15. " BANK3_PIN15 ,Disable the internal pad keeper" "No,Yes" textline " " bitfld.long 0x30 14. " BANK3_PIN14 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 13. " BANK3_PIN13 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 12. " BANK3_PIN12 ,Disable the internal pad keeper" "No,Yes" textline " " bitfld.long 0x30 11. " BANK3_PIN11 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 10. " BANK3_PIN10 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 9. " BANK3_PIN09 ,Disable the internal pad keeper" "No,Yes" textline " " bitfld.long 0x30 8. " BANK3_PIN08 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 7. " BANK3_PIN07 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 6. " BANK3_PIN06 ,Disable the internal pad keeper" "No,Yes" textline " " bitfld.long 0x30 5. " BANK3_PIN05 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 4. " BANK3_PIN04 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 3. " BANK3_PIN03 ,Disable the internal pad keeper" "No,Yes" textline " " bitfld.long 0x30 2. " BANK3_PIN02 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 1. " BANK3_PIN01 ,Disable the internal pad keeper" "No,Yes" bitfld.long 0x30 0. " BANK3_PIN00 ,Disable the internal pad keeper" "No,Yes" line.long 0x34 "HW_PINCTRL_PULL3_SET,Bank 3 Pad Keeper Disable Set Register" bitfld.long 0x34 17. " BANK3_PIN17 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 16. " BANK3_PIN16 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 15. " BANK3_PIN15 ,Disable the internal pad keeper" "No effect,Set" textline " " bitfld.long 0x34 14. " BANK3_PIN14 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 13. " BANK3_PIN13 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 12. " BANK3_PIN12 ,Disable the internal pad keeper" "No effect,Set" textline " " bitfld.long 0x34 11. " BANK3_PIN11 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 10. " BANK3_PIN10 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 9. " BANK3_PIN09 ,Disable the internal pad keeper" "No effect,Set" textline " " bitfld.long 0x34 8. " BANK3_PIN08 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 7. " BANK3_PIN07 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 6. " BANK3_PIN06 ,Disable the internal pad keeper" "No effect,Set" textline " " bitfld.long 0x34 5. " BANK3_PIN05 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 4. " BANK3_PIN04 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 3. " BANK3_PIN03 ,Disable the internal pad keeper" "No effect,Set" textline " " bitfld.long 0x34 2. " BANK3_PIN02 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 1. " BANK3_PIN01 ,Disable the internal pad keeper" "No effect,Set" bitfld.long 0x34 0. " BANK3_PIN00 ,Disable the internal pad keeper" "No effect,Set" line.long 0x38 "HW_PINCTRL_PULL3_CLR,Bank 3 Pad Keeper Disable Clear Register" bitfld.long 0x38 17. " BANK3_PIN17 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 16. " BANK3_PIN16 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 15. " BANK3_PIN15 ,Disable the internal pad keeper" "No effect,Clear" textline " " bitfld.long 0x38 14. " BANK3_PIN14 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 13. " BANK3_PIN13 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 12. " BANK3_PIN12 ,Disable the internal pad keeper" "No effect,Clear" textline " " bitfld.long 0x38 11. " BANK3_PIN11 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 10. " BANK3_PIN10 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 9. " BANK3_PIN09 ,Disable the internal pad keeper" "No effect,Clear" textline " " bitfld.long 0x38 8. " BANK3_PIN08 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 7. " BANK3_PIN07 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 6. " BANK3_PIN06 ,Disable the internal pad keeper" "No effect,Clear" textline " " bitfld.long 0x38 5. " BANK3_PIN05 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 4. " BANK3_PIN04 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 3. " BANK3_PIN03 ,Disable the internal pad keeper" "No effect,Clear" textline " " bitfld.long 0x38 2. " BANK3_PIN02 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 1. " BANK3_PIN01 ,Disable the internal pad keeper" "No effect,Clear" bitfld.long 0x38 0. " BANK3_PIN00 ,Disable the internal pad keeper" "No effect,Clear" line.long 0x3c "HW_PINCTRL_PULL3_TOG,Bank 3 Pad Keeper Disable Toggle Register" bitfld.long 0x3c 17. " BANK3_PIN17 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 16. " BANK3_PIN16 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 15. " BANK3_PIN15 ,Disable the internal pad keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3c 14. " BANK3_PIN14 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 13. " BANK3_PIN13 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 12. " BANK3_PIN12 ,Disable the internal pad keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3c 11. " BANK3_PIN11 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 10. " BANK3_PIN10 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 9. " BANK3_PIN09 ,Disable the internal pad keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3c 8. " BANK3_PIN08 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 7. " BANK3_PIN07 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 6. " BANK3_PIN06 ,Disable the internal pad keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3c 5. " BANK3_PIN05 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 4. " BANK3_PIN04 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 3. " BANK3_PIN03 ,Disable the internal pad keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3c 2. " BANK3_PIN02 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 1. " BANK3_PIN01 ,Disable the internal pad keeper" "Not toggle,Toggle" bitfld.long 0x3c 0. " BANK3_PIN00 ,Disable the internal pad keeper" "Not toggle,Toggle" tree.end tree "Data Registers" group.long 0x500++0x3f "Data Output Registers" width 23. line.long 0x0 "HW_PINCTRL_DOUT0,Bank 0 Data Output Register" bitfld.long 0x0 31. " DOUT31 ,Output value" "0,1" bitfld.long 0x0 30. " DOUT30 ,Output value" "0,1" bitfld.long 0x0 29. " DOUT29 ,Output value" "0,1" textline " " bitfld.long 0x0 28. " DOUT28 ,Output value" "0,1" bitfld.long 0x0 27. " DOUT27 ,Output value" "0,1" bitfld.long 0x0 26. " DOUT26 ,Output value" "0,1" textline " " bitfld.long 0x0 25. " DOUT25 ,Output value" "0,1" bitfld.long 0x0 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x0 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x0 22. " DOUT22 ,Output value" "0,1" bitfld.long 0x0 21. " DOUT21 ,Output value" "0,1" bitfld.long 0x0 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x0 19. " DOUT19 ,Output value" "0,1" bitfld.long 0x0 18. " DOUT18 ,Output value" "0,1" bitfld.long 0x0 17. " DOUT17 ,Output value" "0,1" textline " " bitfld.long 0x0 16. " DOUT16 ,Output value" "0,1" bitfld.long 0x0 15. " DOUT15 ,Output value" "0,1" bitfld.long 0x0 14. " DOUT14 ,Output value" "0,1" textline " " bitfld.long 0x0 13. " DOUT13 ,Output value" "0,1" bitfld.long 0x0 12. " DOUT12 ,Output value" "0,1" bitfld.long 0x0 11. " DOUT11 ,Output value" "0,1" textline " " bitfld.long 0x0 10. " DOUT10 ,Output value" "0,1" bitfld.long 0x0 9. " DOUT9 ,Output value" "0,1" bitfld.long 0x0 8. " DOUT8 ,Output value" "0,1" textline " " bitfld.long 0x0 7. " DOUT7 ,Output value" "0,1" bitfld.long 0x0 6. " DOUT6 ,Output value" "0,1" bitfld.long 0x0 5. " DOUT5 ,Output value" "0,1" textline " " bitfld.long 0x0 4. " DOUT4 ,Output value" "0,1" bitfld.long 0x0 3. " DOUT3 ,Output value" "0,1" bitfld.long 0x0 2. " DOUT2 ,Output value" "0,1" textline " " bitfld.long 0x0 1. " DOUT1 ,Output value" "0,1" bitfld.long 0x0 0. " DOUT0 ,Output value" "0,1" line.long (0x0+0x04) "HW_PINCTRL_DOUT0_SET,Bank 0 Data Output Set Register" bitfld.long (0x0+0x04) 31. " DOUT31 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 30. " DOUT30 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 29. " DOUT29 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 28. " DOUT28 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 27. " DOUT27 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 26. " DOUT26 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " DOUT25 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " DOUT22 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 21. " DOUT21 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " DOUT19 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 18. " DOUT18 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 17. " DOUT17 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " DOUT16 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 15. " DOUT15 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 14. " DOUT14 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " DOUT13 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 12. " DOUT12 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 11. " DOUT11 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " DOUT10 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 9. " DOUT9 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 8. " DOUT8 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " DOUT7 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 6. " DOUT6 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 5. " DOUT5 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " DOUT4 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 3. " DOUT3 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 2. " DOUT2 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " DOUT1 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 0. " DOUT0 ,Output value" "No effect,Set" line.long (0x0+0x08) "HW_PINCTRL_DOUT0_CLR,Bank 0 Data Output Clear Register" bitfld.long (0x0+0x08) 31. " DOUT31 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 30. " DOUT30 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 29. " DOUT29 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 28. " DOUT28 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 27. " DOUT27 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 26. " DOUT26 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " DOUT25 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 22. " DOUT22 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 21. " DOUT21 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 19. " DOUT19 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 18. " DOUT18 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 17. " DOUT17 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " DOUT16 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 15. " DOUT15 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 14. " DOUT14 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 13. " DOUT13 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 12. " DOUT12 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 11. " DOUT11 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 10. " DOUT10 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 9. " DOUT9 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 8. " DOUT8 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 7. " DOUT7 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 6. " DOUT6 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 5. " DOUT5 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 4. " DOUT4 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 3. " DOUT3 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 2. " DOUT2 ,Output value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 1. " DOUT1 ,Output value" "No effect,Clear" bitfld.long (0x0+0x08) 0. " DOUT0 ,Output value" "No effect,Clear" line.long (0x0+0x0c) "HW_PINCTRL_DOUT0_TOG,Bank 0 Data Output Toggle Register" bitfld.long (0x0+0x0c) 31. " DOUT31 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " DOUT30 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " DOUT29 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 28. " DOUT28 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 27. " DOUT27 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " DOUT26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " DOUT25 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 22. " DOUT22 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 21. " DOUT21 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 19. " DOUT19 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 18. " DOUT18 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " DOUT17 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " DOUT16 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 15. " DOUT15 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 14. " DOUT14 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 13. " DOUT13 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 12. " DOUT12 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11. " DOUT11 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 10. " DOUT10 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 9. " DOUT9 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 8. " DOUT8 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 7. " DOUT7 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 6. " DOUT6 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 5. " DOUT5 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 4. " DOUT4 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 3. " DOUT3 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 2. " DOUT2 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 1. " DOUT1 ,Output value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 0. " DOUT0 ,Output value" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_DOUT1,Bank 1 Data Output Register" bitfld.long 0x10 30. " DOUT30 ,Output value" "0,1" bitfld.long 0x10 29. " DOUT29 ,Output value" "0,1" textline " " bitfld.long 0x10 28. " DOUT28 ,Output value" "0,1" bitfld.long 0x10 27. " DOUT27 ,Output value" "0,1" bitfld.long 0x10 26. " DOUT26 ,Output value" "0,1" textline " " bitfld.long 0x10 25. " DOUT25 ,Output value" "0,1" bitfld.long 0x10 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x10 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x10 22. " DOUT22 ,Output value" "0,1" bitfld.long 0x10 21. " DOUT21 ,Output value" "0,1" bitfld.long 0x10 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x10 19. " DOUT19 ,Output value" "0,1" bitfld.long 0x10 18. " DOUT18 ,Output value" "0,1" bitfld.long 0x10 17. " DOUT17 ,Output value" "0,1" textline " " bitfld.long 0x10 16. " DOUT16 ,Output value" "0,1" bitfld.long 0x10 15. " DOUT15 ,Output value" "0,1" bitfld.long 0x10 14. " DOUT14 ,Output value" "0,1" textline " " bitfld.long 0x10 13. " DOUT13 ,Output value" "0,1" bitfld.long 0x10 12. " DOUT12 ,Output value" "0,1" bitfld.long 0x10 11. " DOUT11 ,Output value" "0,1" textline " " bitfld.long 0x10 10. " DOUT10 ,Output value" "0,1" bitfld.long 0x10 9. " DOUT9 ,Output value" "0,1" bitfld.long 0x10 8. " DOUT8 ,Output value" "0,1" textline " " bitfld.long 0x10 7. " DOUT7 ,Output value" "0,1" bitfld.long 0x10 6. " DOUT6 ,Output value" "0,1" bitfld.long 0x10 5. " DOUT5 ,Output value" "0,1" textline " " bitfld.long 0x10 4. " DOUT4 ,Output value" "0,1" bitfld.long 0x10 3. " DOUT3 ,Output value" "0,1" bitfld.long 0x10 2. " DOUT2 ,Output value" "0,1" textline " " bitfld.long 0x10 1. " DOUT1 ,Output value" "0,1" bitfld.long 0x10 0. " DOUT0 ,Output value" "0,1" line.long (0x10+0x04) "HW_PINCTRL_DOUT1_SET,Bank 1 Data Output Set Register" bitfld.long (0x10+0x04) 30. " DOUT30 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 29. " DOUT29 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " DOUT28 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 27. " DOUT27 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 26. " DOUT26 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " DOUT25 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " DOUT22 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 21. " DOUT21 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " DOUT19 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 18. " DOUT18 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 17. " DOUT17 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " DOUT16 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 15. " DOUT15 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 14. " DOUT14 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " DOUT13 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 12. " DOUT12 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 11. " DOUT11 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " DOUT10 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 9. " DOUT9 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 8. " DOUT8 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " DOUT7 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 6. " DOUT6 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 5. " DOUT5 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " DOUT4 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 3. " DOUT3 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 2. " DOUT2 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " DOUT1 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 0. " DOUT0 ,Output value" "No effect,Set" line.long (0x10+0x08) "HW_PINCTRL_DOUT1_CLR,Bank 1 Data Output Clear Register" bitfld.long (0x10+0x08) 30. " DOUT30 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 29. " DOUT29 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 28. " DOUT28 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 27. " DOUT27 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 26. " DOUT26 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " DOUT25 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 22. " DOUT22 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 21. " DOUT21 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 19. " DOUT19 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 18. " DOUT18 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 17. " DOUT17 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " DOUT16 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 15. " DOUT15 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 14. " DOUT14 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 13. " DOUT13 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 12. " DOUT12 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 11. " DOUT11 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 10. " DOUT10 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 9. " DOUT9 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 8. " DOUT8 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 7. " DOUT7 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 6. " DOUT6 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 5. " DOUT5 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 4. " DOUT4 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 3. " DOUT3 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 2. " DOUT2 ,Output value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 1. " DOUT1 ,Output value" "No effect,Clear" bitfld.long (0x10+0x08) 0. " DOUT0 ,Output value" "No effect,Clear" line.long (0x10+0x0c) "HW_PINCTRL_DOUT1_TOG,Bank 1 Data Output Toggle Register" bitfld.long (0x10+0x0c) 30. " DOUT30 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " DOUT29 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 28. " DOUT28 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 27. " DOUT27 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " DOUT26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " DOUT25 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 22. " DOUT22 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 21. " DOUT21 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 19. " DOUT19 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 18. " DOUT18 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " DOUT17 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " DOUT16 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 15. " DOUT15 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 14. " DOUT14 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 13. " DOUT13 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 12. " DOUT12 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11. " DOUT11 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 10. " DOUT10 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 9. " DOUT9 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 8. " DOUT8 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 7. " DOUT7 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 6. " DOUT6 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 5. " DOUT5 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 4. " DOUT4 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 3. " DOUT3 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 2. " DOUT2 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 1. " DOUT1 ,Output value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 0. " DOUT0 ,Output value" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_DOUT2,Bank 2 Data Output Register" bitfld.long 0x20 31. " DOUT31 ,Output value" "0,1" bitfld.long 0x20 30. " DOUT30 ,Output value" "0,1" bitfld.long 0x20 29. " DOUT29 ,Output value" "0,1" textline " " bitfld.long 0x20 28. " DOUT28 ,Output value" "0,1" bitfld.long 0x20 27. " DOUT27 ,Output value" "0,1" bitfld.long 0x20 26. " DOUT26 ,Output value" "0,1" textline " " bitfld.long 0x20 25. " DOUT25 ,Output value" "0,1" bitfld.long 0x20 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x20 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x20 22. " DOUT22 ,Output value" "0,1" bitfld.long 0x20 21. " DOUT21 ,Output value" "0,1" bitfld.long 0x20 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x20 19. " DOUT19 ,Output value" "0,1" bitfld.long 0x20 18. " DOUT18 ,Output value" "0,1" bitfld.long 0x20 17. " DOUT17 ,Output value" "0,1" textline " " bitfld.long 0x20 16. " DOUT16 ,Output value" "0,1" bitfld.long 0x20 15. " DOUT15 ,Output value" "0,1" bitfld.long 0x20 14. " DOUT14 ,Output value" "0,1" textline " " bitfld.long 0x20 13. " DOUT13 ,Output value" "0,1" bitfld.long 0x20 12. " DOUT12 ,Output value" "0,1" bitfld.long 0x20 11. " DOUT11 ,Output value" "0,1" textline " " bitfld.long 0x20 10. " DOUT10 ,Output value" "0,1" bitfld.long 0x20 9. " DOUT9 ,Output value" "0,1" bitfld.long 0x20 8. " DOUT8 ,Output value" "0,1" textline " " bitfld.long 0x20 7. " DOUT7 ,Output value" "0,1" bitfld.long 0x20 6. " DOUT6 ,Output value" "0,1" bitfld.long 0x20 5. " DOUT5 ,Output value" "0,1" textline " " bitfld.long 0x20 4. " DOUT4 ,Output value" "0,1" bitfld.long 0x20 3. " DOUT3 ,Output value" "0,1" bitfld.long 0x20 2. " DOUT2 ,Output value" "0,1" textline " " bitfld.long 0x20 1. " DOUT1 ,Output value" "0,1" bitfld.long 0x20 0. " DOUT0 ,Output value" "0,1" line.long (0x20+0x04) "HW_PINCTRL_DOUT2_SET,Bank 2 Data Output Set Register" bitfld.long (0x20+0x04) 31. " DOUT31 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 30. " DOUT30 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 29. " DOUT29 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 28. " DOUT28 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 27. " DOUT27 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 26. " DOUT26 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " DOUT25 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " DOUT22 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 21. " DOUT21 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " DOUT19 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 18. " DOUT18 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 17. " DOUT17 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " DOUT16 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 15. " DOUT15 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 14. " DOUT14 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " DOUT13 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 12. " DOUT12 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 11. " DOUT11 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " DOUT10 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 9. " DOUT9 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 8. " DOUT8 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " DOUT7 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 6. " DOUT6 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 5. " DOUT5 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " DOUT4 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 3. " DOUT3 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 2. " DOUT2 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " DOUT1 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 0. " DOUT0 ,Output value" "No effect,Set" line.long (0x20+0x08) "HW_PINCTRL_DOUT2_CLR,Bank 2 Data Output Clear Register" bitfld.long (0x20+0x08) 31. " DOUT31 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 30. " DOUT30 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 29. " DOUT29 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 28. " DOUT28 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 27. " DOUT27 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 26. " DOUT26 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " DOUT25 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 22. " DOUT22 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 21. " DOUT21 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 19. " DOUT19 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 18. " DOUT18 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 17. " DOUT17 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " DOUT16 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 15. " DOUT15 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 14. " DOUT14 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 13. " DOUT13 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 12. " DOUT12 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 11. " DOUT11 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 10. " DOUT10 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 9. " DOUT9 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 8. " DOUT8 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 7. " DOUT7 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 6. " DOUT6 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 5. " DOUT5 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 4. " DOUT4 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 3. " DOUT3 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 2. " DOUT2 ,Output value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 1. " DOUT1 ,Output value" "No effect,Clear" bitfld.long (0x20+0x08) 0. " DOUT0 ,Output value" "No effect,Clear" line.long (0x20+0x0c) "HW_PINCTRL_DOUT2_TOG,Bank 2 Data Output Toggle Register" bitfld.long (0x20+0x0c) 31. " DOUT31 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " DOUT30 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " DOUT29 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 28. " DOUT28 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 27. " DOUT27 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " DOUT26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " DOUT25 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 22. " DOUT22 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 21. " DOUT21 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 19. " DOUT19 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 18. " DOUT18 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " DOUT17 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " DOUT16 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 15. " DOUT15 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 14. " DOUT14 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 13. " DOUT13 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 12. " DOUT12 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11. " DOUT11 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 10. " DOUT10 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 9. " DOUT9 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 8. " DOUT8 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 7. " DOUT7 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 6. " DOUT6 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 5. " DOUT5 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 4. " DOUT4 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 3. " DOUT3 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 2. " DOUT2 ,Output value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 1. " DOUT1 ,Output value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 0. " DOUT0 ,Output value" "Not toggle,Toggle" rgroup.long 0x600++0x3f "Data Input Registers" width 22. line.long 0x0 "HW_PINCTRL_DIN0,Bank 0 Data Input Register" bitfld.long 0x0 31. " DIN31 ,Input value" "0,1" bitfld.long 0x0 30. " DIN30 ,Input value" "0,1" bitfld.long 0x0 29. " DIN29 ,Input value" "0,1" textline " " bitfld.long 0x0 28. " DIN28 ,Input value" "0,1" bitfld.long 0x0 27. " DIN27 ,Input value" "0,1" bitfld.long 0x0 26. " DIN26 ,Input value" "0,1" textline " " bitfld.long 0x0 25. " DIN25 ,Input value" "0,1" bitfld.long 0x0 24. " DIN24 ,Input value" "0,1" bitfld.long 0x0 23. " DIN23 ,Input value" "0,1" textline " " bitfld.long 0x0 22. " DIN22 ,Input value" "0,1" bitfld.long 0x0 21. " DIN21 ,Input value" "0,1" bitfld.long 0x0 20. " DIN20 ,Input value" "0,1" textline " " bitfld.long 0x0 19. " DIN19 ,Input value" "0,1" bitfld.long 0x0 18. " DIN18 ,Input value" "0,1" bitfld.long 0x0 17. " DIN17 ,Input value" "0,1" textline " " bitfld.long 0x0 16. " DIN16 ,Input value" "0,1" bitfld.long 0x0 15. " DIN15 ,Input value" "0,1" bitfld.long 0x0 14. " DIN14 ,Input value" "0,1" textline " " bitfld.long 0x0 13. " DIN13 ,Input value" "0,1" bitfld.long 0x0 12. " DIN12 ,Input value" "0,1" bitfld.long 0x0 11. " DIN11 ,Input value" "0,1" textline " " bitfld.long 0x0 10. " DIN10 ,Input value" "0,1" bitfld.long 0x0 9. " DIN9 ,Input value" "0,1" bitfld.long 0x0 8. " DIN8 ,Input value" "0,1" textline " " bitfld.long 0x0 7. " DIN7 ,Input value" "0,1" bitfld.long 0x0 6. " DIN6 ,Input value" "0,1" bitfld.long 0x0 5. " DIN5 ,Input value" "0,1" textline " " bitfld.long 0x0 4. " DIN4 ,Input value" "0,1" bitfld.long 0x0 3. " DIN3 ,Input value" "0,1" bitfld.long 0x0 2. " DIN2 ,Input value" "0,1" textline " " bitfld.long 0x0 1. " DIN1 ,Input value" "0,1" bitfld.long 0x0 0. " DIN0 ,Input value" "0,1" line.long (0x0+0x04) "HW_PINCTRL_DIN0_SET,Bank 0 Data Input Set Register" bitfld.long (0x0+0x04) 31. " DIN31 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 30. " DIN30 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 29. " DIN29 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 28. " DIN28 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 27. " DIN27 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 26. " DIN26 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " DIN25 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 24. " DIN24 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 23. " DIN23 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " DIN22 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 21. " DIN21 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 20. " DIN20 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " DIN19 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 18. " DIN18 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 17. " DIN17 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " DIN16 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 15. " DIN15 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 14. " DIN14 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " DIN13 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 12. " DIN12 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 11. " DIN11 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " DIN10 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 9. " DIN9 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 8. " DIN8 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " DIN7 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 6. " DIN6 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 5. " DIN5 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " DIN4 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 3. " DIN3 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 2. " DIN2 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " DIN1 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 0. " DIN0 ,Input value" "No effect,Set" line.long (0x0+0x08) "HW_PINCTRL_DIN0_CLR,Bank 0 Data Input Clear Register" bitfld.long (0x0+0x08) 31. " DIN31 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 30. " DIN30 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 29. " DIN29 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 28. " DIN28 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 27. " DIN27 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 26. " DIN26 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " DIN25 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 24. " DIN24 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 23. " DIN23 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 22. " DIN22 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 21. " DIN21 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 20. " DIN20 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 19. " DIN19 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 18. " DIN18 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 17. " DIN17 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " DIN16 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 15. " DIN15 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 14. " DIN14 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 13. " DIN13 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 12. " DIN12 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 11. " DIN11 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 10. " DIN10 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 9. " DIN9 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 8. " DIN8 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 7. " DIN7 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 6. " DIN6 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 5. " DIN5 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 4. " DIN4 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 3. " DIN3 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 2. " DIN2 ,Input value" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 1. " DIN1 ,Input value" "No effect,Clear" bitfld.long (0x0+0x08) 0. " DIN0 ,Input value" "No effect,Clear" line.long (0x0+0x0c) "HW_PINCTRL_DIN0_TOG,Bank 0 Data Input Toggle Register" bitfld.long (0x0+0x0c) 31. " DIN31 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " DIN30 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " DIN29 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 28. " DIN28 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 27. " DIN27 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " DIN26 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " DIN25 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " DIN24 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 23. " DIN23 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 22. " DIN22 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 21. " DIN21 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 20. " DIN20 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 19. " DIN19 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 18. " DIN18 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " DIN17 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " DIN16 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 15. " DIN15 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 14. " DIN14 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 13. " DIN13 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 12. " DIN12 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11. " DIN11 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 10. " DIN10 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 9. " DIN9 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 8. " DIN8 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 7. " DIN7 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 6. " DIN6 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 5. " DIN5 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 4. " DIN4 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 3. " DIN3 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 2. " DIN2 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 1. " DIN1 ,Input value" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 0. " DIN0 ,Input value" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_DIN1,Bank 1 Data Input Register" bitfld.long 0x10 30. " DIN30 ,Input value" "0,1" bitfld.long 0x10 29. " DIN29 ,Input value" "0,1" textline " " bitfld.long 0x10 28. " DIN28 ,Input value" "0,1" bitfld.long 0x10 27. " DIN27 ,Input value" "0,1" bitfld.long 0x10 26. " DIN26 ,Input value" "0,1" textline " " bitfld.long 0x10 25. " DIN25 ,Input value" "0,1" bitfld.long 0x10 24. " DIN24 ,Input value" "0,1" bitfld.long 0x10 23. " DIN23 ,Input value" "0,1" textline " " bitfld.long 0x10 22. " DIN22 ,Input value" "0,1" bitfld.long 0x10 21. " DIN21 ,Input value" "0,1" bitfld.long 0x10 20. " DIN20 ,Input value" "0,1" textline " " bitfld.long 0x10 19. " DIN19 ,Input value" "0,1" bitfld.long 0x10 18. " DIN18 ,Input value" "0,1" bitfld.long 0x10 17. " DIN17 ,Input value" "0,1" textline " " bitfld.long 0x10 16. " DIN16 ,Input value" "0,1" bitfld.long 0x10 15. " DIN15 ,Input value" "0,1" bitfld.long 0x10 14. " DIN14 ,Input value" "0,1" textline " " bitfld.long 0x10 13. " DIN13 ,Input value" "0,1" bitfld.long 0x10 12. " DIN12 ,Input value" "0,1" bitfld.long 0x10 11. " DIN11 ,Input value" "0,1" textline " " bitfld.long 0x10 10. " DIN10 ,Input value" "0,1" bitfld.long 0x10 9. " DIN9 ,Input value" "0,1" bitfld.long 0x10 8. " DIN8 ,Input value" "0,1" textline " " bitfld.long 0x10 7. " DIN7 ,Input value" "0,1" bitfld.long 0x10 6. " DIN6 ,Input value" "0,1" bitfld.long 0x10 5. " DIN5 ,Input value" "0,1" textline " " bitfld.long 0x10 4. " DIN4 ,Input value" "0,1" bitfld.long 0x10 3. " DIN3 ,Input value" "0,1" bitfld.long 0x10 2. " DIN2 ,Input value" "0,1" textline " " bitfld.long 0x10 1. " DIN1 ,Input value" "0,1" bitfld.long 0x10 0. " DIN0 ,Input value" "0,1" line.long (0x10+0x04) "HW_PINCTRL_DIN1_SET,Bank 1 Data Input Set Register" bitfld.long (0x10+0x04) 30. " DIN30 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 29. " DIN29 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " DIN28 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 27. " DIN27 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 26. " DIN26 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " DIN25 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 24. " DIN24 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 23. " DIN23 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " DIN22 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 21. " DIN21 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 20. " DIN20 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " DIN19 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 18. " DIN18 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 17. " DIN17 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " DIN16 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 15. " DIN15 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 14. " DIN14 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " DIN13 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 12. " DIN12 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 11. " DIN11 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " DIN10 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 9. " DIN9 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 8. " DIN8 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " DIN7 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 6. " DIN6 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 5. " DIN5 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " DIN4 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 3. " DIN3 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 2. " DIN2 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " DIN1 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 0. " DIN0 ,Input value" "No effect,Set" line.long (0x10+0x08) "HW_PINCTRL_DIN1_CLR,Bank 1 Data Input Clear Register" bitfld.long (0x10+0x08) 30. " DIN30 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 29. " DIN29 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 28. " DIN28 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 27. " DIN27 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 26. " DIN26 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " DIN25 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 24. " DIN24 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 23. " DIN23 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 22. " DIN22 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 21. " DIN21 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 20. " DIN20 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 19. " DIN19 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 18. " DIN18 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 17. " DIN17 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " DIN16 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 15. " DIN15 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 14. " DIN14 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 13. " DIN13 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 12. " DIN12 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 11. " DIN11 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 10. " DIN10 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 9. " DIN9 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 8. " DIN8 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 7. " DIN7 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 6. " DIN6 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 5. " DIN5 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 4. " DIN4 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 3. " DIN3 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 2. " DIN2 ,Input value" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 1. " DIN1 ,Input value" "No effect,Clear" bitfld.long (0x10+0x08) 0. " DIN0 ,Input value" "No effect,Clear" line.long (0x10+0x0c) "HW_PINCTRL_DIN1_TOG,Bank 1 Data Input Toggle Register" bitfld.long (0x10+0x0c) 30. " DIN30 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " DIN29 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 28. " DIN28 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 27. " DIN27 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " DIN26 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " DIN25 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " DIN24 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 23. " DIN23 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 22. " DIN22 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 21. " DIN21 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 20. " DIN20 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 19. " DIN19 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 18. " DIN18 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " DIN17 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " DIN16 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 15. " DIN15 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 14. " DIN14 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 13. " DIN13 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 12. " DIN12 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11. " DIN11 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 10. " DIN10 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 9. " DIN9 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 8. " DIN8 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 7. " DIN7 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 6. " DIN6 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 5. " DIN5 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 4. " DIN4 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 3. " DIN3 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 2. " DIN2 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 1. " DIN1 ,Input value" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 0. " DIN0 ,Input value" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_DIN2,Bank 2 Data Input Register" bitfld.long 0x20 31. " DIN31 ,Input value" "0,1" bitfld.long 0x20 30. " DIN30 ,Input value" "0,1" bitfld.long 0x20 29. " DIN29 ,Input value" "0,1" textline " " bitfld.long 0x20 28. " DIN28 ,Input value" "0,1" bitfld.long 0x20 27. " DIN27 ,Input value" "0,1" bitfld.long 0x20 26. " DIN26 ,Input value" "0,1" textline " " bitfld.long 0x20 25. " DIN25 ,Input value" "0,1" bitfld.long 0x20 24. " DIN24 ,Input value" "0,1" bitfld.long 0x20 23. " DIN23 ,Input value" "0,1" textline " " bitfld.long 0x20 22. " DIN22 ,Input value" "0,1" bitfld.long 0x20 21. " DIN21 ,Input value" "0,1" bitfld.long 0x20 20. " DIN20 ,Input value" "0,1" textline " " bitfld.long 0x20 19. " DIN19 ,Input value" "0,1" bitfld.long 0x20 18. " DIN18 ,Input value" "0,1" bitfld.long 0x20 17. " DIN17 ,Input value" "0,1" textline " " bitfld.long 0x20 16. " DIN16 ,Input value" "0,1" bitfld.long 0x20 15. " DIN15 ,Input value" "0,1" bitfld.long 0x20 14. " DIN14 ,Input value" "0,1" textline " " bitfld.long 0x20 13. " DIN13 ,Input value" "0,1" bitfld.long 0x20 12. " DIN12 ,Input value" "0,1" bitfld.long 0x20 11. " DIN11 ,Input value" "0,1" textline " " bitfld.long 0x20 10. " DIN10 ,Input value" "0,1" bitfld.long 0x20 9. " DIN9 ,Input value" "0,1" bitfld.long 0x20 8. " DIN8 ,Input value" "0,1" textline " " bitfld.long 0x20 7. " DIN7 ,Input value" "0,1" bitfld.long 0x20 6. " DIN6 ,Input value" "0,1" bitfld.long 0x20 5. " DIN5 ,Input value" "0,1" textline " " bitfld.long 0x20 4. " DIN4 ,Input value" "0,1" bitfld.long 0x20 3. " DIN3 ,Input value" "0,1" bitfld.long 0x20 2. " DIN2 ,Input value" "0,1" textline " " bitfld.long 0x20 1. " DIN1 ,Input value" "0,1" bitfld.long 0x20 0. " DIN0 ,Input value" "0,1" line.long (0x20+0x04) "HW_PINCTRL_DIN2_SET,Bank 2 Data Input Set Register" bitfld.long (0x20+0x04) 31. " DIN31 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 30. " DIN30 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 29. " DIN29 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 28. " DIN28 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 27. " DIN27 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 26. " DIN26 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " DIN25 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 24. " DIN24 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 23. " DIN23 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " DIN22 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 21. " DIN21 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 20. " DIN20 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " DIN19 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 18. " DIN18 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 17. " DIN17 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " DIN16 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 15. " DIN15 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 14. " DIN14 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " DIN13 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 12. " DIN12 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 11. " DIN11 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " DIN10 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 9. " DIN9 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 8. " DIN8 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " DIN7 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 6. " DIN6 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 5. " DIN5 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " DIN4 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 3. " DIN3 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 2. " DIN2 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " DIN1 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 0. " DIN0 ,Input value" "No effect,Set" line.long (0x20+0x08) "HW_PINCTRL_DIN2_CLR,Bank 2 Data Input Clear Register" bitfld.long (0x20+0x08) 31. " DIN31 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 30. " DIN30 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 29. " DIN29 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 28. " DIN28 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 27. " DIN27 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 26. " DIN26 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " DIN25 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 24. " DIN24 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 23. " DIN23 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 22. " DIN22 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 21. " DIN21 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 20. " DIN20 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 19. " DIN19 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 18. " DIN18 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 17. " DIN17 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " DIN16 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 15. " DIN15 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 14. " DIN14 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 13. " DIN13 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 12. " DIN12 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 11. " DIN11 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 10. " DIN10 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 9. " DIN9 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 8. " DIN8 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 7. " DIN7 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 6. " DIN6 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 5. " DIN5 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 4. " DIN4 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 3. " DIN3 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 2. " DIN2 ,Input value" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 1. " DIN1 ,Input value" "No effect,Clear" bitfld.long (0x20+0x08) 0. " DIN0 ,Input value" "No effect,Clear" line.long (0x20+0x0c) "HW_PINCTRL_DIN2_TOG,Bank 2 Data Input Toggle Register" bitfld.long (0x20+0x0c) 31. " DIN31 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " DIN30 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " DIN29 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 28. " DIN28 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 27. " DIN27 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " DIN26 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " DIN25 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " DIN24 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 23. " DIN23 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 22. " DIN22 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 21. " DIN21 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 20. " DIN20 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 19. " DIN19 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 18. " DIN18 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " DIN17 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " DIN16 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 15. " DIN15 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 14. " DIN14 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 13. " DIN13 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 12. " DIN12 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11. " DIN11 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 10. " DIN10 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 9. " DIN9 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 8. " DIN8 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 7. " DIN7 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 6. " DIN6 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 5. " DIN5 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 4. " DIN4 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 3. " DIN3 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 2. " DIN2 ,Input value" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 1. " DIN1 ,Input value" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 0. " DIN0 ,Input value" "Not toggle,Toggle" group.long 0x700++0x3f "Data Output Enable Registers" width 22. line.long 0x0 "HW_PINCTRL_DOE0,Bank 0 Data Output Enable Register" bitfld.long 0x0 31. " DOE31 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 30. " DOE30 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 29. " DOE29 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DOE28 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 27. " DOE27 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 26. " DOE26 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " DOE25 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 24. " DOE24 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 23. " DOE23 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 22. " DOE22 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 21. " DOE21 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 20. " DOE20 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " DOE19 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 18. " DOE18 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 17. " DOE17 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " DOE16 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 15. " DOE15 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 14. " DOE14 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " DOE13 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 12. " DOE12 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 11. " DOE11 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " DOE10 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 9. " DOE9 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 8. " DOE8 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " DOE7 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 6. " DOE6 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 5. " DOE5 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DOE4 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 3. " DOE3 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 2. " DOE2 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " DOE1 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 0. " DOE0 ,Output enable" "Disabled,Enabled" line.long (0x0+0x04) "HW_PINCTRL_DOE0_SET,Bank 0 Data Output Enable Set Register" bitfld.long (0x0+0x04) 31. " DOE31 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 30. " DOE30 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 29. " DOE29 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 28. " DOE28 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 27. " DOE27 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 26. " DOE26 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " DOE25 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 24. " DOE24 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 23. " DOE23 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " DOE22 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 21. " DOE21 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 20. " DOE20 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " DOE19 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 18. " DOE18 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 17. " DOE17 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " DOE16 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 15. " DOE15 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 14. " DOE14 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " DOE13 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 12. " DOE12 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 11. " DOE11 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " DOE10 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 9. " DOE9 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 8. " DOE8 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " DOE7 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 6. " DOE6 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 5. " DOE5 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " DOE4 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 3. " DOE3 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 2. " DOE2 ,Output enable" "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " DOE1 ,Output enable" "No effect,Set" bitfld.long (0x0+0x04) 0. " DOE0 ,Output enable" "No effect,Set" line.long (0x0+0x08) "HW_PINCTRL_DOE0_CLR,Bank 0 Data Output Enable Clear Register" bitfld.long (0x0+0x08) 31. " DOE31 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 30. " DOE30 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 29. " DOE29 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 28. " DOE28 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 27. " DOE27 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 26. " DOE26 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " DOE25 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 24. " DOE24 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 23. " DOE23 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 22. " DOE22 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 21. " DOE21 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 20. " DOE20 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 19. " DOE19 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 18. " DOE18 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 17. " DOE17 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " DOE16 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 15. " DOE15 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 14. " DOE14 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 13. " DOE13 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 12. " DOE12 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 11. " DOE11 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 10. " DOE10 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 9. " DOE9 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 8. " DOE8 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 7. " DOE7 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 6. " DOE6 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 5. " DOE5 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 4. " DOE4 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 3. " DOE3 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 2. " DOE2 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 1. " DOE1 ,Output enable" "No effect,Clear" bitfld.long (0x0+0x08) 0. " DOE0 ,Output enable" "No effect,Clear" line.long (0x0+0x0c) "HW_PINCTRL_DOE0_TOG,Bank 0 Data Output Enable Toggle Register" bitfld.long (0x0+0x0c) 31. " DOE31 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " DOE30 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " DOE29 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 28. " DOE28 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 27. " DOE27 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " DOE26 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " DOE25 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " DOE24 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 23. " DOE23 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 22. " DOE22 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 21. " DOE21 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 20. " DOE20 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 19. " DOE19 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 18. " DOE18 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " DOE17 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " DOE16 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 15. " DOE15 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 14. " DOE14 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 13. " DOE13 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 12. " DOE12 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11. " DOE11 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 10. " DOE10 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 9. " DOE9 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 8. " DOE8 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 7. " DOE7 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 6. " DOE6 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 5. " DOE5 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 4. " DOE4 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 3. " DOE3 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 2. " DOE2 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 1. " DOE1 ,Output enable" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 0. " DOE0 ,Output enable" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_DOE1,Bank 1 Data Output Enable Register" bitfld.long 0x10 30. " DOE30 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 29. " DOE29 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " DOE28 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 27. " DOE27 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 26. " DOE26 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " DOE25 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 24. " DOE24 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 23. " DOE23 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " DOE22 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 21. " DOE21 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 20. " DOE20 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " DOE19 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 18. " DOE18 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 17. " DOE17 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 16. " DOE16 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 15. " DOE15 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 14. " DOE14 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 13. " DOE13 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 12. " DOE12 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 11. " DOE11 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " DOE10 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 9. " DOE9 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 8. " DOE8 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " DOE7 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 6. " DOE6 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 5. " DOE5 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " DOE4 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 3. " DOE3 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 2. " DOE2 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " DOE1 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 0. " DOE0 ,Output enable" "Disabled,Enabled" line.long (0x10+0x04) "HW_PINCTRL_DOE1_SET,Bank 1 Data Output Enable Set Register" bitfld.long (0x10+0x04) 30. " DOE30 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 29. " DOE29 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " DOE28 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 27. " DOE27 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 26. " DOE26 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " DOE25 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 24. " DOE24 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 23. " DOE23 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " DOE22 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 21. " DOE21 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 20. " DOE20 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " DOE19 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 18. " DOE18 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 17. " DOE17 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " DOE16 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 15. " DOE15 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 14. " DOE14 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " DOE13 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 12. " DOE12 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 11. " DOE11 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " DOE10 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 9. " DOE9 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 8. " DOE8 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " DOE7 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 6. " DOE6 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 5. " DOE5 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " DOE4 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 3. " DOE3 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 2. " DOE2 ,Output enable" "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " DOE1 ,Output enable" "No effect,Set" bitfld.long (0x10+0x04) 0. " DOE0 ,Output enable" "No effect,Set" line.long (0x10+0x08) "HW_PINCTRL_DOE1_CLR,Bank 1 Data Output Enable Clear Register" bitfld.long (0x10+0x08) 30. " DOE30 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 29. " DOE29 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 28. " DOE28 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 27. " DOE27 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 26. " DOE26 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " DOE25 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 24. " DOE24 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 23. " DOE23 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 22. " DOE22 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 21. " DOE21 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 20. " DOE20 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 19. " DOE19 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 18. " DOE18 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 17. " DOE17 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " DOE16 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 15. " DOE15 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 14. " DOE14 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 13. " DOE13 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 12. " DOE12 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 11. " DOE11 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 10. " DOE10 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 9. " DOE9 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 8. " DOE8 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 7. " DOE7 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 6. " DOE6 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 5. " DOE5 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 4. " DOE4 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 3. " DOE3 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 2. " DOE2 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 1. " DOE1 ,Output enable" "No effect,Clear" bitfld.long (0x10+0x08) 0. " DOE0 ,Output enable" "No effect,Clear" line.long (0x10+0x0c) "HW_PINCTRL_DOE1_TOG,Bank 1 Data Output Enable Toggle Register" bitfld.long (0x10+0x0c) 30. " DOE30 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " DOE29 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 28. " DOE28 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 27. " DOE27 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " DOE26 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " DOE25 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " DOE24 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 23. " DOE23 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 22. " DOE22 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 21. " DOE21 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 20. " DOE20 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 19. " DOE19 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 18. " DOE18 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " DOE17 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " DOE16 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 15. " DOE15 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 14. " DOE14 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 13. " DOE13 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 12. " DOE12 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11. " DOE11 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 10. " DOE10 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 9. " DOE9 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 8. " DOE8 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 7. " DOE7 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 6. " DOE6 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 5. " DOE5 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 4. " DOE4 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 3. " DOE3 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 2. " DOE2 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 1. " DOE1 ,Output enable" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 0. " DOE0 ,Output enable" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_DOE2,Bank 2 Data Output Enable Register" bitfld.long 0x20 31. " DOE31 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 30. " DOE30 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 29. " DOE29 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 28. " DOE28 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 27. " DOE27 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 26. " DOE26 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " DOE25 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 24. " DOE24 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 23. " DOE23 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 22. " DOE22 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 21. " DOE21 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 20. " DOE20 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " DOE19 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 18. " DOE18 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 17. " DOE17 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 16. " DOE16 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 15. " DOE15 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 14. " DOE14 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 13. " DOE13 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 12. " DOE12 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 11. " DOE11 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 10. " DOE10 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 9. " DOE9 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 8. " DOE8 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " DOE7 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 6. " DOE6 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 5. " DOE5 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " DOE4 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 3. " DOE3 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 2. " DOE2 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " DOE1 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 0. " DOE0 ,Output enable" "Disabled,Enabled" line.long (0x20+0x04) "HW_PINCTRL_DOE2_SET,Bank 2 Data Output Enable Set Register" bitfld.long (0x20+0x04) 31. " DOE31 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 30. " DOE30 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 29. " DOE29 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 28. " DOE28 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 27. " DOE27 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 26. " DOE26 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " DOE25 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 24. " DOE24 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 23. " DOE23 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " DOE22 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 21. " DOE21 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 20. " DOE20 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " DOE19 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 18. " DOE18 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 17. " DOE17 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " DOE16 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 15. " DOE15 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 14. " DOE14 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " DOE13 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 12. " DOE12 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 11. " DOE11 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " DOE10 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 9. " DOE9 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 8. " DOE8 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " DOE7 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 6. " DOE6 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 5. " DOE5 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " DOE4 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 3. " DOE3 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 2. " DOE2 ,Output enable" "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " DOE1 ,Output enable" "No effect,Set" bitfld.long (0x20+0x04) 0. " DOE0 ,Output enable" "No effect,Set" line.long (0x20+0x08) "HW_PINCTRL_DOE2_CLR,Bank 2 Data Output Enable Clear Register" bitfld.long (0x20+0x08) 31. " DOE31 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 30. " DOE30 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 29. " DOE29 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 28. " DOE28 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 27. " DOE27 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 26. " DOE26 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " DOE25 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 24. " DOE24 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 23. " DOE23 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 22. " DOE22 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 21. " DOE21 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 20. " DOE20 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 19. " DOE19 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 18. " DOE18 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 17. " DOE17 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " DOE16 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 15. " DOE15 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 14. " DOE14 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 13. " DOE13 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 12. " DOE12 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 11. " DOE11 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 10. " DOE10 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 9. " DOE9 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 8. " DOE8 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 7. " DOE7 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 6. " DOE6 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 5. " DOE5 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 4. " DOE4 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 3. " DOE3 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 2. " DOE2 ,Output enable" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 1. " DOE1 ,Output enable" "No effect,Clear" bitfld.long (0x20+0x08) 0. " DOE0 ,Output enable" "No effect,Clear" line.long (0x20+0x0c) "HW_PINCTRL_DOE2_TOG,Bank 2 Data Output Enable Toggle Register" bitfld.long (0x20+0x0c) 31. " DOE31 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " DOE30 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " DOE29 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 28. " DOE28 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 27. " DOE27 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " DOE26 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " DOE25 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " DOE24 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 23. " DOE23 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 22. " DOE22 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 21. " DOE21 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 20. " DOE20 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 19. " DOE19 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 18. " DOE18 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " DOE17 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " DOE16 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 15. " DOE15 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 14. " DOE14 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 13. " DOE13 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 12. " DOE12 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11. " DOE11 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 10. " DOE10 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 9. " DOE9 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 8. " DOE8 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 7. " DOE7 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 6. " DOE6 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 5. " DOE5 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 4. " DOE4 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 3. " DOE3 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 2. " DOE2 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 1. " DOE1 ,Output enable" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 0. " DOE0 ,Output enable" "Not toggle,Toggle" tree.end tree "Interrupt Registers" group.long 0x800++0x3f "Interrupt Select Registers" width 26. line.long 0x0 "HW_PINCTRL_PIN2IRQ0,Bank 0 Interrupt Select Register" bitfld.long 0x0 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Disabled,Enabled" line.long (0x0+0x04) "HW_PINCTRL_PIN2IRQ0_SET,Bank 0 Interrupt Select Set Register" bitfld.long (0x0+0x04) 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x0+0x04) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Set" line.long (0x0+0x08) "HW_PINCTRL_PIN2IRQ0_CLR,Bank 0 Interrupt Select Clear Register" bitfld.long (0x0+0x08) 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x0+0x08) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Clear" line.long (0x0+0x0c) "HW_PINCTRL_PIN2IRQ0_TOG,Bank 0 Interrupt Select Toggle Register" bitfld.long (0x0+0x0c) 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_PIN2IRQ1,Bank 1 Interrupt Select Register" bitfld.long 0x10 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Disabled,Enabled" line.long (0x10+0x04) "HW_PINCTRL_PIN2IRQ1_SET,Bank 1 Interrupt Select Set Register" bitfld.long (0x10+0x04) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x10+0x04) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Set" line.long (0x10+0x08) "HW_PINCTRL_PIN2IRQ1_CLR,Bank 1 Interrupt Select Clear Register" bitfld.long (0x10+0x08) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x10+0x08) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Clear" line.long (0x10+0x0c) "HW_PINCTRL_PIN2IRQ1_TOG,Bank 1 Interrupt Select Toggle Register" bitfld.long (0x10+0x0c) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_PIN2IRQ2,Bank 2 Interrupt Select Register" bitfld.long 0x20 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Disabled,Enabled" line.long (0x20+0x04) "HW_PINCTRL_PIN2IRQ2_SET,Bank 2 Interrupt Select Set Register" bitfld.long (0x20+0x04) 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long (0x20+0x04) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Set" line.long (0x20+0x08) "HW_PINCTRL_PIN2IRQ2_CLR,Bank 2 Interrupt Select Clear Register" bitfld.long (0x20+0x08) 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long (0x20+0x08) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Clear" line.long (0x20+0x0c) "HW_PINCTRL_PIN2IRQ2_TOG,Bank 2 Interrupt Select Toggle Register" bitfld.long (0x20+0x0c) 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Not toggle,Toggle" group.long 0x900++0x3f "Interrupt Mask Registers" width 24. line.long 0x0 "HW_PINCTRL_IRQEN0,Bank 0 Interrupt Mask Register" bitfld.long 0x0 31. " IRQEN31 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 30. " IRQEN30 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 29. " IRQEN29 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " IRQEN28 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 27. " IRQEN27 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 26. " IRQEN26 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " IRQEN25 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 24. " IRQEN24 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 23. " IRQEN23 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 22. " IRQEN22 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 21. " IRQEN21 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 20. " IRQEN20 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " IRQEN19 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 18. " IRQEN18 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 17. " IRQEN17 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " IRQEN16 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 15. " IRQEN15 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 14. " IRQEN14 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " IRQEN13 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 12. " IRQEN12 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 11. " IRQEN11 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " IRQEN10 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 9. " IRQEN9 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 8. " IRQEN8 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " IRQEN7 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 6. " IRQEN6 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 5. " IRQEN5 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " IRQEN4 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 3. " IRQEN3 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 2. " IRQEN2 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " IRQEN1 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 0. " IRQEN0 ,Enable interrupt" "Disabled,Enabled" line.long (0x0+0x04) "HW_PINCTRL_IRQEN0_SET,Bank 0 Interrupt Mask Set Register" bitfld.long (0x0+0x04) 31. " IRQEN31 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 30. " IRQEN30 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 29. " IRQEN29 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 28. " IRQEN28 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 27. " IRQEN27 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 26. " IRQEN26 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " IRQEN25 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 24. " IRQEN24 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 23. " IRQEN23 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " IRQEN22 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 21. " IRQEN21 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 20. " IRQEN20 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " IRQEN19 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 18. " IRQEN18 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 17. " IRQEN17 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " IRQEN16 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 15. " IRQEN15 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 14. " IRQEN14 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " IRQEN13 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 12. " IRQEN12 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 11. " IRQEN11 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " IRQEN10 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 9. " IRQEN9 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 8. " IRQEN8 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " IRQEN7 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 6. " IRQEN6 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 5. " IRQEN5 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " IRQEN4 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 3. " IRQEN3 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 2. " IRQEN2 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " IRQEN1 ,Enable interrupt" "No effect,Set" bitfld.long (0x0+0x04) 0. " IRQEN0 ,Enable interrupt" "No effect,Set" line.long (0x0+0x08) "HW_PINCTRL_IRQEN0_CLR,Bank 0 Interrupt Mask Clear Register" bitfld.long (0x0+0x08) 31. " IRQEN31 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 30. " IRQEN30 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 29. " IRQEN29 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 28. " IRQEN28 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 27. " IRQEN27 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 26. " IRQEN26 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " IRQEN25 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 24. " IRQEN24 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 23. " IRQEN23 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 22. " IRQEN22 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 21. " IRQEN21 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 20. " IRQEN20 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 19. " IRQEN19 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 18. " IRQEN18 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 17. " IRQEN17 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " IRQEN16 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 15. " IRQEN15 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 14. " IRQEN14 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 13. " IRQEN13 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 12. " IRQEN12 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 11. " IRQEN11 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 10. " IRQEN10 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 9. " IRQEN9 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 8. " IRQEN8 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 7. " IRQEN7 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 6. " IRQEN6 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 5. " IRQEN5 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 4. " IRQEN4 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 3. " IRQEN3 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 2. " IRQEN2 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 1. " IRQEN1 ,Enable interrupt" "No effect,Clear" bitfld.long (0x0+0x08) 0. " IRQEN0 ,Enable interrupt" "No effect,Clear" line.long (0x0+0x0c) "HW_PINCTRL_IRQEN0_TOG,Bank 0 Interrupt Mask Toggle Register" bitfld.long (0x0+0x0c) 31. " IRQEN31 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " IRQEN30 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " IRQEN29 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 28. " IRQEN28 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 27. " IRQEN27 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " IRQEN26 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " IRQEN25 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " IRQEN24 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 23. " IRQEN23 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 22. " IRQEN22 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 21. " IRQEN21 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 20. " IRQEN20 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 19. " IRQEN19 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 18. " IRQEN18 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " IRQEN17 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " IRQEN16 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 15. " IRQEN15 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 14. " IRQEN14 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 13. " IRQEN13 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 12. " IRQEN12 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11. " IRQEN11 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 10. " IRQEN10 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 9. " IRQEN9 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 8. " IRQEN8 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 7. " IRQEN7 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 6. " IRQEN6 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 5. " IRQEN5 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 4. " IRQEN4 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 3. " IRQEN3 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 2. " IRQEN2 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 1. " IRQEN1 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 0. " IRQEN0 ,Enable interrupt" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_IRQEN1,Bank 1 Interrupt Mask Register" bitfld.long 0x10 30. " IRQEN30 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 29. " IRQEN29 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " IRQEN28 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 27. " IRQEN27 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 26. " IRQEN26 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " IRQEN25 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 24. " IRQEN24 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 23. " IRQEN23 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " IRQEN22 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 21. " IRQEN21 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 20. " IRQEN20 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " IRQEN19 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 18. " IRQEN18 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 17. " IRQEN17 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 16. " IRQEN16 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 15. " IRQEN15 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 14. " IRQEN14 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 13. " IRQEN13 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 12. " IRQEN12 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 11. " IRQEN11 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " IRQEN10 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 9. " IRQEN9 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 8. " IRQEN8 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " IRQEN7 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 6. " IRQEN6 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 5. " IRQEN5 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " IRQEN4 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 3. " IRQEN3 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 2. " IRQEN2 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " IRQEN1 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 0. " IRQEN0 ,Enable interrupt" "Disabled,Enabled" line.long (0x10+0x04) "HW_PINCTRL_IRQEN1_SET,Bank 1 Interrupt Mask Set Register" bitfld.long (0x10+0x04) 30. " IRQEN30 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 29. " IRQEN29 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " IRQEN28 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 27. " IRQEN27 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 26. " IRQEN26 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " IRQEN25 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 24. " IRQEN24 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 23. " IRQEN23 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " IRQEN22 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 21. " IRQEN21 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 20. " IRQEN20 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " IRQEN19 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 18. " IRQEN18 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 17. " IRQEN17 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " IRQEN16 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 15. " IRQEN15 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 14. " IRQEN14 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " IRQEN13 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 12. " IRQEN12 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 11. " IRQEN11 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " IRQEN10 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 9. " IRQEN9 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 8. " IRQEN8 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " IRQEN7 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 6. " IRQEN6 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 5. " IRQEN5 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " IRQEN4 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 3. " IRQEN3 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 2. " IRQEN2 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " IRQEN1 ,Enable interrupt" "No effect,Set" bitfld.long (0x10+0x04) 0. " IRQEN0 ,Enable interrupt" "No effect,Set" line.long (0x10+0x08) "HW_PINCTRL_IRQEN1_CLR,Bank 1 Interrupt Mask Clear Register" bitfld.long (0x10+0x08) 30. " IRQEN30 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 29. " IRQEN29 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 28. " IRQEN28 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 27. " IRQEN27 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 26. " IRQEN26 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " IRQEN25 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 24. " IRQEN24 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 23. " IRQEN23 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 22. " IRQEN22 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 21. " IRQEN21 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 20. " IRQEN20 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 19. " IRQEN19 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 18. " IRQEN18 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 17. " IRQEN17 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " IRQEN16 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 15. " IRQEN15 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 14. " IRQEN14 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 13. " IRQEN13 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 12. " IRQEN12 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 11. " IRQEN11 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 10. " IRQEN10 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 9. " IRQEN9 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 8. " IRQEN8 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 7. " IRQEN7 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 6. " IRQEN6 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 5. " IRQEN5 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 4. " IRQEN4 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 3. " IRQEN3 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 2. " IRQEN2 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 1. " IRQEN1 ,Enable interrupt" "No effect,Clear" bitfld.long (0x10+0x08) 0. " IRQEN0 ,Enable interrupt" "No effect,Clear" line.long (0x10+0x0c) "HW_PINCTRL_IRQEN1_TOG,Bank 1 Interrupt Mask Toggle Register" bitfld.long (0x10+0x0c) 30. " IRQEN30 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " IRQEN29 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 28. " IRQEN28 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 27. " IRQEN27 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " IRQEN26 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " IRQEN25 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " IRQEN24 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 23. " IRQEN23 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 22. " IRQEN22 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 21. " IRQEN21 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 20. " IRQEN20 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 19. " IRQEN19 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 18. " IRQEN18 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " IRQEN17 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " IRQEN16 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 15. " IRQEN15 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 14. " IRQEN14 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 13. " IRQEN13 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 12. " IRQEN12 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11. " IRQEN11 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 10. " IRQEN10 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 9. " IRQEN9 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 8. " IRQEN8 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 7. " IRQEN7 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 6. " IRQEN6 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 5. " IRQEN5 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 4. " IRQEN4 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 3. " IRQEN3 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 2. " IRQEN2 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 1. " IRQEN1 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 0. " IRQEN0 ,Enable interrupt" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_IRQEN2,Bank 2 Interrupt Mask Register" bitfld.long 0x20 31. " IRQEN31 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 30. " IRQEN30 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 29. " IRQEN29 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 28. " IRQEN28 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 27. " IRQEN27 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 26. " IRQEN26 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " IRQEN25 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 24. " IRQEN24 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 23. " IRQEN23 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 22. " IRQEN22 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 21. " IRQEN21 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 20. " IRQEN20 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " IRQEN19 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 18. " IRQEN18 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 17. " IRQEN17 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 16. " IRQEN16 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 15. " IRQEN15 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 14. " IRQEN14 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 13. " IRQEN13 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 12. " IRQEN12 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 11. " IRQEN11 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 10. " IRQEN10 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 9. " IRQEN9 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 8. " IRQEN8 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " IRQEN7 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 6. " IRQEN6 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 5. " IRQEN5 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " IRQEN4 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 3. " IRQEN3 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 2. " IRQEN2 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " IRQEN1 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 0. " IRQEN0 ,Enable interrupt" "Disabled,Enabled" line.long (0x20+0x04) "HW_PINCTRL_IRQEN2_SET,Bank 2 Interrupt Mask Set Register" bitfld.long (0x20+0x04) 31. " IRQEN31 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 30. " IRQEN30 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 29. " IRQEN29 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 28. " IRQEN28 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 27. " IRQEN27 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 26. " IRQEN26 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " IRQEN25 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 24. " IRQEN24 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 23. " IRQEN23 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " IRQEN22 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 21. " IRQEN21 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 20. " IRQEN20 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " IRQEN19 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 18. " IRQEN18 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 17. " IRQEN17 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " IRQEN16 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 15. " IRQEN15 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 14. " IRQEN14 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " IRQEN13 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 12. " IRQEN12 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 11. " IRQEN11 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " IRQEN10 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 9. " IRQEN9 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 8. " IRQEN8 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " IRQEN7 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 6. " IRQEN6 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 5. " IRQEN5 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " IRQEN4 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 3. " IRQEN3 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 2. " IRQEN2 ,Enable interrupt" "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " IRQEN1 ,Enable interrupt" "No effect,Set" bitfld.long (0x20+0x04) 0. " IRQEN0 ,Enable interrupt" "No effect,Set" line.long (0x20+0x08) "HW_PINCTRL_IRQEN2_CLR,Bank 2 Interrupt Mask Clear Register" bitfld.long (0x20+0x08) 31. " IRQEN31 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 30. " IRQEN30 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 29. " IRQEN29 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 28. " IRQEN28 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 27. " IRQEN27 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 26. " IRQEN26 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " IRQEN25 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 24. " IRQEN24 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 23. " IRQEN23 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 22. " IRQEN22 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 21. " IRQEN21 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 20. " IRQEN20 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 19. " IRQEN19 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 18. " IRQEN18 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 17. " IRQEN17 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " IRQEN16 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 15. " IRQEN15 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 14. " IRQEN14 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 13. " IRQEN13 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 12. " IRQEN12 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 11. " IRQEN11 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 10. " IRQEN10 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 9. " IRQEN9 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 8. " IRQEN8 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 7. " IRQEN7 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 6. " IRQEN6 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 5. " IRQEN5 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 4. " IRQEN4 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 3. " IRQEN3 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 2. " IRQEN2 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 1. " IRQEN1 ,Enable interrupt" "No effect,Clear" bitfld.long (0x20+0x08) 0. " IRQEN0 ,Enable interrupt" "No effect,Clear" line.long (0x20+0x0c) "HW_PINCTRL_IRQEN2_TOG,Bank 2 Interrupt Mask Toggle Register" bitfld.long (0x20+0x0c) 31. " IRQEN31 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " IRQEN30 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " IRQEN29 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 28. " IRQEN28 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 27. " IRQEN27 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " IRQEN26 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " IRQEN25 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " IRQEN24 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 23. " IRQEN23 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 22. " IRQEN22 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 21. " IRQEN21 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 20. " IRQEN20 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 19. " IRQEN19 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 18. " IRQEN18 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " IRQEN17 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " IRQEN16 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 15. " IRQEN15 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 14. " IRQEN14 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 13. " IRQEN13 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 12. " IRQEN12 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11. " IRQEN11 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 10. " IRQEN10 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 9. " IRQEN9 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 8. " IRQEN8 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 7. " IRQEN7 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 6. " IRQEN6 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 5. " IRQEN5 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 4. " IRQEN4 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 3. " IRQEN3 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 2. " IRQEN2 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 1. " IRQEN1 ,Enable interrupt" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 0. " IRQEN0 ,Enable interrupt" "Not toggle,Toggle" group.long 0xa00++0x3f "Interrupt Level/Edge Registers" width 25. line.long 0x0 "HW_PINCTRL_IRQLVL0,Bank 0 Interrupt Level/Edge Register" bitfld.long 0x0 31. " IRQLVL31 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 30. " IRQLVL30 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 29. " IRQLVL29 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 28. " IRQLVL28 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 27. " IRQLVL27 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 26. " IRQLVL26 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 25. " IRQLVL25 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 24. " IRQLVL24 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 23. " IRQLVL23 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 22. " IRQLVL22 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 21. " IRQLVL21 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 20. " IRQLVL20 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 19. " IRQLVL19 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 18. " IRQLVL18 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 17. " IRQLVL17 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 16. " IRQLVL16 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 15. " IRQLVL15 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 14. " IRQLVL14 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 13. " IRQLVL13 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 12. " IRQLVL12 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 11. " IRQLVL11 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 10. " IRQLVL10 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 9. " IRQLVL9 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 8. " IRQLVL8 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 7. " IRQLVL7 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 6. " IRQLVL6 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 5. " IRQLVL5 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 4. " IRQLVL4 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 3. " IRQLVL3 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 2. " IRQLVL2 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x0 1. " IRQLVL1 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x0 0. " IRQLVL0 ,Select level or edge sensitivity" "Edge,Level" line.long (0x0+0x04) "HW_PINCTRL_IRQLVL0_SET,Bank 0 Interrupt Level/Edge Set Register" bitfld.long (0x0+0x04) 31. " IRQLVL31 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x0+0x04) 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Set" line.long (0x0+0x08) "HW_PINCTRL_IRQLVL0_CLR,Bank 0 Interrupt Level/Edge Clear Register" bitfld.long (0x0+0x08) 31. " IRQLVL31 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x0+0x08) 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Clear" line.long (0x0+0x0c) "HW_PINCTRL_IRQLVL0_TOG,Bank 0 Interrupt Level/Edge Toggle Register" bitfld.long (0x0+0x0c) 31. " IRQLVL31 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " IRQLVL30 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " IRQLVL29 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 28. " IRQLVL28 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 27. " IRQLVL27 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " IRQLVL26 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " IRQLVL25 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " IRQLVL24 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 23. " IRQLVL23 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 22. " IRQLVL22 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 21. " IRQLVL21 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 20. " IRQLVL20 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 19. " IRQLVL19 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 18. " IRQLVL18 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " IRQLVL17 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " IRQLVL16 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 15. " IRQLVL15 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 14. " IRQLVL14 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 13. " IRQLVL13 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 12. " IRQLVL12 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11. " IRQLVL11 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 10. " IRQLVL10 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 9. " IRQLVL9 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 8. " IRQLVL8 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 7. " IRQLVL7 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 6. " IRQLVL6 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 5. " IRQLVL5 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 4. " IRQLVL4 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 3. " IRQLVL3 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 2. " IRQLVL2 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 1. " IRQLVL1 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 0. " IRQLVL0 ,Select level or edge sensitivity" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_IRQLVL1,Bank 1 Interrupt Level/Edge Register" bitfld.long 0x10 30. " IRQLVL30 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 29. " IRQLVL29 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 28. " IRQLVL28 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 27. " IRQLVL27 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 26. " IRQLVL26 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 25. " IRQLVL25 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 24. " IRQLVL24 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 23. " IRQLVL23 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 22. " IRQLVL22 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 21. " IRQLVL21 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 20. " IRQLVL20 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 19. " IRQLVL19 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 18. " IRQLVL18 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 17. " IRQLVL17 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 16. " IRQLVL16 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 15. " IRQLVL15 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 14. " IRQLVL14 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 13. " IRQLVL13 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 12. " IRQLVL12 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 11. " IRQLVL11 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 10. " IRQLVL10 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 9. " IRQLVL9 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 8. " IRQLVL8 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 7. " IRQLVL7 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 6. " IRQLVL6 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 5. " IRQLVL5 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 4. " IRQLVL4 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 3. " IRQLVL3 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 2. " IRQLVL2 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x10 1. " IRQLVL1 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x10 0. " IRQLVL0 ,Select level or edge sensitivity" "Edge,Level" line.long (0x10+0x04) "HW_PINCTRL_IRQLVL1_SET,Bank 1 Interrupt Level/Edge Set Register" bitfld.long (0x10+0x04) 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x10+0x04) 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Set" line.long (0x10+0x08) "HW_PINCTRL_IRQLVL1_CLR,Bank 1 Interrupt Level/Edge Clear Register" bitfld.long (0x10+0x08) 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x10+0x08) 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Clear" line.long (0x10+0x0c) "HW_PINCTRL_IRQLVL1_TOG,Bank 1 Interrupt Level/Edge Toggle Register" bitfld.long (0x10+0x0c) 30. " IRQLVL30 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " IRQLVL29 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 28. " IRQLVL28 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 27. " IRQLVL27 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " IRQLVL26 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " IRQLVL25 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " IRQLVL24 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 23. " IRQLVL23 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 22. " IRQLVL22 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 21. " IRQLVL21 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 20. " IRQLVL20 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 19. " IRQLVL19 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 18. " IRQLVL18 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " IRQLVL17 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " IRQLVL16 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 15. " IRQLVL15 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 14. " IRQLVL14 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 13. " IRQLVL13 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 12. " IRQLVL12 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11. " IRQLVL11 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 10. " IRQLVL10 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 9. " IRQLVL9 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 8. " IRQLVL8 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 7. " IRQLVL7 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 6. " IRQLVL6 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 5. " IRQLVL5 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 4. " IRQLVL4 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 3. " IRQLVL3 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 2. " IRQLVL2 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 1. " IRQLVL1 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 0. " IRQLVL0 ,Select level or edge sensitivity" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_IRQLVL2,Bank 2 Interrupt Level/Edge Register" bitfld.long 0x20 31. " IRQLVL31 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 30. " IRQLVL30 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 29. " IRQLVL29 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 28. " IRQLVL28 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 27. " IRQLVL27 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 26. " IRQLVL26 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 25. " IRQLVL25 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 24. " IRQLVL24 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 23. " IRQLVL23 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 22. " IRQLVL22 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 21. " IRQLVL21 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 20. " IRQLVL20 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 19. " IRQLVL19 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 18. " IRQLVL18 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 17. " IRQLVL17 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 16. " IRQLVL16 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 15. " IRQLVL15 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 14. " IRQLVL14 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 13. " IRQLVL13 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 12. " IRQLVL12 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 11. " IRQLVL11 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 10. " IRQLVL10 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 9. " IRQLVL9 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 8. " IRQLVL8 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 7. " IRQLVL7 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 6. " IRQLVL6 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 5. " IRQLVL5 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 4. " IRQLVL4 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 3. " IRQLVL3 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 2. " IRQLVL2 ,Select level or edge sensitivity" "Edge,Level" textline " " bitfld.long 0x20 1. " IRQLVL1 ,Select level or edge sensitivity" "Edge,Level" bitfld.long 0x20 0. " IRQLVL0 ,Select level or edge sensitivity" "Edge,Level" line.long (0x20+0x04) "HW_PINCTRL_IRQLVL2_SET,Bank 2 Interrupt Level/Edge Set Register" bitfld.long (0x20+0x04) 31. " IRQLVL31 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Set" bitfld.long (0x20+0x04) 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Set" line.long (0x20+0x08) "HW_PINCTRL_IRQLVL2_CLR,Bank 2 Interrupt Level/Edge Clear Register" bitfld.long (0x20+0x08) 31. " IRQLVL31 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long (0x20+0x08) 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Clear" line.long (0x20+0x0c) "HW_PINCTRL_IRQLVL2_TOG,Bank 2 Interrupt Level/Edge Toggle Register" bitfld.long (0x20+0x0c) 31. " IRQLVL31 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " IRQLVL30 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " IRQLVL29 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 28. " IRQLVL28 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 27. " IRQLVL27 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " IRQLVL26 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " IRQLVL25 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " IRQLVL24 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 23. " IRQLVL23 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 22. " IRQLVL22 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 21. " IRQLVL21 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 20. " IRQLVL20 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 19. " IRQLVL19 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 18. " IRQLVL18 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " IRQLVL17 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " IRQLVL16 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 15. " IRQLVL15 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 14. " IRQLVL14 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 13. " IRQLVL13 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 12. " IRQLVL12 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11. " IRQLVL11 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 10. " IRQLVL10 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 9. " IRQLVL9 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 8. " IRQLVL8 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 7. " IRQLVL7 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 6. " IRQLVL6 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 5. " IRQLVL5 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 4. " IRQLVL4 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 3. " IRQLVL3 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 2. " IRQLVL2 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 1. " IRQLVL1 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 0. " IRQLVL0 ,Select level or edge sensitivity" "Not toggle,Toggle" group.long 0xb00++0x3f "Interrupt Polarity Registers" width 25. line.long 0x0 "HW_PINCTRL_IRGPOL0,Bank 0 Interrupt Polarity Register" bitfld.long 0x0 31. " IRGPOL31 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 30. " IRGPOL30 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 29. " IRGPOL29 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 28. " IRGPOL28 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 27. " IRGPOL27 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 26. " IRGPOL26 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 25. " IRGPOL25 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 24. " IRGPOL24 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 23. " IRGPOL23 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 22. " IRGPOL22 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 21. " IRGPOL21 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 20. " IRGPOL20 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 19. " IRGPOL19 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 18. " IRGPOL18 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 17. " IRGPOL17 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 16. " IRGPOL16 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 15. " IRGPOL15 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 14. " IRGPOL14 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 13. " IRGPOL13 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 12. " IRGPOL12 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 11. " IRGPOL11 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 10. " IRGPOL10 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 9. " IRGPOL9 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 8. " IRGPOL8 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 7. " IRGPOL7 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 6. " IRGPOL6 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 5. " IRGPOL5 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 4. " IRGPOL4 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 3. " IRGPOL3 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 2. " IRGPOL2 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 1. " IRGPOL1 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 0. " IRGPOL0 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" line.long (0x0+0x04) "HW_PINCTRL_IRGPOL0_SET,Bank 0 Interrupt Polarity Set Register" bitfld.long (0x0+0x04) 31. " IRGPOL31 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x0+0x04) 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Set" line.long (0x0+0x08) "HW_PINCTRL_IRGPOL0_CLR,Bank 0 Interrupt Polarity Clear Register" bitfld.long (0x0+0x08) 31. " IRGPOL31 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x0+0x08) 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Clear" line.long (0x0+0x0c) "HW_PINCTRL_IRGPOL0_TOG,Bank 0 Interrupt Polarity Toggle Register" bitfld.long (0x0+0x0c) 31. " IRGPOL31 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " IRGPOL30 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " IRGPOL29 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 28. " IRGPOL28 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 27. " IRGPOL27 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " IRGPOL26 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " IRGPOL25 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " IRGPOL24 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 23. " IRGPOL23 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 22. " IRGPOL22 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 21. " IRGPOL21 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 20. " IRGPOL20 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 19. " IRGPOL19 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 18. " IRGPOL18 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " IRGPOL17 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " IRGPOL16 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 15. " IRGPOL15 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 14. " IRGPOL14 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 13. " IRGPOL13 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 12. " IRGPOL12 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11. " IRGPOL11 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 10. " IRGPOL10 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 9. " IRGPOL9 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 8. " IRGPOL8 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 7. " IRGPOL7 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 6. " IRGPOL6 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 5. " IRGPOL5 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 4. " IRGPOL4 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 3. " IRGPOL3 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 2. " IRGPOL2 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 1. " IRGPOL1 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 0. " IRGPOL0 ,Select the polarity for interrupt " "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_IRGPOL1,Bank 1 Interrupt Polarity Register" bitfld.long 0x10 30. " IRGPOL30 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 29. " IRGPOL29 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 28. " IRGPOL28 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 27. " IRGPOL27 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 26. " IRGPOL26 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 25. " IRGPOL25 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 24. " IRGPOL24 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 23. " IRGPOL23 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 22. " IRGPOL22 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 21. " IRGPOL21 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 20. " IRGPOL20 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 19. " IRGPOL19 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 18. " IRGPOL18 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 17. " IRGPOL17 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 16. " IRGPOL16 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 15. " IRGPOL15 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 14. " IRGPOL14 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 13. " IRGPOL13 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 12. " IRGPOL12 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 11. " IRGPOL11 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 10. " IRGPOL10 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 9. " IRGPOL9 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 8. " IRGPOL8 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 7. " IRGPOL7 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 6. " IRGPOL6 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 5. " IRGPOL5 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 4. " IRGPOL4 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 3. " IRGPOL3 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 2. " IRGPOL2 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 1. " IRGPOL1 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 0. " IRGPOL0 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" line.long (0x10+0x04) "HW_PINCTRL_IRGPOL1_SET,Bank 1 Interrupt Polarity Set Register" bitfld.long (0x10+0x04) 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x10+0x04) 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Set" line.long (0x10+0x08) "HW_PINCTRL_IRGPOL1_CLR,Bank 1 Interrupt Polarity Clear Register" bitfld.long (0x10+0x08) 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x10+0x08) 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Clear" line.long (0x10+0x0c) "HW_PINCTRL_IRGPOL1_TOG,Bank 1 Interrupt Polarity Toggle Register" bitfld.long (0x10+0x0c) 30. " IRGPOL30 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " IRGPOL29 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 28. " IRGPOL28 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 27. " IRGPOL27 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " IRGPOL26 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " IRGPOL25 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " IRGPOL24 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 23. " IRGPOL23 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 22. " IRGPOL22 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 21. " IRGPOL21 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 20. " IRGPOL20 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 19. " IRGPOL19 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 18. " IRGPOL18 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " IRGPOL17 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " IRGPOL16 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 15. " IRGPOL15 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 14. " IRGPOL14 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 13. " IRGPOL13 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 12. " IRGPOL12 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11. " IRGPOL11 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 10. " IRGPOL10 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 9. " IRGPOL9 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 8. " IRGPOL8 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 7. " IRGPOL7 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 6. " IRGPOL6 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 5. " IRGPOL5 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 4. " IRGPOL4 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 3. " IRGPOL3 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 2. " IRGPOL2 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 1. " IRGPOL1 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 0. " IRGPOL0 ,Select the polarity for interrupt " "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_IRGPOL2,Bank 2 Interrupt Polarity Register" bitfld.long 0x20 31. " IRGPOL31 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 30. " IRGPOL30 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 29. " IRGPOL29 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 28. " IRGPOL28 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 27. " IRGPOL27 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 26. " IRGPOL26 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 25. " IRGPOL25 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 24. " IRGPOL24 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 23. " IRGPOL23 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 22. " IRGPOL22 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 21. " IRGPOL21 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 20. " IRGPOL20 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 19. " IRGPOL19 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 18. " IRGPOL18 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 17. " IRGPOL17 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 16. " IRGPOL16 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 15. " IRGPOL15 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 14. " IRGPOL14 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 13. " IRGPOL13 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 12. " IRGPOL12 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 11. " IRGPOL11 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 10. " IRGPOL10 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 9. " IRGPOL9 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 8. " IRGPOL8 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 7. " IRGPOL7 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 6. " IRGPOL6 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 5. " IRGPOL5 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 4. " IRGPOL4 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 3. " IRGPOL3 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 2. " IRGPOL2 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 1. " IRGPOL1 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 0. " IRGPOL0 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" line.long (0x20+0x04) "HW_PINCTRL_IRGPOL2_SET,Bank 2 Interrupt Polarity Set Register" bitfld.long (0x20+0x04) 31. " IRGPOL31 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Set" bitfld.long (0x20+0x04) 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Set" line.long (0x20+0x08) "HW_PINCTRL_IRGPOL2_CLR,Bank 2 Interrupt Polarity Clear Register" bitfld.long (0x20+0x08) 31. " IRGPOL31 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long (0x20+0x08) 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Clear" line.long (0x20+0x0c) "HW_PINCTRL_IRGPOL2_TOG,Bank 2 Interrupt Polarity Toggle Register" bitfld.long (0x20+0x0c) 31. " IRGPOL31 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " IRGPOL30 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " IRGPOL29 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 28. " IRGPOL28 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 27. " IRGPOL27 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " IRGPOL26 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " IRGPOL25 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " IRGPOL24 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 23. " IRGPOL23 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 22. " IRGPOL22 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 21. " IRGPOL21 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 20. " IRGPOL20 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 19. " IRGPOL19 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 18. " IRGPOL18 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " IRGPOL17 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " IRGPOL16 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 15. " IRGPOL15 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 14. " IRGPOL14 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 13. " IRGPOL13 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 12. " IRGPOL12 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11. " IRGPOL11 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 10. " IRGPOL10 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 9. " IRGPOL9 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 8. " IRGPOL8 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 7. " IRGPOL7 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 6. " IRGPOL6 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 5. " IRGPOL5 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 4. " IRGPOL4 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 3. " IRGPOL3 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 2. " IRGPOL2 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 1. " IRGPOL1 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 0. " IRGPOL0 ,Select the polarity for interrupt " "Not toggle,Toggle" group.long 0xc00++0x3f "Interrupt Status Registers" width 26. line.long 0x0 "HW_PINCTRL_IRQSTAT0,Bank 0 Interrupt Status Register" bitfld.long 0x0 31. " IRQSTAT31 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 30. " IRQSTAT30 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 29. " IRQSTAT29 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 28. " IRQSTAT28 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 27. " IRQSTAT27 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 26. " IRQSTAT26 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 25. " IRQSTAT25 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 24. " IRQSTAT24 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 23. " IRQSTAT23 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 22. " IRQSTAT22 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 21. " IRQSTAT21 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 20. " IRQSTAT20 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 19. " IRQSTAT19 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 18. " IRQSTAT18 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 17. " IRQSTAT17 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 16. " IRQSTAT16 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 15. " IRQSTAT15 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 14. " IRQSTAT14 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 13. " IRQSTAT13 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 12. " IRQSTAT12 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 11. " IRQSTAT11 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 10. " IRQSTAT10 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 9. " IRQSTAT9 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 8. " IRQSTAT8 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 7. " IRQSTAT7 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 6. " IRQSTAT6 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 5. " IRQSTAT5 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 4. " IRQSTAT4 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 3. " IRQSTAT3 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 2. " IRQSTAT2 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 1. " IRQSTAT1 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 0. " IRQSTAT0 ,Interrupt status " "Not pending,Pending" line.long (0x0+0x04) "HW_PINCTRL_IRQSTAT0_SET,Bank 0 Interrupt Status Set Register" bitfld.long (0x0+0x04) 31. " IRQSTAT31 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 30. " IRQSTAT30 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 29. " IRQSTAT29 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 28. " IRQSTAT28 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 27. " IRQSTAT27 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 26. " IRQSTAT26 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " IRQSTAT25 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 24. " IRQSTAT24 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 23. " IRQSTAT23 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " IRQSTAT22 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 21. " IRQSTAT21 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 20. " IRQSTAT20 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " IRQSTAT19 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 18. " IRQSTAT18 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 17. " IRQSTAT17 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " IRQSTAT16 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 15. " IRQSTAT15 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 14. " IRQSTAT14 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " IRQSTAT13 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 12. " IRQSTAT12 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 11. " IRQSTAT11 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " IRQSTAT10 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 9. " IRQSTAT9 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 8. " IRQSTAT8 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " IRQSTAT7 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 6. " IRQSTAT6 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 5. " IRQSTAT5 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " IRQSTAT4 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 3. " IRQSTAT3 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 2. " IRQSTAT2 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " IRQSTAT1 ,Interrupt status " "No effect,Set" bitfld.long (0x0+0x04) 0. " IRQSTAT0 ,Interrupt status " "No effect,Set" line.long (0x0+0x08) "HW_PINCTRL_IRQSTAT0_CLR,Bank 0 Interrupt Status Clear Register" bitfld.long (0x0+0x08) 31. " IRQSTAT31 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 30. " IRQSTAT30 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 29. " IRQSTAT29 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 28. " IRQSTAT28 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 27. " IRQSTAT27 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 26. " IRQSTAT26 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " IRQSTAT25 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 24. " IRQSTAT24 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 23. " IRQSTAT23 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 22. " IRQSTAT22 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 21. " IRQSTAT21 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 20. " IRQSTAT20 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 19. " IRQSTAT19 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 18. " IRQSTAT18 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 17. " IRQSTAT17 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " IRQSTAT16 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 15. " IRQSTAT15 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 14. " IRQSTAT14 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 13. " IRQSTAT13 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 12. " IRQSTAT12 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 11. " IRQSTAT11 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 10. " IRQSTAT10 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 9. " IRQSTAT9 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 8. " IRQSTAT8 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 7. " IRQSTAT7 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 6. " IRQSTAT6 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 5. " IRQSTAT5 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 4. " IRQSTAT4 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 3. " IRQSTAT3 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 2. " IRQSTAT2 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x0+0x08) 1. " IRQSTAT1 ,Interrupt status " "No effect,Clear" bitfld.long (0x0+0x08) 0. " IRQSTAT0 ,Interrupt status " "No effect,Clear" line.long (0x0+0x0c) "HW_PINCTRL_IRQSTAT0_TOG,Bank 0 Interrupt Status Toggle Register" bitfld.long (0x0+0x0c) 31. " IRQSTAT31 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " IRQSTAT30 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " IRQSTAT29 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 28. " IRQSTAT28 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 27. " IRQSTAT27 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " IRQSTAT26 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " IRQSTAT25 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " IRQSTAT24 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 23. " IRQSTAT23 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 22. " IRQSTAT22 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 21. " IRQSTAT21 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 20. " IRQSTAT20 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 19. " IRQSTAT19 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 18. " IRQSTAT18 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " IRQSTAT17 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " IRQSTAT16 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 15. " IRQSTAT15 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 14. " IRQSTAT14 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 13. " IRQSTAT13 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 12. " IRQSTAT12 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11. " IRQSTAT11 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 10. " IRQSTAT10 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 9. " IRQSTAT9 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 8. " IRQSTAT8 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 7. " IRQSTAT7 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 6. " IRQSTAT6 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 5. " IRQSTAT5 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 4. " IRQSTAT4 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 3. " IRQSTAT3 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 2. " IRQSTAT2 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 1. " IRQSTAT1 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x0+0x0c) 0. " IRQSTAT0 ,Interrupt status " "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_IRQSTAT1,Bank 1 Interrupt Status Register" bitfld.long 0x10 30. " IRQSTAT30 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 29. " IRQSTAT29 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 28. " IRQSTAT28 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 27. " IRQSTAT27 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 26. " IRQSTAT26 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 25. " IRQSTAT25 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 24. " IRQSTAT24 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 23. " IRQSTAT23 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 22. " IRQSTAT22 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 21. " IRQSTAT21 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 20. " IRQSTAT20 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 19. " IRQSTAT19 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 18. " IRQSTAT18 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 17. " IRQSTAT17 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 16. " IRQSTAT16 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 15. " IRQSTAT15 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 14. " IRQSTAT14 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 13. " IRQSTAT13 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 12. " IRQSTAT12 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 11. " IRQSTAT11 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 10. " IRQSTAT10 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 9. " IRQSTAT9 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 8. " IRQSTAT8 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 7. " IRQSTAT7 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 6. " IRQSTAT6 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 5. " IRQSTAT5 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 4. " IRQSTAT4 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 3. " IRQSTAT3 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 2. " IRQSTAT2 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 1. " IRQSTAT1 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 0. " IRQSTAT0 ,Interrupt status " "Not pending,Pending" line.long (0x10+0x04) "HW_PINCTRL_IRQSTAT1_SET,Bank 1 Interrupt Status Set Register" bitfld.long (0x10+0x04) 30. " IRQSTAT30 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 29. " IRQSTAT29 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " IRQSTAT28 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 27. " IRQSTAT27 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 26. " IRQSTAT26 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " IRQSTAT25 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 24. " IRQSTAT24 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 23. " IRQSTAT23 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " IRQSTAT22 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 21. " IRQSTAT21 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 20. " IRQSTAT20 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " IRQSTAT19 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 18. " IRQSTAT18 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 17. " IRQSTAT17 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " IRQSTAT16 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 15. " IRQSTAT15 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 14. " IRQSTAT14 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " IRQSTAT13 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 12. " IRQSTAT12 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 11. " IRQSTAT11 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " IRQSTAT10 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 9. " IRQSTAT9 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 8. " IRQSTAT8 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " IRQSTAT7 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 6. " IRQSTAT6 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 5. " IRQSTAT5 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " IRQSTAT4 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 3. " IRQSTAT3 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 2. " IRQSTAT2 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " IRQSTAT1 ,Interrupt status " "No effect,Set" bitfld.long (0x10+0x04) 0. " IRQSTAT0 ,Interrupt status " "No effect,Set" line.long (0x10+0x08) "HW_PINCTRL_IRQSTAT1_CLR,Bank 1 Interrupt Status Clear Register" bitfld.long (0x10+0x08) 30. " IRQSTAT30 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 29. " IRQSTAT29 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 28. " IRQSTAT28 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 27. " IRQSTAT27 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 26. " IRQSTAT26 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " IRQSTAT25 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 24. " IRQSTAT24 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 23. " IRQSTAT23 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 22. " IRQSTAT22 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 21. " IRQSTAT21 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 20. " IRQSTAT20 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 19. " IRQSTAT19 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 18. " IRQSTAT18 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 17. " IRQSTAT17 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " IRQSTAT16 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 15. " IRQSTAT15 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 14. " IRQSTAT14 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 13. " IRQSTAT13 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 12. " IRQSTAT12 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 11. " IRQSTAT11 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 10. " IRQSTAT10 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 9. " IRQSTAT9 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 8. " IRQSTAT8 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 7. " IRQSTAT7 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 6. " IRQSTAT6 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 5. " IRQSTAT5 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 4. " IRQSTAT4 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 3. " IRQSTAT3 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 2. " IRQSTAT2 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x10+0x08) 1. " IRQSTAT1 ,Interrupt status " "No effect,Clear" bitfld.long (0x10+0x08) 0. " IRQSTAT0 ,Interrupt status " "No effect,Clear" line.long (0x10+0x0c) "HW_PINCTRL_IRQSTAT1_TOG,Bank 1 Interrupt Status Toggle Register" bitfld.long (0x10+0x0c) 30. " IRQSTAT30 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " IRQSTAT29 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 28. " IRQSTAT28 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 27. " IRQSTAT27 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " IRQSTAT26 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " IRQSTAT25 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " IRQSTAT24 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 23. " IRQSTAT23 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 22. " IRQSTAT22 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 21. " IRQSTAT21 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 20. " IRQSTAT20 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 19. " IRQSTAT19 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 18. " IRQSTAT18 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " IRQSTAT17 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " IRQSTAT16 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 15. " IRQSTAT15 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 14. " IRQSTAT14 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 13. " IRQSTAT13 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 12. " IRQSTAT12 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11. " IRQSTAT11 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 10. " IRQSTAT10 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 9. " IRQSTAT9 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 8. " IRQSTAT8 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 7. " IRQSTAT7 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 6. " IRQSTAT6 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 5. " IRQSTAT5 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 4. " IRQSTAT4 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 3. " IRQSTAT3 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 2. " IRQSTAT2 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 1. " IRQSTAT1 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x10+0x0c) 0. " IRQSTAT0 ,Interrupt status " "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_IRQSTAT2,Bank 2 Interrupt Status Register" bitfld.long 0x20 31. " IRQSTAT31 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 30. " IRQSTAT30 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 29. " IRQSTAT29 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 28. " IRQSTAT28 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 27. " IRQSTAT27 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 26. " IRQSTAT26 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 25. " IRQSTAT25 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 24. " IRQSTAT24 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 23. " IRQSTAT23 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 22. " IRQSTAT22 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 21. " IRQSTAT21 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 20. " IRQSTAT20 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 19. " IRQSTAT19 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 18. " IRQSTAT18 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 17. " IRQSTAT17 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 16. " IRQSTAT16 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 15. " IRQSTAT15 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 14. " IRQSTAT14 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 13. " IRQSTAT13 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 12. " IRQSTAT12 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 11. " IRQSTAT11 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 10. " IRQSTAT10 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 9. " IRQSTAT9 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 8. " IRQSTAT8 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 7. " IRQSTAT7 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 6. " IRQSTAT6 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 5. " IRQSTAT5 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 4. " IRQSTAT4 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 3. " IRQSTAT3 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 2. " IRQSTAT2 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 1. " IRQSTAT1 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 0. " IRQSTAT0 ,Interrupt status " "Not pending,Pending" line.long (0x20+0x04) "HW_PINCTRL_IRQSTAT2_SET,Bank 2 Interrupt Status Set Register" bitfld.long (0x20+0x04) 31. " IRQSTAT31 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 30. " IRQSTAT30 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 29. " IRQSTAT29 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 28. " IRQSTAT28 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 27. " IRQSTAT27 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 26. " IRQSTAT26 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " IRQSTAT25 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 24. " IRQSTAT24 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 23. " IRQSTAT23 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " IRQSTAT22 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 21. " IRQSTAT21 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 20. " IRQSTAT20 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " IRQSTAT19 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 18. " IRQSTAT18 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 17. " IRQSTAT17 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " IRQSTAT16 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 15. " IRQSTAT15 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 14. " IRQSTAT14 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " IRQSTAT13 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 12. " IRQSTAT12 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 11. " IRQSTAT11 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " IRQSTAT10 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 9. " IRQSTAT9 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 8. " IRQSTAT8 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " IRQSTAT7 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 6. " IRQSTAT6 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 5. " IRQSTAT5 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " IRQSTAT4 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 3. " IRQSTAT3 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 2. " IRQSTAT2 ,Interrupt status " "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " IRQSTAT1 ,Interrupt status " "No effect,Set" bitfld.long (0x20+0x04) 0. " IRQSTAT0 ,Interrupt status " "No effect,Set" line.long (0x20+0x08) "HW_PINCTRL_IRQSTAT2_CLR,Bank 2 Interrupt Status Clear Register" bitfld.long (0x20+0x08) 31. " IRQSTAT31 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 30. " IRQSTAT30 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 29. " IRQSTAT29 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 28. " IRQSTAT28 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 27. " IRQSTAT27 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 26. " IRQSTAT26 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " IRQSTAT25 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 24. " IRQSTAT24 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 23. " IRQSTAT23 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 22. " IRQSTAT22 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 21. " IRQSTAT21 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 20. " IRQSTAT20 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 19. " IRQSTAT19 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 18. " IRQSTAT18 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 17. " IRQSTAT17 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " IRQSTAT16 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 15. " IRQSTAT15 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 14. " IRQSTAT14 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 13. " IRQSTAT13 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 12. " IRQSTAT12 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 11. " IRQSTAT11 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 10. " IRQSTAT10 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 9. " IRQSTAT9 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 8. " IRQSTAT8 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 7. " IRQSTAT7 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 6. " IRQSTAT6 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 5. " IRQSTAT5 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 4. " IRQSTAT4 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 3. " IRQSTAT3 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 2. " IRQSTAT2 ,Interrupt status " "No effect,Clear" textline " " bitfld.long (0x20+0x08) 1. " IRQSTAT1 ,Interrupt status " "No effect,Clear" bitfld.long (0x20+0x08) 0. " IRQSTAT0 ,Interrupt status " "No effect,Clear" line.long (0x20+0x0c) "HW_PINCTRL_IRQSTAT2_TOG,Bank 2 Interrupt Status Toggle Register" bitfld.long (0x20+0x0c) 31. " IRQSTAT31 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " IRQSTAT30 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " IRQSTAT29 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 28. " IRQSTAT28 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 27. " IRQSTAT27 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " IRQSTAT26 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " IRQSTAT25 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " IRQSTAT24 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 23. " IRQSTAT23 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 22. " IRQSTAT22 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 21. " IRQSTAT21 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 20. " IRQSTAT20 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 19. " IRQSTAT19 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 18. " IRQSTAT18 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " IRQSTAT17 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " IRQSTAT16 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 15. " IRQSTAT15 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 14. " IRQSTAT14 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 13. " IRQSTAT13 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 12. " IRQSTAT12 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11. " IRQSTAT11 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 10. " IRQSTAT10 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 9. " IRQSTAT9 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 8. " IRQSTAT8 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 7. " IRQSTAT7 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 6. " IRQSTAT6 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 5. " IRQSTAT5 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 4. " IRQSTAT4 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 3. " IRQSTAT3 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 2. " IRQSTAT2 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 1. " IRQSTAT1 ,Interrupt status " "Not toggle,Toggle" bitfld.long (0x20+0x0c) 0. " IRQSTAT0 ,Interrupt status " "Not toggle,Toggle" tree.end width 0xb tree.end textline ""